TW201725776A - Intermixing prevention in electrochemical devices - Google Patents

Abstract

A thin film battery may comprise: an intermixing barrier layer on a thin substrate, such as a YSZ substrate, with a substrate thickness in the range of 10 microns to 100 microns, the intermixing barrier layer comprising one or more of Al2O3, Si3N4 and other electrically insulating layers, and in embodiments having a higher cation packing density than the substrate; a patterned current collector layer on the intermixing barrier layer; and a cathode layer, such as LCO, on the current collector layer, wherein the intermixing barrier layer, the patterned current collector and the cathode layer form a stack on the substrate; wherein the intermixing barrier layer prevents intermixing of the current collector and cathode layers, and any other layers in the stack during annealing, at a temperature in the range of 500 DEG C to 800 DEG C, with a soak time in the range of 2 to 30 hours.

Description

Mutual mixing suppression in electrochemical devices

Embodiments of the present disclosure generally relate to electrochemical devices and methods of fabricating electrochemical devices, and more specifically, but not exclusively, to having a miscible barrier layer deposited on a substrate and between a substrate and a collector layer Thin film battery.

A thin film battery (TFB) may include a thin film stacked layer including an anode and cathode current collector (ACC, CCC), a cathode (positive electrode), a solid electrolyte, an anode (negative electrode), and a packaging layer or package. During a thin film cell fabrication process, one of the positive electrodes (referred to herein as a cathode) is typically formed of a material such as lithium cobalt oxide (LCO) that needs to be annealed at relatively high temperatures to form the desired material properties (eg, An electrode having a high percentage (greater than 90%) of high temperature phase LiCoO ₂ (HT-LCO). In order to form a robust and functional device structure, it is necessary to control and optimize the various aspects of the manufacturing process, particularly when the positive electrode is subjected to this relatively high temperature (e.g., in the range of 500 ° C to 800 ° C) heat treatment.

In addition, there is a need to improve device metrics, where energy density is an important metric. In order to increase the energy density and further improve the formation factor of the thin film solid state battery, the use of a thinner substrate is one of the most efficient and necessary methods. However, the use of thinner (e.g., 10 micron to 100 micron thick) substrates presents many challenges associated with fabricating devices having satisfactory operational and robust properties. One of the important problems that the inventors have discovered is the intermixing of the cathode layer (LiCoO ₂ ) and the CCC layer during the LCO thermal annealing process, which leads to higher impedance of the current collector and loss of the active material (LiCoO ₂ ), wherein the mutual mixing The severity depends on the substrate material, LiCoO ₂ deposition treatment and annealing temperature. The intermixing of LiCoO ₂ layers may result in: poor adhesion of the structure/CCC to the substrate; impurities in the LCO layer and loss of active material; not to mention the stress at the intermixing position, which depends on the severity of the intermixing. This intermixing can be visually observed through the back side of the optically transparent/translucent substrate (discussed in more detail below), and this intermixing causes deterioration in device performance due to the increased impedance of CCC (due to the LCO in CCC) With reduced efficiency of the positive electrode and/or positive electrode (due to the CCC material in the positive electrode), this can measure lower cell capacity utilization, higher IR drop, and the like during cell cycle testing. Furthermore, intermixing may reduce the mechanical yield of TFB and be manifested in wafer/substrate curvature.

An example of such a thin substrate is a polycrystalline ceramic substrate such as yttria-stabilized zirconia (YSZ). Although these YSZ substrates can withstand higher thermal budgets, including annealing beyond 600 °C to form higher quality LCOs, have a purer phase and higher crystallinity (higher than 90% by weight or volume percent of HT-LiCO) However, as described above, the inventors have found that the intermixing of the CCC layer and the LiCoO ₂ layer during the LCO annealing process significantly causes device stability and performance problems.

Clearly, there is a need for manufacturing processes and electrochemical device configurations that reduce device layer intermixing during high temperature annealing (eg, LCO annealing) and thereby maintain the following properties: CCC function (adhesion and conductivity); cathode layer purity, Phase and effective mass; integrity of the overall electrochemical device configuration (by stratifying the device layer and/or the stress between the device layer and the stack of substrates to avoid delamination of the device layer).

According to some embodiments, the thin film battery may include: a miscible barrier layer on the thin substrate, the substrate thickness is in the range of 10 micrometers to 100 micrometers, the intermixed barrier layer comprises an electrically insulating material, and the thickness of the intermixed barrier layer is a range of 50 nm to 5,000 nm; a patterned collector layer on the intermixed barrier layer; and a cathode layer on the patterned collector layer, wherein the intermixed barrier layer, the patterned collector layer and the cathode layer are formed Stacked on a thin substrate, the cathode layer has been annealed at a temperature in the range of 500 ° C to 800 ° C for a holding time in the range of 2 to 30 hours; wherein the intermixed barrier layer avoids the collector layer and the cathode layer during the annealing of the cathode layer Mutual mix.

According to some embodiments, a method of fabricating a thin film battery may include depositing an intermixed barrier layer on a thin substrate having a substrate thickness in a range of 10 micrometers to 100 micrometers, and the intermixed barrier layer comprises an electrically insulating material, mutually The thickness of the mixed barrier layer is in the range of 50 nm to 5,000 nm; the collector layer is deposited on the intermixed barrier layer and the collector layer is patterned; and the cathode layer is deposited on the patterned collector layer to form a stack On a thin substrate; and annealing the stack at a temperature in the range of 500 ° C to 800 ° C; wherein the intermixed barrier layer avoids intermixing of the patterned collector layer and the cathode layer.

According to some embodiments, an apparatus for manufacturing a thin film battery may include: a first system for depositing an intermixed barrier layer on a thin substrate, the thin substrate having a substrate thickness in a range of 10 micrometers to 100 micrometers, and a mutually miscible barrier layer Including an electrically insulating material, the thickness of the intermixed barrier layer is in the range of 50 nm to 5,000 nm; the second system is for depositing a collector layer on the intermixed barrier layer and patterning the collector layer; And for depositing a cathode layer on the patterned collector layer to form a stack on the thin substrate; and a fourth system for annealing the stack at a temperature in the range of 500 ° C to 800 ° C; wherein the intermixed barrier layer The intermixing of the patterned collector layer and the cathode layer is avoided.

The disclosure will be described in detail with reference to the drawings, and the accompanying claims It is noted that the following figures and examples are not intended to limit the scope of the disclosure to a single embodiment, and that other embodiments may be derived by exchanging some or all of the elements described or depicted. Furthermore, while some or all of the elements of the present disclosure may be utilized in part or in whole, only those portions of the above-described conventional components that are essential to the present disclosure will be described, and other portions of the above-described conventional components will be omitted. A detailed description of the content is not obscured. In the present specification, an embodiment showing a single component is not to be considered as limiting; rather, the disclosure is intended to include other embodiments including a plurality of identical components, and vice versa, unless otherwise explicitly recited herein. Furthermore, the Applicant does not intend to attribute any words in the specification or the scope of the claims to the rare or special meaning unless explicitly stated as described above. In addition, the present disclosure includes both current and future equivalents of the conventional components described herein.

1 shows an example of a TFB device 100 in accordance with certain embodiments, including: a substrate 110 (eg, YSZ ceramic having 2 to 8 weight percent cerium oxide and other trace impurities), a miscible barrier layer covering the top surface of the substrate 120. An adhesive layer 130 (eg, Ti) on the top surface of the intermixed barrier layer and a cathode current collector (CCC) 140 (such as Au, Pt), a cathode 150 (eg, an LCO layer) on the CCC, and a cathode and a portion. CCC and isolates the electrolyte 160 of the CCC from any other electrode, the partial top surface of the electrolyte and the anode 170 (eg Li) on the anode current collector (ACC) 180 (eg Au) and the exposed surface and part of the current collector covering the anode and electrolyte Packaging layer 190. It is worth noting that the adhesion layer 130 may be provided between the intermixed barrier layer and the ACC if desired, but is not required in all embodiments.

An example of the TFB device of Figure 1 is described in more detail below. The TFB of Figure 1 will be fabricated using a shadow mask and will be described below in this manner, but those skilled in the art will appreciate that maskless fabrication processes can be utilized to fabricate TFBs having the same material and layer order in the device stack. And only a slightly different configuration. A thin substrate, such as a glass, ceramic, metal or tantalum substrate, can have a thickness in the range of 10 microns to 700 microns. The layer deposited on the substrate is then described. The intermixed barrier layer deposited on the surface of the thin substrate may include Al ₂ O ₃ , Si ₃ N ₄ and other electrically insulating layers (including suboxides, stoichiometric and non-stoichiometric variations, and crystalline, amorphous and One or more of the mixed phase forms, and having a thickness in the range of 50 nm to 5000 nm, and in some embodiments a thickness in the range of 50 nm to 500 nm, and in some embodiments, thickness In the range of 100 nm to 300 nm. An adhesive metal layer (such as Ti, Ta, TaN) having an area larger than the area of the cathode layer and having a thickness ranging from 10 nm to 1000 nm is deposited on the substrate barrier layer. A cathode current collector (such as Au, Pt) having the same area as the adhesive layer and having a thickness ranging from 50 nm to 1000 nm is deposited on top of the adhesive layer. A cathode layer (e.g., LiCoO ₂ ) having a thickness ranging from 0.5 μm to 40 μm is deposited on top of the cathode current collector layer. The stack may be heat treated as needed to anneal the cathode layer prior to further deposition steps. A solid electrolyte layer (e.g., LiPON) having an area greater than and extending beyond the cathode and cathode current collectors (except for the electrical contact regions, where CCC is not covered) and having a thickness ranging from 0.5 microns to 4 microns is deposited on top of the interlayer. An anode current collector (such as Cu, Au, Pt) that does not overlap with the cathode layer and the cathode current collector and has a thickness ranging from 100 nm to 1000 nm is deposited on top of the solid electrolyte; in addition, if necessary, similar to An adhesive metal layer is deposited prior to the anode current collector in a manner that is in the cathode current collector layer. An anode (e.g., Li metal) having an area larger than the area of the cathode and smaller than the area of the electrolyte layer, ranging from 1 micrometer to 15 micrometers and partially overlapping the anode current collector layer is deposited on the electrolyte and a portion of the ACC. Different functional packaging layers having an area larger than the area of the anode layer and smaller than the area of the electrolyte layer and having a thickness ranging from 400 nm to 3 μm are deposited on top of the anode layer; the packaging layer may be a metal layer (such as Cu, Au, Pt) In combination with a dielectric layer such as LiPON, Al ₂ O ₃ , ZrO ₂ , SiO ₂ , Si ₃ N ₄ , a planarized polymer layer, and the like.

As described in more detail below, the intermixed barrier layer of FIG. 1 is incorporated into the device stack of the embodiment to overcome the adhesion and collector layers and LCO cathodes found in devices without intermixed barrier layers. The problem caused by the intermixing. It is speculated that the root cause of intermixing during LCO annealing is that thin flexible substrate sheets (eg, YSZ ceramics) having a thickness ranging from 10 microns to 100 microns and in some embodiments from 20 microns to 40 microns have a rougher surface (phase) This may result in a coarser surface than the smoother glass and mica substrate (the surface roughness characteristic is Rms = 32.2 nm measured on a 5 micron x 5 micron area in the first example, and in the second example) Rms = 28.5 nm measured over a 5 μm x 5 μm area, where Rms is the root mean square surface roughness measured by calculating the root mean square of the surface peaks and valleys), more porous, and variable The thickness of the current collector layer is built on top of the thin flexible substrate sheet, that is, the "valley" of the rougher surface has a smaller thickness. Further, the Zr ion packing density in the ZrO ₂ unit cell having a fluorite structure was 58.8%, which represents a porous barrier structure. Therefore, during the deposition of a cathode (eg, LiCoO ₂ ) by PVD sputtering, there may be plasma damage on the porous and thinner regions of the CCC film, which causes the LiCoO ₂ layer to initially infiltrate the CCC and the intermixing of the LCO and the CCC material. It is expected that the above conditions will further deteriorate during the high temperature annealing process after deposition of the cathode material, thus leading to the discovery of mutual mixing.

In view of the above hypothesis, the present disclosure provides for modifying a substrate surface by adding a layer having a high ion packing density, which layer can produce a smoother surface and/or a less porous layer on which smooth and dense CCC can be formed. The layer (CCC with a smooth surface and/or less hole layer) exhibits better adhesion properties (bidirectional) between the substrate and the CCC. This article "bidirectional" is used to mean adhesion promotion occurs in two interfaces, the substrate/intermixing barrier layer interface and the intermixed barrier/metal adhesion layer interface. Moreover, in an embodiment, a miscible barrier layer can be used to limit atom/ion interdiffusion between the substrate and the CCC layer.

In an embodiment, a thin, dense, and electrically insulating (eg, having an impedance greater than 30 MΩ) a miscible barrier layer (eg, Al ₂ O ₃ having an ion packing density of 65.6%) is deposited on the substrate and the adhesion layer and Between the collector layers. Deposition of a 200 nm thick aluminum oxide film reduces the surface roughness of the YSZ substrate. In the first example, Rms = 32.2 nm from an area of 5 μm x 5 μm is reduced to Rms = 5 μm x 5 μm area. 28.2, and in the second example, Rms = 28.5 nm over an area of 5 microns x 5 microns was reduced to Rms = 26.6 over an area of 5 microns x 5 microns. For example, optimized alumina film deposition can be achieved by using physical vapor deposition (PVD) in a higher region power density (eg, greater than 3.5 W/cm ² ) in an argon/oxygen plasma environment. Smooth surfaces and/or fewer holes to avoid intermixing. The composition is expected to be divided into AlO _x (alumina in which x is in the range of 1.2 to 1.5 may have desirable properties for certain embodiments. The intermixed barrier layer may be Al ₂ O ₃ , Si ₃ N ₄ and other electrical insulation Layers (including suboxides, stoichiometric and non-stoichiometric variations, and crystalline, amorphous, and mixed phase forms) have higher cations than Zr ions in ZrO ₂ cells of YSZ substrates at temperatures above 700 °C Packaging density and higher stability (eg, maintaining mechanical strength, stable chemical composition). The thickness of the intermixed barrier layer is in the range of 50 nm to 5000 nm, in some embodiments the intermixed barrier layer The thickness is in the range of 50 nanometers to 500 nanometers, and in some embodiments the thickness of the intermixed barrier layer is in the range of 100 nanometers to 300 nanometers.

Furthermore, even though the intermixed barrier layer has been shown to be effective in preventing intermixing of the CCC and the cathode layer, it should be noted that the substrate barrier layer is effective to prevent intermixing of all layers in the TFB stack.

Although a PVD (physical vapor deposition) sputtering interlayer is used to demonstrate an intermixed barrier layer, it is contemplated that the concept remains agnostic to the deposition mode, for example, the deposition technique of the interlayer can provide any desired component. , phase and crystallinity deposition techniques, and may include, for example, PVD, reactive sputtering, non-reactive sputtering, RF (radio frequency) sputtering, multi-frequency sputtering, evaporation, CVD (chemical vapor deposition), ALD (Atomic layer deposition) and other deposition techniques. The deposition method can also be a non-vacuum based form such as plasma spray, spray pyrolysis, slot die coating, screen printing, and the like.

In order to show the efficacy of the intermixed barrier layer, the following experiment was performed. As a control, the underlying stack was fabricated: an adhesion layer/CCC (Ti/Au) and an LCO layer were deposited on the YSZ substrate (the substrate did not have a miscible barrier layer). The stack was annealed at 650 ° C, and the intermixing of the LCO and CCC layers was observed through the transparent substrate (the darkening of the stack was clearly observed). A second stack was fabricated: an adhesion/CCC (Ti/Au) and LCO layer on a YSZ substrate coated with an alumina intermixed barrier layer. The stack was annealed at 650 ° C, but no intermixing of the LCO and CCC layers was observed through the transparent substrate (no signs of discoloration or delamination of the layers). The YSZ substrate with the alumina intermixed barrier layer does not show discoloration, whereas the YSZ substrate without the intermixed barrier layer does show discoloration (the gold of the CCC is severely interrupted by the black (LCO) material), which shows that the alumina is mixed. The barrier layer serves to avoid the effectiveness of intermixing of several layers of the stack deposited on the surface of the YSZ substrate. The addition of an alumina intermixed barrier layer on the YSZ substrate effectively avoids intermixing of the LCO cathode material with the gold current collector during LCO cathode annealing, and thus maintains (1) layer integrity with little or no intermixing. (2) Good electrical conductivity of the CCC layer, (3) robustness of the device structure, and (4) phase/effective mass/compositional integrity of the cathode layer. Furthermore, even though the intermixed barrier layer has been shown to be effective in preventing intermixing of the CCC and the cathode layer, it should be noted that the intermixed barrier layer is effective to prevent intermixing of all layers in the TFB stack.

Although embodiments of the present disclosure have been described with particular reference to planar TFBs (ACCs and CCCs having the same plane), the theory and teachings of the present disclosure can be applied to other TFB configurations, including vertical stack configurations, where ACC and CCC Parallel but on opposite sides of the stack.

2 is a schematic diagram of a processing system 500 for fabricating a TFB in accordance with certain embodiments. Processing system 500 includes a standard mechanical interface (SMIF) 501 for a cluster tool 502 having a reactive plasma cleaning (RPC) chamber 503 and processing chambers C1 - C4 (504, 505, 506, and 507) mounted thereon. Chambers C1 - C4 can be used in the above processing steps. A glove box 508 can also be attached to the cluster tool. The glove box can store the substrate in an inert environment (eg, in an inert gas such as He, Ne, or Ar), which is useful after alkali metal/alkaline earth metal deposition. If desired, an ante chamber 509 can also be used for the glove box. The preparatory chamber is a gas exchange chamber (inert gas to air or air to inert gas) that allows the substrate to be transported into and out of the glove box without contaminating the glove. An inert environment in the box. (Note that when used by a lithium foil manufacturer, the glove box may be replaced by a dry room environment with a sufficiently low dew point.) Chambers C1 - C4 may be provided with processing steps for manufacturing TFB, for example, the above processing steps include: The deposited alumina intermixed barrier layer is on the YSZ substrate, and the CCC is on the intermixed barrier layer, followed by the LCO cathode. Examples of suitable cluster tool platforms include display cluster tools. It will be appreciated that while a cluster configuration of a processing system 500 has been shown, a linear system can be utilized in which the processing chamber is configured without a linear configuration of the transfer chamber such that the substrate continues to move from one chamber to the next. .

FIG. 3 shows a schematic diagram of an inline manufacturing system 600 having a plurality of inline tools 601 through 699 (including tools 630, 640, 650) in accordance with certain embodiments. The inline tool can include tools for depositing all layers of the TFB. Further, the in-line tool can include a pre-conditioning chamber and a rear adjustment chamber. For example, the tool 601 can be a evacuation chamber for establishing a vacuum before the substrate moves through the vacuum gas lock 602 into the deposition tool. Some or all of the on-line tools can be vacuum tools separated by vacuum air locks. It is noted that the order of the processing tools and the particular processing tools in the processing line will be determined by the particular TFB manufacturing method of the application, for example, as mentioned in the processing flow described above. Furthermore, the substrate can be moved through a manufacturing system that points to a horizontal or vertical line.

In order to depict the movement of the substrate through, for example, the in-line manufacturing system shown in FIG. 3, a substrate conveyor 701 having only one in-line tool 630 in place is shown in FIG. As shown, a substrate holder 702 (a partially cut substrate holder is shown to view the substrate) including a substrate 703 is mounted on a conveyor 701 or equivalent to move the holder and substrate through the wire tool 630. In some embodiments, the on-line platform of the processing tool 630 can be configured for a vertical substrate, while in some embodiments, the on-line platform of the processing tool 630 can be configured for a horizontal substrate.

Some examples of devices for making TFBs in accordance with certain embodiments are as follows. A first apparatus for fabricating a TFB according to some embodiments may include: a first system for depositing an intermixed barrier layer on a thin substrate having a substrate thickness in a range of 10 micrometers to 100 micrometers, and at some In some embodiments, the thin substrate has a substrate thickness in the range of 20 micrometers to 40 micrometers; the second system is configured to deposit a collector layer on the intermixed barrier layer and to pattern the collector layer to form CCC and ACC; A third system for depositing a cathode layer (eg, an LCO layer) on the CCC layer to form a stack on the substrate; and a fourth system for annealing the stack; wherein the intermixed barrier layer avoids intermixing of the CCC and the cathode layer. Moreover, in some embodiments, the apparatus may further include: a fifth system for depositing an electrolyte layer on the annealed cathode layer; and a sixth system for depositing an anode layer on the electrolyte layer to form a second stack And a seventh system for depositing a packaging layer covering the second stack. The apparatus can also include a system for patterning a plurality of layers, and in some embodiments, a shadow mask can be used in one or more of the deposition systems described above. The system can be a cluster tool, an online tool, a standalone tool, or a combination of one or more of the above. Moreover, the system can include certain tools that are identical to one or more of the other systems.

Moreover, the second apparatus for fabricating a TFB according to some embodiments may include: a first system for depositing a cross-mixing barrier layer on a thin substrate having a substrate thickness in a range of 10 micrometers to 100 micrometers, And in some embodiments, the thin substrate has a substrate thickness in the range of 20 microns to 40 microns; the second system is used to deposit the CCC layer on the intermixed barrier layer; and the third system is used to deposit the cathode layer (eg The LCO layer is formed on the CCC layer to be stacked on the substrate; and the fourth system is used to anneal the stack; wherein the intermixed barrier layer avoids intermixing of the CCC and the cathode layer. Furthermore, in some embodiments, the apparatus may further include: a fifth system for depositing an electrolyte layer on the annealed cathode layer; a sixth system for depositing the anode layer on the electrolyte layer; For depositing ACC on the anode layer to form a second stack on the substrate; and an eighth system for depositing the packaging layer to cover the second stack. The apparatus can also include a system for patterning a plurality of layers, and in some embodiments, a shadow mask can be used in one or more of the deposition systems described above. The system can be a cluster tool, an online tool, a standalone tool, or a combination of one or more of the above. Moreover, the system can include certain tools that are identical to one or more of the other systems.

Although embodiments of the present disclosure have been described with particular reference to a TFB having an LCO cathode, the theory and teachings of the present disclosure can be applied to TFBs having other cathode materials, including LiMO ₂ (M=Co, Ni). , Mn, etc.). Among them, for example, LiMnO ₂ and LiFePO ₄ may be annealed at a temperature in the range of 500 ° C to 800 ° C for a holding time in the range of 4 to 15 hours, and in some embodiments, an annealing period of 2 to 30 hours The holding time in the middle depends on the thickness of the layer to be annealed.

Although embodiments of the present disclosure have been described with particular reference to TFBs, the teachings and teachings of the present disclosure can be applied to other electrochemical devices, including conventional energy storage devices, and also include electrochromic devices.

Although embodiments of the present disclosure have been described with particular reference to a one-sided TFB, the theory and teachings of the present disclosure can be applied to a two-sided TFB.

Although the embodiments of the present disclosure have been described with particular reference to certain embodiments of the present disclosure, those skilled in the art should readily understand that changes in form and detail may be made without departing from the spirit and scope of the disclosure. Modification.

100‧‧‧TFB device
110, 703‧‧‧ substrate
120‧‧‧Intermixed barrier layer
130‧‧‧Adhesive layer
140‧‧‧Cathode Collector
150‧‧‧ cathode
160‧‧‧ Electrolytes
170‧‧‧Anode
180‧‧‧Anode collector
190‧‧‧Package
500‧‧‧Processing system
501‧‧‧ standard mechanical interface
502‧‧‧ Cluster Tools
503‧‧‧Reactive plasma cleaning chamber
504, 505, 506, 507‧‧ ‧ processing chamber
508‧‧‧Gift box
509‧‧‧Preparation chamber
600‧‧‧Online Manufacturing System
601, 630, 640, 650, 699‧‧‧ online tools
602‧‧‧Vacuum air lock
701‧‧‧Substrate conveyor
702‧‧‧Substrate holder

These and other aspects and features of the present disclosure will become apparent to those skilled in the art of the <RTIgt;

1 is a cross-sectional view of a thin film battery including a miscible barrier layer between a substrate and an adhesive layer and a current collector layer, in accordance with certain embodiments;

2 is a schematic diagram of a cluster tool for TFB manufacturing in accordance with certain embodiments;

Figure 3 is a drawing of a TFB manufacturing system having a plurality of in-line tools in accordance with certain embodiments; and

Figure 4 is a diagram of an inline tool in accordance with Figure 3 of some embodiments.

Domestic deposit information (please note according to the order of the depository, date, number)

Foreign deposit information (please note in the order of country, organization, date, number)

(Please change the page separately) No

100‧‧‧TFB device

110‧‧‧Substrate

120‧‧‧Intermixed barrier layer

130‧‧‧Adhesive layer

140‧‧‧Cathode Collector

150‧‧‧ cathode

160‧‧‧ Electrolytes

170‧‧‧Anode

180‧‧‧Anode collector

190‧‧‧Package

Claims (20)

A thin film battery (TFB) comprising: an intermixed barrier layer on a thin substrate having a substrate thickness ranging from 10 micrometers to 100 micrometers, the intermixed barrier layer comprising an electrically insulating material, The intermixed barrier layer has a thickness in the range of 50 nm to 5,000 nm; a patterned collector layer on the intermixed barrier layer; and a cathode layer on the patterned collector layer, Wherein the intermixed barrier layer, the patterned collector layer and the cathode layer are stacked on the thin substrate, and the cathode layer has been annealed at a temperature in the range of 500 ° C to 800 ° C for 2 to 30 hours. One of the temperature holding time; wherein the intermixed barrier layer avoids intermixing of the current collector layer and the cathode layer during the annealing of the cathode layer. The TFB of claim 1, wherein a thickness of the thin substrate is in the range of 20 micrometers to 40 micrometers. The TFB of claim 1, wherein the intermixed barrier layer has a higher cationic packing density than the thin substrate. The TFB of claim 1, wherein the thin substrate is a yttria-stabilized zirconia substrate. The TFB of claim 4, wherein the thin substrate has a root mean square surface roughness greater than about 28 nm. The TFB of claim 1, wherein the cathode layer is an LCO layer having greater than 90% by volume of high temperature phase lithium cobalt oxide (LCO). The TFB of claim 1, wherein the thickness of the intermixed barrier layer is in the range of 100 nm to 300 nm. The TFB of claim 1, wherein the intermixed barrier layer is an aluminum oxide layer. A method of fabricating a plurality of thin film batteries, comprising: depositing an intermixed barrier layer on a thin substrate having a substrate thickness ranging from 10 micrometers to 100 micrometers, the intermixed barrier layer comprising an electrical insulation a thickness of the intermixed barrier layer in the range of 50 nm to 5,000 nm; depositing a current collector layer on the intermixed barrier layer and patterning the collector layer; depositing a cathode layer on the via Patterning the current collector layer to form a stack on the thin substrate; and annealing the stack at a temperature ranging from 500 ° C to 800 ° C; wherein the intermixed barrier layer avoids the patterned collector layer Intermixing with the cathode layer. The method of claim 9, wherein a thickness of the thin substrate is in the range of 20 micrometers to 40 micrometers. The method of claim 9, wherein the intermixed barrier layer has a higher cationic packing density than the thin substrate. The method of claim 9, wherein the thin substrate is a yttria-stabilized zirconia substrate. The method of claim 12, wherein the thin substrate has a root mean square surface roughness greater than about 28 nm. The method of claim 9, wherein the cathode layer is an LCO layer having a high temperature phase lithium cobalt oxide (LCO) of greater than 90% by volume after the annealing step. The method of claim 14, wherein the annealing step lasts for a period of time ranging from 4 to 15 hours. The method of claim 9, wherein a thickness of the intermixed barrier layer is in the range of 100 nm to 300 nm. The method of claim 9, wherein the intermixed barrier layer is an aluminum oxide layer. The method of claim 17, wherein the aluminum oxide layer is deposited by a physical vapor deposition in an argon/oxygen plasma environment and at a level greater than 3.5 W/cm ² Under regional power density. An apparatus for manufacturing a plurality of thin film batteries, comprising: a first system for depositing an intermixed barrier layer on a thin substrate, wherein a thickness of a substrate of the thin substrate is in a range of 10 micrometers to 100 micrometers, the mutual mixing The barrier layer comprises an electrically insulating material, the intermixed barrier layer has a thickness in the range of 50 nm to 5,000 nm; and a second system for depositing a collector layer on the intermixed barrier layer and Patterning the current collector layer; a third system for depositing a cathode layer on the patterned collector layer to form a stack on the thin substrate; and a fourth system for operating at 500 ° C The stack is annealed at a temperature in the range of 800 ° C; wherein the intermixed barrier layer avoids intermixing of the patterned collector layer with the cathode layer. The apparatus of claim 19, wherein the first system comprises a physical vapor deposition tool for depositing an oxidation in an argon/oxygen plasma environment at a power density greater than 3.5 W/cm ² Aluminum intermixed barrier layer.