TW201724594A - Spin hall effect MRAM with thin-film selector - Google Patents

Abstract

A one-transistor (1T), one-selector (1S), one magnetic tunnel junction (1MTJ), spin torque transfer (STT), spin Hall effect (SHE), magnetic random access memory (MRAM) may be configured to provide separate write current and read current paths. In such a configuration, the write current may pass through a SHE electrode disposed proximate the MTJ device. The direction of write current flow through the SHE electrode determines spin polarization of the write current, the magnetic field orientation of a free magnetic layer in the MTJ device, and consequently the resistance of the MTJ device. The write current can be at a level sufficient to cause the reliable storage of binary information in the MTJ device. The read current, at a lower level than the write current, passes through the MTJ.

Description

Spin Hall effect magnetoresistive random access memory with thin film selector

The present invention is directed to a magnetoresistive random access memory (MRAM).

Magnetoresistive random access memory (MRAM) uses magnetic storage elements instead of electronic charge or current to store data. A magnetic tunnel junction (MTJ) can be used as a magnetic storage element. The MTJ is formed in a thin, insulating, tunneling barrier between two ferromagnetic plates, each of which maintains a separate magnetization. One of the plates in the MTJ (fixed magnetic layer) is a permanent magnet set to a specific polarity, and the magnetic field generated by the second plate in the MTJ (free magnetic layer) can be changed so that the polarity of the second plate matches The polarity of a plate (parallel) or the polarity of the second plate is opposite to the polarity of the first plate (anti-parallel). Due to the relative orientation of the magnetic fields generated by the free and fixed magnetic plates, the change in resistance of the MTJ is caused by separating the magnetic tunnel layers of the tunnel layers that free and fix the magnetic layer.

A typical MTJ device used in the STT-MRAM bit cell includes a series coupling with a control device such as a transistor (ie, 1T-1MTJ bit cell) Combined MTJ. The series MTJ and the transistor are connected between the bit line and the source line. The read path and write path of the STT-MRAM device are the same and require design compromise. This compromise is usually evidenced by the resistance of the MTJ - typically, a higher resistance during a read operation and a lower resistance during a write operation (reducing the current consumption required to change the state of the bit cell) is preferred. However, due to the common path of read and write operations, the difference in resistance between read and write operations is not allowed.

The 1T-1MTJ bit cell thus has several significant disadvantages. First, large write currents (eg, over 100 microamps, μA) and higher voltages (eg, over 0.7 volts, V) may be required to change the alignment of the free magnetic layer in the MTJ and thus successfully completed Write operation of the MTJ device. Many MTJs cannot handle this large current on a regular basis, and thus the write current can be limited to lower values, which provides a satisfactory service life for the MTJ. However, the need to limit current during write operations can result in unacceptably high error rates and/or low speed switching (eg, greater than 20 nanoseconds) in the MTJ base MRAM. Moreover, even at low current values, the presence of tunnel paths within the MTJ can lead to reliability issues in the MTJ.

100‧‧‧Magnetoresistive random access memory location cells

110‧‧‧Magnetic tunnel junction device

112‧‧‧ free magnetic layer

114‧‧‧Fixed magnetic layer

116‧‧‧Oxide

122‧‧‧钌

124‧‧‧cobalt/iron

126‧‧‧anti-magnetic layer

130‧‧‧ Spin Hall Effect (SHE) Electrode

132‧‧‧First end

134‧‧‧second end

140‧‧‧ source line

142‧‧‧Read bit line

144‧‧‧Write bit line

146‧‧‧ word line

150‧‧‧First transistor

152‧‧‧Diffusion area

154‧‧‧Electrical structure

155‧‧‧ gate

156‧‧‧Diffusion area

158‧‧‧Electrical structure

160‧‧‧Film Selector

100A‧‧‧ cell "A"

100A‧‧‧Rotational moment transfer (STT), spin Hall effect (SHE) magnetic Resistive random access memory (MRAM) device

100B‧‧‧ cell "B"

100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K, 100L, 100M, 100N, 100O, 100P‧‧‧ spin torque transfer (STT), spin Hall effect (SHE) magnetic Resistive random access memory (MRAM) device

140A‧‧‧Source line 0 (M0)

140B‧‧‧Source Line 1 (M0)

140C‧‧‧Source Line 2 (M0)

140D‧‧‧Source Line 3 (M0)

142A‧‧‧Read bit line 0 (M4)

142B‧‧‧Read bit line 1 (M4)

142C‧‧‧Read bit line 2 (M4)

142D‧‧‧Read bit line 3 (M4)

144A‧‧‧Write bit line (M0)

144B‧‧‧Write bit line 1 (M0)

144C‧‧‧Write bit line 2 (M0)

144D‧‧‧Write bit line 3 (M0)

146A‧‧‧Word line 0

146B‧‧‧Word line 1

200‧‧‧Executive Magnetic Tunnel Junction (MTJ) device

202‧‧‧ central part

204‧‧‧ copper

206‧‧‧ copper

220‧‧‧Write current

230‧‧‧Read current

300‧‧‧Executive magnetic tunnel junction device

302‧‧‧ length

304‧‧‧Width

400‧‧‧Executive Spin Hall Effect (SHE) Electrode

402‧‧‧Upper spin current

404‧‧‧ under spin current

410‧‧‧Charge current

412‧‧‧Charge current

500‧‧‧1 O crystal (1T), a selector (1S), spin Hall effect (SHE), spin torque transfer (STT) magnetoresistive random access memory during read operation ( MRAM)

502‧‧‧Read current

510‧‧‧Write current

512‧‧‧First direction

520‧‧‧Write current

522‧‧‧second direction

600‧‧‧write operation

602‧‧‧Read current

610‧‧‧Write current

612‧‧‧First direction

620‧‧‧Write current

622‧‧‧second direction

700‧‧‧Array

800‧‧‧Configuration

810‧‧‧1.5 times the gate spacing

820‧‧‧2.5 times M0 spacing

900‧‧‧Configuration

910‧‧‧1.5 times gate spacing

920‧‧‧3.5 times M0 spacing

1300‧‧‧Process-based environment

1302‧‧‧Processor-based devices

1304‧‧‧Storage device

1312‧‧‧Processing Circuit

1314‧‧‧System Memory

1316‧‧‧Communication chain

1318‧‧‧Reading memory

1320‧‧‧ random access memory

1322‧‧‧Basic input and output system

1324‧‧‧Disk drive

1328‧‧‧Optical storage

1330‧‧‧Magnetic storage

1332‧‧‧Atomic or Quantum Storage

1336‧‧‧ operating system

1338‧‧‧Application

1340‧‧‧Other modules

1342‧‧‧ data

1344‧‧‧Browser

1360‧‧‧Network interface

1370‧‧‧Physical input device

1372‧‧‧ keyboard

1374‧‧‧Touch screen

1376‧‧‧ audio

1378‧‧‧ pointing device

1380‧‧‧ physical output device

1382‧‧ Vision

1384‧‧‧Touch

1386‧‧‧ audio

The features and advantages of the various embodiments of the invention will be apparent from the following detailed description. 1 is an illustration of at least one embodiment of the present disclosure. A transistor (1T), a selector (1S), a section of the STT-MRAM cell using a spin Hall effect (SHE) electrode to change the resistance of the magnetic tunnel junction (MTJ); A perspective view of an exemplary magnetic tunnel junction (MTJ) device having a free magnetic layer disposed adjacent to a spin Hall effect (SHE) electrode in accordance with at least one embodiment of the present disclosure. 3 is a top plan view of an exemplary magnetic tunnel junction (MTJ) device having a free magnetic layer disposed adjacent to a spin Hall effect (SHE) electrode, in accordance with at least one embodiment of the present disclosure; FIG. An enlarged cross-sectional view of an exemplary spin Hall effect (SHE) electrode in accordance with at least one embodiment of the present disclosure, in which the passage of current produces an upper rotation mode and a lower rotation mode within various SHE electrodes; An exemplary transistor (1T), a selector (1S), a spin Hall effect (SHE), and a spin torque transfer (STT) during a read operation in accordance with at least one embodiment of the present disclosure. a schematic diagram of a magnetoresistive random access memory (MRAM) in which a current is read through the MTJ and the first transistor; FIG. 5B is an example depicted in FIG. 5A in accordance with at least one embodiment of the present disclosure. Transistor (1T), a selector (1S) spin torque transfer (STT), spin Hall effect (SHE), magnetoresistive random access memory (MRAM) (1T-1S-1MTJ-STT -SHE-MRAM) a schematic diagram during a write operation in which a write current flows through the first transistor, SHE Electrode, and a thin film selector; 6A is another exemplary transistor (1T), a selector (1S), a spin Hall effect (SHE), self-rotation during a read operation, in accordance with at least one embodiment of the present disclosure. A schematic diagram of a moment transfer (STT) magnetoresistive random access memory (MRAM) in which a current is read through an MTJ and a first transistor; FIG. 6B is a diagram of FIG. 6A in accordance with at least one embodiment of the present disclosure. Exemplary one transistor (1T), one selector (1S) spin torque transfer (STT), spin Hall effect (SHE), and magnetoresistive random access memory (MRAM) (1T-1S) -1MTJ-STT-SHE-MRAM) Schematic diagram during a write operation in which a write current flows through a first transistor, a SHE electrode, and a thin film selector; FIG. 7 is at least one embodiment in accordance with the present disclosure. A top view of an exemplary 4x4 array comprising sixteen 1T-1S-1MTJ-STT-SHE-MRAM bit cells; FIG. 8A is an exemplary 1T-1S-1MTJ-STT in accordance with at least one embodiment of the present disclosure -SHE-MRAM bit cell configuration; Figure 8B is an exemplary 1T-1S-1MTJ-STT-SHE- depicted in Figure 8A in accordance with at least one embodiment of the present disclosure. A cross-sectional view of the MRAM bit cell along section line BB; FIG. 8C is an exemplary 1T-1S-1MTJ-STT-SHE-MRAM bit cell depicted in FIG. 8A in accordance with at least one embodiment of the present disclosure. A cross-sectional view along section line CC; FIG. 9A is a configuration of another exemplary 1T-1S-1MTJ-STT-SHE-MRAM bit cell in accordance with at least one embodiment of the present disclosure; 9B is a cross-sectional view of the exemplary 1T-1S-1MTJ-STT-SHE-MRAM bit cell depicted in FIG. 9A along section line BB in accordance with at least one embodiment of the present disclosure; FIG. 9C is A cross-sectional view of an exemplary 1T-1S-1MTJ-STT-SHE-MRAM bit cell depicted in FIG. 9A along section line CC in accordance with at least one embodiment of the present disclosure; FIG. 10A is a disclosure in accordance with the present invention. At least one embodiment depicts a diagram of an exemplary, recursive, and thin film selector used in an exemplary 1T-1S-1MTJ-STT-SHE-MRAM cell; FIG. 10B is a disclosure in accordance with the present invention. At least one embodiment depicts a diagram of an exemplary thin film selector used in an exemplary 1T-1S-1MTJ-STT-SHE-MRAM bit cell; FIG. 11 is an at least one implementation in accordance with the present disclosure. A high-level flowchart of a method for providing an exemplary 1T-1S-1MTJ-STT-SHE-MRAM bit cell; FIG. 12 is a diagram of stored digital data in an exemplary 1T-1S- according to at least one embodiment of the present disclosure. a high-level flowchart of a method of 1MTJ-STT-SHE-MRAM bit cell; FIG. 13 is a diagram of at least one embodiment according to the present disclosure Example high block diagram of processor-based devices, non-transitory data providing at least a portion of an exemplary embodiment wherein a 1T-1S-1MTJ-STT-SHE-MRAM bit cell.

While the following detailed description is described with reference to the exemplary embodiments, many alternatives, modifications and It is obvious.

SUMMARY OF THE INVENTION AND EMBODIMENTS

Spin Torque Transfer (STT) uses rotational alignment electrons in a spin Hall effect material adjacent to the free magnetic layer of the MTJ to change the magnetic orientation or alignment of the free magnetic layer. For example, current flowing through a metal layer with large spin-orbital coupling can produce a spin current through the MTJ (via the large spin Hall effect) sufficient to cause realignment or reorientation of the free magnetic field in the MTJ device. The spin Hall effect is a phenomenon occurring in a metal having a large atomic weight in which electrodes having different spins are deflected in different lateral directions. Thus, the applied charge current produces a spin angular momentum flow transverse to the charge flow. In addition, the direction of the electrode in the material is changed by the direction of the current of the spin Hall effect material - thus, the spin Hall effect electrode placed adjacent to the MTJ can pass through the spin Hall effect material, simply in the direction of the current Change or change the resistance of the MTJ base.

A transistor (1T), a selector (1S), a magnetic tunnel junction (1MTJ), spin torque transfer (STT), spin Hall effect (SHE), magnetoresistive random access memory ( The MRAM) bit cell (hereinafter abbreviated as: 1T-1S-1MTJ-STT-SHE MRAM) includes an MTJ device having a free magnetic layer disposed adjacent to the SHE electrode. The polarity or magnetic direction of the MTJ free magnetic layer can be altered by passing a directional current through the SHE electrode. When current flows through the SHE electrode in the first direction, the spin polarization of the current flowing through the SHE electrode causes parallel alignment of the magnetic fields in the MTJ free magnetic layer and the MTJ fixed magnetic layer. In a parallel configuration, The MTJ device presents a relatively low resistance path for current flowing through the MTJ device. When the current flows through the SHE electrode in a second direction opposite the first direction, the spin polarization of the current flowing through the SHE electrode causes an anti-parallel alignment of the magnetic fields in the MTJ free magnetic layer and the MTJ fixed magnetic layer. In an anti-parallel configuration, the MTJ device presents a relatively high resistance path for current flowing through the MTJ.

The resistance presented by the MTJ allows for non-volatile storage of binary data (eg, low resistance may indicate a first logic state and high resistance may indicate a second logic state). Advantageously, due to the cooperative coupling between the SHE electrode to the MTJ free magnetic layer (ie, spin torque transfer), the direction of the MTJ free magnetic layer is altered by current flow through the SHE electrode rather than the MTJ itself. It may allow for significantly higher write current branch usage, which advantageously provides for faster cycling or timing of MRAM bit cells while advantageously reducing the error rate within the MRAM bit cell at the same time.

The 1T-1S-1MTJ-STT-SHE MRAM bit cell uses the Giant Spin Hall Effect (GSHE) to improve high spin injection efficiency and provides relatively robust and reliable but tight random access memory. Since the write current does not pass through the SHE electrode through the MTJ, the GSHE achieves the use of a low program voltage or, alternatively, achieves a higher current at the same voltage. The 1T-1S-1MTJ-STT-SHE MRAM bit cell is characterized by a low error rate at relatively fast (eg, <10 nanoseconds) write speed. The read and write paths within the 1T-1S-1MTJ-STT-SHE MRAM bit cells are advantageously coupled to improve read latency. The 1T-1S-1MTJ-STT-SHE MRAM bit cell is further characterized as having a low resistance write operation, which allows for a larger The current is written and the MTJ is quickly changed state. The separate read and write paths within the 1T-1S-1MTJ-STT-SHE MRAM bit cell allow for the use of lower read currents (eg, 10μA read current vs. 100μA write current), which improves MTJ The performance and reliability of the device.

A transistor (1T), a selector (1S), a magnetic tunnel junction (1MTJ), spin torque transfer (STT), spin Hall effect (SHE) magnetoresistive random access memory (MRAM) ) The device is provided. The apparatus can include a spin Hall effect (SHE) electrode and a first transistor electrically coupled between the SHE electrode and the source line, the first transistor being controlled by a word line. The apparatus can additionally include a thin film selector electrically coupled between the SHE electrode and the write bit line, and a magnetic tunnel junction (MTJ) device, wherein the MTJ device includes conductive coupling to the first transistor and to film selection The position between the conductive couplings of the device is electrically coupled to the free magnetic layer of the SHE electrode.

A transistor (1T), a selector (1S), a magnetic tunnel junction (1MTJ), spin torque transfer (STT), spin Hall effect (SHE) magnetoresistive random access memory (MRAM) The method is provided. The method can include forming a first transistor having a source region, a drain region, and a gate region. The method can further include forming a source line in the first metal layer and electrically coupling the source region to the source line of the first transistor. The method can also include forming a SHE electrode and electrically coupling the drain region of the first transistor to the SHE electrode. The method can additionally include forming an MTJ device comprising a free magnetic layer and a fixed magnetic layer and electrically coupling the free magnetic layer of the MTJ device to the SHE electrode. The method can be further included in the second metal layer A write bit line is formed and a read bit line is formed. The method can also include forming a thin film selector, and electrically coupling the thin film selector and the write bit line between the SHE electrodes, and conductively coupling the fixed magnetic layer of the MTJ device for reading the bit lines.

A transistor (1T), a selector (1S), a magnetic tunnel junction (1MTJ), spin torque transfer (STT), spin Hall effect (SHE) magnetoresistive random access memory (MRAM) The method is provided. The method can include selectively writing a binary value to the MRAM cell, the MTJ coupled to the SHE electrode by causing the write current to flow through the electrode in any of the following directions: being placed in the first state magnetically coupled to The first direction of the resistance value of the MTJ device of the SHE electrode, or the second direction of the resistance value of the MTJ device magnetically coupled to the SHE electrode in a second state different from the first state.

A transistor (1T), a selector (1S), a magnetic tunnel junction (1MTJ), spin torque transfer (STT), spin Hall effect (SHE) magnetoresistive random access memory (MRAM) The system is provided. The system can include means for selectively writing a binary value to the MRAM cell, the MTJ coupled to the SHE electrode by causing the write current to flow through the electrode in any of the following directions: placed in the first state A first direction of resistance value magnetically coupled to the MTJ device of the SHE electrode, or a second direction of resistance value of the MTJ device magnetically coupled to the SHE electrode in a second state different from the first state.

As used herein, the term "transistor" and the plural term "transistor" may refer to any type having a 汲 terminal, a source terminal, and a gate terminal. A metal oxide semiconductor (MOS) transistor with a large number of terminals. The term "transistor" and the plural term "transistor" may also refer to any other type of current or future developed transistor or transistor (ie, switching) device including, but not limited to, a 场 field effect transistor. (FinFETs), triple gate transistors, wraparound gate column transistors, carbon nanotube devices, and spintronic devices. As described herein, the terms "source" and "drain" refer to the transistor terminals and can thus be freely replaced with each other. The term "transistor" and the plural term "transistors" may also refer to bipolar junction transistors (BJT or BJTs).

1 is an exemplary transistor, a selector, a magnetic tunnel junction, a spin torque transfer, a spin Hall effect, and a magnetoresistive random access memory device according to at least one embodiment of the present invention. A block diagram of the cell 100 (hereinafter referred to as "1T-1S-1MTJ-STT-SHE MRAM cell 100" or "bit cell 100"). The 1T-1S-1MTJ-STT-SHE MRAM bit cell 100 includes a magnetic tunnel junction (MTJ) device 110, a spin Hall effect (SHE) electrode 130, a first transistor 150, and a thin film selector 160.

A plurality of conductive structures 154, such as one or more pillar vias, electrically couple the first diffusion region 152 (eg, the source region) of the first transistor 150 to the source line 140. In some examples, source line 140 can be disposed on a zero metal (M0) layer within the semiconductor die. A plurality of conductive structures 158, such as one or more pillar vias, electrically couple the second diffusion region 156 (eg, the drain region) of the first transistor 150 to the first end 132 of the SHE electrode 130. Word line 146 can be electrically coupled to the first transistor Gate 155 of body 150 and can control the operation and/or logic state of first transistor 150.

Membrane selector 160 is selectively conductively coupled to write bit line 144 to second end 134 of SHE electrode 130. In some examples, the write bit line may be disposed in whole or in part on a second metal (M2) layer within the semiconductor die. The thin film selector 160 allows bidirectional current when a positive or negative voltage difference or bias across the membrane selector 160 reaches a defined threshold.

The free magnetic layer 112 of the MTJ device 110 is electrically coupled to the SHE electrode 130, and the fixed magnetic layer 114 of the MTJ device 110 can be electrically coupled to the read bit line 142, either directly or indirectly. In some embodiments, the read bit line 142 may be disposed in whole or in part on a fourth metal (M4) layer within the semiconductor die. In some embodiments, a synthetic antiferromagnetic (SAF) layer comprising at least one germanium layer 122 and at least one cobalt/iron layer 124 can be disposed adjacent to the MTJ between the fixed magnetic layer 114 and the read bit line 142. The fixed magnetic layer 114 of the device 110. In some embodiments, an antiferromagnetic (AFM) device 126 can be disposed between at least one cobalt/iron layer 124 and the read bit line 142. In an embodiment, the 1T-1S-1MTJ-STT-SHE MRAM bit cell 100 provides a four-terminal device (ie, for each of the following connections: source line 140, read bit line 142, write bit) Yuan line 144, word line 146)

In an embodiment, a spin-polarized write current may pass between the source line 140 and the write bit line 144 for performing a write operation. The potential difference between the source line 140 and the write bit line 144 determines whether the write current is from Source line 140 flows to write bit line 144, or vice versa. The direction in which the write current flows through the SHE electrode 130 determines the direction of the magnetic field of the free magnetic layer 112 in the MTJ device 110, and thus determines the resistance (and logic state) of the MTJ device 110. In an embodiment, the write current flows through the SHE electrode 130 in a first direction, causing the free magnetic layer 112 in the MTJ device 110 to exhibit a magnetic field direction that is substantially parallel to the magnetic field direction of the fixed magnetic layer 114. The magnetic fields of the free magnetic layer 112 and the fixed magnetic layer 114 are arranged in a substantially parallel configuration in which the MTJ device 110 is placed in a relatively high tunneling current/low resistance state. Conversely, the write current flowing through the SHE electrode 130 in the second direction can cause the free magnetic layer 112 in the MTJ device 110 to assume a magnetic field direction that is substantially antiparallel to the magnetic field direction of the fixed magnetic layer 114. The magnetic field of the free magnetic layer 112 and the fixed magnetic layer 114 is arranged in a substantially anti-parallel configuration in which the MTJ device 110 is placed in a relatively low tunneling current/high resistance state.

In an embodiment, the potential difference between the source line 140 and the write bit line 144 can be used for distribution by controlling the direction in which the write current passes and thus writing the current spin polarization in the SHE electrode 130. And storing the binary values in the MTJ device 110. In an embodiment, the write current may be about 30 μA or greater; about 50 μA or greater; about 70 μA or greater; about 100 μA or greater; about 150 μA or greater; about 200 μA or greater. Advantageously, a relatively high write current does not pass through the MTJ device 110, but only through the SHE electrode 130. In addition, the ability to use relatively high write currents improves write speed and data reliability while not compromising MTJ devices used in 1T-1S-1MTJ-STT-SHE MRAM cells 100 110 long-term reliability and performance.

In an embodiment, the read current is passed from the read bit line 142 through the MTJ device 110 to perform a read operation. The resistance of the MTJ device 110 determines the logic value returned by the read operation. The read current may be about 30 μA or less; 25 μA or less; 20 μA or less; 15 μA or less; 10 μA or less; 5 μA or less. Advantageously, the MTJ device 110 only checks for relatively low read currents, rather than substantially higher write currents. The reduction in read current through the MTJ device 110 advantageously improves the long-term reliability and performance of the 1T-1S-1MTJ-STT-SHE MRAM cell 100.

The MTJ device 110 includes a free magnetic layer 112 in which a free magnetic layer is disposed adjacent to or in contact with the SHE electrode 130. In an embodiment, the MTJ device 110 may include any current or future developed MTJ device 110 including, but not limited to, a perpendicular magnetization MTJ device 110 and an in-plane magnetized MTJ device 110. In an embodiment, the free magnetic layer 112 and the fixed magnetic layer 114 of the MTJ device 110 may comprise any current or future developed magnetic material. In at least some embodiments, the free magnetic layer 112 and/or the fixed magnetic layer 114 of the MTJ device 110 can include one or more materials having relatively high spin polarization, such as cobalt (Co), iron (Fe), Or cobalt, iron, boron alloys (Co _a Fe _b B _c - where a, b, and c are integer values). In one embodiment, each of the free magnetic layer 112 and the fixed magnetic layer 114 may include a CoFeB layer that is sputtered as an amorphous thin film layer, which is about 80% CoFe and about 20% B ((CoFe) ₈₀ B ₂₀ ).

One or more tunneling barrier layers 116 separate the free magnetic layer 112 from the fixed magnetic layer 114. In an embodiment, one or more tunneling barrier layers 116 may include one or more metal oxides. Examples of metal oxides include, but are not limited to, titanium oxide (TiO _x ), magnesium oxide (MgO _x ), aluminum oxide (AlO _x ), or combinations thereof. The tunneling barrier layer 116 can be a thickness of a few angstroms to a few nanometers.

The MTJ device 110 can include or otherwise incorporate one or both of a synthetic antiferromagnetic (SAF) layer and/or an antiferromagnetic (AFM) layer. The synthetic antiferromagnetic (SAF) layer may include a ruthenium (Ru) layer 122 deposited adjacent to the fixed magnetic layer 114, and a cobalt/iron (CoFe) layer 124 deposited adjacent to the ruthenium (Ru) layer 122. In an embodiment, the SAF/AFM layer can be coupled to the fixed magnetic layer 114 by an exchange bias and can cause at least a portion of the atoms in the fixed magnetic layer 114 to interact with at least a portion of the atoms in the SAF/AFM layer. Precisely, thereby "pinning" or fixing the magnetic field direction of the magnetic layer 114. Although described as including a tantalum layer 122 and a cobalt/iron layer 124, the SAF layer can include additional or alternative materials that can pin or secure the direction of the magnetic field of the magnetic layer 114. The MTJ device 110 can be electrically coupled to the read bit line 142 through a SAF/AFM layer. Although depicted in FIG. 1, in some embodiments, one or more conductive structures, such as one or more vias, can electrically couple the MTJ device 110 to the read bit line 142.

The SHE electrode 130 may include a giant spin Hall effect (GSHE) metal including, but not limited to, β-钽 (β-Ta), β-tungsten (β-W), platinum (Pt), gold (Au). , silver (Ag), copper (Cu), or a combination or alloy thereof. In some embodiments, the SHE electrode 130 can include one or more dopants, such as iridium (Ir), bismuth (Bi), any one of the elements from 3d, 4d, 5d, 4f, or 5, or a combination thereof. Or alloy.

The MTJ device 110 can be placed on the SHE electrode 130 with optimized dimensions and thickness to achieve high spin injection. The SHE electrode 130 within each bit cell 100 can be placed over the source line 140, and in some embodiments, can be patterned into a zero metal (M0) layer. One or more conductive structures 158, such as one or more pillar vias, are electrically coupled to the first end 132 of the SHE electrode 130 within each bit cell 100 to a second diffusion of the first transistor 150 Area 156. The two terminal film selector 160 can be electrically coupled between the second end 134 of the SHE electrode 130 and the write bit line 144 within the bit cell 100.

The first transistor 150 can include any combination or number of devices or systems capable of controlling the write current between the source line 140 and the first end 132 of the SHE electrode 130. In at least some embodiments, one or more conductive structures 154, such as one or more pillar vias formed or otherwise disposed in a trench (eg, TCN), are communicably coupled to the first transistor A first diffusion region 152 (eg, a source) of 150 is coupled to the source line 140. In an embodiment, one or more conductive structures 158, such as one or more column vias, electrically couple the second diffusion region 152 (eg, the drain) of the first transistor 150 to the first of the SHE electrodes 130. One end portion 132. In an embodiment, word line 146 is conductively coupled to gate 155 of first transistor 150 for controlling the operation of first transistor 150.

The thin film selector 160 can include any combination or number of devices and/or systems capable of controlling the write current between the second end 134 of the SHE electrode 130 and the write bit line 144. In an embodiment, the thin film selector 160 may include, but is not limited to, at least one bidirectional limit switch (OTS), a Mote oxide MIT switch, a hybrid ion electronic conductor switch (MIEC), a high selectivity MIM tunnel switch. Examples of Mott oxide switches are NbO2, Ti2O3, SmNiO3-based MIT switches. An example of a MIEC switch is a Cu-based chalcogenide. An example of a MIM tunnel switch is a TaO _x /TiO2/TaO _x film stack. In an embodiment, the membrane selector 160 is characterized by a relatively high resistance to current at low bias and a very high current at high bias. The partial selector material exhibits a S-shape IV and is characterized by a low current until the positive or negative voltage across the membrane selector 160 exceeds a defined threshold in which the device voltage is rebounded and the device current is limited by the load line. In some embodiments, the membrane selector 160 can include, but is not limited to, an amorphous chalcogenide alloy sandwiched between electrodes (including at least one chalcogen anion and an alloy of at least one positively charged element, including cycles) All of the Group 16 elements on the table - sulfur, selenium, tellurium). In at least some embodiments, the electrode can comprise a carbon electrode or a carbon containing electrode. In some embodiments, the turn-on time of the thin film selector 160 can vary with the application of a voltage (eg, an applied voltage greater than a threshold can shorten the turn-on time of the thin film selector). In some embodiments, the turn-off time of the thin film selector 160 can vary with the applied voltage (eg, the applied voltage is less than the threshold to shorten the turn-off time of the thin film selector).

2 depicts an exemplary MTJ device 110 including an SAF layer and an AFM layer disposed on the exemplary SHE electrode 130, in accordance with at least one embodiment of the present invention. The free magnetic layer 122 of the MTJ device 110 can be disposed adjacent the central portion 202 of the SHE electrode 130, which includes or is fabricated using one or more Giant Spin Hall Effects (GSHE). The GSHE material Examples include, but are not limited to, β-tellurium (β-Ta), β-tungsten (β-W), platinum (Pt), gold (Au), silver (Ag), copper (Cu), or combinations thereof or alloy. In some embodiments, the central portion 202 of the SHE electrode 130 can include one or more dopants, such as iridium (Ir), bismuth (Bi), elements from 3d, 4d, 5d, 4f, or 5 One or a combination or alloy thereof. In some embodiments, the first end 132 of the SHE electrode 130 can comprise or be fabricated using one or more electrically conductive materials, such as copper, copper alloys, aluminum, aluminum alloys, gold, gold alloys, silver, silver alloys, platinum. , a platinum alloy, or a combination thereof. In some embodiments, the second end 134 of the SHE electrode 130 can include or be fabricated using one or more electrically conductive materials, such as copper, copper alloys, aluminum, aluminum alloys, gold, gold alloys, silver, silver alloys, Platinum, platinum alloys, or combinations thereof. Fabricating either or both of the first end 132 and the second end 134 of the SHE electrode 130 with a highly electrically conductive material advantageously reduces the resistance of the SHE electrode 130 and potentially allows for lower write current levels. .

The spin-polarized write current 220 can flow along the SHE electrode 130 in a first direction or a second direction, as indicated by the double-headed arrow shown in FIG. Advantageously, write current 220 does not flow through MTJ device 110, thereby allowing the use of relatively high write currents (e.g., 100 [mu]A or greater) to provide fast and reliable writes to MTJ device 110 to form MRAM bits. Cell. In contrast to the write current 220, the read current 230 can flow from the read bit line 142 and through the MTJ device 110, as indicated by the single-headed arrow shown in FIG. Since the write current and the read current flow through the 1T-1S-1MTJ-STT-SHE MRAM bit cell 100 along different paths, the current is read and Both of the write currents can advantageously select their respective functions. The relatively high write current strongly provides fast and reliable writes to the 1T-1S-1MTJ-STT-SHE MRAM bit cell 100, and the relatively low read current (eg, 10μA) advantageously improves 1T-1S-1MTJ -STT-SHE MRAM bit cell 100 long-term reliability.

FIG. 3 depicts an exemplary MTJ device 110 geometry in accordance with at least one embodiment of the present disclosure. The MTJ device 110 can have any shape, size, or configuration. In at least one embodiment, the MTJ device 110 can have a generally elliptical footprint. In this embodiment, the MTJ device 110 can have an elliptical geometry characterized by a major axis (or length) 302 and a minor axis (or width) 304. In at least some embodiments, the MTJ device 110 can be oriented along the width of the SHE electrode 130 for proper spin injection. Binary data can be written to the MTJ device 110 by applying a spin-polarized write current 220 along the SHE electrode 130 in either the first direction or the second direction. The direction of magnetic writing can be determined by the direction in which the write current is applied. For example, a positive current (along the +y axis) produces a spin injection current with a transport direction (along the +z axis) and a spin oriented in the +x direction.

4 depicts a cross-sectional view of the GSHE illustrating the direction of the upper spin current 402, the direction of the lower spin current 404, and the charge generated from the spin Hall effect in the GSHE material without externally applied magnetic field. Currents 410, 412. The injected spin current produces a spin torque for aligning the magnets in the +x or -x direction. Charge current for writing into electrons ( Spin direction Lateral spin current It can be expressed as:

among them It is the spin Hall injection efficiency (ratio of the amplitude of the lateral spin current to the lateral charge current), w is the width of the magnet, t is the thickness of the GSHE metal electrode, and λ _sf is the spin in the GSE metal. Flip length, Θ _SHE is the spin Hall angle for the GSHE-metal to FM1 interface. The injected spin angular momentum responsible for the spin torque is given by the following formula:

FIG. 5A depicts an exemplary read operation on the example 1T-1S-1MTJ-STT-SHE-MRAM bit cell 100 in accordance with at least one embodiment of the present disclosure. During a read operation, read current 502 flows from read bit line 142 through MTJ 110, and through SHE electrode 130, through first transistor 150, to source line 140. In an embodiment, the read bit line 142 and the source line 140 are electrically coupled to a sense amplifier (not shown in Figure 5A). The resistance of the MTJ device 110 determines whether or not to read a "low" logic value or a "high" logic value. In an embodiment, the read current 502 can be about 30 μA or less; 25 μA or less; 20 μA or less; 15 μA or less; 10 μA or less; 5 μA or less.

FIG. 5B is an exemplary write operation 600 depicting an example 1T-1S-1MTJ-STT-SHE-MRAM bit cell 100 in accordance with at least one embodiment of the present disclosure. The direction in which the write current flows through the SHE electrode 130 determines the spin polarization of the write current and thus determines the free magnetic The direction of the magnetic field of the layer 112. To write a "low" logic value or state to the MTJ device 110, a write current can flow through the SHE electrode 130 in a first direction. To write a "high" logic value or state to the MTJ device 110, the write current may flow through the SHE electrode 130 in a second direction that is opposite the first direction. In an embodiment, the relative potential difference between the source line 140 and the write bit line 144 determines the direction in which the write current flows through the SHE electrode 130.

In the left 1T-1S-1MTJ-STT-SHE MRAM bit cell 100A (bit cell "A") depicted in FIG. 5B, the source line 140 is maintained at a higher potential than the write bit line 144. In this example, write current 510 flows through thin film selector 160, through SHE electrode 130 in a first direction 512, and through first transistor 150. In the right 1T-1S-1MTJ-STT-SHE MRAM bit cell 100B shown in FIG. 5B, the write bit line 144 is maintained at a higher potential than the source line 140. In this example, write current 520 flows through thin film selector 160, through SHE electrode 130 in a second direction 522, and through first transistor 150.

6A is an exemplary read operation depicting another example 1T-1S-1MTJ-STT-SHE-MRAM bit cell 100, in accordance with at least one embodiment of the present disclosure. As depicted in FIG. 6A, during a read operation, read current 602 flows from read bit line 142 through MTJ 110, and through SHE electrode 130, through thin film selector 160, to source line 140. In an embodiment, the read bit line 142 and the source line 140 are electrically coupled to a sense amplifier (not shown in Figure 6A). The write actuation line 604 maintains the first transistor 150 in a closed or conductively non-conductive state during a read operation Pass state. The resistance of the MTJ device 110 determines whether or not to read a "low" logic value or a "high" logic value. In an embodiment, the read current 502 can be about 30 μA or less; 25 μA or less; 20 μA or less; 15 μA or less; 10 μA or less; 5 μA or less.

6B is an exemplary write operation 600 depicting another example 1T-1S-1MTJ-STT-SHE-MRAM bit cell 100, in accordance with at least one embodiment of the present disclosure. During the write operation, the write actuation line 604 maintains the first transistor 150 in an on or conductively conducting state. The direction in which the write current flows through the SHE electrode 130 determines the spin polarization of the write current and thus the direction of the magnetic field of the free magnetic layer 112. To write a "low" logic value or state to the MTJ device 110, a write current can flow through the SHE electrode 130 in a first direction. To write a "high" logic value or state to the MTJ device 110, the write current may flow through the SHE electrode 130 in a second direction that is opposite the first direction. In an embodiment, the relative potential difference between the source line 140 and the write bit line 144 determines the direction in which the write current flows through the SHE electrode 130.

In the left 1T-1S-1MTJ-STT-SHE MRAM bit cell 100A (bit cell "A") depicted in FIG. 6B, the write bit line 144 is maintained at a higher potential than the source line 140. In this example, write current 610 flows through first transistor 150, through SHE electrode 130 in first direction 612, and through thin film selector 160. In the right 1T-1S-1MTJ-STT-SHE MRAM bit cell 100B depicted in FIG. 6B, the source line 140 is maintained at a higher potential than the write bit line 144. In this example, the write current 620 flows through the thin film selector 160, passes through the SHE electrode 130 in the second direction 622, And passing through the first transistor 150 to the source line 140.

7 depicts an exemplary array 700 including sixteen (16) 1T-1S-1MTJ-STT-SHE MRAM bit cells 100A-100P, such as depicted in FIGS. 5A and 5B, in accordance with at least one embodiment of the present disclosure. description. Although depicted as a 4x4 array of exemplary 1T-1S-1MTJ-STT-SHE MRAM bit cells 100, the array 700 can have any number or configuration of 1T-1S-1MTJ-STT-SHE MRAM bit cells 100. Each 1T-1S-1MTJ-STT-SHE MRAM bit cell 100A-100P includes a SHE electrode 130 and an MTJ device 110 which, when combined, provides a three terminal device. Further, each 1T-1S-1MTJ-STT-SHE MRAM bit cell includes a first transistor 150 and a thin film selector 160. The MTJ device 110 can be connected to a read bit line 142 that can be included in a metal layer within the semiconductor die, such as a fourth metal (M4) layer within the semiconductor die. The SHE electrons 130 can be formed using one or more spin Hall materials including, but not limited to, beta-ruthenium, beta-tungsten, platinum, or tantalum selenide. The MTJ device 110 can be sized, shaped, and placed on the SHE electrode 130 in the correct orientation for spin injection.

By actuating word line 146 to actuate first transistor 150 in unit cell 100, a write operation for each bit cell 100 can occur. As depicted and described above in FIG. 5B, write currents 510, 520 flow through respective bit cells 100. The adjacent bit cells 100 in the respective columns can remain undisturbed due to the selection of the presence of the transistor and the separation of the spin Hall metal in each bit cell. The potential of the write bit line 144 coupled to the respective bit cell 100 is adjusted by selectively coupling the respective write bit line 144 to ground (low potential) or V _cc (high potential) depending on the input data. (ie, whether logical "1" or logical "0" is written to the bit cell). The appropriate spins are injected into the MTJ device 110 (respectively) by the direction 512, 522 of the write currents 510, 520 of the bit cells 100. To perform a read operation, the first transistor 150 can be actuated such that the read current 502 can flow from the read bit line 142 through the MTJ device 110 and through the first transistor 150 for detecting the resistance of the MTJ device 110. .

Array 700 includes separate source lines 140A-140D, respective read bit lines 142A-142D, and respective data for each "column" of 1T-1S-1MTJ-STT-SHE MRAM bit cell 100. Lines 144A-144D. Array 700 also includes respective word lines 146A-146B, each of which is shared between two contiguous columns of 1T-1S-1MTJ-STT-SHE MRAM cells 100.

FIG. 8A is a top plan view of an exemplary configuration 800 depicting a 1T-1S-1MTJ-STT-SHE-MRAM bit cell 100 in accordance with at least one embodiment of the present disclosure. In the embodiment depicted in Figure 8, each 1T-1S-1MTJ-STT-SHE MRAM cell has a one-and-a-half (1-1⁄2) gate interval or three (3) times the half gate interval. The second dimension 820 of the first source size 810 and the double half (2-1⁄2) source line 140 is (5F) or five (5) times the half source line pitch. In this embodiment, each 1T-1S-1MTJ-STT-SHE MRAM bit cell 100 includes a dedicated SHE electrode 130 that is not shared by any other 1T-1S-1MTJ-STT-SHE MRAM bit cell 100.

Figure 8B is a diagram depicted in accordance with at least one embodiment of the present invention. A cross-sectional view of an exemplary 1T-1S-1MTJ-STT-SHE MRAM bit cell 100 depicted along 8A along its section line B-B. 8C is a cross-sectional view of the exemplary 1T-1S-1MTJ-STT-SHE MRAM cell 100 depicted along FIG. 8A along its section line C-C, in accordance with at least one embodiment of the present invention. It can be seen more clearly in Figures 8B and 8C, which are unit geometry, in which the read bit line 142 is formed, patterned, or otherwise deposited in, on or around the fourth metal (M4) layer, written. The in-bit line 144 is formed, patterned, or otherwise deposited in, on, or around the second metal (M2) layer, and the source line 140 is formed, patterned, or otherwise deposited on the zeroth metal ( M0) In, on or around the layer.

9A is a top plan view of an exemplary configuration 900 depicting a 1T-1S-1MTJ-STT-SHE-MRAM bit cell 100 in accordance with at least one embodiment of the present disclosure. In the embodiment depicted in Figure 8, each 1T-1S-1MTJ-STT-SHE MRAM cell has a one-and-a-half (1-1⁄2) gate interval or three (3) times the half gate interval. The second dimension 920 of the first dimension 910 and the triple half (3-1⁄2) source line 140 between (3F) or seven (7) times the half source line spacing. In this embodiment, each 1T-1S-1MTJ-STT-SHE MRAM bit cell 100 includes a dedicated SHE electrode 130 that is not shared by any other 1T-1S-1MTJ-STT-SHE MRAM bit cell 100.

9B is a cross-sectional view of the exemplary 1T-1S-1MTJ-STT-SHE MRAM cell 100 depicted along FIG. 9A along its section line B-B, in accordance with at least one embodiment of the present invention. Figure 9C is an illustration of an exemplary 1T-1S- depicted in Figure 9A, in accordance with at least one embodiment of the present invention. 1MTJ-STT-SHE MRAM bit cell 100 is a cross-sectional view along its section line C-C. It can be seen more clearly in Figures 9B and 9C, which are unit geometry, in which the read bit line 142 is formed, patterned, or otherwise deposited in, on or around the fourth metal (M4) layer, written The in-line line 144 and the source line 140 are formed, patterned, or otherwise deposited in, on or around the zeroth metal (M0) layer.

FIG. 10A depicts an example graph 1000 of current (amperes) vs. voltage (volts) for an exemplary thin film (single or multi-layer) flashback selector 160, in accordance with at least one embodiment of the present invention. From FIG. 10A, the current flowing through the flashback film selector 160 maintains a relatively low voltage difference across the film selector 160 from about ±0.8V to about ±1V. Advantageously, this low current (eg, 0.1 μA to 10 μA) flowing through the SHE electrode 130 is unlikely to result in a change in the direction of the magnetic field of the free magnetic layer 112. As such, current leakage through the thin film selector 160 at a forward or reverse voltage difference of less than about 0.8V to 1V is unlikely to cause a change in the direction of the magnetic field of the free magnetic layer 112. However, when the voltage difference across the thin film selector 160 is greater than about ±0.8V to about ±1V, the current flowing through the thin film selector 160 can be rapidly increased to about 200μA. Even if the voltage drops to about ±0.8V to about ±1V, the current continues to increase. A current flow above about 100 [mu]A can change the direction of the magnetic field of the free magnetic layer 112 through the SHE electrode 130.

FIG. 10B depicts an example graph 1050 of current (amperes) vs. voltage (volts) for an exemplary thin film (single or multi-layer) selector 160, in accordance with at least one embodiment of the present invention. From Figure 10B, the current flowing through the flashback film selector 160 maintains a relatively low voltage difference (increased for a single layer selector) Adding less than 20 μA and increasing the multilayer selector by less than about 5 μA), the voltage difference across the thin film selector 160 is from about ±0.8V to about ±1V. Advantageously, a current of less than about 20 [mu]A flowing through the SHE electrode 130 is unlikely to result in a change in the direction of the magnetic field of the free magnetic layer 112. As such, current leakage through the thin film selector 160 at a voltage difference of less than about 0.8V is unlikely to cause a change in the direction of the magnetic field of the free magnetic layer 112. However, when the voltage difference across the thin film selector 160 is greater than about ±0.8V to about ±1V, the current flowing through the thin film selector 160 can be rapidly increased to about 200μA. A current flow above about 100 [mu]A can change the direction of the magnetic field of the free magnetic layer 112 through the SHE electrode 130.

11 is a high-order exemplary method 1100 depicting forming a 1T-1S-1MTJ-STT-SHE-MRAM bit cell 100 in accordance with at least one embodiment of the present disclosure. Method 1100 begins at 1102.

At 1104, the first transistor 150 can be formed in, on, or around the substrate. The first transistor 150 can include a first diffusion region 152 (eg, a source), a gate region 155, and a second diffusion region 156 (eg, a drain). The first transistor 150 may include a metal oxide semiconductor (MOS) transistor, a tri-gate transistor, a german-type field effect transistor (FinFET), a wraparound gate column transistor, or any other current function that provides a transistor-like function. Or a device, system, or combination of systems and devices in future development (eg, carbon nanotubes, spintronics, and the like).

At 1106, source line 140 can be deposited, patterned, or formed in the first metal layer in any other manner. In at least some embodiments, The first metal layer can include a zero metal (M0) layer, such as depicted in Figures 1, 8A-8C, and 9A-9C. Source line 140 may be deposited or patterned in, on, or around the first metal layer using any current or future developed deposition, removal, and/or patterning techniques. In various embodiments, example deposition techniques may include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and atomic layers. Deposition (ALD). In various implementations, example removal techniques can include, but are not limited to, wet etch removal, dry etch removal, and chemical mechanical polishing. In various embodiments, example patterning techniques can include, but are not limited to, photolithography.

At 1108, a first diffusion region 152 (eg, a source region) of the first transistor 150 is electrically coupled to the source line 140. In some embodiments, the first diffusion region 152 can be electrically coupled to the source line 140 using one or more conductive structures 154, such as one or more pillar vias. In at least some embodiments, all or a portion of the electrically conductive structure 154 can be at least partially disposed within a trench or similar structure that provides access to the diffusion region 152.

At 1110, the SHE electrode 130 can be deposited. Although depicted as a solid rectangular member, the SHE electrode 130 can comprise any number or combination of members formed using a GSHE material having any three-dimensional shape, a combination of three-dimensional shapes, and/or a three-dimensional shape. Other SHE electrode shapes, sizes, and configurations can be substituted. In some embodiments, the SHE electrode 130 can include a heterogeneous member. In this embodiment, set in proximity The central portion 202 of the SHE electrode 130 of the MTJ device 110, which may be formed from any current or future developed GSHE material or material such as beta-bismuth, beta-tungsten, platinum, strontium selenide or the like. In this embodiment, the SHE electrode 130 is similar to at least a portion of one or more ends of the surrounding regions 204, 206, which may be made of a material that provides a low electrical resistance or a material having a high electrical conductivity, such as copper, silver, gold. . In some embodiments, the SHE electrode 130 can be advantageously doped with one or more materials including, but not limited to: 铱, 铋, 3d, 4d, 5d, 4f, and any element of the 5f periodic group, gold, Silver, platinum, copper, or the like.

At 1112, a second diffusion region 156 (eg, a drain) of the first transistor 150 is electrically coupled to the SHE electrode 130. In some embodiments, the second diffusion region 156 can be electrically coupled to the SHE electrode 130 using one or more conductive structures 158, such as one or more pillar vias.

At 1114, the MTJ device 110 can be formed on at least a portion of the SHE electrode 130. In at least some embodiments, the MTJ device 110 can be formed at an intermediate point of the SHE electrode 130 between the second diffusion region 156 electrically coupled to the first transistor 150 and the second diffusion region 166 of the second transistor 160. position. The MTJ device can be disposed adjacent to portion 202 of SHE electrode 130 fabricated or otherwise formed using one or more GSHE metals. In some embodiments, the MTJ device stack can include a free magnetic layer 112, a tunnel oxide layer 116, and a fixed magnetic layer 114. In some embodiments, the MTJ stack can additionally include a conductively conductive, synthetic antiferromagnetic (SAF) layer that facilitates fixing the fixed magnetic layer 114 magnetic field. In some embodiments, the SAF layer can include, but is not limited to, a tantalum layer 122 and a cobalt/iron layer 126. In some embodiments, the MTJ device stack can additionally include an electrically conductive, anti-ferromagnetic layer (AFM) 126 disposed adjacent the SAF layer, as opposed to the fixed magnetic layer 114.

At 1116, the free magnetic layer 112 of the MTJ device 110 is coupled to the SHE electrode 130.

At 1118, write bit line 144 can be deposited or otherwise patterned in a metal layer within the semiconductor die. In some embodiments, write bit line 144 can be deposited, patterned, or otherwise formed in a zero metal (M0) layer. In this embodiment, write bit line 144 can be isolated from any source line 140 that can also be formed in a zero metal layer. In some embodiments, write bit line 144 can be deposited, patterned, or otherwise formed in a second metal (M2) layer.

The write bit line 144 can be deposited or patterned in, on, or around the metal layer using any current or future developed deposition, removal, and/or patterning techniques. In various embodiments, example deposition techniques may include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and atomic layers. Deposition (ALD). In various implementations, example removal techniques can include, but are not limited to, wet etch removal, dry etch removal, and chemical mechanical polishing. In various embodiments, example patterning techniques can include, but are not limited to, photolithography.

At 1120, the read bit line 142 can be deposited or otherwise patterned in a fourth metal (M4) layer within the semiconductor die. Read bit The line 142 can be deposited or patterned in, on, or around the metal layer using any current or future developed deposition, removal, and/or patterning techniques. In various embodiments, example deposition techniques may include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and atomic layers. Deposition (ALD). In various implementations, example removal techniques can include, but are not limited to, wet etch removal, dry etch removal, and chemical mechanical polishing. In various embodiments, example patterning techniques can include, but are not limited to, photolithography.

At 1122, the film selector 160 can be deposited, patterned, or otherwise formed in, on, or around one or more layers of the semiconductor experience. The thin film selector 160 can include any combination or number of devices and/or systems capable of controlling the write current between the second end 134 of the SHE electrode 130 and the write bit line 144. In an embodiment, the membrane selector 160 can include, but is not limited to, at least one bidirectional limit switch (OTS). In an embodiment, the thin film selector 160 can be characterized as the current having a relatively high resistance until the positive or negative voltage difference across the thin film selector 160 exceeds a critical value.

In some embodiments, the membrane selector 160 can include, but is not limited to, a first electrode that is separated from the second electrode by a thin, amorphous chalcogenide layer. In at least some embodiments, either or both of the first electrode and the second electrode can comprise any number of carbon electrodes or a combination of carbon-containing electrodes. In some embodiments, the turn-on time of the thin film selector 160 can be shortened with the applied voltage (eg, the applied voltage is greater than the critical value to shorten the thin film selector) Change time). In some embodiments, the turn-off time of the thin film selector 160 can vary with the applied voltage (eg, the applied voltage is less than the threshold to shorten the turn-off time of the thin film selector).

At 1124, in an embodiment, a first electrode of thin film selector 160 is electrically coupled to second end 134 of SHE electrode 130. In an embodiment, the second electrode is electrically coupled to the write bit line 142 such that a voltage difference between the SHE electrode 130 and the write bit line 142 exceeding approximately 0.8 V will cause a current flow of more than 20 μA to pass Film selector 160.

At 1126, the fixed magnetic layer 114 of the MTJ device 110 can be electrically coupled to the read bit line 142, either directly or indirectly. In some embodiments, a conductively conductive, synthetic antiferromagnetic (SAF) layer can be disposed between the fixed electrode 114 and the read bit line 142. In this embodiment, the SAF layer can include, but is not limited to, a tantalum layer 122 and a cobalt/iron layer 124. In some embodiments, a conductively conductive, antiferromagnetic (AFM) layer 126 can be disposed between the SAF layer and the read bit line 142. In some embodiments, one or more conductive structures, such as one or more vias 120, are electrically coupled to the AFM layer 126 of the MTJ device 110 to the read bit line 142. Method 1100 ends at 1128.

12 is a high level flow diagram 1200 depicting an exemplary write operation of the example 1T-1S-1MTJ-STT-SHE-MRAM bit cell 100, in accordance with at least one embodiment of the present disclosure. Method 1200 begins at 1202.

At 1204, write currents 510, 520 flow through SHE electrode 130. The spin polarization of the write current is caused by the freedom in the MTJ device 110 The magnetic layer 112 generates a magnetic field that exhibits one of two defined directions that depends, at least in part, on the direction of the write current flow through the SHE electrode 130. In an embodiment, the first direction of the magnetic field generated by the free magnetic layer 112 may correspond to a logical "low" state or value, and the second direction of the magnetic field generated by the free magnetic layer 112 may correspond to a logical " High state or value. Since the write current does not flow through the MTJ device 110 itself, a higher write current (eg, more than 100 μA known write current) is possible compared to other designs in which the write current flows through the MTJ device 110. The use of higher currents advantageously allows for faster write cycles while the write errors remain at or below the acceptable error level.

In some examples, to write the first logic value to the MTJ device 110, the potential of the write bit line 144 can be maintained at a higher level than the potential of the source line 140. In this example, write current 510 can flow through write bit line 144, through first transistor 150, through SHE electrode 130 in first direction 512 (eg, from first end 132 of SHE electrode 130 to The second end 134), and through the second transistor 160 to the source line 140.

In some examples, to write the second logic value to the MTJ device 110, the potential of the source line 140 can be maintained at a higher level than the potential of the write bit line 144. In this example, write current 520 may flow through source line 140, through second transistor 160, through SHE electrode 130 in second direction 522 (eg, from second end 134 of SHE electrode 130 to first end) Portion 132) and through the first transistor 150 to the write bit line 144. The method ends at 1206.

13 is a processor-based environment 1300 in which at least a portion of the non-volatile storage can include a 1T-1S-1MTJ-STT-SHE-MRAM bit cell, in accordance with at least one embodiment of the present disclosure. 100. The processor-based environment 1300 includes one or more processor-based devices 1302 communicatively coupled to one or more non-transitory processor-based storage devices 1304. The associated non-transitory processor readable storage medium 1304 is communicatively coupled to one or more processor-based devices 1302 via one or more communication channels, such as one or more parallel cables for high speed communication , tandem cable, or wireless channel cable, for example via BLUETOOTH ^® , Universal Serial Bus (USB), FIREWIRE ^® , or the like.

One or more processor-based devices 1302 can be communicatively coupled to one or more external devices using one or more wireless or wired network interfaces 1360. Examples of wireless network interfaces 1360 can include, but are not limited to, BLUETOOTH ^®, Near Field Communication (NFC), ZigBee, IEEE802.11 ( Wi-Fi), 3G, 4G, LTE, CDMA, GSM, and the like. The example wired network interface 1360 can include, but is not limited to, IEEE 802.3 (Ethernet), and the like. The structure and operation of the various block diagrams illustrated in Figure 13 are conventional designs unless otherwise stated. Therefore, as will be understood by those skilled in the relevant art, the block diagrams are not required to be further described in detail in the present invention.

The processor-based system 1300 can include one or more circuits of executable processor readable instructions to provide any number of dedicated processing circuits 1312, system memory 1314, and system communication chains 1316 that are bidirectional The various system components including system memory 1314 are communicatively coupled to processing circuitry 1312. Processing circuitry 1312 may include, but is not limited to, any circuitry capable of processing one or more sets of processor readable instructions, such as one or more single or multiple core central processing units (CPUs), digital signal processors (DSPs), Special application integrated circuits (ASICs), field programmable gate arrays (FPGAs), single chip systems (SOCs). Communication link 1316 can take any known bus structure or architecture, including a memory bus with a memory controller, a peripheral bus, and/or a regional bus. System memory 1314 includes read only memory ("ROM") 1318 and random access memory ("RAM") 1320. In at least some embodiments, at least a portion of RAM 1320 includes STT-SHE-MRAM bit cells. In at least some embodiments, at least a portion of RAM 1320 includes a 1T-1S-1MTJ-STT-SHE MRAM bit cell 100. A basic input-output system ("BIOS") 1322, which may form part of ROM 1318, may contain a basic routine that may cause transmission of information between elements within processor-based device 1302, such as during startup.

The processor-based device 1302 can include one or more disk drives 1324, one or more optical storage devices 1328, one or more magnetic storage devices 1330, and/or one or more atomic or quantum storage devices 1332 . One or more optical storage devices 1328 can include, but are not limited to, one or more CD-ROM drives. One or more magnetic storage devices may include, but are not limited to, a magnetic disk or a magnetic disk. One or more disk drives 1324, one or more optical storage devices 1328, one or more magnetic storage devices 1330, and one or more atomic/quantum storage devices 1332 may include integration Or discrete interface or controller (not shown).

The processor readable instruction set may be stored, in whole or in part, or otherwise retained in system memory 1314. The processor readable instruction set can include, but is not limited to, an operating system 1336, one or more applications 1338, other programs or modules 1340, and program data 1342. Although shown in FIG. 13 as being stored in system memory 1314, operating system 1336, application 1338, other programs/modules 1340, program data 1342, and browser 1344 may be stored in one or more disk drives 1324. One or more optical storage devices 1328, one or more magnetic storage devices 1330, and/or one or more atomic or quantum storage devices 1332.

The system user can use one or more physical input devices 1370 to enter commands and information into the processor-based device 1302. The example entity input device 1370 includes, but is not limited to, one or more keyboards 1372, one or more touch screen I/O devices 1374, one or more audio input devices 1376 (eg, microphones), and/or one or A plurality of pointing devices 1378. The plurality of input devices and other entities may communicate with the interface 1350 may be coupled to the processor-based device 1302 through one or more wired or wireless, such as Universal Serial Bus (USB) connection and / or BLUETOOTH ^® wireless connector.

The system user can receive output from the processor-based device 1302 via one or more physical output devices 1380. The instance entity output device 1380 can include, but is not limited to, one or more visual or video output devices 1382, one or more haptic or tactile output devices 1384, and/or a Or a plurality of audio output devices 1386. One or more video or visual output devices 1382, one or more haptic output devices 1384, and one or more audio output devices 1386 can be communicatively coupled to communication link 1316 via one or more interfaces or adapters.

The following examples relate to embodiments using the 1T-1S-1MTJ-STT-SHE MRAM bit cell device, system, and method described in part or in full. The examples are not to be considered as exhaustive, and the examples are not to be construed as limiting the systems, methods, and apparatus disclosed herein, and other combinations not specifically enumerated herein.

According to the example 1, a transistor, a selector, a magnetic tunnel junction (1T-1S-1MTJ), spin torque transfer (STT), and spin Hall effect (SHE) magnetoresistive random access are provided. Memory (MRAM) device. The 1T-1S-1MTJ-STT-SHE MRAM device can include a spin Hall effect (SHE) electrode. The 1T-1S-1MTJ-STT-SHE MRAM device may additionally include a first transistor and a thin film selector. The 1T-1S-1MTJ-STT-SHEMRAM device can additionally include a magnetic tunnel junction (MTJ) device, wherein the MTJ device includes between the conductive coupling to the first transistor and the conductive coupling to the thin film selector. Position, electrically coupled to the free magnetic layer of the SHE electrode.

Example 2 can include the component of Example 1, wherein the first transistor is conductively coupled between the SHE electrode and the source line, the first transistor is controlled by a word line, and wherein the thin film selector is electrically coupled to the SHE Between the electrode and the write bit line.

Example 3 can include the component of Example 1, wherein the first transistor is electrically conductive Coupled between the SHE electrode and the write bit line, the first transistor is controlled by the write actuator line, and the thin film selector is conductively coupled between the SHE electrode and the source line.

Example 4 can include the elements of Example 2, wherein the MTJ device can include a fixed magnetic layer that is electrically coupled to the read bit line.

Example 5 can include the elements of Example 4, wherein the write bit line and the read bit line can be formed in two different metal layers.

Example 6 can include the element of Example 1, wherein the SHE electrode can include a SHE material having a first end and an opposite second end, wherein the first transistor is electrically conductively coupled to the first end of the SHE electrode, and wherein A membrane selector is electrically coupled to the second end of the SHE electrode.

Example 7 can include the element of Example 1, wherein the source line can be formed in a zero metal (M0) layer.

Example 8 can include the component of Example 1, wherein the first transistor, the SHE electrode, and the thin film selector form a reversible circuit during a write operation.

Example 9 can include the element of Example 8, wherein a current in a first direction is passed through the SHE electrode in the MTJ device to place the free magnetic parallel alignment with a fixed magnetic in the MTJ device, the MTJ device being placed In a low resistance state.

Example 10 can include the element of Example 9, wherein a current in a second direction opposite the first direction passes through the SHE electrode in the MTJ device, wherein a current in the first direction passes through the SHE electrode at In the MTJ device, in anti-parallel pair with the fixed magnetic field in the MTJ device The free magnetism is placed, which places the MTJ device in a high resistance state.

Example 11 can include any of the components of Examples 1 through 10, wherein the SHE electrode comprises a patterned SHE electrode.

Example 12 can include the elements of Example 11, wherein the SHE electrode can include β-钽 (β-Ta), β-tungsten (β-W), platinum (Pt), or copper (Cu).

Example 13 can include the elements of Example 12, wherein the SHE electrode can comprise one or more dopants selected from the group consisting of: ruthenium, osmium, any 3D congener element, any 4D congener element, any 5D congener element, Any 4F congener element, any 5F congener element, silver, gold, copper, and platinum.

Example 14 can include any of the elements of Examples 1 through 10, wherein the SHE electrode can include an MTJ device having an elliptical pattern of width and length.

Example 15 can include any of the components of Examples 4 through 10, wherein the MTJ device can be physically disposed between a zero metal layer comprising a source line and a second metal layer comprising at least a bit line and a data line, and wherein the source The polar lines, bit lines, and data lines are parallel to each other.

Example 16 may include any one of Examples 4-10 of the element, wherein the selector may comprise a thin film of niobium oxide (NbO _x) film selector.

Example 17 Example 16 may include a member of which the niobium oxide (NbO _x) may comprise a single layer film selected niobium oxide (NbO _x) film selector.

Examples may include 18 instances of element 16, wherein a niobium oxide (NbO _x) may comprise a multilayer film selective niobium oxide (NbO _x) film selector.

Example 19 can include any of the components of claims 4 through 10, wherein the membrane selector can include a membrane selector having an opening voltage of about 0.7 volts.

According to Example 20, a transistor, a selector, a magnetic tunnel junction (1T-1S-1MTJ), spin torque transfer (STT), and spin Hall effect (SHE) magnetoresistive random access are provided. Memory (MRAM) method. The method can further include forming a first transistor having a source region, a drain region, and a gate region, forming a source line in the first metal layer, and electrically coupling the source region to the source of the first transistor line. The method can also further include forming a SHE electrode and electrically coupling the drain of the first transistor to the SHE electrode. The method can include forming an MTJ device comprising a free magnetic layer and a fixed magnetic layer and electrically coupling the free magnetic layer of the MTJ device to the SHE electrode. The method can further include forming a write bit line and forming a read bit line in the second metal layer. The method can also include forming a thin film selector, and electrically coupling the thin film selector and the write bit line between the SHE electrodes, and conductively coupling the fixed magnetic layer of the MTJ device for reading the bit lines.

Example 21 can include the elements of Example 20, and can further include electrically conductively coupling a gate region of the first transistor to the word line.

Example 22 can include the elements of Example 20, and wherein the free magnetic layer that electrically couples the MTJ device to the SHE electrode can include electrically conductively coupled at a point between the drain region of the first transistor and the thin film selector The free magnetic layer of the MTJ device is to the SHE electrode.

Example 23 can include the elements of Example 20, and can additionally include a free magnetic layer that electrically couples at least one additional MTJ device to the SHE electrode.

Example 24 can include the elements of Example 20, wherein forming the MTJ device can include forming a generally elliptical MTJ device having a length and a width.

Example 25 can include any of the elements of Examples 20 through 2242, wherein forming the source line in the first metal layer comprises forming a source line in the zero metal (M0) layer.

Example 26 can include the element of example 25, wherein forming the read bit line in the second metal layer can include forming a read bit line in the fourth metal (M4) layer.

Example 27 can include the elements of example 26, wherein forming the write bit line can include forming a write bit line at the zero metal (M0) layer.

Example 28 can include the element of example 26, wherein forming the write bit line can include forming a write bit line at the second metal (M2) layer.

Example 29 can include the element of Example 20, wherein forming the SHE electrode can include forming a SHE electrode comprising beta-tellurium (beta-Ta), beta-tungsten (beta-W), platinum (Pt), or copper (Cu).

Example 30 can include the element of Example 29, wherein forming the SHE electrode can further comprise forming a SHE electrode comprising one or more dopants selected from the group consisting of: 铱, 铋, any 3D congener, any 4D congener Any 5D congener element, any 4F congener element, any 5F congener element, silver, gold, copper, and platinum.

According to example 31, a transistor, a selector, a magnetic Tunnel junction (1T-1S-1MTJ), spin torque transfer (STT), spin Hall effect (SHE) magnetoresistive random access memory (MRAM) method. The method can include selectively writing a binary value to an MRAM cell that includes an MTJ coupled to the SHE electrode. The method can include causing the write current to flow through the electrode in either of the following directions, the MTJ coupled to the SHE electrode: placing the first direction of the resistance value of the MTJ device magnetically coupled to the SHE electrode in the first state, or placing it differently The second direction of the resistance value of the MTJ device of the SHE electrode is magnetically coupled in the second state of the first state.

Example 32 can include the element of example 31, wherein selectively causing a write current to flow through the spin Hall effect electrode in a first direction, can include selectively causing the write current to pass from the source line through the first transistor And flowing through the SHE electrode in the first direction and through the thin film selector to a write bit line having a lower potential than the source line.

Example 33 can include the element of example 32, wherein selectively causing a write current to flow through the spin Hall effect electrode in a second direction, which can include selectively causing the write current to pass from the write bit line through the thin film selection The device passes through the SHE electrode in the second direction and flows through the first transistor to a source line having a low potential of the write bit line.

Example 34 can include any of the elements of Example 32 or 33, wherein the write current passes through the SHE electrode for about 10 nanoseconds (ns).

Example 35 can include the elements of Example 31, and can additionally include selectively reading binary values from the MRAM cell including the MTJ coupled to the SHE electrode by causing a read current flow through the MTJ.

Example 36 can include the component of example 35, wherein the binary value is selectively read from the MRAM cell MTJ by causing a read current flow to pass, which can selectively cause the read current to pass from the read bit line through the MTJ, Flows through the SHE electrode and through the first transistor to the source line.

Example 37 can include any of the elements of example 35 or 36, wherein the binary value is selectively read from the MRAM cell by causing a read current flow through the MTJ, which can include a potential floating of the write bit line.

Example 38 can include the component of example 36, wherein the write current can comprise a current value that is at least five times greater than a current value of the read current.

Example 39 can include the elements of Example 36, wherein the write current can be about 100 μA and the read current can be about 10 μA.

According to the example 40, a transistor, a selector, a magnetic tunnel junction (1T-1S-1MTJ), a spin torque transfer (STT), a spin Hall effect (SHE), and a magnetoresistive random memory are provided. Take the memory (MRAM) system. The system can include means for selectively writing a binary value to the MRAM cell, the MTJ coupled to the SHE electrode by causing the write current to flow through the electrode in any of the following directions: placed in the first state A first direction of resistance value magnetically coupled to the MTJ device of the SHE electrode, or a second direction of resistance value of the MTJ device magnetically coupled to the SHE electrode in a second state different from the first state.

Example 41 can include the element of example 40, wherein the method of selectively causing a write current to flow through the spin Hall effect electrode in a first direction, can include selectively causing the write current to pass from the source line through the first a transistor, passing the SHE electrode in the first direction, and passing through a membrane selector A method of flowing to a write bit line that is lower than the source line potential.

Example 42 can include the element of example 41, wherein selectively causing a write current to flow from the source line through the first transistor, through the SHE electrode in a first direction, and through the thin film selector to a lower potential than the source line A method of writing a bit line, comprising selectively causing a write current of at least 100 μA to pass from a source line through a first transistor, through a SHE electrode in a first direction, and through a thin film selector to a source line potential A low method of writing bit lines.

Example 43 can include any of the elements of example 41 or 42, wherein selectively causing a write current to flow from the source line through the first transistor, through the SHE electrode in a first direction, and through the thin film selector to the source A method of writing a bit line with a low line potential, comprising selectively causing a write current to pass from a source line through a first transistor, a first direction through a SHE electrode, and through a thin film at a maximum of 10 nanoseconds (ns) The selector flows to a write bit line that has a lower potential than the source line.

Example 44 can include the element of example 40, wherein the method of selectively causing a write current to flow through the spin Hall effect electrode in a second direction can include selectively causing the write current to pass from the write bit line The thin film selector, the method of flowing through the SHE electrode in the second direction, and flowing through the first transistor to a source line having a lower potential than the write bit line.

Example 45 can include the component of example 44, wherein selectively causing a write current to flow from the write bit line through the thin film selector, through the SHE electrode in the second direction, and through the first transistor to the write bit a method of a source line having a low line potential, which may include selectively causing at least A write current of 100 μA flows from the write bit line through the thin film selector, through the SHE electrode in the second direction, and through the first transistor to a source line having a lower potential than the write bit line.

Example 46 can include any of the elements of example 44 or 45, wherein selectively causing write current to flow from the write bit line through the thin film selector, through the SHE electrode in the second direction, and through the first transistor A method of writing a source line having a low potential of a bit line, which may include selectively causing a write current to be maximally 10 nanoseconds (ns) from a write bit line through a film selector, passing in a second direction The SHE electrode, and a method of flowing through the first transistor to a source line having a lower potential than the write bit line.

Example 47 can include the elements of example 40, and can additionally include a method of selectively reading binary values from an MRAM cell that includes an MTJ coupled to the SHE electrode.

Example 48 can include the element of example 47, wherein the method of selectively reading a binary value from the MRAM cell MTJ can selectively cause a read current to pass from the read bit line through the MTJ, through the SHE electrode, and through the A method of flowing a transistor to a source line.

The terms and expressions used herein are used to describe and not to limit the terms, and the use of such terms and expressions are not intended to exclude and describe any equivalents of the features (or portions thereof) and It will be understood that various modifications are possible within the scope of the patent application. Therefore, the scope of the patent application is intended to cover all such equivalents.

100‧‧‧Magnetoresistive random access memory location cells

110‧‧‧Magnetic tunnel junction device

112‧‧‧ free magnetic layer

114‧‧‧Fixed magnetic layer

116‧‧‧Oxide

122‧‧‧钌

124‧‧‧cobalt/iron

126‧‧‧anti-magnetic layer

130‧‧‧ Spin Hall Effect (SHE) Electrode

132‧‧‧First end

134‧‧‧second end

140‧‧‧ source line

142‧‧‧Read bit line

144‧‧‧Write bit line

146‧‧‧ word line

150‧‧‧First transistor

152‧‧‧Diffusion area

154‧‧‧Electrical structure

155‧‧‧ gate

156‧‧‧Diffusion area

158‧‧‧Electrical structure

160‧‧‧Film Selector

Claims (25)

A transistor, a selector, a magnetic tunnel junction (1T-1S-1MTJ), a spin torque transfer (STT), a spin Hall effect (SHE) magnetoresistive random access memory (MRAM) device, Including: a spin Hall effect (SHE) electrode; a first transistor; a thin film selector; and a magnetic tunnel junction (MTJ) device, wherein the MTJ device includes the conductive coupling to the thin film to the first transistor The position between the conductive couplings of the selector is electrically coupled to the free magnetic layer of the SHE electrode. The 1T-1S-1MTJ-STT-SHE MRAM device of claim 1, wherein the first transistor is electrically coupled between the SHE electrode and the source line, the first transistor borrowing Controlled by the word line; and wherein the thin film selector is electrically coupled between the SHE electrode and the write bit line. The 1T-1S-1MTJ-STT-SHE MRAM device of claim 1, wherein the first transistor is electrically coupled between the SHE electrode and the write bit line, the first The crystal is controlled by a write actuation line; and wherein the thin film selector is electrically coupled between the SHE electrode and the source line. 1T-1S-1MTJ-STT- as described in item 1 of the patent application scope A SHE MRAM device in which the MTJ device includes a fixed magnetic layer that is electrically coupled to a read bit line. The 1T-1S-1MTJ-STT-SHE MRAM device of claim 1, wherein the SHE electrode comprises a SHE material having a first end and an opposite second end; wherein the first electrical A crystal is conductively coupled to the first end of the SHE electrode; and wherein the thin film selector is conductively coupled to the second end of the SHE electrode. The 1T-1S-1MTJ-STT-SHE MRAM device of claim 1, wherein the first transistor, the SHE electrode, and the thin film selector form a reversible circuit during a write operation. The 1T-1S-1MTJ-STT-SHE MRAM device according to claim 6, wherein a current in the first direction passes through the SHE electrode in the MTJ device to be fixed in the MTJ device The magnetic parallel alignment places the free magnetic state, the MTJ device is placed in a low resistance state; and the current in a second direction opposite the first direction passes through the SHE electrode in the MTJ device, in which Current in the first direction passes through the SHE electrode in the MTJ device to place the free magnetism in anti-parallel alignment with the fixed magnetic field in the MTJ device, which places the MTJ device in a high resistance state. The 1T-1S-1MTJ-STT-SHE MRAM device according to claim 1, wherein the SHE electrode comprises β-钽 (β- Ta), β-tungsten (β-W), platinum (Pt), or copper (Cu). The 1T-1S-1MTJ-STT-SHE MRAM device of claim 8, wherein the SHE electrode comprises one or more dopants selected from the group consisting of: 铱, 铋, any 3D congener element, any 4D congener element, any 5D congener element, any 4F congener element, any 5F congener element, silver, gold, copper, and platinum. The 1T-1S-1MTJ-STT-SHE MRAM device of claim 1, wherein the SHE electrode comprises an elliptical patterned MTJ device having a width and a length. The 1T-1S-1MTJ-STT-SHE MRAM device according to claim 1, wherein the film selector comprises at least one of: a single layer yttrium oxide (NbO ₂ ) film selector or a multilayer NbO ₂ film selector . A transistor, a selector, a magnetic tunnel junction (1T-1S-1MTJ), a spin torque transfer (STT), and a spin Hall effect (SHE) magnetoresistive random access memory (MRAM) method, The method includes forming a first transistor having a source region, a drain region, and a gate region. Forming a source line in the first metal layer; electrically coupling the source region of the first transistor to the source line; forming a SHE electrode; electrically coupling the drain region of the first transistor to the SHE An electrode; forming an MTJ device comprising a free magnetic layer and a fixed magnetic layer; electrically coupling the free magnetic layer of the MTJ device to the SHE Forming a write bit line; forming a read bit line in the second metal layer; forming a thin film selector electrically conductively coupling the thin film selector between the SHE electrode and to the write bit line; The fixed magnetic layer of the MTJ device is conductively coupled to the read bit line. The 1T-1S-1MTJ-STT-SHE MRAM method of claim 12, further comprising: electrically coupling the gate region of the first transistor to a word line. The 1T-1S-1MTJ-STT-SHE MRAM method according to claim 12, wherein the free magnetic layer electrically conductively coupled to the MTJ device to the SHE electrode comprises: in the first transistor A point between the drain region and the thin film selector electrically couples the free magnetic layer of the MTJ device to the SHE electrode. The 1T-1S-1MTJ-STT-SHE MRAM method of claim 12, further comprising: electrically coupling a free magnetic layer of at least one additional MTJ device to the SHE electrode. The 1T-1S-1MTJ-STT-SHE MRAM method of claim 12, wherein forming the MTJ device comprises forming a substantially elliptical MTJ device having a length and a width. 1T-1S-1MTJ- as described in item 12 of the patent application scope The STT-SHE MRAM method, in which the SHE electrode is formed, comprises: forming a SHE electrode comprising β-钽 (β-Ta), β-tungsten (β-W), platinum (Pt), or copper (Cu). The 1T-1S-1MTJ-STT-SHE MRAM method according to claim 17, wherein forming the SHE electrode further comprises: forming a SHE electrode comprising one or more blends selected from the group consisting of Miscellaneous: 铱, 铋, any 3D congener, any 4D congener, any 4D congener, any 5F congener, silver, gold, copper, and platinum. The 1T-1S-1MTJ-STT-SHE MRAM method according to claim 12, wherein forming the thin film selector comprises: forming at least one: a single layer of niobium oxide (NbO ₂ ) film selector or a plurality of layers of NbO ₂ film Selector. A transistor, a selector, a magnetic tunnel junction (1T-1S-1MTJ), a spin torque transfer (STT), and a spin Hall effect (SHE) magnetoresistive random access memory (MRAM) method, Including: selectively writing a binary value to an MRAM cell, the MTJ coupled to the SHE electrode by causing a write current to flow through the SHE electrode in any of the following directions: a first direction, which is placed first The resistance value of the MTJ device magnetically coupled to the SHE electrode in the state; or the second direction, the resistance value of the MTJ device magnetically coupled to the SHE electrode in a second state different from the first state. The 1T-1S-1MTJ-STT-SHE MRAM method according to claim 20, wherein the write current is selectively caused to flow through the spin Hall effect electrode in the first direction, which comprises: selectively The write current is caused to flow from the source line through the first transistor, through the SHE electrode in the first direction, and through the thin film selector to a write bit line having a lower potential than the source line. The 1T-1S-1MTJ-STT-SHE MRAM method according to claim 21, wherein the write current is selectively caused to flow through the spin Hall effect electrode in the second direction, which comprises: selectively Causing the write current to flow from the write bit line through the thin film selector, through the SHE electrode in the second direction, and through the first transistor to a source having a lower potential than the write bit line Polar line. A transistor (1T), a selector (1S), a magnetic tunnel junction (1MTJ), a spin torque transfer (STT), a spin Hall effect (SHE), a magnetoresistive random access memory (MRAM) a system comprising: a method of selectively writing a binary value to an MRAM cell, the MTJ coupled to the SHE electrode by causing a write current to flow through the SHE electrode in any of the following directions: a first direction, a resistance value of the MTJ device that is magnetically coupled to the SHE electrode in a first state; or a second direction that is placed in an MTJ device that is magnetically coupled to the SHE electrode in a second state different from the first state Resistance value. 1T-1S-1MTJ- as described in item 23 of the patent application scope An STT-SHE MRAM system, in which a method of selectively causing a write current to flow through a spin Hall effect electrode in a first direction, comprising: selectively causing the write current to flow from a source line through a first A crystal, a method of flowing through the SHE electrode in the first direction, and a write bit line having a lower potential than the source line through the thin film selector. The 1T-1S-1MTJ-STT-SHE MRAM system of claim 23, wherein the method of selectively causing a write current to flow through the spin Hall effect electrode in the second direction comprises: selecting Sexually causing the write current to flow from the write bit line through the thin film selector, through the SHE electrode in the second direction, and through the first transistor to a lower potential than the write bit line The method of the source line.