TW201639048A - Manufacturing method of lead frame structure - Google Patents
Manufacturing method of lead frame structure Download PDFInfo
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- TW201639048A TW201639048A TW104113405A TW104113405A TW201639048A TW 201639048 A TW201639048 A TW 201639048A TW 104113405 A TW104113405 A TW 104113405A TW 104113405 A TW104113405 A TW 104113405A TW 201639048 A TW201639048 A TW 201639048A
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- lead frame
- barrier layer
- plating
- carrier
- fabricating
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000010410 layer Substances 0.000 claims abstract description 58
- 238000007747 plating Methods 0.000 claims abstract description 52
- 238000000034 method Methods 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 229920000642 polymer Polymers 0.000 claims abstract description 26
- 239000011247 coating layer Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims description 46
- 238000001723 curing Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 4
- 239000003960 organic solvent Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000013007 heat curing Methods 0.000 claims description 3
- 229920005992 thermoplastic resin Polymers 0.000 claims description 3
- 239000002103 nanocoating Substances 0.000 claims 1
- 238000009713 electroplating Methods 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
Description
本發明是有關於一種導線架結構的製作方法，且特別是有關於一種導線架結構形成金屬鍍層的製作方法。 The present invention relates to a method of fabricating a leadframe structure, and more particularly to a method of fabricating a metallization of a leadframe structure.
近年來，隨著電子技術的日新月異，高科技電子產業的相繼問世，使得更人性化、功能更佳的電子產品不斷地推陳出新，並朝向輕、薄、短、小的趨勢設計。就晶片構裝的技術而言，每一顆由晶圓(wafer)切割所形成的裸晶片(die)，例如以導線接合(wire bonding)或覆晶接合(flip chip bonding)等方式，而配置於一承載器之表面，其中此承載器例如為導線架或基板等，而晶片之主動表面則具有多個接合墊，使得晶片之接合墊得以經由承載器之傳輸線路及接點，而電性連接至外部之電子裝置。 In recent years, with the rapid development of electronic technology, the high-tech electronics industry has come out one after another, making more humanized and better-functioning electronic products constantly innovating and designing towards light, thin, short and small trends. In the art of wafer fabrication, each die formed by wafer dicing is configured, for example, by wire bonding or flip chip bonding. On the surface of a carrier, wherein the carrier is, for example, a lead frame or a substrate, and the active surface of the wafer has a plurality of bonding pads, so that the bonding pads of the wafer can pass through the transmission lines and contacts of the carrier, and the electrical properties are Connect to an external electronic device.
圖2繪示習知的一種導線架結構形成金屬鍍層的方法示意圖。一般而言，導線架的製作會先於其電鍍表面上電鍍一層金屬鍍層，使導線架具有較好的可焊性、導線鍵結能力、抗腐蝕性以及抗氧化性。此電鍍製程的習知流程可如圖2所示之先將具有 多個引腳226的導線架220設置於一膠帶300上，使膠帶300覆蓋導線架220(引腳226)的底面224，再對此導線架220進行電鍍，電鍍完成後再撕除膠帶300。然而，此種製程的膠帶300為耗材而無法重複利用，無形中增加了製作成本，並且，此種製程很容易因膠帶300移除不完全而導致有殘膠殘留於導線架220底面224的問題，或是因膠帶300未緊密貼合導線架220的底面224而導致導線架220的底面224還是被電鍍到。再者，由於膠帶300係整片式地貼覆於導線架220的底面224，引腳226間的間隙G皆為膠帶300所覆蓋住，使得導線架220上下為不流通的，因此易形成氣泡，且電鍍液中的氣泡很容易積存於引腳226間的間隙G之間(如圖2的虛線箭頭所示)，因而導致電鍍不完全的情形。 2 is a schematic view showing a conventional method for forming a metal plating layer on a lead frame structure. In general, the lead frame is fabricated by plating a metal coating on the surface of the lead, so that the lead frame has good solderability, wire bonding ability, corrosion resistance and oxidation resistance. The conventional process of this electroplating process can be as shown in FIG. 2 The lead frame 220 of the plurality of pins 226 is disposed on a tape 300 such that the tape 300 covers the bottom surface 224 of the lead frame 220 (pin 226), and then the lead frame 220 is plated, and the tape 300 is peeled off after the plating is completed. However, the tape 300 of such a process is a consumable material and cannot be reused, which inevitably increases the manufacturing cost, and the process is easy to cause the residual glue to remain on the bottom surface 224 of the lead frame 220 due to incomplete removal of the tape 300. Or, because the tape 300 does not closely fit the bottom surface 224 of the lead frame 220, the bottom surface 224 of the lead frame 220 is still plated. Moreover, since the tape 300 is attached to the bottom surface 224 of the lead frame 220 in a whole piece, the gap G between the pins 226 is covered by the tape 300, so that the lead frame 220 is not circulated up and down, so bubbles are easily formed. And the bubbles in the plating solution are easily accumulated between the gaps G between the leads 226 (as indicated by the dashed arrows in Fig. 2), thus causing incomplete plating.
本發明提供一種導線架結構的製作方法，其製程的良率較高，更可節省製作的成本。 The invention provides a method for manufacturing a lead frame structure, which has a high yield of a process and can save the manufacturing cost.
本發明的導線架結構的製作方法包括下列步驟。首先，提供一金屬基板。接著，對金屬基板進行一圖案化製程，以形成一導線架。導線架具有一電鍍表面以及一底面。接著，提供一載板。接著，形成一高分子塗料層於載板上。接著，將導線架設置於載板上，使高分子塗料層沾附於底面而形成一阻障層，阻障層覆蓋底面。接著，移除載板。接著，以阻障層作為電鍍罩幕對導線架進行一電鍍製程，以形成一金屬鍍層於電鍍表面。接著，移 除阻障層。 The method of fabricating the leadframe structure of the present invention includes the following steps. First, a metal substrate is provided. Next, a metallization process is performed on the metal substrate to form a lead frame. The lead frame has a plated surface and a bottom surface. Next, a carrier plate is provided. Next, a polymer coating layer is formed on the carrier. Next, the lead frame is placed on the carrier, and the polymer coating layer is adhered to the bottom surface to form a barrier layer, and the barrier layer covers the bottom surface. Next, remove the carrier. Then, the lead frame is subjected to an electroplating process using the barrier layer as a plating mask to form a metal plating layer on the plating surface. Then move In addition to the barrier layer.
在本發明的一實施例中，上述的高分子塗料層的材料包括熱塑性樹脂。 In an embodiment of the invention, the material of the polymer coating layer comprises a thermoplastic resin.
在本發明的一實施例中，上述的導線架包括多個引腳，引腳之間各以一間隙隔離。 In an embodiment of the invention, the lead frame includes a plurality of pins, and the pins are separated by a gap.
在本發明的一實施例中，上述的阻障層完全覆蓋引腳之底面。 In an embodiment of the invention, the barrier layer completely covers the bottom surface of the pin.
在本發明的一實施例中，上述的阻障層暴露出間隙。 In an embodiment of the invention, the barrier layer exposes a gap.
在本發明的一實施例中，上述的移除阻障層的步驟更包括以有機溶劑去除阻障層。 In an embodiment of the invention, the step of removing the barrier layer further comprises removing the barrier layer with an organic solvent.
在本發明的一實施例中，上述的形成阻障層的步驟更包括使高分子塗料層沾附於底面之後，對高分子塗料層進行一固化製程以形成阻障層。 In an embodiment of the invention, the step of forming the barrier layer further comprises: after the polymer coating layer is adhered to the bottom surface, performing a curing process on the polymer coating layer to form the barrier layer.
在本發明的一實施例中，上述的固化製程包括常溫固化、加熱固化或紫外光固化。 In an embodiment of the invention, the curing process includes ambient temperature curing, heat curing or ultraviolet curing.
在本發明的一實施例中，上述的圖案化製程包括蝕刻製程。 In an embodiment of the invention, the patterning process described above includes an etching process.
在本發明的一實施例中，上述的載板包括一金屬板或一絕緣薄板。 In an embodiment of the invention, the carrier board comprises a metal plate or an insulating sheet.
基於上述，本發明的導線架結構的製作方法是先將高分子塗料層塗佈於載板上，再將導線架設置於載板上，以使高分子塗料層沾附於導線架的底面而形成覆蓋導線架的底面的阻障層， 之後，再以阻障層作為電鍍罩幕對導線架進行電鍍而形成金屬鍍層於導線架的電鍍表面上。如此，由於阻障層是以沾附的方式形成於導線架的底面上，故阻障層可暴露引腳之間以及引腳與晶片座之間的間隙，因此，之後在進行電鍍製程時，電鍍液可順利通過引腳之間以及引腳與晶片座之間的間隙，氣泡不易形成，進而使導線架除了被阻障層所覆蓋的底面以外的電鍍表面皆能均勻地浸泡到電鍍液，因此可避免習知中電鍍液內的氣泡積存於引腳之間導致電鍍不均勻的問題。此外，亦可避免習知中膠帶未緊密貼合，使得電鍍液流入膠帶與導線架的底面之間，而在部份之底面也形成金屬鍍層的情形。 Based on the above, the lead frame structure of the present invention is formed by first coating a polymer coating layer on a carrier board, and then placing the lead frame on the carrier board so that the polymer coating layer is adhered to the bottom surface of the lead frame. Forming a barrier layer covering the bottom surface of the lead frame, Thereafter, the lead frame is plated with the barrier layer as a plating mask to form a metal plating on the plating surface of the lead frame. Thus, since the barrier layer is formed on the bottom surface of the lead frame in an adhesive manner, the barrier layer can expose a gap between the leads and between the leads and the wafer holder, and thus, after performing the electroplating process, The plating solution can smoothly pass through the gap between the pins and between the pins and the wafer holder, and the bubbles are not easily formed, so that the plating surface of the lead frame except the bottom surface covered by the barrier layer can be uniformly immersed in the plating solution. Therefore, it is possible to avoid the problem that the bubbles in the plating solution are accumulated between the pins in the prior art, resulting in uneven plating. In addition, it is also possible to avoid the case where the tape is not tightly bonded, so that the plating solution flows between the tape and the bottom surface of the lead frame, and a metal plating layer is formed on the bottom surface of the portion.
此外，本發明的載板可重複使用，因而可減少本發明的耗材，更可降低製作成本。並且，阻障層可輕易移除而可避免習知中膠帶撕除不完全而於導線架上留有殘膠的問題。因此，本發明的導線架結構的製作方法確實可有效提升製程良率以及降低製作成本。 In addition, the carrier of the present invention can be reused, thereby reducing the consumables of the present invention and reducing the manufacturing cost. Moreover, the barrier layer can be easily removed to avoid the problem that the tape is not completely removed and the residual glue remains on the lead frame. Therefore, the manufacturing method of the lead frame structure of the present invention can effectively improve the process yield and reduce the manufacturing cost.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.
100‧‧‧導線架結構 100‧‧‧ lead frame structure
110‧‧‧金屬基板 110‧‧‧Metal substrate
120、220‧‧‧導線架 120, 220‧‧‧ lead frame
122‧‧‧電鍍表面 122‧‧‧ plating surface
124、224‧‧‧底面 124, 224‧‧‧ bottom
126、226‧‧‧引腳 126, 226‧‧‧ pin
128‧‧‧晶片座 128‧‧‧ Wafer holder
130‧‧‧載板 130‧‧‧ Carrier Board
140‧‧‧高分子塗料層 140‧‧‧ polymer coating
142‧‧‧阻障層 142‧‧‧Barrier layer
150‧‧‧金屬鍍層 150‧‧‧Metal plating
300‧‧‧膠帶 300‧‧‧ Tape
G‧‧‧間隙 G‧‧‧ gap
圖1A至圖1F是依照本發明的一實施例的一種導線架結構的製作方法的示意圖。 1A-1F are schematic views of a method of fabricating a leadframe structure in accordance with an embodiment of the present invention.
圖2繪示習知的一種導線架結構形成金屬鍍層的方法示意圖。 2 is a schematic view showing a conventional method for forming a metal plating layer on a lead frame structure.
有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之各實施例的詳細說明中，將可清楚的呈現。以下實施例中所提到的方向用語，例如：「上」、「下」、「前」、「後」、「左」、「右」等，僅是參考附加圖式的方向。因此，使用的方向用語是用來說明，而並非用來限制本發明。並且，在下列各實施例中，相同或相似的元件將採用相同或相似的標號。 The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the embodiments of the invention. The directional terms mentioned in the following embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only directions referring to the additional schema. Therefore, the directional terminology used is for the purpose of illustration and not limitation. Also, in the following embodiments, the same or similar elements will be given the same or similar reference numerals.
圖1A至圖1F是依照本發明的一實施例的一種導線架結構的製作方法的示意圖。本實施例的導線架結構的製作方法包括下列步驟。首先，提供如圖1A所示的一金屬基板110。舉例來說，金屬基板110可為一金屬薄片，其材質可包括銅、銅合金或是其他適合的金屬材料。 1A-1F are schematic views of a method of fabricating a leadframe structure in accordance with an embodiment of the present invention. The manufacturing method of the lead frame structure of this embodiment includes the following steps. First, a metal substrate 110 as shown in FIG. 1A is provided. For example, the metal substrate 110 can be a metal foil, and the material thereof can include copper, copper alloy or other suitable metal materials.
接著，對金屬基板110進行一圖案化製程，以形成如圖1B所示的一導線架120，並且，導線架120具有一電鍍表面122以及一底面124。在本實施例中，電鍍表面122可為導線架120除了底面124以外的其他表面，而所謂的圖案化製程可例如為蝕刻製程。詳細而言，導線架120可包括多個引腳126以及一晶片座128。引腳126可環繞晶片座128設置，並且，引腳126之間以及引腳126與晶片座128之間如圖1B所示係各以間隙G隔離開， 並例如透過多個連接桿(未繪示)連接引腳126與晶片座128，其中，引腳126之間的間隙G的距離可不同於引腳126與晶片座128之間的間隙G的距離。當然，本實施例僅用以舉例說明，本發明並不限制導線架的形式。 Next, a metallization process is performed on the metal substrate 110 to form a lead frame 120 as shown in FIG. 1B, and the lead frame 120 has a plating surface 122 and a bottom surface 124. In the present embodiment, the plating surface 122 may be other surfaces than the bottom surface 124 of the lead frame 120, and the so-called patterning process may be, for example, an etching process. In detail, the leadframe 120 can include a plurality of pins 126 and a wafer holder 128. The pins 126 can be disposed around the wafer holder 128, and the gaps G are separated between the pins 126 and between the pins 126 and the wafer holder 128 as shown in FIG. 1B. And connecting the pin 126 and the wafer holder 128 through a plurality of connecting rods (not shown), for example, wherein the distance G between the pins 126 may be different from the distance G between the pins 126 and the wafer holder 128. . Of course, this embodiment is for illustrative purposes only, and the present invention does not limit the form of the lead frame.
請接續參照圖1C以及圖1D，提供一載板130。在本實施例中，載板130可為金屬板或絕緣薄板，當然，本發明並不侷限載板130的種類。接著，再形成一高分子塗料層140於載板130上。在本實施例中，高分子塗料層140可為熱塑性樹脂，當然，本實施例僅用以舉例說明，本發明並不侷限高分子塗料層140的種類。之後，再將導線架120設置於載板130上，使載板130上的高分子塗料層140沾附於導線架120的底面124，之後，可例如對高分子塗料層140進行一固化製程，以形成阻障層142。在本實施例中，固化製程可例如為常溫固化、加熱固化或紫外光固化，當然，本發明並不限制固化的方法，在一實施例中，亦可不特別對高分子塗料層140執行固化製程，而讓高分子塗料層140自然風乾而形成覆蓋底面124的阻障層142。上述的阻障層142均勻地覆蓋導線架120的底面124，並暴露出引腳126之間以及引腳126與晶片座128之間的間隙G。之後，再移除載板130。 Referring to FIG. 1C and FIG. 1D, a carrier 130 is provided. In the present embodiment, the carrier 130 may be a metal plate or an insulating thin plate. Of course, the present invention does not limit the type of the carrier 130. Next, a polymer coating layer 140 is formed on the carrier 130. In the present embodiment, the polymer coating layer 140 may be a thermoplastic resin. Of course, this embodiment is for illustrative purposes only, and the present invention is not limited to the type of the polymer coating layer 140. Then, the lead frame 120 is placed on the carrier 130, and the polymer coating layer 140 on the carrier 130 is adhered to the bottom surface 124 of the lead frame 120. Thereafter, for example, the polymer coating layer 140 can be subjected to a curing process. A barrier layer 142 is formed. In this embodiment, the curing process may be, for example, room temperature curing, heat curing or ultraviolet curing. Of course, the present invention does not limit the curing method. In one embodiment, the curing process may not be performed on the polymer coating layer 140. The polymer coating layer 140 is naturally air dried to form a barrier layer 142 covering the bottom surface 124. The barrier layer 142 described above uniformly covers the bottom surface 124 of the leadframe 120 and exposes the gap G between the leads 126 and between the leads 126 and the wafer holder 128. Thereafter, the carrier 130 is removed.
在本實施例中，為使導線架120的底面124能完全被阻障層142所覆蓋，可將高分子塗料層140至少沾附於導線架120的底面124以及部份側壁，也就是說，本實施例可於載板130上塗佈厚度較厚的高分子塗料層140，使導線架120設置於載板130 上時，高分子塗料層140可如圖1D所示完全沾附導線架120的底面124並沾附至導線架120之引腳126與晶片座128的部份側壁，進而使形成的阻障層142可完全覆蓋導線架120的底面124並覆蓋引腳126與晶片座128的部份側壁。 In this embodiment, in order to completely cover the bottom surface 124 of the lead frame 120 by the barrier layer 142, the polymer coating layer 140 may be adhered to at least the bottom surface 124 of the lead frame 120 and some sidewalls, that is, In this embodiment, a thick polymer coating layer 140 is coated on the carrier 130, and the lead frame 120 is disposed on the carrier 130. In the upper case, the polymer coating layer 140 can completely adhere to the bottom surface 124 of the lead frame 120 as shown in FIG. 1D and adhere to the lead 126 of the lead frame 120 and a part of the sidewall of the wafer holder 128, thereby forming a barrier layer. 142 may completely cover the bottom surface 124 of the leadframe 120 and cover the leads 126 and portions of the sidewalls of the wafer holder 128.
請接續參照圖1E，以上述的阻障層142作為電鍍罩幕對導線架120進行一電鍍製程，以形成如圖1E的金屬鍍層150於電鍍表面122上。在本實施例中，由於阻障層142是以沾附的方式形成於導線架120的底面124上，因而可暴露出引腳126之間以及引腳126與晶片座128之間的間隙G，如此，在進行電鍍製程時，電鍍液即可順利通過引腳126之間以及引腳126與晶片座128之間的間隙G，進而使導線架120除了被阻障層142所覆蓋的底面124以外的電鍍表面122皆能均勻地浸泡到電鍍液，因此可避免習知中電鍍液內的氣泡積存於引腳之間導致電鍍不均勻的問題。 Referring to FIG. 1E, the lead frame 120 is subjected to an electroplating process using the barrier layer 142 as a plating mask to form a metal plating layer 150 on the plating surface 122 of FIG. 1E. In the present embodiment, since the barrier layer 142 is formed on the bottom surface 124 of the lead frame 120 in an adhesive manner, the gap G between the leads 126 and between the leads 126 and the wafer holder 128 can be exposed. Thus, during the electroplating process, the plating solution can smoothly pass through the gap G between the leads 126 and between the pins 126 and the wafer holder 128, thereby making the lead frame 120 besides the bottom surface 124 covered by the barrier layer 142. The plating surface 122 can be uniformly immersed in the plating solution, thereby avoiding the problem that the bubbles in the plating solution are accumulated between the pins and the plating is uneven.
請同時參照圖1E以及圖1F，接著，移除如圖1E所示的阻障層142，而形成如圖1F所示的導線架結構100。在本實施例中，移除阻障層142的方法可例如以有機溶劑來溶解並去除阻障層142。當然，本發明並不限制移除阻障層142的方法。 Referring to FIG. 1E and FIG. 1F simultaneously, the barrier layer 142 as shown in FIG. 1E is removed to form the leadframe structure 100 as shown in FIG. 1F. In the present embodiment, the method of removing the barrier layer 142 may dissolve and remove the barrier layer 142, for example, with an organic solvent. Of course, the present invention does not limit the method of removing the barrier layer 142.
綜上所述，本發明將高分子塗料層塗佈於載板上，再將導線架設置於載板上，以使高分子塗料層沾附於導線架的底面而形成覆蓋導線架的底面的阻障層，之後，再以阻障層作為電鍍罩幕對導線架進行電鍍而形成金屬鍍層於導線架的電鍍表面上。由 於阻障層是以沾附的方式形成於導線架的底面上，故阻障層可暴露出引腳之間以及引腳與晶片座之間的間隙，如此，之後在進行電鍍製程時，電鍍液可順利通過引腳之間以及引腳與晶片座之間的間隙，氣泡不易形成，進而使導線架除了被阻障層所覆蓋的底面以外的電鍍表面皆能均勻地浸泡到電鍍液，因此可避免習知中電鍍液內的氣泡積存於引腳之間導致電鍍不均勻的問題。此外，亦可避免習知中膠帶未緊密貼合，使得電鍍液流入膠帶與導線架的底面之間，而在部份之底面也形成金屬鍍層。 In summary, the present invention applies a polymer coating layer on a carrier board, and then places the lead frame on the carrier board so that the polymer coating layer adheres to the bottom surface of the lead frame to form a bottom surface covering the lead frame. The barrier layer is then plated with a barrier layer as a plating mask to form a metal plating on the plating surface of the lead frame. by The barrier layer is formed on the bottom surface of the lead frame in an adhesive manner, so that the barrier layer can expose a gap between the leads and between the pins and the wafer holder, and then, after performing the electroplating process, plating The liquid can smoothly pass through the gap between the pins and between the pins and the wafer holder, and the bubbles are not easily formed, so that the plating surface of the lead frame except the bottom surface covered by the barrier layer can be uniformly immersed in the plating solution, It is possible to avoid the problem that the bubbles in the plating solution are accumulated between the pins in the prior art, resulting in uneven plating. In addition, it is also possible to prevent the tape from being intimately bonded so that the plating solution flows between the tape and the bottom surface of the lead frame, and a metal plating layer is also formed on the bottom surface of the portion.
並且，本發明的載板可重複使用，因而可減少本發明的耗材，更可降低製作成本。此外，阻障層可透過例如有機溶劑來移除，亦可避免膠帶撕除不完全而於導線架上留有殘膠的情形。因此，本發明的導線架結構的製作方法確實可達到提升製程良率以及降低製作成本的功效。 Moreover, the carrier of the present invention can be reused, so that the consumables of the present invention can be reduced, and the manufacturing cost can be reduced. In addition, the barrier layer can be removed by, for example, an organic solvent, or it can be avoided that the tape is not completely removed and the residual glue remains on the lead frame. Therefore, the manufacturing method of the lead frame structure of the present invention can achieve the effects of improving the process yield and reducing the manufacturing cost.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
122‧‧‧電鍍表面 122‧‧‧ plating surface
124‧‧‧底面 124‧‧‧ bottom
126‧‧‧引腳 126‧‧‧ pin
128‧‧‧晶片座 128‧‧‧ Wafer holder
142‧‧‧阻障層 142‧‧‧Barrier layer
G‧‧‧間隙 G‧‧‧ gap
Claims (10)
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| Application Number | Priority Date | Filing Date | Title |
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| TW104113405A TWI625799B (en) | 2015-04-27 | 2015-04-27 | Manufacturing method of lead frame structure |
| CN201510356927.3A CN106206325B (en) | 2015-04-27 | 2015-06-25 | Manufacturing method of lead frame structure |
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| Application Number | Priority Date | Filing Date | Title |
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| TW104113405A TWI625799B (en) | 2015-04-27 | 2015-04-27 | Manufacturing method of lead frame structure |
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| TW201639048A true TW201639048A (en) | 2016-11-01 |
| TWI625799B TWI625799B (en) | 2018-06-01 |
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| TWI224836B (en) * | 2003-09-26 | 2004-12-01 | Shin-Guo Hung | Semiconductor carrying board, its manufacturing method, and semiconductor packaging device |
| TWI262587B (en) * | 2005-03-08 | 2006-09-21 | Yi-Ling Jang | Leadframe and the manufacturing method thereof |
| JP2007051336A (en) * | 2005-08-18 | 2007-03-01 | Shinko Electric Ind Co Ltd | Method for forming metal sheet pattern and circuit board |
| CN101499427A (en) * | 2008-01-29 | 2009-08-05 | 菱生精密工业股份有限公司 | Semiconductor packaging method |
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| TW201025463A (en) * | 2008-12-25 | 2010-07-01 | Powertech Technology Inc | Manufacturing process of a leadless semiconductor package process and its structure |
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