TW201606326A - Chip testing system for accessing memory through scan chain and method thereof - Google Patents

Abstract

The invention relates to a chip testing system for accessing a memory through a scan chain and a method thereof. It comprises a value scanning module, a bus interface module, a clock multiplexer and a controller. The value scanning module is provided with at least one first scan chain for inputting an operating frequency, test information and outputting a test result for chip testing; a scan controller for selecting the operating frequency; and a strobe for outputting a control signal to transmit the test information. The bus interface module is provided with a second scan chain for inputting the operating frequency, the testing information and outputting the result. The clock multiplexer receives the test information output by the value scanning module or the bus interface module. The controller receives the test information and transmits it to a memory so that the test information can be grabbed by a target element to proceed with an electrical test. Accordingly, the electrical test and the difficulty of yield verification can be simplified.

Description

Wafer test system for scanning memory to scan memory and method thereof

The present invention relates to a wafer test system and method for accessing memory by scan chain, and more particularly to a wafer test system and method for editing memory contents on a wafer in a faster and simpler manner, thereby simplifying The difficulty of electrical testing and yield verification of the wafer.

According to the system-on-chip (SoC) to realize complex semiconductor system architecture has become the main trend of integrated circuit (IC) design, the system single chip design needs to integrate more on the one hand. An Intelligent Property (IP) is on a single system chip. On the other hand, it needs to be verified by electrical test and yield to confirm that the process of the single chip meets the design requirements. It is not easy to synthesize the process of integrating the single chip with the integrated system, and it is a challenge to confirm whether the system single chip is able to operate correctly after the completion of the manufacturing.

In the verification process of the system single chip, the traditional sequence circuit usually needs several clock cycles to specify the nodes inside the circuit to be tested to the required value during the electrical test. However, this step often causes electrical Difficulties in testing; using scanning test techniques Improve the testability of the circuit under test. Scan design is a structural circuit design method that can effectively reduce the complexity of functional testing. The scanning architecture can make all or part of the circuit under test positive. The D-type flip-flops (DFF) are replaced by scan D-type flip-flops. The main design principle is to add a multiplexer to the input of the original DEF. That is, a scan DEF is formed, and the scan chain is a series of scan dFFs, which are tested by an external automatic test equipment (ATE) through the scan chain. The pattern is sent to the circuit under test for testing. The traditional method of using the scan chain to test or verify the chip is done by the Joint Test Action Group (JTAG) technology, which mainly connects all the registers into one. After a plurality of scan chains, the test values are sequentially written into the scratchpad, and then the circuit performs operations and tests, and finally the results are swept out to achieve good controllability and observation. However, such a method has a low operation speed and cannot effectively achieve high test coverage in the at-speed testing, and it is difficult for the circuit to perform a large amount of data operations; in addition, the current execution frequency of the wafer can usually reach megahertz. The frequency level of (GHz), and the external automatic test machine (ATE), which is responsible for controlling the scan chain and reaching the megahertz level of execution frequency, is usually too expensive, often increasing the cost of the overall wafer test and verification, and the test time it takes. It is also relatively large; therefore, in order to test and verify wafers or bare crystals in a quick and easy manner, it is easier for wafer developers to perform many wafer testing and wafer function verification on an automatic test machine (ATE). And the function of wafer diagnostics, which can greatly increase the amount of calculations performed, simplify the difficulty of testing and verification, and save the time and money of wafer verification, testing and diagnosis. It is still the design and development of wafers today. Industry or researchers need to continue to work hard to overcome and solve important issues.

Now, the inventor is considering the above-mentioned traditional wafer electrical test and yield verification system. Due to the low computational speed and the inability to achieve high test coverage and high test frequency in the scan delay test, it is a tireless spirit and is supported by its rich professional knowledge and years of practical experience. Improvements have been made, and the present invention has been developed based on this.

The main object of the present invention is to provide a crystal for accessing a memory by a scan chain. A chip test system and method thereof, in particular, a wafer test system and method for editing memory contents on a wafer in a faster and easier manner, in a faster and easier manner, writing a program or data into a memory for a wafer Test, verification, and manufacturing defects and diagnostics make it easier for wafer developers to perform silicon wafer testing, wafer functional verification, and wafer diagnostics on the test bench to simplify wafer electrical testing and The difficulty of yield verification.

In order to achieve the above-mentioned implementation purpose, the inventors propose a scan chain pair memory The body access wafer testing system includes at least one numerical scanning module, a bus interface module, a clock multiplexer, and a controller; the numerical scanning module includes at least one first scanning chain, and a a scan controller, and a flash frequency observer, wherein at least one first scan chain inputs the operating frequency and test information required for the wafer test, and outputs the test result, and the scan controller is used to select the operating frequency, and the flash frequency observer system Outputting a control signal to transmit test information; the bus interface module includes at least a second scan chain, the second scan chain is used to input the working frequency and test information required for the wafer test, and output test results; clock multiplexing The device is electrically connected to the numerical scanning module and the bus interface module, and the clock multiplexer receives the test information outputted by one of the numerical scanning module or the bus interface module; and the controller is electrically connected. a pulse multiplexer and a memory, the controller receives the test information transmitted by the clock multiplexer and transmits it to the memory, waiting for the target component to grab and advance Wafer electrical test.

The wafer test system for accessing memory by scan chain as described above, wherein the numerical scan module determines that the memory system is controlled by the bus interface module or by at least one of the first scan chains.

The wafer test system for accessing memory by scan chain as described above, wherein the operating frequency is one of a system operating frequency (SCLK) or a scanning frequency (TCK).

The wafer test system for accessing memory by scan chain as described above, wherein the test information includes an electrical test data and an address data.

The wafer test system for accessing memory by scan chain as described above, wherein the numerical scan module is further provided with an input register, and the input register is electrically connected to the scan controller and the clock multiplexer. The utility model is configured to temporarily store the electrical test data input by the at least one first scan chain and transmit the data to the clock multiplexer.

The wafer test system for accessing memory by scan chain as described above, wherein the numerical scan module is further provided with an address register, and the address register is electrically connected to the scan controller and the clock multiplexer. The address data input by the at least one first scan chain is temporarily stored and transmitted to the clock multiplexer.

The wafer test system for accessing memory by scan chain as described above, wherein the numerical scan module may further be provided with an output register, and the output register is electrically connected to the clock multiplexer and the scan controller. It is used to temporarily store the test result output by the memory and pass it to the scan controller.

In addition, in order to achieve the above-mentioned implementation of the wafer test system for scan chain-to-memory access, the inventors have developed the following implementation techniques. First, a scan controller in a numerical scanning module is used to select at least one a scan chain input operating frequency and at least The test information input to the first scan chain is transmitted to the flash frequency observer in the numerical scanning module; then, the test information required for the wafer test is transmitted to the one-clock multiplexer, the clock multiplexer using the flash frequency observer The test information from a bus interface module is shielded, and only the test information from the numerical scanning module is allowed to be transmitted to a memory through a controller; finally, the target component in the wafer is self-obtained to the memory capture station. The test information is required, and a test result is written into the memory, and the test result is output through the clock multiplexer and the numerical scanning module.

a wafer test method for accessing a memory by a scan chain as described above, wherein The frequency of the system is one of a system operating frequency or a scanning frequency, and the test information includes an electrical test data and an address data.

a wafer test method for accessing a memory by scan chain as described above, wherein The value scanning module can further be provided with an input register, an address register, and an output register, and the input register is electrically connected to the scan controller and the clock multiplexer for temporarily storing At least one electrical test data input by the first scan chain, the address register is electrically connected to the scan controller and the clock multiplexer for temporarily storing the address data input by the at least one first scan chain, and outputting the temporary storage The device is electrically connected to the clock multiplexer and the scan controller for temporarily storing the test result output by the memory.

Thereby, the wafer test system and the side thereof with the scan chain-to-memory access method of the present invention The system provides a faster and easier way to write programs or data into memory for electrical testing of wafers, yield verification, or manufacturing defects and diagnostics. The invention can also be used in bare state. Verification, making it easier for wafer developers to perform the functions of wafer testing, wafer functional verification, and wafer diagnostics on the testing machine, thereby simplifying the difficulty of electrical testing and yield verification of the wafer; Wafer test system for accessing memory by scan chain and its square The biggest difference between the method and the traditional wafer test method lies in the object to which the test data is written. The conventional technology writes the data into the scratchpad of the wafer, and the system and method of the present invention writes the data into the memory in the wafer. The present invention is mainly used to solve the shortcomings of the conventional technology that it is difficult to perform a large number of operations, and can effectively increase the amount of execution of the system, thereby reducing the cost of wafer manufacturing and improving the yield of the wafer; The wafer test system and method for scanning memory to memory access are based on a common scan chain of traditional electrical test, so as to build a platform for the user to edit the memory content freely, so the wafer can Corresponding actions are performed according to the user's arrangement, and test diagnosis and function verification are performed. Since the present invention allows the target components of the chip core to capture the required programs and materials, it does not require an expensive test machine. Achieving the purpose of wafer testing; finally, the invention relates to a wafer testing system and method method for scanning chain-to-memory access With the software self-test program, it can effectively achieve the function of wafer error diagnosis, let the designer know the location of the circuit error in the chip, and carefully locate the cause of the error, the foundry can locate the error according to the diagnosis result. The location of the occurrence and the detection of possible process problems effectively solve the problem of increasing the yield of the wafer.

(1)‧‧‧Numerical Scanning Module

(11)‧‧‧First scan chain

(12)‧‧‧ scan controller

(13)‧‧‧Flashing observer

(14)‧‧‧Input register

(15)‧‧‧Address register

(16)‧‧‧Output register

(2) ‧‧‧ bus interface module

(21)‧‧‧Second scan chain

(3) ‧ ‧ clock multiplexer

(4) ‧ ‧ controller

(5) ‧‧‧ memory

(S1)‧‧‧Step one

(S2)‧‧‧Step 2

(S3) ‧ ‧ Step 3

The first figure: a test system configuration block diagram of a preferred embodiment of the wafer test system for scanning chain-to-memory access of the present invention

The second figure: a block diagram of a numerical scanning module configuration of a preferred embodiment of a wafer test system for scanning chain-to-memory access

The third figure: the flow chart of the method for testing the wafer by scan chain to memory in the present invention

The purpose of the present invention and the structural design advantages thereof will be based on the following drawings The preferred embodiment is illustrated to provide a more in-depth and specific understanding of the invention.

First, please refer to the first and second figures, which is a scan chain pair memory for the present invention. A test system configuration block diagram and a numerical scanning module configuration block diagram of a preferred embodiment of the wafer test system, wherein the wafer test system for scanning the memory to the memory includes: a numerical scanning module ( 1) comprising at least one first scan chain (11), a scan controller (12), and a flash frequency observer (13), wherein at least one first scan chain (11) is required for input wafer test Frequency and test information, and output test results, the scan controller (12) is used to select the operating frequency, and the flash frequency observer (13) outputs a control signal to transmit test information; in a preferred embodiment of the present invention The input operating frequency is a system operating frequency or a scanning frequency, and the test information includes an electrical test data and an address data; and a bus interface interface. The module (2) includes a second scan chain (21), the second scan chain (21) is an input frequency and test information required for inputting a wafer test, and an output test result; in a preferred embodiment of the present invention In the example The input operating frequency is a system operating frequency or a scanning frequency, and the test information includes an electrical test data and an address data; a clock multiplexer (3), Electrically connected to the numerical scanning module (1) and the bus interface module (2), the clock multiplexer (3) receives the numerical scanning module (1) or the bus interface module (2), etc. An output test information is transmitted and transmitted; and a controller (4) is electrically connected to the clock multiplexer (3) and a memory (5). The controller (4) receives the test information of the clock multiplexer (3) and transmits it to the memory (5) for the target component to be grabbed and the electrical test of the wafer.

In addition, the numerical scanning module (1) determines that the memory (5) is connected by the bus interface mode. Group (2) or controlled access by at least one of the first scan chains (11) to shoulder the role of the arbitrator function of the memory (5) resource usage.

Furthermore, the numerical scanning module (1) can further be provided with an input register (14) The input register (14) is electrically connected to the scan controller (12) and the clock multiplexer (3) for temporarily storing the electrical test input by the at least one first scan chain (11). Data and pass to the clock multiplexer (3).

In addition, the numerical scanning module (1) may further be provided with an address register (15) The address register (15) is electrically connected to the scan controller (12) and the clock multiplexer (3) for temporarily storing the address data input by the at least one first scan chain (11). And passed to the clock multiplexer (3).

Furthermore, the numerical scanning module (1) can further be provided with an output register (16), the output register (16) is electrically connected to the clock multiplexer (3) and the scan controller (12) for temporarily storing the test result output by the memory (5) and transmitting it to the scan. Controller (12).

In addition, in order to enable the review board to have a deeper and more specific understanding of the present invention, please Referring to the third figure, the flow chart of the method for testing the wafer by scan chain to memory is the following steps: Step 1 (S1): using a numerical scanning module (1) The scan controller (12) selects the operating frequency input by the at least one first scan chain (11), and transmits the test information input by the at least one first scan chain (11) to the flash in the numerical scanning module (1) The frequency observer (13); in a preferred embodiment of the present invention, the operating frequency is input to the system operating frequency or a scanning frequency by at least one first scanning chain (11), and the testing information system Including an electrical test data And one address data; step two (S2): using the flash frequency observer (13) to transfer the test information required for the wafer test to a clock multiplexer (3), the clock multiplexer (3) is shielded from one The test information of the bus interface module (2) allows only the test information from the numerical scanning module (1) to be transmitted to a memory (5) via a controller (4); and step 3 (S3): The target component in the wafer is self-obtained to the memory (5) to capture the required test information, and a test result is written into the memory (5), and then via the clock multiplexer (3) and the numerical scanning module. (1) Output the test results.

Furthermore, the numerical scanning module (1) can further be provided with an input register (14), an address register (15), and an output register (16), the input register (14) is electrically connected to the scan controller (12) and the clock multiplexer (3), For temporarily storing electrical test data input by at least one first scan chain (11), the address register (15) is electrically connected to the scan controller (12) and the clock multiplexer (3) for The address data input by the at least one first scan chain (11) is temporarily stored, and the output register (16) is electrically connected to the clock multiplexer (3) and the scan controller (12) for temporarily storing The test result of the output of the memory (5).

In addition, the wafer test system for scanning memory to memory access using the present invention The method and the method can quickly realize the test diagnosis and verification of the multi-core processor, wherein the operating frequency and the test information can be input by using at least one first scan chain (11) of the present invention before the system of the four-core processor is started. To the numerical scanning module (1), and then transferred to the memory (5) via the clock multiplexer (3) and the controller (4), so that the target component of the quad core processor grabs itself to the memory (5) Take the required test information to start self-test. After the test is completed, pass the test result to the external test machine through the bus bridge to let the external test machine read correctly.

It can be seen from the above description that the present invention has the following advantages in comparison with the prior art by the scan chain-to-memory access wafer test system and the method thereof:

1. The present invention provides a faster and easier way to write programs or data into a memory by means of a scan chain-to-memory access wafer test system and method for wafer electrical testing, yield verification or The invention can also be used in the verification of the bare state, so that the wafer developer can more easily perform the functions of the wafer test, the wafer function verification, and the wafer diagnosis on the test machine. Simplify the difficulty of electrical testing and yield verification of wafers.

2. The biggest difference between the wafer test system and the method for scanning memory to memory access in the present invention is that the test data is written in the object, and the conventional technology writes the data into the scratchpad of the wafer. The system and method of the present invention writes data into the memory and the scratchpad in the wafer. Therefore, the present invention is mainly for solving the shortcomings of the conventional technology that it is difficult to perform a large number of operations, and can effectively improve the amount of execution of the system. , thereby reducing the cost of wafer manufacturing and increasing the yield of wafer output.

3. The wafer test system and method for scanning memory to memory in the present invention are based on a scan chain commonly used in conventional electrical testing to build a platform for users to edit memory contents at will, so the wafer The corresponding actions can be performed according to the user's arrangement, and the test diagnosis and function verification can be performed. Since the present invention allows the target components of the chip core to automatically capture the required programs and materials, there is no need for a high-cost test machine. The purpose of wafer testing can be achieved.

4. The wafer test system and method for scanning memory to memory access in the present invention can be combined with a software self-test program to effectively achieve the function of wafer error diagnosis, allowing design Knowing the location of the circuit error in the chip and carefully locating the cause of the error, the foundry can locate the location of the error and detect the possible process problems according to the diagnosis result, effectively solving the improvement of the wafer yield. .

In summary, the wafer test system and method for the scan chain-to-memory access method of the present invention can achieve the intended use efficiency by the above disclosed embodiments, and the present invention has not been disclosed before the application. , Cheng has fully complied with the requirements and requirements of the Patent Law.爰Issuing an application for a patent for invention in accordance with the law, and asking for a review, and granting a patent, is truly sensible.

The illustrations and descriptions of the present invention are merely preferred embodiments of the present invention, and are not intended to limit the scope of the present invention; those skilled in the art, which are characterized by the scope of the present invention, Equivalent variations or modifications are considered to be within the scope of the design of the invention.

(1)‧‧‧Numerical Scanning Module

(11)‧‧‧First scan chain

(2) ‧‧‧ bus interface module

(21)‧‧‧Second scan chain

(3) ‧ ‧ clock multiplexer

(4) ‧ ‧ controller

(5) ‧‧‧ memory

Claims (10)

A wafer testing system for accessing memory by scan chain includes: a numerical scanning module comprising at least one first scan chain, a scan controller, and a flash frequency observer, wherein the at least one a scan chain is used to input the operating frequency and test information required for the wafer test, and output the test result, the scan controller is used to select the operating frequency, and the flash frequency observer outputs a control signal to transmit the test information; a bus interface module includes at least a second scan chain, the second scan chain is used to input the operating frequency and test information required for the wafer test, and output test results; a clock multiplexer is electrically connected a numerical scanning module and the bus interface module, the clock multiplexer receiving test information outputted by one of the numerical scanning module or the bus interface module; and a controller Connecting the clock multiplexer and a memory, the controller receives the test information transmitted by the clock multiplexer and transmits the test information to the memory for the target component to be captured Electrical testing of the wafer. The wafer test system for scanning chain-to-memory access as described in claim 1, wherein the numerical scanning module determines that the memory system is from the bus interface module or the at least one first scan chain One of them controls access. A wafer test system for scanning chain-to-memory access as described in claim 1 wherein the operating frequency is one of a system operating frequency or a scanning frequency. A wafer test system for scanning chain-to-memory access as described in claim 1 wherein the test information is an electrical test data and an address data. The wafer test system for scanning chain-to-memory access according to claim 1, wherein the numerical scanning module is further provided with an input register, wherein the input register is electrically connected to the scan control. And the clock multiplexer for temporarily storing the electrical test data input by the at least one first scan chain and transmitting the electrical test data to the clock multiplexer. The wafer test system for scanning chain-to-memory access according to claim 1, wherein the numerical scanning module is further provided with an address register, wherein the address register is electrically connected to the scan control. And the clock multiplexer for temporarily storing the address data input by the at least one first scan chain and transmitting the address data to the clock multiplexer. The wafer test system for scanning chain-to-memory access according to claim 1, wherein the numerical scanning module is further provided with an output register, wherein the output register is electrically connected to the clock. The multiplexer and the scan controller are configured to temporarily store the test result output by the memory and transmit the test result to the scan controller. A wafer testing method for accessing memory by scan chain, the steps of which include: Step 1: using a scan controller in a numerical scanning module to select an operating frequency input by at least one first scan chain, and transmitting test information input by the at least one first scan chain to the flash in the numerical scanning module Frequency observer; Step 2: The test information required for the wafer test is transmitted to a clock multiplexer using the flash frequency observer, and the clock multiplexer shields test information from a bus interface module, and only allows The test information from the numerical scanning module is transmitted to a memory via a controller; and step 3: the target component in the wafer is self-obtained to the memory to acquire the required test information, and a test result is written. The test result is outputted through the clock multiplexer and the numerical scanning module. The method for testing a wafer by scan chain-to-memory access as described in claim 8 wherein the operating frequency is one of a system operating frequency or a scanning frequency, and the test information is an electrical property. Test data and one address data. The method for testing a wafer for scanning chain-to-memory access as described in claim 8 wherein the numerical scanning module is further provided with an input register, an address register, and an output register. The input register is electrically connected to the scan controller and the clock multiplexer for temporarily storing electrical test data input by the at least one first scan chain, and the address register is electrically connected. The scan controller and the clock multiplexer for temporarily storing the input by the at least one first scan chain The address data is electrically connected to the clock multiplexer and the scan controller for temporarily storing the test result output by the memory.