TW201531851A - Light controlling system and electronic device having same - Google Patents

Abstract

The present invention provides a light controlling system which is used on a HDD backplane. The light controlling system includes a light, a CPLD module, a PCH module, and a buffer. The CPLD module controls the light and is electrically connected to the light via the buffer. The PCH module is electrically connected to the buffer. When a system of the electronic device starts, the PCH module cuts off the buffer to cut off a connection between the light and the CPLD module, which make the light in a state of off. When the electronic device enters an operation system, the PCH conducts the buffer, the light reconnects to the CPLD module. An electronic device having the light controlling system is also disclosed.

Description

Indicator light control system and electronic device

The present invention relates to an indicator light control system, and more particularly to an indicator light control system for a hard disk drive (HDD) backplane and an electronic device using the same.

In the server, it is often necessary to simultaneously access multiple HDDs on the HDD backplane to achieve large-capacity storage of data. Generally, each HDD is provided with two indicator lights on the HDD backplane to indicate the working state of the HDD, including an in-position indicator and an error indicator. Usually, the error indicator is controlled by a Complex Programmable Logic Device (CPLD) on the HDD. However, when the server is booted into the operating system, the CPLD often has difficulty controlling the error light before the system enters the operable state, so the error light often appears in the state of the server during startup. It is easy to give the user a wrong guiding instruction, which causes the user to misunderstand that the HDD is abnormal, and the status indication is ambiguous.

In view of the above, it is necessary to provide an indicator control system that allows the indicator to accurately indicate the status.

In addition, an electronic device to which the indicator control system is applied is also provided.

An indicator light control system is applied to a hard disk (HDD) backplane of an electronic device, the indicator control system includes a complex programmable logic device (CPLD) module and an indicator light, and the CPLD module is used to control the indication The state of the light. The indicator control system further includes an integrated south bridge (PCH) module and a buffer. The CPLD module is electrically connected to the indicator light through the buffer, and the PCH module is further electrically connected to the buffer. After the system of the electronic device is started, before entering the operating system, the PCH module controls the buffer to be turned off, so that the indicator light is not controlled by the CPLD module, so that the indicator light is in an off state; when the electronic device enters the operating system The PCH module controls the buffer to be turned on, so that the indicator light is again controlled by the CPLD module.

An electronic device includes a motherboard, an HDD backplane, and the indicator light control system described above.

The indicator control system prevents the indicator light from being turned off by controlling the buffer to be off during the period from the start of the electronic device to the operating system, thereby avoiding the situation that the indicator light is erroneously illuminated during the startup of the electronic device. Make the indicator status of the indicator light more accurate.

1 is a schematic diagram of an indicator light control system in accordance with an embodiment of the present invention.

Referring to FIG. 1, a preferred embodiment of the present invention provides an indicator light control system 100 for use on a hard disk drive (HDD) backplane 1 of an electronic device. The indicator control system 100 can be operated after the electronic device system is started, that is, after the power is turned on. The indicator control system 100 is used to control an indicator light 10. The indicator light control system 100 includes the indicator light 10, a Complex Programmable Logic Device (CPLD) module 20, an integrated South Bridge (Platform Controller Hub (PCH) module 30, and a basic input output system (Basic Input Output). System, BIOS) module 40 and buffer 50. The indicator light 10, the CPLD module 20, and the buffer 50 are disposed on the HDD backplane 1. The PCH module 30 and the BIOS module 40 are disposed on the main board 2 of the electronic device.

One end of the indicator light 10 is electrically connected to a power source P3V3 through a first resistor R1, and the other end is electrically connected to the buffer 50. In this embodiment, the indicator light 10 is a light-emitting diode, and an anode thereof is electrically connected to the power source P3V3 through the first resistor R1, and a cathode thereof is electrically connected to the buffer 50. The indicator light 10 is used to indicate an error status of a corresponding HDD connected to the HDD backplane 1. When the HDD is abnormal, the indicator light 10 is in a bright state; when the HDD is in a normal state, the indicator light 10 is in an off state.

The CPLD module 20 includes a control pin LED that controls the indicator light 10 , and the control pin LED is electrically connected to the indicator light 10 through the buffer 50 . When the corresponding HDD connected to the HDD backplane 1 is abnormal, for example, because the connector of the HDD and the HDD backplane 1 is poorly connected, and the HDD is not detected, the CPLD module 20 transmits the control. The pin LED sends a control signal to the indicator light 10, and the state of the indicator light 10 is turned off. It can be understood that when the HDD returns to normal, the CPLD module 20 no longer sends a control signal, and the state of the indicator light 10 is turned off.

The PCH module 30 includes a general purpose input output (GPIO) pin for controlling the buffer 50. The GPIO pin is electrically connected to the buffer 50 through a second resistor R2. The GPIO pin is used to output an enable control signal to the buffer 50 to control the on or off state of the buffer 50.

The BIOS module 40 is electrically connected to the PCH module 30 for writing an output level to a register corresponding to the GPIO pin to control an output level of the GPIO pin. In this embodiment, after the electronic device system is booted up to enter the operating system, the BIOS module 40 writes a high level to the GPIO pin; after the electronic device enters the operating system, the BIOS module 40 The GPIO pin is written low.

The buffer 50 includes a first pin P1, a second pin P2, a third pin P3, a fourth pin P4, and a fifth pin P5. The first pin P1 is electrically connected to the GPIO pin through the second resistor R2, and the first pin P1 is an enable control pin. The second pin P2 is electrically connected to the control pin LED. The third pin P3 is electrically connected to the indicator light 10, and is also electrically connected to the power source P3V3 through a third resistor R3. The fourth pin P4 is electrically connected to a power source P5V, and is also grounded through a capacitor C1. The fifth pin P5 is grounded. When the first pin P1 receives a high level, the buffer 50 is turned off, and the indicator light 10 is not controlled by the CPLD module 20; when the first pin P1 receives a low level, the The buffer 50 is turned on, and the indicator light 10 is restored to be controlled by the CPLD module 20.

Before the electronic device system enters the operating system, the BIOS module 40 writes a high level to the corresponding register of the GPIO pin, and the PCH module outputs a high level to the buffer through the GPIO pin. The first pin P1 of the device 50 is turned off at this time, and the indicator light 10 is not controlled by the CPLD module 20, so that the indicator light 10 is always off. After the electronic device enters the operating system, the BIOS module 40 writes a low level to the corresponding register of the GPIO pin, and the PCH module outputs a low level to the buffer 50 through the GPIO pin. The first pin P1, at which time the buffer 50 resumes conduction, and the indicator light 10 is restored to be controlled by the CPLD module 20. During operation of the operating system, the indicator light 10 can indicate the status of a corresponding HDD connected to the HDD backplane 1. When the corresponding HDD is abnormal, the CPLD module 20 passes through its control pin. The LED outputs a control signal to the indicator light 10 to make the indicator light 10 brighter, thereby giving an error.

The indicator light control system 100 prevents the indicator light 10 from being turned off by controlling the buffer 50 to be turned off during the period from the start of the electronic device to the operating system, thereby preventing the indicator light 10 from being highlighted during the startup of the electronic device. The situation of the indicator light 10 makes the indication state of the indicator light 10 more accurate.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be covered by the following claims.

100‧‧‧ indicator control system

1‧‧‧HDD backplane

2‧‧‧ motherboard

10‧‧‧ indicator light

20‧‧‧CPLD module

LED‧‧‧ control pin

30‧‧‧PCH module

40‧‧‧BIOS module

50‧‧‧ buffer

P1~P5‧‧‧first pin~fifth pin

R1~R3‧‧‧first resistance~third resistance

C1‧‧‧ capacitor

no

100‧‧‧ indicator control system

1‧‧‧HDD backplane

2‧‧‧ motherboard

10‧‧‧ indicator light

20‧‧‧CPLD module

LED‧‧‧ control pin

30‧‧‧PCH module

40‧‧‧BIOS module

50‧‧‧ buffer

P1~P5‧‧‧first pin~fifth pin

R1~R3‧‧‧first resistance~third resistance

C1‧‧‧ capacitor

Claims (10)

An indicator light control system is applied to a hard disk (HDD) backplane of an electronic device, the indicator control system includes a complex programmable logic device (CPLD) module and an indicator light, and the CPLD module is used to control the indication The improvement of the state of the lamp is that the indicator control system further includes an integrated south bridge (PCH) module and a buffer, and the CPLD module is electrically connected to the indicator light through the buffer, and the PCH module is further electrically Connected to the buffer, the PCH module controls the buffer to be turned off when the system of the electronic device is started, and before the operating system is entered, so that the indicator light is not controlled by the CPLD module, so that the indicator light is in an off state; After the electronic device enters the operating system, the PCH module controls the buffer to be turned on, so that the indicator light is again controlled by the CPLD module. The indicator light control system of claim 1, wherein the indicator light control system further comprises a basic input/output system (BIOS) module disposed on a main board of the electronic device, wherein the BIOS module is electrically connected. The PCH module is used to control the output level of the PCH module. The indicator light control system of claim 2, wherein the PCH module comprises a general purpose input/output (GPIO) pin, the GPIO pin is electrically connected to the buffer, and the BIOS module is in the GPIO. The pin writes the output level. For example, in the indicator light control system described in claim 3, when the system of the electronic device is started and before entering the operating system, the BIOS module writes a high level on the GPIO pin, and the PCH module transmits the The GPIO pin outputs a high level to the buffer to control the buffer to be turned off; when the electronic device enters the operating system, the BIOS module writes a low level on the GPIO pin, and the PCH module transmits the GPIO through the GPIO pin. The pin outputs a low level to the buffer to control the buffer to turn on. The indicator light control system of claim 4, wherein the indicator light is electrically connected to a first power source through a first resistor. The indicator light control system of claim 4, wherein the buffer comprises a first pin, a second pin, a third pin, a fourth pin, and a fifth pin, the first lead The pin is an enable control pin, and the first pin is electrically connected to the GPIO pin through a second resistor. The indicator light control system of claim 6, wherein the CPLD module includes a control pin electrically connected to the second pin of the buffer, and the third lead of the buffer The foot is electrically connected to the indicator light, and the CPLD module sends a control signal to the indicator light through the control pin. The indicator light control system of claim 7, wherein the third pin of the buffer is further electrically connected to the first power source through a third resistor, and the fourth pin of the buffer is electrically Connected to a second power source and also grounded through a capacitor; the fifth pin of the buffer is grounded. For example, in the indicator light control system described in claim 7, wherein the indicator light is controlled by the CPLD module, when the corresponding hard disk connected to the HDD backplane is abnormal, the CPLD module transmits the control. The pin output control signal to the indicator light causes the indicator to be turned off. When the corresponding hard disk connected to the HDD backplane is normal, the CPLD module does not output a control signal, and the indicator does not light. An electronic device comprising a main board and an HDD backplane, the improvement being that the electronic device comprises the indicator light control system according to any one of claims 1 to 9.