TW201523798A - IC substrate, semiconductor device with IC substrate and manufucturing method thereof - Google Patents

Abstract

This disclosure relates to an IC substrate. The IC substrate includes an interposer, a solder resist layer and an interposer substrate. The interposer substrate includes a first dielectric layer, a forth dielectric layer, a first conductive circuit layer, a forth conductive circuit layer and a fifth conductive circuit layer. The fifth conductive circuit layer, the forth dielectric layer, the forth conductive circuit layer, the first dielectric layer and the first conductive circuit layer are arranged in above described order. Each conductive circuit layer is electrically connected to the adjacent one via conductive holes in the adjacent dielectric layer. The formation of the conductive holes in the forth dielectric layer and that in the first dielectric layer are in contrary directions. The interposer is embedded in the first dielectric layer. Opposite sides of the interposer have a plurality of first electrical contact pads and a plurality of second electrical contact pads. Each first electrical contact pads is electrically connected to one second electrical contact pads respectively. The second electrical contact pads are adjacent to the first conductive circuit layer. A recess is formed from the fifth conductive circuit layer to the first dielectric layer. The recess runs through the fifth conductive circuit layer and the forth dielectric layer. The first electrical contact pads are exposed from the bottom of the recess. The disclosure also relates to a semiconductor device with the IC substrate and manufacturing method thereof.

Description

IC carrier board, semiconductor device having the same, and method of manufacturing the same

The present invention relates to an IC carrier, a semiconductor device having the IC carrier, and a method of fabricating the same.

With the increasing development of wafer technology, the line width and line spacing of the wires in the wafer are getting thinner and finer. In order to adapt the wire density of the carrier substrate carrying the wafer to the line pitch of the wafer, an interposer is generally used as the connection medium, but the overall thickness of the semiconductor device is increased because the interposer and the wafer electrically connected thereto protrude from the carrier substrate. It is not conducive to achieving thinning. In addition, the interposer protrudes from the carrier substrate and its electrical characteristics are susceptible to external influences.

In view of the above, it is necessary to provide an IC carrier board that overcomes the above problems, a semiconductor device having the IC carrier board, and a method of fabricating the same.

A method for fabricating an IC carrier board includes the steps of: providing a carrier substrate, wherein the carrier substrate comprises a first conductive circuit layer, a first dielectric layer and a first copper foil layer disposed in sequence, from the first conductive circuit layer The first dielectric layer is formed with a first recess, a portion of the first copper foil layer is exposed from the bottom of the recess; and an interposer is adhered to the first copper foil layer exposed from the first recess. a first electrical contact pad and a second electrical contact pad having a plurality of one-to-one electrical connections on opposite sides of the interposer, the first electrical contact pad being adjacent to the first copper foil layer; Forming a second dielectric layer on the surface of the first conductive circuit layer and the interposer, forming a second conductive circuit layer on the surface of the second dielectric layer, and forming a third conductive hole in the second dielectric layer. The second conductive circuit layer is electrically connected to the second electrical contact pad through the third conductive via; the first copper foil layer is formed into a fourth conductive circuit layer; formed on the fourth conductive circuit layer a fourth dielectric layer having a fifth conductive via and forming a surface on the surface of the fourth dielectric layer a conductive circuit layer; and forming a second recess from the fifth conductive circuit layer toward the first dielectric layer to expose the interposer, the plurality of first electrical contact pads from the second recess The groove is exposed.

A method for fabricating an IC carrier board includes the steps of: providing a substrate, the substrate comprising a carrier board, a first copper foil layer on opposite sides of the carrier board, and a side of the two first copper foil layers away from the carrier board a first dielectric layer; a first conductive wiring layer is formed on the first dielectric layer; a first recess is formed from the first conductive wiring layer to the first dielectric layer, and a portion of the first copper foil a layer is exposed from the bottom of the groove; an interposer is adhered on the first copper foil layer exposed from the first groove, and the first side of the interposer has a plurality of one-to-one corresponding electrical connections An electrical contact pad and a second electrical contact pad, the first electrical contact pad is adjacent to the first copper foil layer; and the second conductive layer is laminated on the first conductive circuit layer and the interposer Forming a second conductive circuit layer on the surface of the second dielectric layer, and forming a third conductive hole in the second dielectric layer, wherein the second conductive circuit layer passes through the third conductive hole and the Electrically connecting the second electrical contact pads; separating the first copper foil layer from the carrier plate; The first copper foil layer is formed into a fourth conductive circuit layer; a fourth dielectric layer having a fifth conductive via is formed on the fourth conductive wiring layer, and a fifth surface is formed on the surface of the fourth dielectric layer a conductive circuit layer; and forming a second recess from the fifth conductive circuit layer toward the first dielectric layer to expose the interposer, the plurality of first electrical contact pads from the second recess The groove is exposed.

A method of fabricating a semiconductor device, comprising the steps of: providing a carrier substrate, wherein the carrier substrate comprises a first conductive circuit layer, a first dielectric layer and a first copper foil layer disposed in sequence, from the first conductive circuit layer The first dielectric layer is formed with a first recess, a portion of the first copper foil layer is exposed from the bottom of the recess; and an interposer is adhered to the first copper foil layer exposed from the first recess. a first electrical contact pad and a second electrical contact pad having a plurality of one-to-one electrical connections on opposite sides of the interposer, the first electrical contact pad being adjacent to the first copper foil layer; Forming a second dielectric layer on the surface of the first conductive circuit layer and the interposer, forming a second conductive circuit layer on the surface of the second dielectric layer, and forming a third conductive hole in the second dielectric layer. The second conductive circuit layer is electrically connected to the second electrical contact pad through the third conductive via; the first copper foil layer is formed into a fourth conductive circuit layer; formed on the fourth conductive circuit layer a fourth dielectric layer having a fifth conductive via and on the surface of the fourth dielectric layer Forming a fifth conductive circuit layer; forming a second recess from the fifth conductive circuit layer toward the first dielectric layer to expose the interposer, the plurality of first electrical contact pads from the first a second groove is exposed; and a wafer is mounted in the groove, the wafer has a plurality of electrode pads on one side thereof, and the plurality of electrode pads are electrically connected to the first electrical contact pads through a conductive bump respectively In the thickness direction, the surface of the wafer away from the electrode pad does not extend beyond the surface of the fourth dielectric layer away from the fourth conductive wiring layer.

An IC carrier board includes an interposer, a solder mask, and an interposer carrier. The interposer board includes a fifth conductive circuit layer, a fourth dielectric layer, a fourth conductive circuit layer, a first dielectric layer, and a first conductive circuit layer that are sequentially contacted. Each of the conductive circuit layers is electrically connected to the adjacent conductive circuit layer through a conductive hole in the dielectric layer adjacent thereto. The conductive holes in the first dielectric layer are oriented in a hole opposite to the conductive holes in the fourth dielectric layer. The interposer is embedded in the first dielectric layer. The first and second electrical contact pads are electrically connected to each other on opposite sides of the interposer. The second electrical contact pad is located on a side of the interposer adjacent to the first conductive circuit layer. A recess is formed from the fifth conductive wiring layer toward the first dielectric layer. The recess extends through the fifth conductive circuit layer and the fourth dielectric layer to expose the interposer. The plurality of first electrical contact pads are exposed from the recess.

A semiconductor device includes an IC carrier board and a wafer, the IC carrier board including an interposer, a solder resist layer, and an interposer carrier board. The interposer board includes a fifth conductive circuit layer, a fourth dielectric layer, a fourth conductive circuit layer, a first dielectric layer, and a first conductive circuit layer that are sequentially contacted. Each of the conductive circuit layers is electrically connected to the adjacent conductive circuit layer through a conductive hole in the dielectric layer adjacent thereto. The conductive holes in the first dielectric layer are oriented in a hole opposite to the conductive holes in the fourth dielectric layer. The interposer is embedded in the first dielectric layer. The first and second electrical contact pads are electrically connected to each other on opposite sides of the interposer. The second electrical contact pad is located on a side of the interposer adjacent to the first conductive circuit layer. A recess is formed from the fifth conductive wiring layer toward the first dielectric layer. The recess extends through the fifth conductive circuit layer and the fourth dielectric layer to expose the interposer. The plurality of first electrical contact pads are exposed from the recess. The wafer has a plurality of electrode pads on one side. The plurality of electrode pads are electrically connected to the first electrical contact pads through a conductive bump. In the thickness direction, the surface of the wafer away from the electrode pad does not extend beyond the surface of the fourth dielectric layer away from the fourth conductive wiring layer.

The invention embeds the interposer in the IC carrier board, so that the interposer and the IC carrier board are integrated into one structure, on the one hand, the overall thickness after mounting the wafer is reduced, and on the other hand, the interposer is embedded in the IC carrier board. In the middle, it is closely connected to the IC carrier board and is less affected by the outside world.

10‧‧‧Semiconductor devices

100‧‧‧IC carrier board

110‧‧‧Substrate

111‧‧‧First conductive circuit layer

112‧‧‧First dielectric layer

113‧‧‧First copper foil layer

114‧‧‧Central District

115‧‧‧The surrounding area

116‧‧‧First groove

117‧‧‧ carrying board

1121‧‧‧First conductive hole

120‧‧‧Intermediary board

121‧‧‧First glass substrate

1211‧‧‧Second conductive hole

1212‧‧‧First conductive line

122‧‧‧First electrical contact pads

123‧‧‧Second electrical contact pads

124‧‧‧Dielectric film

130‧‧‧First copper-clad substrate

131‧‧‧Second dielectric layer

132‧‧‧Second copper foil layer

1311‧‧‧Three conductive holes

1321‧‧‧Second conductive circuit layer

141‧‧‧ Third dielectric layer

1421‧‧‧ Third conductive circuit layer

1411‧‧‧4th conductive hole

1131‧‧‧4th conductive layer

151‧‧‧4th dielectric layer

1521‧‧‧ fifth conductive circuit layer

1511‧‧‧5th conductive hole

160‧‧‧First solder mask

161‧‧‧ first opening

162‧‧‧First pad

170‧‧‧Second solder mask

171‧‧‧ second opening

172‧‧‧Second pad

173‧‧‧ third opening

180‧‧‧ Groove

181‧‧‧ openings

190‧‧‧ wafer

191‧‧‧electrode pad

192‧‧‧Electrical bumps

193‧‧‧ underfill

1 is a cross-sectional view of a substrate provided by an embodiment of the present invention.

2 is a cross-sectional view showing a first conductive wiring layer formed on the first dielectric layer of FIG. 1 and a plurality of first conductive vias formed in the first dielectric layer.

3 is a cross-sectional view of the first conductive wiring layer of FIG. 2 after forming a first recess into the first dielectric layer.

Figure 4 is a cross-sectional view showing the mounting of an interposer in the first recess of the carrier substrate shown in Figure 3.

5 is a cross-sectional view showing the first copper-clad material formed on the first conductive wiring layer of the carrier substrate shown in FIG. 4.

6 is a cross-sectional view showing a third conductive via and a second conductive via layer formed on the second dielectric layer shown in FIG. 5.

7 is a cross-sectional view showing a third dielectric layer and a third conductive wiring layer formed on the second conductive wiring layer shown in FIG. 6, and a fourth conductive via is formed in the third dielectric layer.

Figure 8 is a cross-sectional view showing the first copper foil layer shown in Figure 7 separated from the carrier sheet.

Figure 9 is a cross-sectional view showing the formation of a fourth conductive wiring layer on the first copper foil layer shown in Figure 8.

Figure 10 is a cross-sectional view showing the fourth dielectric layer and the fifth conductive wiring layer formed on the fourth conductive wiring layer shown in Figure 9.

Figure 11 is a cross-sectional view showing the formation of a first solder resist layer on the third conductive wiring layer shown in Figure 10 and the formation of a second solder resist layer on the fifth conductive wiring layer shown.

12 is a cross-sectional view of the IC carrier board obtained by removing a portion of the fourth dielectric layer and the second solder resist layer corresponding to the first dielectric layer shown in FIG. 11 and forming a second recess.

Figure 13 is a cross-sectional view of the semiconductor device obtained after mounting a wafer in the second recess shown in Figure 12 .

The present invention provides an IC carrier board 100 and a method of manufacturing the same according to the semiconductor device 10 having the IC carrier board. The specific steps are as follows:

In the first step, referring to FIG. 1, a substrate 110 is provided.

The substrate 110 includes a carrier plate 117, two first copper foil layers 113, and two first dielectric layers 112. The first copper foil layers 113 are respectively bonded to opposite sides of the carrier plate 117. The first dielectric layer 112 is located on the side of the first copper foil layer 113 away from the carrier plate 117. The substrate 110 includes a central region 114 and a peripheral region 115 surrounding the central region 114 (separated by dashed lines in the figure).

In the subsequent process, the second step to the eighth step are performed in both directions. For the convenience of description, the second step to the eighth step are all described by taking a single side as an example.

In the second step, referring to FIG. 2, a first conductive wiring layer 111 is formed on the first dielectric layer 112 of the peripheral region 115, and a plurality of first conductive vias 1121 are formed in the first dielectric layer 112. The first conductive circuit layer 111 is electrically connected to the first copper foil layer 113 through the first conductive vias 1121 .

Specifically, first, in the peripheral region 115, a plurality of first blinds are formed by laser ablation from the side of the first dielectric layer 112 away from the carrier plate 117 toward the first dielectric layer 112. Hole (not shown). The first blind via penetrates the first dielectric layer 112 to expose a portion of the first copper foil layer 113. Next, a plating barrier layer (not shown) having a patterned structure is formed on the first dielectric layer 112. The first blind via and a portion of the first dielectric layer 112 are exposed from the plating barrier. Then, the first blind via hole is formed by plating to form the first conductive via 1121, and is plated on the first conductive via 1121 away from the end of the first copper foil layer 113 and the exposed portion of the first dielectric layer 112. The first conductive wiring layer 111. Finally, the plating barrier is removed.

In the third step, referring to FIG. 3, a first recess 116 is formed in the central region 114 from the first conductive wiring layer 111 toward the first dielectric layer 112 to expose a portion of the first copper foil layer 113.

Specifically, first, an opening is formed along the boundary of the central region 114 and the peripheral region 115 from the side of the first dielectric layer 112 away from the carrier plate 117 toward the first dielectric layer 112 (not shown). . The opening is cut in thickness from the side of the first copper foil layer 113 away from the carrier plate 117. Then, the first dielectric layer 112 in the opening is removed to expose a portion of the first copper foil layer 113 to form the first recess 116.

In the fourth step, referring to FIG. 4, an interposer 120 is adhered to a portion of the first copper foil layer exposed by the first recess 116 through a dielectric film 124. The interposer 120 is received in the first recess. Inside the slot 116. The interposer 120 includes a first glass substrate 121 and a plurality of first electrical contact pads 122 and second electrical contact pads 123 exposed on opposite sides of the first glass substrate 121. A plurality of second conductive vias 1211 and a plurality of first conductive traces 1212 are formed in the first glass substrate 121. The plurality of second conductive holes 1211 are located at a side of the first glass substrate 121 away from the first copper foil layer 113, and each of the second conductive holes 1211 is away from the first copper foil layer 113. One end of the second conductive contact pad 123 is electrically connected to one end of the second conductive pad 1211. The one end of the second conductive via 1211 is electrically connected to a first conductive line 1212. The plurality of first conductive lines 1212 are located on the side of the first glass substrate 121 adjacent to the first copper foil layer 113, and each of the first conductive lines 1212 is adjacent to the first copper foil layer 113. One of the first electrical contact pads 122 is electrically connected. One end of each of the first conductive lines 1212 away from the first copper foil layer 113 is electrically connected to one end of the second conductive hole 1211 adjacent to the first copper foil layer 113 to achieve each of the The second electrical contact pads 123 are electrically connected to the corresponding one of the first electrical contact pads 122 through a second conductive via 1211 and a first conductive trace 1212.

In the fifth step, referring to FIG. 5, a first copper-clad substrate 130 is laminated on the first conductive circuit layer 111. The first copper-clad substrate 130 includes a second dielectric layer 131 and a second copper foil layer 132. The second dielectric layer 131 is located between the first conductive wiring layer 111 and the second copper foil layer 132. The second dielectric layer 131 covers the first conductive circuit layer 111, the first dielectric layer 112 exposed from the first conductive circuit layer 111, the second electrical contact pad 123, and the second electrical contact The pad 123 exposes the first glass substrate 121 and fills a gap between the first dielectric layer 112 and the interposer 120.

In a sixth step, referring to FIG. 6, a third conductive via 1311 is formed in the second dielectric layer 131 and a second conductive trace layer 1321 is formed on the second copper foil layer 132 side. The second conductive circuit layer 1321 is electrically connected to the first conductive circuit layer 111 and the second electrical contact pad 123 through the third conductive via 1311. A cross section of the third conductive via 1311 parallel to the second dielectric layer 131 gradually increases from the first conductive wiring layer 111 to the second conductive wiring layer.

Specifically, first, a plurality of first blind holes (not shown) are formed by laser ablation from the second copper foil layer 132 to the first conductive circuit layer 111 and the second electrical contact pad 123. The first blind via penetrates the second copper foil layer 132 and the second dielectric layer 131 to expose the second electrical contact pad 123 and a portion of the first conductive trace layer 111. Next, a plating barrier layer (not shown) having a patterned structure is formed on the second copper foil layer 132, and the first blind via and a portion of the second copper foil layer 132 are exposed from the plating barrier layer. Then, the first blind via hole is filled to form a third conductive via 1311, and the second conductive via 1311 is away from the first conductive trace layer 111 side and the exposed portion of the second copper foil layer 132. Plated with a layer of copper. Then, the plating barrier layer is removed to expose a portion of the second copper foil layer 132 that is blocked by it. Finally, the exposed portion of the second copper foil layer 132 is quickly etched away to form the second conductive wiring layer 1321. The second conductive circuit layer 1321 is electrically connected to the first conductive circuit layer 111 and the second electrical contact pad 123 through the third conductive via 1311.

In a seventh step, referring to FIG. 7, a third dielectric layer 141 is formed on the second conductive wiring layer 1321 and a third conductive wiring layer 1421 is formed on the surface of the third dielectric layer 141.

The third dielectric layer 141 is located between the second conductive wiring layer 1321 and the third conductive wiring layer 1421. The third dielectric layer 141 covers the second conductive wiring layer 1321 and the second dielectric layer 131 exposed from the second conductive wiring layer 1321. A plurality of fourth conductive vias 1411 are formed in the third dielectric layer 141. A cross section of the fourth conductive via 1411 parallel to the third dielectric layer 141 gradually increases from the second conductive wiring layer 1321 to the third conductive wiring layer 1421. The third conductive circuit layer 1421 is located away from the second conductive layer 1321 side of the third dielectric layer 141. The third conductive circuit layer 1421 and the second conductive circuit layer 1321 are electrically connected through the fourth conductive via 1411. The third conductive layer 1421 and the fourth conductive via 1411 are formed in the same manner as the second conductive via 1321 and the third conductive via 1311 in the third and fourth steps.

In the eighth step, referring to FIG. 8 and FIG. 9, each of the first copper foil layers 113 is separated from the carrier plate 117, and each of the first copper foil layers 113 is subjected to image transfer and etching. The method is to form the fourth conductive wiring layer 1131. The fourth conductive wiring layer 1131 is formed in the peripheral region 115. The fourth conductive circuit layer 1131 and the first conductive circuit layer 111 are electrically connected through the first conductive via 1121.

In the ninth step, referring to FIG. 10, a fourth dielectric layer 151 is formed on the fourth conductive wiring layer 1131, and a fifth conductive wiring layer 1521 is formed on the surface of the fourth dielectric layer 151. The fourth dielectric layer 151 is located between the fourth conductive circuit layer 1131 and the fifth conductive circuit layer 1521. The fourth dielectric layer 151 covers the fourth conductive wiring layer 1131, the first dielectric layer 112 and the dielectric film 124 exposed from the fourth conductive wiring layer 1131. The fourth dielectric layer 151 is formed with a plurality of fifth conductive vias 1511. A cross section of the fifth conductive via 1511 parallel to the fourth dielectric layer 151 gradually decreases from the fifth conductive wiring layer 1521 to the fourth conductive wiring layer 1131. The fifth conductive circuit layer 1521 and the fourth conductive circuit layer 1131 are electrically connected through the fifth conductive via 1511. A portion of the fifth conductive circuit layer 1521 corresponding to the central region 114 is not provided with a conductive line, that is, the fifth conductive circuit layer 1521 is formed on the fourth dielectric layer 151 corresponding to the peripheral region 115. It is away from the side surface of the fourth conductive wiring layer 1131. The fifth conductive circuit layer 1521 and the fifth conductive via 1511 are formed in the same manner as the second conductive circuit layer 1321 and the third conductive via 1311 in the third and fourth steps. It can be understood that the forming direction of the fifth conductive hole 1511 is opposite to the forming direction of the second conductive hole 1211, the third conductive hole 1311 and the fourth conductive hole.

In the tenth step, referring to FIG. 11, a first solder resist layer 160 is formed on the surface of the third conductive wiring layer 1421 and the second dielectric layer 131 exposed from the third conductive wiring layer 1421. The first solder resist layer 160 has a plurality of first openings 161, and the exposed portion of the third conductive trace layer 1421 forms a first pad 162. A second solder resist layer 170 is formed on the surface of the fifth conductive wiring layer 1521 and the fourth dielectric layer 151 exposed from the fifth conductive wiring layer 1521. The second solder resist layer 170 has a plurality of second openings 171 exposing a portion of the fifth conductive circuit layer 1521 to form a second pad 172.

In an eleventh step, referring to FIG. 12, a recess 180 is formed from the second solder resist layer 170 toward the first dielectric layer 112 to expose the first electrical contact pad 122.

Specifically, first, an opening 181 (not shown) is formed from the second solder resist layer 170 to the first dielectric layer 112 along the boundary between the central region 114 and the peripheral region 115. The opening 181 is cut off from the first conductive layer 111 side of the first dielectric layer 112 in the thickness direction. Then, the second solder resist layer 170, the fourth dielectric layer 151 and the dielectric film 124 in the opening 181 are removed to form a recess 180 to expose the interposer 120 and a portion of the first dielectric layer 112. The plurality of first electrical contact pads 122 are exposed from the recess 180 to obtain the IC carrier 100.

In a twelfth step, referring to FIG. 13, a wafer 190 is mounted in the recess 180. The wafer 190 is completely received in the recess 180. The wafer 190 has a plurality of electrode pads 191 on one side. The electrode pads 191 are electrically connected to the first electrical contact pads 122 through a conductive bump 192, respectively. The surface of the wafer 190 away from the electrode pad 191 does not extend beyond the surface of the fourth dielectric layer 151 away from the fourth conductive wiring layer 1131. Preferably, the gap between the electrode pad 191, the conductive bump 192 and the first electrical contact pad 122 is formed with an underfill 193 to prevent the wafer 190 from falling off.

So far, the fabrication of the semiconductor device 10 is completed.

It can be understood that after the completion of the eighth step, surface treatment may be performed on the exposed first pad 162 and second pad 172 to avoid oxidation of the surface of the pad, thereby affecting electrical characteristics. The surface treatment method may form a protective layer by means of electroless gold plating, electroless nickel plating, or the like, or form an organic solder resist film (OSP) on the solder pad.

It can be understood that the method for fabricating the IC carrier board provided by the technical solution may further include forming solder balls on the first pad 162 and the second pad 172 and electrically connecting the electrical component or the package through the solder ball. Body steps.

It can be understood that, in other embodiments, after the third step is completed, the first copper foil layer 113 can be separated from the carrier plate 117 to obtain two carrier substrates having the same structure. The carrier substrate includes a first copper foil layer 113, a first dielectric layer 112, and a first conductive wiring layer 111. The first copper foil layer 113 and the first conductive circuit layer 111 are located on opposite sides of the first dielectric layer 112 and are electrically connected through the first conductive holes 1121 in the first dielectric layer. A first recess 116 is formed in the first dielectric layer 112 from the first conductive wiring layer 111 to expose a portion of the first copper foil layer 113. The IC carrier 100 is then formed on the carrier substrate. Of course, one of the carrier substrates may also be directly provided, and then the IC carrier 100 may be formed thereon.

It can be understood that the opening 181 can be formed by fishing or laser cutting.

It can be understood that in other embodiments, the third dielectric layer 141 and the third conductive circuit layer 1421 may not be formed. At this time, the first solder resist layer 160 having a plurality of openings is formed directly on the second conductive wiring layer 1321. Of course, a new dielectric layer and a conductive circuit layer may be formed on the third conductive wiring layer 1421 and the fifth conductive wiring layer 1521.

It can be understood that, in other embodiments, an opening may be formed from the fifth conductive circuit layer 1521 toward the first dielectric layer 112 along the boundary between the central region 114 and the peripheral region 115 to remove the opening. After the fourth dielectric layer 151 and the dielectric film 124 are in the recess 180, a second solder resist layer 170 is formed on the fifth conductive wiring layer 1521. At this time, the second solder resist layer 170 has a third opening 173 in addition to the plurality of second openings 171 exposing a portion of the fifth conductive wiring layer 1521 to form the second pad 172. The third opening 173 corresponds to the recess 180 to expose the interposer 120 and a portion of the first dielectric layer 112.

It can be understood that, in this embodiment, the first copper foil layer 113 can be bonded to the carrier plate 117 through a bonding film.

Referring to FIG. 13 , the present technical solution further provides a semiconductor device 10 fabricated by the above method, which includes an IC carrier 100 and a wafer 190 .

The IC carrier board 100 includes a first conductive wiring layer 111, a first dielectric layer 112, a second conductive wiring layer 1321, a second dielectric layer 131, a third conductive wiring layer 1421, and a third dielectric layer 141. The fourth conductive wiring layer 1131, the fourth dielectric layer 151, the fifth conductive wiring layer 1521, the first solder resist layer 160, the second solder resist layer 170, and the interposer 120.

The first dielectric layer 112 is located between the fourth conductive circuit layer 1131 and the first conductive circuit layer 111, and is in contact with the fourth conductive circuit layer 1131 and the first conductive circuit layer 111, respectively. The first conductive circuit layer 111 and the fourth conductive circuit layer 1131 are electrically connected to each other through the first conductive holes 1121 in the first dielectric layer 112. The second dielectric layer 131 is located between the first conductive circuit layer 111 and the second conductive circuit layer 1321 and is in contact with the first conductive circuit layer 111 and the second conductive circuit layer 1321, respectively. The second conductive circuit layer 1321 and the first conductive circuit layer 111 are electrically connected through the third conductive hole 1311 in the second dielectric layer 131. The third dielectric layer is located between the second conductive circuit layer 1321 and the third conductive circuit layer 1421 and is in contact with the second conductive circuit layer 1321 and the third conductive circuit layer 1421. The second conductive circuit layer 1321 and the third conductive circuit layer 1421 are electrically connected through the fourth conductive hole 1411 in the third dielectric layer. The fourth dielectric layer 151 is located between the fourth conductive circuit layer 1131 and the fifth conductive circuit layer 1521 and is in contact with the fourth conductive circuit layer 1131, respectively. The fourth conductive circuit layer 1131 and the fifth conductive circuit layer 1521 are electrically connected through the fifth conductive hole 1511 in the fourth dielectric layer 151. The hole forming direction of the first conductive hole 1121, the third conductive hole 1311, and the fourth conductive hole 1411 is opposite to the hole forming direction of the fifth conductive hole 1511. That is, each of the first conductive vias 1121, the third conductive vias 1311, and the fourth conductive vias 1411 are parallel to the cross section of the corresponding dielectric layer from the side closer to the third conductive trace layer 1421 to the fifth conductive trace layer 1521. The side gradually decreases, and the cross section of each of the fifth conductive holes 1511 parallel to the fourth dielectric layer 151 gradually increases from the side closer to the third conductive wiring layer 1421 to the side closer to the fifth conductive wiring layer 1521. Increase.

The first solder resist layer 160 is formed on the third conductive wiring layer 1421. The first solder resist layer 160 has a plurality of first openings 161, and the exposed portion of the third conductive circuit layer 1421 forms a first pad 162; the second solder resist layer 170 is formed on the fifth conductive layer 1521. The second solder resist layer has a plurality of second openings 171, and the exposed portion of the fifth conductive wiring layer 1521 forms a second pad 172.

The interposer 120 is embedded in the first dielectric layer 112. The interposer 120 includes a first glass substrate 121 and a first electrical contact pad 122 and a second electrical contact pad 123 exposed on opposite sides of the first glass substrate 121. The first glass substrate 121 includes a plurality of first conductive lines 1212 and second conductive holes 1211 therein. The second conductive hole 1211 is located on the side of the first glass substrate 121 adjacent to the second electrical contact pad 123, and is adjacent to the second electrical contact pad 123 and the second electrical contact. The pad 123 is electrically connected. The second electrical contact pad 123 is electrically connected to the second conductive circuit layer 1321 through the third conductive via 1311 . The first conductive line 1212 is located in the first glass substrate 121 near the first electrical contact pad 122, and is adjacent to the end of the first electrical contact pad 122 and the first electrical The contact pads 122 are electrically connected. An end of the first conductive line 1212 away from the first electrical contact pad 122 is electrically connected to an end of the second conductive hole 1211 away from the second electrical contact pad 123 . The second electrical contact pad 123 and the first electrical contact pad 122 are electrically connected through a second conductive via 1211 and a first conductive trace 1212.

A recess 180 is formed from the second solder resist layer 170 toward the first dielectric layer 112. The recess 180 extends through the fourth dielectric layer 151, the fifth conductive wiring layer 1521, and the second solder resist layer 170 to expose the interposer 120 and a portion of the first dielectric layer 112. The plurality of first electrical contact pads 122 are exposed from the recess 180.

The wafer 190 is mounted in the recess 180. The wafer 190 is completely received in the recess 180. The wafer 190 has a plurality of electrode pads 191 on one side. Each of the electrode pads 191 is electrically connected to the first electrical contact pad 122 through a conductive bump 192. In the thickness direction, the surface of the wafer 190 away from the electrode pad 191 does not extend beyond the surface of the fourth dielectric layer 151 away from the fourth conductive wiring layer 1131. The gap between the electrode pad 191, the conductive bump 192 and the first electrical contact pad 122 is formed with an underfill 193 to prevent the wafer 190 from falling off.

It can be understood that the IC carrier 100 may not include the third dielectric layer 141 and the third conductive circuit layer 1421. At this time, the first solder resist layer 160 having the plurality of first openings 161 is formed on the second conductive wiring layer 1321.

It can be understood that the fifth conductive circuit layer 1521, the fourth dielectric layer 151, the fourth conductive circuit layer 1131, the first dielectric layer 112, the first conductive circuit layer 111, the second dielectric layer 131, and the The structure in which the two conductive wiring layers 1321, the third dielectric layer 141, and the third conductive wiring layer 1421 are sequentially stacked may be regarded as a carrier board of the interposer 120, that is, an interposer carrier. Of course, the interposer board may not include the second dielectric layer 131, the second conductive circuit layer, the third dielectric layer, and the third conductive circuit layer.

The invention embeds the interposer in the IC carrier board, so that the interposer and the IC carrier board are integrated into one structure, on the one hand, the overall thickness after mounting the wafer is reduced, and on the other hand, the interposer is embedded in the IC carrier board. In the middle, it is tightly connected to the IC carrier board and is less affected by the outside world.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

no

10‧‧‧Semiconductor devices

100‧‧‧IC carrier board

111‧‧‧First conductive circuit layer

112‧‧‧First dielectric layer

1121‧‧‧First conductive hole

120‧‧‧Intermediary board

121‧‧‧First glass substrate

1211‧‧‧Second conductive hole

1212‧‧‧First conductive line

122‧‧‧First electrical contact pads

123‧‧‧Second electrical contact pads

131‧‧‧Second dielectric layer

1311‧‧‧Three conductive holes

1321‧‧‧Second conductive circuit layer

141‧‧‧ Third dielectric layer

1421‧‧‧ Third conductive circuit layer

1411‧‧‧4th conductive hole

1131‧‧‧4th conductive layer

151‧‧‧4th dielectric layer

1521‧‧‧ fifth conductive circuit layer

1511‧‧‧5th conductive hole

160‧‧‧First solder mask

161‧‧‧ first opening

162‧‧‧First pad

170‧‧‧Second solder mask

171‧‧‧ second opening

172‧‧‧Second pad

180‧‧‧ Groove

190‧‧‧ wafer

191‧‧‧electrode pad

192‧‧‧Electrical bumps

193‧‧‧ underfill

Claims (10)

A method for manufacturing an IC carrier board, comprising the steps of:
Providing a carrier substrate, the carrier substrate includes a first conductive circuit layer, a first dielectric layer and a first copper foil layer disposed in sequence, and the first conductive layer is formed first from the first conductive layer a groove, a portion of the first copper foil layer is exposed from the bottom of the groove;
An interposer is adhered to the first copper foil layer exposed from the first recess, and the first and second electrical contacts of the first and second electrical contacts are electrically connected to each other on opposite sides of the interposer a pad, the first electrical contact pad is adjacent to the first copper foil layer;
Forming a second dielectric layer on the surface of the first conductive circuit layer and the interposer, forming a second conductive circuit layer on the surface of the second dielectric layer, and forming a third conductive layer in the second dielectric layer a second conductive circuit layer electrically connected to the second electrical contact pad through the third conductive hole;
Forming the first copper foil layer into a fourth conductive circuit layer;
Forming a fourth dielectric layer having a fifth conductive via on the fourth conductive wiring layer, and forming a fifth conductive wiring layer on the surface of the fourth dielectric layer; and from the fifth conductive wiring layer to the A dielectric layer forms a second recess to expose the interposer, and the plurality of first electrical contact pads are exposed from the second recess. The method for fabricating an IC carrier according to claim 1, wherein the first dielectric layer and the second conductive layer are formed on the first conductive circuit layer and the interposer, the first Before the copper foil layer is formed into the fourth conductive circuit layer, the method for fabricating the IC carrier further includes forming a third dielectric layer having a fourth conductive via on the second conductive wiring layer, and in the third A third conductive circuit layer is formed on the surface of the dielectric layer, and the third conductive circuit layer and the second conductive circuit layer are electrically connected through the fourth conductive via. The method for fabricating an IC carrier according to claim 2, wherein a fourth dielectric layer is formed on the fourth conductive wiring layer, and a fifth conductive wiring is formed on the surface of the fourth dielectric layer. After the layer, before the forming a second recess from the fifth conductive circuit layer to the first dielectric layer, the method for fabricating the IC carrier further comprises: at the third conductive circuit layer and from the Forming a first solder resist layer having a first opening on the exposed third dielectric layer, forming a first solder pad from the first opening exposed portion of the third conductive trace layer; forming the first conductive pad on the fifth conductive layer A second solder resist layer having a second opening is formed on the wiring layer and the fourth dielectric layer exposed from the fifth conductive wiring layer, and the fifth conductive wiring layer is exposed from the second opening to form a second solder pad. The manufacturing method of the IC carrier board according to the first aspect of the invention, wherein the carrier substrate comprises a central area and a peripheral area, and the fourth conductive circuit layer and the fifth conductive circuit layer are both formed in the peripheral area. . The method for fabricating an IC carrier according to claim 4, wherein an opening is formed from the fifth conductive wiring layer to the first dielectric layer along a boundary between the central region and the peripheral region, and is removed. The fourth dielectric layer in the opening obtains the second recess. A method for manufacturing an IC carrier board, comprising the steps of:
Providing a substrate, the substrate comprising a carrier plate, a first copper foil layer on opposite sides of the carrier plate, and a first dielectric layer on the side of the two first copper foil layers away from the carrier plate;
Forming a first conductive circuit layer on the first dielectric layer;
Forming a first recess from the first conductive circuit layer toward the first dielectric layer, and a portion of the first copper foil layer is exposed from a bottom of the recess;
An interposer is adhered to the first copper foil layer exposed from the first recess, and the first electrical contact pads and the second electrical property of the interposer have a plurality of corresponding electrical connections a contact pad, the first electrical contact pad being adjacent to the first copper foil layer;
Forming a second dielectric layer on the first conductive circuit layer and the interposer, forming a second conductive circuit layer on the surface of the second dielectric layer, and forming a second layer in the second dielectric layer a third conductive via, the second conductive circuit layer is electrically connected to the second electrical contact pad through the third conductive via;
Separating the first copper foil layer from the carrier plate;
Forming the first copper foil layer into a fourth conductive circuit layer;
Forming a fourth dielectric layer having a fifth conductive via on the fourth conductive wiring layer, and forming a fifth conductive wiring layer on the surface of the fourth dielectric layer; and from the fifth conductive wiring layer The first dielectric layer forms a second recess to expose the interposer, and the plurality of first electrical contact pads are exposed from the second recess. An IC carrier board comprising an interposer, a solder resist layer and an interposer carrier board, the interposer board comprising a fifth conductive circuit layer, a fourth dielectric layer, a fourth conductive circuit layer, and a first interface sequentially contacting The electrical layer and the first conductive circuit layer are electrically connected to the adjacent conductive circuit layer through the conductive holes in the dielectric layer adjacent thereto, and the conductive holes in the first dielectric layer are formed in the hole direction. The interposer is embedded in the first dielectric layer opposite to the conductive holes in the fourth dielectric layer, and the first side of the interposer has electrically connected to each other a contact pad and a second electrical contact pad, the second electrical contact pad is located on a side of the interposer adjacent to the first conductive circuit layer, and the first dielectric is from the fifth conductive circuit layer The layer is formed with a recess penetrating through the fifth conductive circuit layer and the fourth dielectric layer to expose the interposer, and the plurality of first electrical contact pads are exposed from the recess. The IC carrier board of claim 7, wherein the interposer carrier further comprises a second dielectric layer having a conductive via and a second conductive wiring layer, wherein the second dielectric laminate is On the first conductive circuit layer and the second electrical contact pad, the second conductive circuit layer is formed on a surface of the second dielectric layer, and passes through the conductive hole in the second dielectric layer The first conductive circuit layer and the second electrical contact pad are electrically connected. A method of fabricating a semiconductor device, comprising: providing an IC carrier as described in claim 7 or 8 and mounting a wafer in the recess, the wafer having a plurality of electrode pads on one side thereof, The electrode pads are respectively electrically connected by the first electrical contact pads through a conductive bump, and the surface of the wafer away from the electrode pad does not exceed the fourth dielectric layer away from the fourth in the thickness direction. The surface of the conductive circuit layer. A semiconductor device comprising the IC carrier board and the wafer according to claim 7 or 8, wherein the wafer is mounted in the recess, the wafer side has a plurality of electrode pads, and the plurality of electrodes The pads are electrically connected to the first electrical contact pads respectively through a conductive bump, and the surface of the wafer away from the electrode pad does not extend beyond the fourth dielectric layer away from the fourth conductive line in a thickness direction. The surface of the layer.