TW201508874A - Electronic system with a composite substrate - Google Patents

Abstract

A composite substrate made of a conductive pattern structure mounted on a lead frame is used for an electronic system package. High heat generated electronic components are adapted to mount on the lead frame and relatively low heat generated electronic components are adapted to mount on the conductive pattern structure. Metal lines are used for electrical coupling between the circuitry of the IC chip and the conductive pattern structure. An electronic system with the composite substrate gains both advantages-good circuitry arrangement capability from the conductive pattern structure and good heat distribution from the lead frame.

Description

Electronic system with composite substrate

The present invention relates to an electronic system; and more particularly to a package of an electronic system having a composite substrate, which is a composite substrate composed of a circuit board and a lead frame.

As shown in Fig. 1, U.S. Patent No. 6,212,086 discloses a DC-to-DC converter system on April 3, 2001, which incorporates a copper substrate 110 to provide uniformity at the bottom of the system. The heat dissipation function also includes a circuit board 120 disposed on the copper substrate 110. The electronic component includes a main transformer 130, an output inductor 140, a synchronous rectifier 150, an output capacitor 160, and an input capacitor 170. Above the system board 120. A separate output connector is coupled to the system board 120 via a flexible circuit board to the right of the system board 120.

One of the disadvantages of the aforementioned electronic system is that the system circuit board 120 is not a good heat sink, and the heat generated by the electronic components 120, 130, 140, 150, 160, and 170 mounted thereon cannot be effectively conducted to the lower side. The copper substrate 110 dissipates heat. The circuit board facilitates the circuit configuration but is not conducive to the conduction of heat. In contrast, the copper substrate is disadvantageous to the circuit configuration but facilitates the conduction of heat. People in the same industry are actively researching and developing, and it is expected that there will be a substrate that has both advantages.

In one embodiment, an electronic device provided by the present invention includes: a lead frame having a plurality of metal pins; at least one electronic component disposed on the lead frame; and a conductive pattern structure disposed on the wire And overlying the at least one electronic component; wherein the conductive pattern structure comprises at least one insulating layer and at least one conductive pattern layer to electrically connect the plurality of metal pins and the at least one electronic component.

In one embodiment, in the above electronic device of the present invention, the at least one electronic component comprises a wafer or a bare crystal.

In one embodiment, in the above electronic device of the present invention, the lead frame has a flat surface to mount the at least one electronic component.

In one embodiment, in the electronic device of the present invention, the at least one electronic component includes a first electronic component and a second electronic component mounted on the lead frame, wherein the at least one insulating layer covers the a lead frame, a first electronic component, and a second electronic component; and the at least one conductive pattern layer is disposed on the at least one insulating layer for electrically connecting the plurality of metal pins, the first electronic component, and Second electronic component.

In one embodiment, the electronic device of the present invention further includes a package, wherein a bottom surface of the package is flush with a bottom surface of the lead frame to form a surface mount component.

In one embodiment, in the above electronic device of the present invention, the at least one conductive pattern is formed by yellow etching.

In one embodiment, in the above electronic device of the present invention, the upper surface of the conductive pattern structure has a plurality of wiring pads to electrically connect external circuits.

To solve the above technical problem, the electronic device provided by the present invention comprises: a lead frame having a mounting area and a plurality of metal pins disposed along the periphery of the mounting area, wherein each metal pin and the mounting area are Separating a gap; a first electronic component mounted on the mounting area of the lead frame; an insulator covering the lead frame, the first electronic component and the plurality of gaps; and at least one conductive pattern layer disposed on the insulator And electrically connected to the plurality of metal pins and the first electronic component.

In one embodiment, in the above electronic device of the present invention, the first electronic component is a wafer or a bare crystal.

In one embodiment, in the above electronic device of the present invention, the mounting area has a flat surface to mount the first electronic component.

In one embodiment, the electronic device of the present invention further includes a second electronic component mounted on the mounting area of the lead frame, wherein the insulator covers the lead frame, the first electronic component, and the second electronic component And a plurality of gaps; and the at least one conductive pattern layer is disposed on the insulator for electrically connecting the plurality of metal pins, the first electronic component, and the second electronic component.

In one embodiment, the electronic device of the present invention further includes a package, wherein a bottom surface of the package is flush with a bottom surface of the lead frame to form a surface mount component.

In one embodiment, in the electronic device of the present invention, the metal pins and the plurality of terminal contacts of the wafer are exposed to the upper surface of the insulator to electrically connect the at least one conductive pattern.

In one embodiment, in the above electronic device of the present invention, the at least one conductive pattern is formed by yellow etching.

In one embodiment, in the above electronic device of the present invention, the uppermost layer of the at least one conductive pattern layer has a plurality of wiring pads to electrically connect external circuits.

In one embodiment, the electronic device of the present invention further includes at least one second electronic component, wherein an uppermost layer of the at least one conductive pattern layer has a plurality of wiring pads, and the at least one second electronic component is disposed in the The uppermost layer of the at least one conductive pattern layer is electrically connected to the plurality of wiring pads.

In one embodiment, a method of fabricating an electronic device provided by the present invention includes: providing a lead frame having a mounting area and a plurality of metal pins disposed around the mounting area, wherein each metal pin is The mounting area is separated by a gap; an electronic component is provided to be mounted on the mounting area of the lead frame; an insulator covers the lead frame, the electronic component and the plurality of gaps; and at least one conductive pattern layer is formed The plurality of metal pins and the electronic component are electrically connected to the insulator.

In one embodiment, the above method of the present invention further comprises packaging the leadframe with a package, wherein a bottom surface of the package is flush with a bottom surface of the leadframe to form a surface mount component.

In one embodiment, in the above method of the present invention, at least one of the conductive pattern layers is formed by yellow etching.

In contrast to the prior art, the present invention discloses that a composite substrate is used in a "DC-to-DC converter system" which is constructed by placing a circuit board on a metal frame. The composite substrate allows an electronic component such as an integrated circuit to be placed on a metal frame, and a low-heat electronic component can be placed on the circuit board, and then the integrated circuit is electrically coupled to the circuit board by a metal wire. The circuit on it. The electronic system using such a composite substrate can have both the wiring advantages of the circuit board and the heat conduction advantages of the metal frame.

The invention is further illustrated below in conjunction with the drawings and specific embodiments. These examples are intended to be illustrative only and not to limit the scope of the invention. Various modifications and alterations of the present invention will be apparent to those skilled in the art in the <RTIgt;

As shown in FIG. 2A, the circuit board 20 has a rectangular opening 21 around which a set of metal pads 22 surrounds the four edges 24 of the rectangular opening 21. Metal pad 22 is part of the circuitry on circuit board 20, and metal pad 22 is electrically coupled to circuitry on circuit board 20 (not shown) via metal line 23.

As shown in FIG. 2B, a set of bottom metal contacts 25 are disposed on the bottom surface 20B of the circuit board 20, and the metal contacts 25 are subsequently electrically coupled to corresponding metal legs 262 on the circuit board 20.

As shown in FIG. 2C, a piece of metal frame 26 has a plurality of large pieces of metal 261, which can carry high-heating electronic components; a metal frame 26 and a set of peripheral metal legs 262 distributed around the periphery of the metal frame 26, followed by After encapsulation by the encapsulant, the peripheral metal leg 262 acts as an output/input pin for the electronic system. The circuit board 20 will then be placed on the metal frame 26 to form the composite substrate used in the present invention.

As shown in FIG. 3, the circuit board 20 of FIG. 2A is placed over the metal frame 26 of FIG. 2C to form a composite substrate 26C. The bottom surface 20B of the circuit board 20 has a bottom metal contact 25, and the bottom metal contact 25 is electrically coupled to the corresponding peripheral metal leg 262, respectively. The rectangular opening 21 of the circuit board 20 exposes a metal surface 261S which is a partial surface of the bulk metal 261.

As shown in FIG. 4A, the wafer 30 is disposed on a metal surface 261S exposed within the rectangular opening 21 of the circuit board 20. The circuitry (not shown) inside the wafer 30 is electrically connected to the conductor 32 via the metal contacts on the wafer 30. The metal pads 22 are electrically coupled to the circuit board 20. The rectangular opening 21 has four flat sides 24 adjacent to the four flat sides of the wafer 30. This arrangement provides for a four-sided electrical coupling between the wafer 30 and the circuit board 20.

As shown in FIG. 4B, the bottom surface 26CB of the composite substrate 26C of FIG. 4A is disposed, showing that the bottom surface of the bulk metal 261 and the bottom surface of the peripheral metal leg 262 are coplanar.

As shown in FIG. 4C, the wafer 30 is disposed over the metal surface 261S of a bulk metal 261 in the metal frame 26 having a thickness T1 equal to or close to the thickness T3 of the circuit board 20. Such a highly similar design allows the metal wire 32 to electrically couple the top surface contacts (not shown) of the wafer 30 to the metal pads 22 on the circuit board 20.

As shown in FIG. 4D, the wafer 30B is placed on a height adjustment pad 27 so that when the thickness T2 of the wafer 30B is significantly smaller than the thickness T3 of the circuit board 20, the height adjustment pad 27 can be used below to make the wafer 30B. The upper surface may be approximately coplanar with the upper surface of the circuit board 20. Such a highly similar design allows the metal wire 32 to electrically couple the top surface contacts of the wafer 30B to the metal pads 22 on the circuit board 20.

As shown in FIG. 5A, the edge of the circuit board 203 has a U-shaped opening 213, and a set of metal pads 223 are disposed beside the three edges 243 of the U-shaped opening 213. The metal pad 223 is a part of the circuit on the circuit board 203. The metal pad 223 is electrically coupled to the circuit (not shown) on the circuit board 203 by a metal line 233. A set of metal contacts 253 is disposed on the bottom surface of the circuit board 203 as an input and output contact of the circuit on the circuit board 203.

As shown in FIG. 5B, the metal frame 26 has a plurality of bulk metals 261 adapted to carry high heat-generating electronic components such as wafers; a set of peripheral metal legs 262 are disposed at the periphery of the metal frame 26 as a follow-up The input and output points of the entire electronic system. Subsequently, the circuit board 203 will be placed over the metal frame 26.

As shown in FIG. 5C, the circuit board 203 shown in FIG. 5A is placed over the metal frame 26 as shown in FIG. 5B to constitute the second composite substrate 26C3 of the present invention. The bottom metal contacts 253 below the circuit board 203 are electrically coupled to corresponding peripheral metal legs 262 of the metal frame 26, respectively. The U-shaped opening 213 of the circuit board 203 exposes a portion of the metal surface 261S of the bulk metal 261.

As shown in FIG. 5D, a wafer 303 is disposed over the metal surface 261S in the U-shaped opening 213 of the circuit board 203. The internal circuitry of wafer 303 is electrically coupled to circuitry above circuit board 203 via metal lines 323. The metal line 323 is shown to electrically couple the metal pads 223 of the circuit board 203 to the metal contacts on the top surface of the wafer 303. The U-shaped opening 213 has three edges that abut the three edges of the wafer 303, respectively, such that the wafer 303 and the circuit board 203 have a capacity of three-sided electrical coupling.

As shown in FIG. 6A, the edge of the circuit board 202 has an L-shaped opening 212 with a set of metal pads 222 disposed beside the two edges 242 of the L-shaped opening 212. The metal pad 222 is part of the circuitry above the circuit board 202. The metal pad 222 is electrically coupled to the circuitry above the board 202 by metal lines 232. A set of metal contacts 252 is disposed on the bottom surface of the circuit board 202 as an input and output contact of the circuit on the circuit board 202.

As shown in Fig. 6B, the basic concept of the present embodiment is the same as that of Embodiment 1-2, the only difference being that the circuit board has different opening shapes. 6A shows that circuit board 202 has an L-shaped opening 212 that is disposed over metal surface 261S to which opening 212 is exposed. The circuitry within wafer 302 is electrically coupled to circuitry above circuit board 202 via metal lines 322 that electrically couple metal pads 222 over circuit board 202 to metal contacts on the top surface of wafer 302. The L-shaped opening 212 has two edges 242 abutting the two edges of the wafer 302, respectively, such that the wafer 302 and the circuit board 202 have a capacity to be electrically coupled on both sides.

As shown in FIG. 7A, a circuit board 201 has a linear edge 211 with a set of metal pads 221 disposed beside the linear edge 211. The metal pad 221 is part of the circuit on the circuit board 201, and the metal pad 221 is electrically coupled to the circuit on the circuit board 201 by wires 231 (not shown). A set of bottom metal contacts 251 are disposed on the bottom surface of the circuit board 201 as input and output contacts of the circuit on the circuit board 201.

As shown in Fig. 7B, the basic concept of the present embodiment is the same as that of Embodiment 1-2 except that the circuit board 201 used in the present embodiment has a linear edge 241. An integrated circuit wafer 301 is placed over the exposed metal surface 261S near the linear edge 241. The circuit (not shown) in the chip 301 is electrically coupled to the circuit on the circuit board 201 (not shown) via the metal line 321 , and the metal line 321 electrically couples the metal pad 221 on the circuit board 201 to Metal contacts on the wafer 301. The linear edge 241 of the circuit board 201 is adjacent to the linear edge of the wafer 301. This design provides a unilateral electrical coupling between the wafer 301 and the circuit board 201.

As shown in FIG. 8A, the electronic system having the composite substrate shown in FIG. 4A, FIG. 5D, FIG. 6B and FIG. 7B of the foregoing Embodiment 1-4 is encapsulated and protected by the encapsulant 51. The peripheral metal leg 262 protrudes from the encapsulant 51, and the bottom surface of the metal leg 262 is aligned with the bottom surface of the encapsulant 51 or is referred to as a coplanar surface.

As shown in FIG. 8B, the bottom surface of the encapsulant 51 is flush with the bottom surface of the metal frame, and the bottom surface of the exposed metal frame is convenient for heat dissipation. In other words, the entire bottom surface is planar, forming a package with a bottom surface to form a surface adhesive type. element.

In one embodiment, an electronic device is described, comprising: a lead frame having a plurality of metal pins; at least one electronic component disposed on the lead frame; and a conductive pattern structure disposed over the lead frame And covering the at least one electronic component; wherein the conductive pattern structure comprises at least one insulating layer and at least one conductive pattern layer to electrically connect the plurality of metal pins and the at least one electronic component.

In one embodiment, the at least one electronic component comprises a wafer or a die.

In one embodiment, the leadframe has a flat surface to mount the at least one electronic component.

In one embodiment, the at least one electronic component includes a first electronic component and a second electronic component mounted on the lead frame, wherein the at least one insulating layer covers the lead frame, the first electron And the at least one conductive pattern layer is disposed on the at least one insulating layer for electrically connecting the plurality of metal pins, the first electronic component, and the second electronic component.

In one embodiment, an electronic device is described, wherein the electronic system includes: a lead frame having a wafer mounting area and a plurality of metal pins disposed around the wafer mounting area, wherein each metal pin Separating from the wafer mounting region by a gap; at least one conductive pattern structure disposed on the lead frame to form a circuit, the conductive pattern structure bridging each of the metal pins and the wafer mounting region A gap therebetween, and a wafer, mounted in the wafer mounting region of the leadframe and electrically coupled to circuitry formed by the conductive pattern structure.

In one embodiment, the conductive pattern structure has a bottom surface to encapsulate the wafer, wherein the bottom surface includes a plurality of contacts, wherein each of the contacts is electrically coupled to a corresponding one of the lead frames Metal pin. In one embodiment, the conductive pattern structure includes a plurality of conductive pattern layers disposed on the leadframe and the wafer to electrically connect the wafer to each metal pin. In one embodiment, the plurality of conductive pattern layers are formed on the leadframe and the wafer by yellow etching.

In one embodiment, the conductive pattern structure has an upper surface, and the electronic system further includes at least one electronic component disposed on the upper surface, wherein the at least one electronic component passes through a layer of the plurality of conductive patterns A circuit electrically coupled to the conductive pattern structure. In one embodiment, each of the at least one electronic component generates less heat than the heat generated by the wafer.

In one embodiment, a wafer includes a plurality of pins, wherein the plurality of pins are electrically coupled to circuitry of the structure of the conductive pattern through the plurality of conductive pattern layers.

In one embodiment, the electronic device further includes an insulating material to encapsulate the lead frame and the wafer to form a substantially flat surface, wherein the wafer and the lead frame are exposed to a plurality of contacts, and then the The conductive pattern structure is disposed on the substantially flat surface to be connected to the plurality of contacts exposed to the outside. In one embodiment, the upper surface of the leadframe is at the same height or level as the upper surface of the wafer to form a flat surface on which the plurality of conductive layers are disposed.

9A depicts a top plan view of a leadframe 900 and a wafer or a semiconductor component 910 to be mounted on the leadframe; the leadframe 900 has a wafer mounting area, wherein the wafer mounting area has a first A plane 901 for mounting the wafer or semiconductor component 910, wherein the leadframe has a plurality of metal pins 902, 903. In one embodiment, each metal pin and wafer mounting area are separated by a gap; the wafer is mounted on the wafer mounting area of the lead frame. In one embodiment, a metal pin is connected to the wafer mounting area. Semiconductor component 910 can be in the form of a bare crystal prior to packaging. Note that the lead frame 900 can be of many different shapes and is not limited to the examples shown in this embodiment.

9B depicts a structural view of a packaged leadframe 900 and semiconductor component 910, wherein the insulating material 920 encapsulates the leadframe 900 and the wafer 910 to form a second planar surface 930 prior to arranging the structure of the conductive pattern. The metal pins and the input or output terminal contacts of the wafer are exposed such that a conductive structure can be placed on the second plane to electrically couple the metal pins and the wafer input or output terminal contacts. In one embodiment, the metal pins and the upper surface of the wafer are substantially at the same level to form a flat surface such that a plurality of conductor pattern layers can be disposed on the flat surface. The upper surface of the wafer has a plurality of input or output terminal contacts for electrical connection to other components.

9C depicts a bottom view of the package structure of leadframe 900 and semiconductor component 910 with the wafer mounting region 904 exposed and aligned with the bottom surface; a plurality of wiring pads disposed on the bottom surface and connected to the wires The metal pins 902, 903 of the frame 900.

9D depicts a side view of the package structure of leadframe 900 and semiconductor component 910, with each metal pin 902 having a side surface 905, respectively.

As shown in FIG. 10, a plurality of conductive pattern layers are disposed on the lead frame and the wafer, and a plurality of wiring pads 960 are disposed on the upper surface of the conductive pattern layers 930, 940, 950 for mounting other components, such as capacitors. , resistor, inductor, or any other device.

Figure 11 shows a top view of the electronic device after all components have been assembled, with first electronic components 970, such as capacitors, resistors, inductors or other devices, and second electronic components 980 such as capacitors, resistors, inductors. Or other device, connected to the wiring pad on the upper surface of the conductive layer.

In one embodiment, a wafer is a semiconductor die having a plurality of input or output terminal contacts, wherein the input or output terminal contacts are electrically coupled to the conductive through circuitry of the plurality of conductive pattern layers The circuit of the pattern structure.

In one embodiment, the system further includes a package having a bottom surface that is flush with the bottom surface of the leadframe to form a flat mounting surface for mounting other components such as capacitors, resistors, inductors, Or any other device. In other words, the entire bottom surface is planar, forming a package with a flat bottom surface to form a surface-adhesive component.

In one embodiment, a method of fabricating an electronic device is described, comprising: providing a leadframe having a mounting area and a plurality of metal pins disposed along the mounting area, wherein each metal pin is mounted The area is separated by a gap; an electronic component is provided to be mounted on the mounting area of the lead frame; an insulator covers the lead frame, the electronic component and the plurality of gaps; and at least one conductive pattern layer is formed on the insulator The plurality of metal pins and the electronic component are electrically connected.

In one embodiment, the at least one conductive pattern layer is formed by yellow etching.

While the present invention has been described above in terms of the preferred embodiments thereof, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. These possible modifications and substitutions are not fully disclosed in the above description, and all of these aspects are substantially covered by the scope of the patent protection attached to the specification.

20, 203, 202, 201‧‧‧ boards
20B‧‧‧Bottom of the circuit board
21‧‧‧ Rectangular opening
213 U‧‧‧ Shaped opening
212 L‧‧‧ shaped opening
213 U‧‧‧ Shaped opening
211‧‧ ‧ flat edge
22, 223, 222, 221‧‧‧metal pads
24, 243, 242, 241‧‧ ‧ the edge of the opening
25, 253, 252, 251‧‧‧ bottom metal contacts
26‧‧‧Metal frame
26C, 26C3‧‧‧Composite substrate
261S‧‧‧Metal surface
262‧‧‧ peripheral metal feet
27‧‧‧thickness adjustment film
30, 30B, 303, 302, 301‧‧‧ wafer
900‧‧‧ lead frame
910‧‧‧Semiconductor components
901‧‧‧One of the first planes of the wafer mounting area
902, 903‧‧‧Multiple metal pins
920‧‧‧Insulation materials
930‧‧‧ a second flat surface
904‧‧‧ wafer mounting area
905‧‧‧ side surface
930, 940, 950‧‧‧ conductive pattern layer
960‧‧‧Wiring pads
970‧‧‧First electronic components
980‧‧‧Second electronic components

1 is a schematic structural view of an electronic system in the prior art. Figure 2A is a top plan view of a circuit board used in Embodiment 1 of the present invention. Figure 2B is a bottom plan view of Figure 2A. 2C is a schematic structural view of a metal frame used in Embodiment 1 of the present invention. Fig. 3 is a schematic view showing the structure of a composite substrate used in Example 1 of the present invention. Fig. 4A is a top plan view of Embodiment 1 of the present invention. Figure 4B is a bottom plan view of Figure 4A. Fig. 4C is an enlarged cross-sectional view taken along line AA' of Fig. 4A. Fig. 4D is an enlarged cross-sectional view taken along line AA' of Fig. 4A. Figure 5A is a top plan view of a circuit board used in Embodiment 2 of the present invention. Fig. 5B is a schematic structural view of a metal frame used in Embodiment 2 of the present invention. Fig. 5C is a schematic view showing the structure of a composite substrate used in Example 2 of the present invention. Figure 5D is a top plan view of Embodiment 2 of the present invention. Figure 6A is a top plan view of a circuit board used in Embodiment 3 of the present invention. Figure 6B is a top plan view of Embodiment 3 of the present invention. Figure 7A is a top plan view of a circuit board used in Embodiment 4 of the present invention. Figure 7B is a top plan view of Embodiment 4 of the present invention. Fig. 8A is a side elevational view showing the electronic system of the embodiment 1-4 having a composite substrate after sealing. Figure 8B is a bottom plan view of the electronic system having the composite substrate after the sealing of the embodiment 1-4 of the present invention. Figure 9A shows a top plan view of a leadframe and a wafer or semiconductor device. Fig. 9B shows a plan view of a package structure of a lead frame and a semiconductor device. Fig. 9C shows a bottom view of the structure of the lead frame and the package of the semiconductor device. Fig. 9D shows a side view of the lead frame and the package structure of the semiconductor device. Figure 10 shows the form in which a plurality of conductor pattern layers are on the leadframe and the wafer. Figure 11 shows a top plan view of the assembled electronic electronic device.

Wherein: 20, 203, 202, 201 are circuit boards; 20B is a circuit board bottom surface; 21 is a rectangular opening; 213 is a U-shaped opening; 212 is an L-shaped opening; 213 is a U-shaped opening; 211 is a flat edge; 223, 222, 221 are metal pads; 24, 243, 242, 241 are open edges; 25, 253, 252, 251 are bottom metal contacts; 26 is metal frame; 26C, 26C3 are composite substrates; Metal surface; 262 is a peripheral metal leg; 27 is a thickness adjustment sheet; 30, 30B, 303, 302, 301 are wafers; and 32 is a metal wire.

900‧‧‧ lead frame

902,903‧‧‧Multiple metal pins

930,940,950‧‧‧ conductive pattern layer

960‧‧‧Wiring pads

Claims (18)

An electronic device comprising: a lead frame having a plurality of metal pins; at least one electronic component disposed on the lead frame; and a conductive pattern structure disposed over the lead frame and covering the at least one electronic component The conductive pattern structure includes at least one insulating layer and at least one conductive pattern layer, and the at least one conductive pattern layer electrically connects the plurality of metal pins and the at least one electronic component. The electronic device according to claim 1, wherein the at least one electronic component comprises a wafer or a bare crystal. The electronic device of claim 1, wherein the lead frame has a flat surface to mount the at least one electronic component. The electronic device of claim 1, wherein the at least one electronic component comprises a first electronic component and a second electronic component mounted on the lead frame, wherein the at least one An insulating layer covering the lead frame, the first electronic component and the second electronic component; and the at least one conductive pattern layer is disposed on the at least one insulating layer for electrically connecting the plurality of metal pins, An electronic component and a second electronic component. The electronic device of claim 1, further comprising a package, wherein a bottom surface of the package is flush with a bottom surface of the lead frame to form a surface mount component. The device of claim 1, wherein the at least one conductive pattern is formed by yellow etching. The electronic device according to claim 1, wherein the upper surface of the conductive pattern structure has a plurality of wiring pads for electrically connecting external circuits. An electronic device comprising: a lead frame having a mounting area and a plurality of metal pins disposed along the periphery of the mounting area, wherein each metal pin is separated from the mounting area by a gap; a first electron An element mounted on the mounting area of the lead frame; an insulator covering the lead frame, the first electronic component, and a plurality of gaps; and at least one conductive pattern layer disposed on the insulator for electrically connecting the a plurality of metal pins and the first electronic component. The device according to claim 8 is characterized in that the first electronic component is a wafer or a bare crystal. The electronic device of claim 8, wherein the mounting area has a flat surface to mount the first electronic component. The electronic device of claim 8, further comprising a second electronic component mounted on the mounting area of the lead frame, wherein the insulator covers the lead frame and the first electronic component And a second electronic component and a plurality of gaps; and the at least one conductive pattern layer is disposed on the insulator for electrically connecting the plurality of metal pins, the first electronic component, and the second electronic component. The electronic device of claim 8, further comprising a package, wherein a bottom surface of the package is flush with a bottom surface of the lead frame to form a surface mount component. The electronic device according to claim 8, wherein the metal pin and the plurality of terminal contacts of the wafer are exposed to an upper surface of the insulator to electrically connect the at least one conductive pattern. The device according to claim 8 is characterized in that the at least one conductive pattern is formed by yellow etching. The electronic device according to claim 8, wherein the uppermost layer of the at least one conductive pattern layer has a plurality of wiring pads to electrically connect the external circuit. The electronic device of claim 8, further comprising at least one second electronic component, wherein an uppermost layer of the at least one conductive pattern layer has a plurality of wiring pads, and the at least one second electronic The component is disposed above the uppermost layer of the at least one conductive pattern layer and electrically connected to the plurality of wiring pads. A method of fabricating an electronic device, comprising: providing a leadframe having a mounting area and a plurality of metal pins disposed around the mounting area, wherein each metal pin is separated from the mounting area by a gap; Providing an electronic component mounted on the mounting area of the lead frame; covering the lead frame, the electronic component, and the plurality of gaps with an insulator; and forming at least one conductive pattern layer on the insulator to electrically connect the A plurality of metal pins and the electronic component. The method of claim 17, wherein the at least one conductive pattern layer is formed by yellow etching.