TW201505143A - Chip package and method of manufacturing same - Google Patents

Abstract

The invention discloses a chip package comprising a wafer having an upper surface, a lower surface and a sidewall, and a signal pad region adjacent to the upper surface. A first recess extends along the sidewall from the upper surface toward the lower surface. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first recess and the second recess extend laterally along one side of the upper surface, and the length of the first recess extending along the side is greater than the length of the second recess extending along the side. A wiring layer is electrically connected to the signal pad region and extends into the second recess. The invention also discloses a method of manufacturing a chip package.

Description

Chip package and method of manufacturing same

The present invention relates to a chip package technology, and more particularly to a chip package and a method of fabricating the same.

The wafer packaging process is an important step in the process of forming electronic products. In addition to protecting the wafer from the external environment, the chip package also provides an electrical connection path between the electronic components inside the wafer and the outside. The process of the conventional chip package involves a multi-pass patterning process and a material deposition process, which not only consumes production costs but also requires a long process time.

Therefore, it is necessary to find a novel chip package and a method of fabricating the same that can solve or improve the above problems and provide a more simplified and fast chip packaging technology.

Embodiments of the present invention provide a chip package including a wafer having an upper surface, a lower surface, and sidewalls, and including a signal pad region adjacent to the upper surface. A first recess extends along the sidewall from the upper surface toward the lower surface. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first recess and the second recess extend laterally along one side of the upper surface, and the length of the first recess extending along the side is greater than the length of the second recess extending along the side. A wiring layer is electrically connected to the signal pad region and extends into the second recess.

Embodiments of the present invention provide a method of fabricating a chip package, comprising providing a wafer including a plurality of wafers, each wafer having an upper surface and a lower surface and including a signal pad region adjacent to the upper surface. A first recess is formed extending from the upper surface toward the lower surface. At least one second recess is formed extending from a first bottom of the first recess toward the lower surface. A redistribution layer is formed, electrically connected to the signal pad region and extending into the second recess. The wafer is diced to separate the wafers such that each wafer has a sidewall and the first recess extends along the sidewall. The first recess and the second recess extend laterally along one side of the upper surface, and the length of the first recess extending along the side is greater than the length of the second recess extending along the side.

100‧‧‧ wafer

100a‧‧‧ upper surface

100b‧‧‧ lower surface

101, 102, 103, 104‧‧‧ side

140, 260‧‧‧ insulation

150‧‧‧Base

160‧‧‧Signal pad area

200‧‧‧Sensor or component area

220‧‧‧ first notch

220a‧‧‧first side wall

220b‧‧‧ first bottom

230‧‧‧second notch

230a‧‧‧second side wall

230b‧‧‧ second bottom

280‧‧‧Rewiring layer

300‧‧ ‧ protective layer

320, 340‧‧‧ openings

360‧‧‧Adhesive layer

380‧‧‧ wafer, interposer or board

440‧‧‧Conductive structure/wiring

440a‧‧‧first endpoint

440b‧‧‧second endpoint

The highest part of 440c‧‧

D1, D2‧‧ depth

L1, L 2‧‧‧ length

Part P‧‧‧

SC‧‧‧Cut Road

W1, W 2‧‧‧ width

1 to 6 are schematic cross-sectional views showing a method of fabricating a chip package in accordance with an embodiment of the present invention.

Figure 7 is a plan view showing a chip package in accordance with an embodiment of the present invention.

Fig. 8 is an enlarged perspective view showing a portion P of the chip package in Fig. 7.

The manner of making and using the embodiments of the present invention will be described in detail below. It should be noted, however, that the present invention provides many inventive concepts that can be applied in various specific forms. The specific embodiments discussed herein are merely illustrative of specific ways of making and using the invention, and are not intended to limit the scope of the invention. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the invention and are not representative of the various embodiments discussed and/or Or have any connection between structures. Furthermore, when a first material layer is referred to or on a second material layer, the first material layer is in direct contact with or separated from the second material layer by one or more other material layers.

The chip package of one embodiment of the present invention can be used to package a sensing wafer, such as a biometric wafer such as a fingerprint reader. However, the application is not limited thereto. For example, in the embodiment of the chip package of the present invention, it can be applied to various active or passive elements, digital circuits or analog circuits. The electronic components of the integrated circuit are, for example, related to opto electronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, or utilizing heat, light, A physical sensor that measures physical quantities such as capacitance and pressure to measure. In particular, some or all of the process of wafer scale package (WSP) can be used for image sensing components, light-emitting diodes (LEDs), solar cells, and radio frequency components. RF circuits), accelerators, gyroscopes, micro actuators, surface acoustic wave devices, process sensors, or ink printer heads The semiconductor wafer is packaged.

The above wafer level packaging process mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed in a supporting crystal. On the circle, the encapsulation process can also be called a wafer level packaging process. In addition, the above wafer level packaging process is also suitable for stacking by means of stacking. A plurality of wafers of a circuit to form a chip package of multi-layer integrated circuit devices.

Please refer to FIG. 6, which is a cross-sectional view of a chip package according to an embodiment of the invention. To simplify the drawing, only a portion of the chip package is shown here. In this embodiment, the chip package includes a wafer 100, a first recess 220, a second recess 230, and a redistribution layer (RDL) 280. The wafer 100 has an upper surface 100a and a lower surface 100b. In one embodiment, the wafer 100 includes an insulating layer 140 adjacent to the upper surface 100a and a lower layer substrate 150 adjacent to the lower surface 100b. Generally, the insulating layer 140 may be composed of an interlayer dielectric (ILD), It consists of an inter-metal dielectric (IMD) and a passivation covering. In the present embodiment, the insulating layer 140 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination of the foregoing or other suitable insulating materials. In this embodiment, substrate 150 can comprise germanium or other semiconductor material.

In this embodiment, the wafer 100 can include a signal pad region 160 and a sensing region or component region 200 that can be adjacent to the upper surface 100a. In one embodiment, the signal pad region 160 includes a plurality of conductive pads, which may be a single conductive layer or a conductive layer structure having multiple layers. To simplify the drawing, only a single conductive layer is exemplified herein, and only one conductive pad in the insulating layer 140 is illustrated as an example. In this embodiment, one or more openings may be included in the insulating layer 140 to expose corresponding conductive pads.

In one embodiment, the sensing region or component region 200 of the wafer 100 includes a sensing element that can be used to sense a biological feature, that is, the wafer 100 is a biosensing wafer (eg, a fingerprinting wafer). In another embodiment, the wafer The 100 series is used to sense environmental characteristics. For example, the wafer 100 may include a temperature sensing element, a humidity sensing element, a pressure sensing element, a capacitive sensing element, or other suitable sensing element. In yet another embodiment, the wafer 100 can include an image sensing element. In one embodiment, the sensing elements in the wafer 100 are electrically connected to the signal pad region 160 through an interconnect structure (not shown) in the insulating layer 140.

In one embodiment, the first recess 220 is located outside the sensing region or component region 200 and the signal pad region 160, and extends from the upper surface 100a toward the lower surface 100b along a sidewall of the wafer 100 to expose the underlying substrate. 150. In other embodiments, the first recess 220 can be located outside of the sensing region or component region 200 and expose the underlying substrate 150.

The first recess 220 has a first sidewall 220a and a first bottom 220b. In an embodiment, the first sidewall 220a of the first recess 220 is an edge of the insulating layer 140. Moreover, the first bottom portion 220b can be located at or below the interface between the insulating layer 140 and the substrate 150. In an embodiment, the first sidewall 220a can be substantially perpendicular to the upper surface 100a. In other embodiments, the first sidewall 220a can be substantially oblique to the upper surface 100a. In addition, the first bottom portion 220b is not limited to be parallel to the upper surface 100a.

In one embodiment, the first recess 220 extends laterally across the entire length of the four sides 101, 102, 103, and 104 of the upper surface 100a such that the sides 101, 102, 103, and 104 face the upper surface 100a. The inside is retracted, as shown in Figure 7. In another embodiment, the first recess 220 can extend laterally across the entire length of the side 101 of the upper surface 100a and further along a portion or all of the length of the adjacent side 102 or side 103. Without extending along side 104. In still another embodiment, the first recess 220 can extend laterally across the entire side 101 of the upper surface 100a. The length of the portion extends further along a portion or all of the length of the adjacent two sides 102 and 103 without extending along the side edge 104. In other embodiments, the first recess 220 can extend laterally along a portion or all of the length of the side edges 101 without extending along the sides 102, 103, and 104.

The second recess 230 extends from the first bottom portion 220b of the first recess 220 toward the lower surface 100b along the sidewall of the wafer 100, and the second recess 230 has a second sidewall 230a and a second bottom portion 230b. In this embodiment, the second side wall 230a can be substantially perpendicular to the upper surface 100a. In other embodiments, the second sidewall 230a can be substantially oblique to the upper surface 100a. In addition, the second bottom portion 230b is not limited to be parallel to the upper surface 100a.

In this embodiment, as shown in FIGS. 7 and 8, the chip package may include a plurality of independent second notches 230 extending from the first bottom portion 220b toward the lower surface 100b and along the sides of the upper surface 100a, respectively. A portion of the sides 101, 102, 103, and 104 extend in length. Moreover, the length L1 of the first recess 220 extending laterally along the side edge 101 is greater than the length L2 of the second recess 230 extending laterally along the side edge 101. Similarly, the length of the first recess 220 extending laterally along the sides 102, 103 or 104 is greater than the length of the corresponding second recess 230 extending laterally along the same side 102, 103 or 104. In addition, although not shown in the drawings, it can be understood that as long as the first recess 220 extends laterally along the side of the upper surface 100a, the length of the second recess 230 extends laterally along the same side of the corresponding second recess 230. The length, the length of the first recess 220, the position, number and size of the second recess 230 can have other configurations. For example, the chip package may have only one second recess 230 extending laterally along a portion of the length of the side edges 101, 102, 103 or 104 of the upper surface 100a, and the first recess 220 may be along the same The entire length of the sides extends laterally.

In the present embodiment, the depth D1 of the first recess 220 is smaller than the depth D2 of the second recess 230, as shown in FIG. Furthermore, the width W1 of the first bottom portion 220b is smaller than the width W2 of the second bottom portion 230b.

In an embodiment, an insulating layer 260 may be selectively disposed to be disposed on the upper surface 100a of the wafer 100 in compliance. The insulating layer 260 extends to the second sidewall 230a and the second bottom portion 230b via the first recess 220 and exposes a portion of the signal pad region 160. In the present embodiment, the insulating layer 260 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination thereof, or other suitable insulating materials.

The patterned redistribution layer 280 is compliantly disposed on the insulating layer 260. The redistribution layer 280 extends to the second sidewall 230a and the second bottom portion 230b and is electrically connected to the exposed signal pad region 160. In an embodiment, the redistribution layer 280 does not extend to the edge of the second bottom portion 230b. In an embodiment, when the substrate 150 includes a semiconductor material, the redistribution layer 280 can be electrically insulated from the semiconductor material through the insulating layer 260. In an embodiment, the redistribution layer 280 may include copper, aluminum, gold, platinum, nickel, tin, a combination of the foregoing, a conductive polymer material, a conductive ceramic material (eg, indium tin oxide or indium zinc oxide) or other suitable Conductive material.

A protection layer 300 is disposed on the redistribution layer 280 and the insulating layer 260 and extends into the first recess 220 and the second recess 230. The protective layer 300 includes one or more openings therein to expose a portion of the redistribution layer 280. In the present embodiment, the protective layer 300 includes openings 320 and 340 that expose the redistribution layer 280 on the signal pad region 160 and the second recess 230, respectively. In another embodiment, the protective layer 300 may include only the opening 340 therein, for example, the protective layer 300 completely covers the redistribution layer 280 on the signal pad region 160. In other In an embodiment, the protective layer 300 can include a plurality of openings 340 that expose the redistribution layer 280 within the second recess 230. In the present embodiment, the protective layer 300 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination thereof, or other suitable insulating materials.

Another wafer (eg, a processor), an interposer, or a circuit board 380 may be attached to the lower surface 100b of the wafer 100 through an adhesive layer (eg, glue) 360, and extended to the second through The redistribution layer 280 and the conductive structure 440 (eg, conductive bumps or wires) in the recess 230 are electrically connected to the signal pad region 160. In other embodiments, a circuit board (not shown) may be additionally disposed under the wafer or interposer 380 to form a wafer stack package. Taking the wiring as an electrically conductive structure as an example, the wiring 440 has a first end point 440a and a second end point 440b. The first end point 440a is disposed on the redistribution layer 280 extending into the second recess 230, and is electrically connected to the redistribution layer 280 through the opening 340, and the second end point 440b is disposed on the wafer, the interposer or the circuit board. On and in 380, it is electrically connected. In other embodiments, the first end 440a of the wiring 440 can be disposed on the redistribution layer 280 on the signal pad region 160 and electrically connected to the redistribution layer 280 through the opening 320.

In one embodiment, one of the highest portions 440c of the wiring 440 is lower than the upper surface 100a. In other embodiments, the highest portion 440c of the wire 440 can protrude from the upper surface 100a. Again, wiring 440 can include gold or other suitable electrically conductive material.

An encapsulant (not shown) may selectively cover the conductive structure 440 and a portion of the wafer 100, or may extend over the upper surface 100a to form a flattening over the sensing region or the component region 200. Contact the surface. In this embodiment, the encapsulant may be composed of a molding material or a sealing material.

According to the above embodiment of the present invention, since the wafer 100 includes the first notch 220 and the second notch 230, and a part of the conductive structure/wiring 440 is disposed therein, the size of the chip package can be reduced. When the highest portion 440c of the conductive structure/wiring 440 is made lower than the upper surface 100a through the first recess 220 and the second recess 230, the size of the chip package can be further reduced. Furthermore, when the encapsulation layer extends further to the upper surface 100a and a flattened contact surface is formed over the sensing region or the component region 200, the sensing region or the component region can be greatly reduced through the first recess 220 and the second recess 230. The thickness of the encapsulation layer above 200 can thus increase the sensitivity of the sensing region or component region 200.

Hereinafter, a method of manufacturing a chip package according to an embodiment of the present invention will be described with reference to FIGS. 1 to 6, in which FIGS. 1 to 6 are schematic cross-sectional views showing a method of manufacturing a chip package according to an embodiment of the present invention.

Referring to FIG. 1, a wafer having a plurality of wafer regions 120 is provided. Wafer region 120 defines a plurality of wafers 100, and scribe lines SC are defined between wafer regions 120. To simplify the drawing, only a portion of a single wafer region 120 is depicted herein. The wafer 100 has an upper surface 100a and a lower surface 100b. In one embodiment, the wafer 100 includes an insulating layer 140 adjacent to the upper surface 100a and a lower layer substrate 150 adjacent to the lower surface 100b. Generally, the insulating layer 140 may be composed of an interlayer dielectric layer (ILD) and an intermetallic dielectric layer. The electrical layer (IMD) and the covered passivation layer. In the present embodiment, the insulating layer 140 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination of the foregoing or other suitable insulating materials. In this embodiment, the substrate 150 may include germanium or other semiconductors. material.

In the present embodiment, the wafer 100 within each wafer region 120 can include a signal pad region 160 and a sensing region or component region 200 that can be adjacent to the upper surface 100a. In one embodiment, the signal pad region 160 includes a plurality of conductive pads, which may be a single conductive layer or a conductive layer structure having multiple layers. To simplify the drawing, only a single conductive layer is exemplified herein, and only one conductive pad in the insulating layer 140 is illustrated as an example. In this embodiment, one or more openings may be included in the insulating layer 140 to expose corresponding conductive pads.

In one embodiment, the sensing region or component region 200 of the wafer 100 includes a sensing element that can be used to sense a biological feature, that is, the wafer 100 is a biosensing wafer (eg, a fingerprinting wafer). In another embodiment, the wafer 100 is used to sense environmental characteristics. For example, the wafer 100 may include a temperature sensing component, a humidity sensing component, a pressure sensing component, a capacitive sensing component, or other suitable sense. Measuring component. In yet another embodiment, the wafer 100 can include an image sensing element. In one embodiment, the sensing elements in the wafer 100 are electrically connected to the signal pad region 160 through an interconnect structure (not shown) in the insulating layer 140.

Please refer to FIG. 2, through lithography process and etching process (for example, dry etching process, wet etching process, plasma etching process, reactive ion etching process or other suitable process) or cutting process in each wafer area. A first recess 220 is formed in the wafer 100 within 120. A first recess 220 in each wafer region 120 is formed outside the sensing region or component region 200 and the signal pad region 160, and extends from the upper surface 100a toward the lower surface 100b along the scribe line SC between the wafer regions 120. To expose the underlying substrate 150. In other embodiments, the first recess 220 can be formed outside of the sensing region or component region 200 and expose the underlying substrate 150.

The first recess 220 has a first sidewall 220a and a first bottom 220b. In an embodiment, the first sidewall 220a of the first recess 220 is an edge of the insulating layer 140. Moreover, the first bottom portion 220b can be located at or below the interface between the insulating layer 140 and the substrate 150. In an embodiment, the first sidewall 220a can be substantially perpendicular to the upper surface 100a. In other embodiments, the first sidewall 220a can be substantially oblique to the upper surface 100a. In addition, the first bottom portion 220b is not limited to be parallel to the upper surface 100a.

Please refer to Figure 3, through the lithography process and etching process (for example, dry etching process, wet etching process, plasma etching process, reactive ion etching process or other suitable process) or cutting process, in each wafer area. One or more second recesses 230 are formed in the wafer 100 within 120. The second recess 230 in each wafer region 120 extends from the first bottom 220b of the first recess 220 toward the lower surface 100b along the scribe line SC between the wafer regions 120. The second recess 230 has a second sidewall 230a and a second bottom 230b. In this embodiment, the second side wall 230a can be substantially perpendicular to the upper surface 100a. In other embodiments, the second sidewall 230a can be substantially oblique to the upper surface 100a. In addition, the second bottom portion 230b is not limited to be parallel to the upper surface 100a.

In the present embodiment, the depth D1 of the first recess 220 is smaller than the depth D2 of the second recess 230, as shown in FIG. Furthermore, the width W1 of the first bottom portion 220b is smaller than the width W2 of the second bottom portion 230b, as shown in FIG.

Referring to FIG. 4, a selective process can be formed on the upper surface 100a of the wafer 100 through a deposition process (for example, a coating process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process). An insulating layer 260 extending through the first recess 220 to the second sidewall 230a and the second bottom 230b. In the present embodiment, the insulating layer 260 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination thereof, or other suitable insulating materials.

Then, the insulating layer 260 above the signal pad region 160 can be removed through a lithography process and an etching process (eg, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, or other suitable process). To expose a portion of the signal pad region 160. Then, through the deposition process (for example, coating process, physical vapor deposition process, chemical vapor deposition process, electroplating process, electroless process or other suitable process), lithography process and etching process, on the insulating layer 260 A patterned redistribution layer 280 is formed. The redistribution layer 280 extends to the second sidewall 230a and the second bottom portion 230b and is electrically connected to the exposed signal pad region 160. In an embodiment, the redistribution layer 280 does not extend to the edge of the second bottom portion 230b. In an embodiment, when the substrate 150 includes a semiconductor material, the redistribution layer 280 can be electrically insulated from the semiconductor material through the insulating layer 260. In an embodiment, the redistribution layer 280 may include copper, aluminum, gold, platinum, nickel, tin, a combination of the foregoing, a conductive polymer material, a conductive ceramic material (eg, indium tin oxide or indium zinc oxide) or other suitable Conductive material.

Referring to FIG. 5, the protection can be formed on the redistribution layer 280 and the insulating layer 260 by a deposition process (for example, a coating process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process). Layer 300 extends into first recess 220 and second recess 230. In the present embodiment, the protective layer 300 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination thereof, or other suitable insulating materials.

Then, through the lithography process and the etching process (for example, dry etching) A process, a wet etch process, a plasma etch process, a reactive ion etch process, or other suitable process), one or more openings are formed in the protective layer 300 to expose a portion of the redistribution layer 280. In the present embodiment, openings 320 and 340 are formed in the protective layer 300 to expose the redistribution layer 280 on the signal pad region 160 and the second recess 230, respectively. In another embodiment, the protective layer 300 may include only the opening 340 therein, for example, the protective layer 300 completely covers the redistribution layer 280 on the signal pad region 160. In other embodiments, the protective layer 300 can include a plurality of openings 340 that expose the redistribution layer 280 within the second recess 230. It will be understood that the number and location of the openings in the protective layer 300 are not limited to this depending on the design requirements.

Next, the wafer is subjected to a dicing process along the scribe lines SC between the wafer regions 120 to form a plurality of individual wafers 100. After the cutting process is performed, the first recess 220 of each wafer extends from the upper surface 100a toward the lower surface 100b along the sidewall of the wafer 100, and the second recess 230 extends from the first bottom 220b along the sidewall of the wafer 100. The lower surface 100b extends. In one embodiment, the first recess 220 extends laterally to the four corners of the upper surface 100a and continuously extends across the entire length of the sides 101, 102, 103, and 104 such that the sides 101, 102, 103 and 104 is retracted toward the inside of the upper surface 100a as shown in Fig. 7. In another embodiment, the first recess 220 can extend laterally across the entire length of the side 101 of the upper surface 100a and further along a portion or all of the length of the adjacent side 102 or side 103. Without extending along side 104. In still another embodiment, the first recess 220 can extend laterally across the entire length of the side 101 of the upper surface 100a and further along a portion or all of the length of the adjacent two sides 102 and 103. Without extending along side 104. In other embodiments, the first recess 220 can be along the sides A portion or all of the length of 101 extends laterally without extending along sides 102, 103, and 104.

In this embodiment, as shown in FIGS. 7 and 8, the chip package may include a plurality of independent second notches 230 extending from the first bottom portion 220b toward the lower surface 100b and along the sides of the upper surface 100a, respectively. A portion of the sides 101, 102, 103, and 104 extend in length. Moreover, the length L1 of the first recess 220 extending laterally along the side edge 101 is greater than the length L2 of the second recess 230 extending laterally along the side edge 101. Similarly, the length of the first recess 220 extending laterally along the sides 102, 103 or 104 is greater than the length of the corresponding second recess 230 extending laterally along the same side 102, 103 or 104. In addition, although not shown in the drawings, it can be understood that when the first recess 220 extends across the entire length or width of one side of the upper surface 100a, the second recess extends laterally along the same side. Port 230 can have a variety of configurations.

In this embodiment, the wafer 100 includes a step-like sidewall formed by the first sidewall 220a, the first bottom portion 220b, the second sidewall 230a, and the second bottom portion 230b, and the first sidewall 220a and the first sidewall The adjacent cliff-form side walls formed by the bottom portion 220b are as shown in Fig. 8, and Fig. 8 is an enlarged perspective view showing a portion P of the chip package in Fig. 7.

It can be understood that the number of the second notches 230 in the first to eighth figures is merely illustrative and not limited thereto, and the actual number depends on the design requirements. For example, in one embodiment, two or more consecutive second notches 230 may be formed in the wafer 100 by performing a plurality of dicing processes or multiple lithography processes and etching processes, so that the wafer 100 may be The multi-step sidewall formed by the first sidewall 220a, the first bottom portion 220b, the plurality of second sidewalls 230a, and the plurality of second bottom portions 230b is included.

Referring to FIG. 6, another wafer (eg, a processor), an interposer, or a circuit board 380 may be attached to the lower surface 100b of the individual wafer 100 through an adhesive layer (eg, adhesive) 360. And electrically connected to the signal pad region 160 through the redistribution layer 280 extending into the second recess 230 and a conductive structure 440 (eg, conductive bumps or wires). In other embodiments, a circuit board (not shown) may be additionally disposed under the wafer or interposer 380 to form a wafer stack package.

Taking the wiring as an example, a wire 440 having a first end point 440a and a second end point 440b can be formed by a wire bonding process. The first terminal end 440a of the wiring 440 is formed on the redistribution layer 280 extending into the second recess 230, and is electrically connected to the redistribution layer 280 through the opening 340. The second terminal end 440b of the wiring 440 is formed on and electrically connected to the wafer, the interposer, or the circuit board 380. For example, the second end point 440b of the wire 440 can be the starting point of the weld, and the first end point 440a of the wire 440 is subsequently formed. In other embodiments, the first terminal 440a of the wiring 440 can be formed on the redistribution layer 280 on the signal pad region 160 and electrically connected to the redistribution layer 280 through the opening 320.

In one embodiment, the highest portion 440c of the wire 440 is lower than the upper surface 100a. In other embodiments, the highest portion 440c of the wire 440 can protrude from the upper surface 100a. Again, wiring 440 can include gold or other suitable electrically conductive material. Since the wafer 100 includes the first recess 220 and the second recess 230, the conductive path between the wafer 100 and the wafer, interposer or circuit board 380 can be directed downward from the upper surface 100a via the sidewalls of the wafer 100.

In an embodiment, an encapsulation layer (not shown) may be formed on the wafer 100 through a molding process or other suitable process. The conductive structure 440 and a portion of the wafer 100 are selectively covered or may extend further onto the upper surface 100a to form a flattened contact surface over the sensing region or component region 200. In this embodiment, the encapsulation layer may comprise a shaped material or a sealing material.

In one embodiment, by forming the first recess 220 and the second recess 230, the highest portion 440c of the conductive structure/wiring 440 can be lower than the upper surface 100a, such that the overall height of the chip package can be greatly reduced. Moreover, since the thickness of the encapsulation layer above the sensing region or the component region 200 can also be further reduced through the first recess 220 and the second recess 230, the sensing sensitivity of the sensing region or the component region 200 can be improved.

According to the above embodiment of the present invention, the first recess 220 and the second recess 230 are continuously formed in the wafer 100, and not only a single recess is formed but is directly extended downward to remove excess base material, except In addition to minimizing the highest portion of the conductive structure/wiring 440, the wafer 100 can have sufficient structural strength and avoid undercutting at the interface between the insulating layer 140 and the substrate 150, thereby improving the quality of the chip package. Moreover, the first recess 220 spans the entire length or width of the wafer 100, which increases the layout flexibility of the output signal of the chip package.

While the invention has been described above in terms of the preferred embodiments thereof, which are not intended to limit the invention, the invention may be modified and combined with the various embodiments described above without departing from the spirit and scope of the invention. example.

100a‧‧‧ upper surface

100b‧‧‧ lower surface

101, 102‧‧‧ side

140‧‧‧Insulation

150‧‧‧Base

200‧‧‧Sensor or component area

220‧‧‧ first notch

220a‧‧‧first side wall

220b‧‧‧ first bottom

230‧‧‧second notch

230a‧‧‧second side wall

230b‧‧‧ second bottom

Part P‧‧‧

Claims (20)

A chip package comprising: a wafer having an upper surface, a lower surface and a sidewall, wherein the wafer includes a signal pad region adjacent to the upper surface; a first recess along the sidewall from the upper surface Extending toward the lower surface; at least one second recess extending from a first bottom of the first recess toward the lower surface, wherein the first recess and the at least one second recess further along the upper surface One side of the side extends laterally, and the length of the first recess extending along the side is greater than the length of the second recess along the side; and a redistribution layer electrically connected to the signal pad region Extending into the at least one second recess. The chip package of claim 1, wherein the wafer includes an insulating layer adjacent to the upper surface and a substrate adjacent to the lower surface, and the first bottom is at or below the insulating layer and the substrate The interface between. The chip package of claim 1, wherein the first recess extends across the entire length of the side of the upper surface. The chip package of claim 3, wherein the first recess extends along at least a portion of the upper surface adjacent to at least a portion of the other side of the side. The chip package of claim 4, wherein the chip package comprises a plurality of second recesses extending along the side of the upper surface and the adjacent one of the other sides. The chip package of claim 3, wherein the first recess is further along at least a portion of the upper surface adjacent to both sides of the side edge. Degree extension. The chip package of claim 6, wherein the chip package comprises a plurality of second recesses extending along the side edges of the upper surface and the adjacent side edges. The chip package of claim 1, wherein the depth of the first recess is less than the depth of the at least one second recess. The chip package of claim 1, wherein a width of the first bottom of the first recess is smaller than a width of the first bottom of the at least one second recess. The chip package of claim 1, further comprising a further wafer, an interposer or a circuit board disposed under the lower surface and electrically connected to the redistribution layer. A method of fabricating a chip package, comprising: providing a wafer comprising a plurality of wafers, each wafer having an upper surface and a lower surface and including a signal pad region adjacent to the upper surface; forming a first recess Extending from the upper surface toward the lower surface; forming at least one second recess extending from a first bottom of the first recess toward the lower surface; forming a redistribution layer electrically connected to the signal pad region And extending into the at least one second recess; and cutting the wafer to separate the wafers such that each wafer has a sidewall, and the first recess extends along the sidewall, wherein the first recess And the at least one second recess extends laterally along a side of the upper surface, and the length of the first recess extending along the side is greater than the second recess along the second recess The length of the side extension. The method of manufacturing a chip package according to claim 11, wherein the wafer includes an insulating layer adjacent to the upper surface and a substrate adjacent to the lower surface, and the first bottom is at or below the insulating layer The interface with the substrate. The method of fabricating a chip package according to claim 11, wherein the first recess extends across the entire length of the side of the upper surface. The method of manufacturing a chip package according to claim 13, wherein the first recess extends along at least a portion of the length of the upper surface adjacent to the other side of the side. The method of manufacturing a chip package according to claim 14, wherein the chip package comprises a plurality of second notches extending along the side of the upper surface and the adjacent side of the other side, respectively. . The method of manufacturing a chip package according to claim 13, wherein the first recess extends along at least a portion of the upper surface adjacent to at least a portion of the sides of the side. The method of manufacturing a chip package according to claim 16, wherein the chip package comprises a plurality of second notches extending along the side edges of the upper surface and the adjacent side edges. The method of manufacturing a chip package according to claim 11, wherein the depth of the first recess is smaller than the depth of the at least one second recess. The method of manufacturing a chip package according to claim 11, wherein a width of the first bottom of the first recess is smaller than a width of the first bottom of the at least one second recess. The method for manufacturing a chip package according to claim 11, further comprising a further wafer, an interposer or a circuit board disposed under the lower surface and electrically connected to the redistribution layer.