TW201501097A - Output buffer circuit of source driver - Google Patents

Abstract

The present invention is directed to an output buffer circuit of an source driver, which includes two rail to rail circuits, a plurality of current mirrors and a clamping circuit. The two rail to rail circuits receive an input voltage to separately generate a first input current and a second input current. Two of the plurality of current mirrors separately receive the first input current and the second input current. The clamping circuit electrically connects to an output voltage terminal, a positive power terminal, a negative power terminal and the two current mirrors. The clamping circuit includes a first input transistor, a second input transistor and an enabled switch. The first input transistor electrically connects to the current mirror receiving the first input current so as to generate a first enabled current according to the first input current. The second input transistor electrically connects to the current mirror receiving the second input current so as to generate a second enabled current according to the second input current. The enabled switch is enabled according to the first enabled current and the second enabled current so as to electrically connect the output voltage terminal to the positive power terminal or the negative power terminal.

Description

Output buffer circuit of source driver

The present invention relates to an output buffer circuit for a source driver, and more particularly to an output buffer circuit for clamping an overshoot of a source driver charge and discharge voltage of an operational amplifier.

Many of today's portable electronic products are designed to be light, thin, short, and small. However, these electronic products may have a problem of slow response in circuit design using an operational amplifier.

Please refer to the first A diagram, which is a circuit diagram of a conventional operational amplifier. The positive power input terminal of the operational amplifier 1 is electrically connected to the PMOS (M _p ), and the negative power input terminal is electrically connected to the NMOS (M _n ), thereby the gate according to the PMOS (M _p ) and the NMOS (M _n ) The pole voltages V _gp and V _{gn are} used as the operating voltage of the operational amplifier 1.

The operational amplifier 1 receives the input voltage V _in from the positive input terminal (+). When the operational amplifier 1 is charged, the gate voltage V _{gp of the} PMOS (M _p ) can be boosted by increasing the input voltage V _in . When the operational amplifier 1 is discharging, the gate voltage V _{gn of the} NMOS (M _n ) can be reduced by lowering the input voltage V _in .

As shown in FIG. 1B and FIG. 1C, it is a schematic diagram of the operational amplifier 1 charging and V _gn discharging for the gate voltage V _gp . Since the current portable electronic device has a small bandwidth and a low current, when the operational amplifier 1 is charged or discharged with the input voltage V _in , the gate voltage V _gp or V _gn is overshooted (overshoot). )The phenomenon. In other words, when the gate voltage V _{gp is to be} charged to the level of the input voltage V _in , the time during which the gate voltage V _{gp is} charged to the input voltage V _in becomes longer due to the overshoot phenomenon, so that the portable type The response of the electronic device is slow. Similarly, the phenomenon of overshoot caused by the discharge of the gate voltage V _gn as shown in the first C diagram has the same problem.

Therefore, there is a need for a circuit that can clamp the charge and discharge voltage of the source driver of an operational amplifier.

The invention provides an output buffer circuit of a source driver, comprising a two-track-to-rail circuit, a plurality of current mirrors and a clamp circuit. A two-rail rail torail circuit receives an input voltage to generate a first input current and a second input current, respectively. Two of the plurality of current mirrors receive the first input current and the second input current, respectively. The clamping circuit is electrically connected to a voltage output terminal, a positive power input terminal, a negative power input terminal and two current mirrors. The clamping circuit comprises a first input transistor, a second input transistor and an actuating switch. The first input transistor is electrically connected to the current mirror that receives the first input current to generate a first actuation current according to the first input current. The second input transistor is electrically connected to the current mirror that receives the second input current to generate a second actuation current according to the second input current. The actuation switch is opened according to the first actuation current and the second actuation current, so that the voltage output terminal is electrically connected to the positive power input terminal or the negative power input terminal.

Accordingly, the output buffer circuit of the source driver of the present invention can clamp the operating voltage level of the positive and negative power input terminals of the operational amplifier during charging and discharging by the action of the clamping circuit, thereby reducing the overshoot time and utilizing The portable electronic product of the output buffer circuit of the invention can further improve the reaction speed when charging and discharging.

Please refer to the second figure, which is a schematic diagram of the output buffer circuit of the source driver of the present invention. The detailed output buffer circuits 2, 3 can be referred to the third A diagram and the third B diagram. The output buffer circuit 2 includes a two-track-to-rail circuit 21, a plurality of current mirrors 22, and a clamp circuit 23. A rail-to-rail circuit 21 receives an input voltage V _in to generate a first input current I _in1 and a second input current I _{in2 , respectively} . Two of the plurality of current mirrors 22, CM ₁ and CM ₂ , receive the first input current I _in1 and the second input current I _{in2 , respectively} . The clamping circuit 23 is electrically connected to a voltage output terminal V _out , a positive power input terminal V _gp , a negative power input terminal V _gn and two current mirrors CM ₁ , CM ₂ , and respectively via a PMOS M _p and an NMOS M _n respectively Electrically connected to a positive power terminal V _DDA and a negative power terminal (ground). The clamping circuit 23 includes a first input transistor M _in1 , a second input transistor M _in2 and an _{uninterrupting} switch M _sw1 . The first input transistor M _{in1 is} electrically connected to the current mirror CM ₁ receiving the first input current I _in1 to generate a first actuation current I _en1 according to the first input current I _in1 . The second input transistor M _{in2 is} electrically connected to the current mirror CM ₂ receiving the second input current I _in2 to generate a second actuation current I _en2 according to the second input current I _in2 . The actuation switch M _{sw1 is} opened according to the first actuation current I _en1 and the second actuation current I _en2 , so that the voltage output terminal V _{out is} electrically connected to the positive power input terminal V _gp or the negative power input terminal V _gn . In addition, in the following embodiments, for the sake of brevity, the voltage output terminal V _out has an output voltage V _out , the positive power input terminal V _gp has a gate voltage V _gp , and the negative power input terminal V _gn has a gate voltage V _Gn , the positive power supply terminal V _DDA has a power supply voltage V _DDA , which is expressed as the node has a node voltage, and the skilled artisan should clearly understand the meaning thereof, and details are not described herein.

Please refer to FIG. 3A, which is a circuit diagram for charging the output buffer circuit 2 of the present invention. The two-track rail circuit 21 includes an n-type differential input rail-to-rail circuit and a p-type differential input rail-to-rail circuit.

The n-type differential input rail-to-rail circuit includes an n-type differential pair transistor (M ₁ , M ₂ ) and a first current source M ₆ , wherein the first current source is an NMOS. The n-type differential pair transistor (M ₁ , M ₂ ) includes two NMOSs whose sources are electrically connected to each other, and the gate of M ₁ receives the input voltage V _in to generate a gate of the first current I ₁ , M ₂ Electrically connected to the voltage output terminal V _out . The first current source M _{6 is} electrically connected to the source of the n-type differential pair transistor (M ₁ , M ₂ ) to provide an n-type differential pair transistor (M ₁ , M ₂ ) and a first constant current I _c1 The first input current I _in1 is the first constant current I _c1 minus the first current I ₁ .

The rail-to-rail circuit of the p-type differential input includes a p-type differential pair transistor (M ₃ , M ₄ ) and a second current source M ₅ , wherein the second current source is a PMOS. The p-type differential pair transistor (M ₃ , M ₄ ) includes two PMOSs whose sources are electrically connected to each other, and the gate of M ₃ is electrically connected to the gate of M ₁ to receive an input voltage V _{in to} generate a first Two currents I ₂ . In addition, the gate of M ₄ is electrically connected to the gate of M ₂ and the voltage output terminal V _out . The second current source M _{5 is} electrically connected to the source of the p-type differential pair transistor (M ₃ , M ₄ ) to provide a p-type differential pair transistor (M ₃ , M ₄ ) to a second constant current I _c2 The second input current I _in2 is a second constant current I _c2 minus the second current I ₂ .

The plurality of current mirrors 22 includes a first current mirror CM ₁ and a second current mirror CM ₂ . The first current mirror CM ₁ has a first node electrically connected to the M ₂ drain of the n-type differential pair transistor (M ₁ , M ₂ ) to receive the first input current I _in1 from the first node, and first The node has a first node voltage V _A such that the first node voltage V _A follows a magnitude change of the first input current I _in1 . The second current mirror CM ₂ has a second node electrically connected to the M ₄ drain of the p-type differential pair transistor (M ₃ , M ₄ ) to receive the second input current I _in2 from the second node, and the second The node has a second node voltage V _E such that the second node voltage V _E follows a magnitude change of the second input current I _in2 .

The plurality of current mirrors 22 further includes a third current mirror CM ₃ and a fourth current mirror CM ₄ . The third current mirror CM _{3 is} electrically connected to the first current mirror CM ₁ and the fourth current mirror CM ₄ , and the fourth current mirror CM _{4 is} electrically connected to the second current mirror CM ₂ and the third current mirror CM ₃ , that is, the third The current mirror CM ₃ and the fourth current mirror CM ₄ are electrically connected to each other and electrically connected between the first current mirror CM ₁ and the second current mirror CM ₂ as the first input current I _in1 and the second input current I Current buffer between _in2 .

In addition, the first input transistor M _{in1 is} electrically connected to the first node, and the second input transistor M _{in2 is} electrically connected to the second node, so that the first input transistor M _in1 and the second input transistor M _in2 can be respectively according to the first The magnitude of a node voltage V _A and the second node voltage V _E generates a first actuation current I _en1 and a second actuation current I _en2 . In other words, the first actuation current I _en1 and the second actuation current I _en2 are indirectly varied according to the _magnitudes of the first input current I _in1 and the second input current I _in2 .

In the embodiment of the present invention, the actuation switch M _sw1 includes a first actuation transistor M ₇ , a second actuation transistor M _{8 ,} and a buffer transistor M ₉ , wherein the first actuation transistor system is The PMOS, the second actuated electro-emissive system is an NMOS. The first actuating transistor M ₇ has a source electrically connected to the power terminal V _DDA , and the gate is electrically connected to the _{drains of the} first input transistor M _in1 and the second input transistor M _in2 to enable the first actuating transistor When the input voltage V _in rises, M ₇ is turned on according to the first actuation current I _en1 and the second actuation current I _en2 .

Further, when the input voltage V _in rises, the n-type differential of the n-type differential input is increased to the first current I ₁ on the M _{1 of} the transistor (M ₁ , M ₂ ). , where the increase in current is indicated by a thick arrow. However, since the first constant current I _c1 supplied from the first current source M ₆ to the n-type differential pair transistor (M ₁ , M ₂ ) is a fixed value, it flows through the n-type differential pair transistor (M). _1, M ₂₎ M ₂ of a first input current I _in1 on which reduces.

Furthermore, as described above, when the first input current I _in1 decreases, the first node voltage V _A on the first current mirror CM ₁ increases accordingly, so that the first input transistor M _{in1 is} increased according to the first node The first actuating current I _en1 generated by the voltage V _A is then reduced.

Similarly, when the input voltage V _in rises, the p-type differential of the p-type differential input is reduced to the second current I ₂ on the M _{3 of} the transistor (M ₃ , M ₄ ), However, since the second constant current I _c2 supplied from the second current source M ₅ to the p-type differential pair transistor (M ₃ , M ₄ ) is a fixed value, it flows through the p-type differential pair transistor (M _3, a second input current I _in2 M ₄₎ M ₄ thereon is increased.

Moreover, when the second input current I _in2 increases, the second node voltage V _E on the second current mirror CM ₂ increases accordingly, so that the second input transistor M _{in2 is} according to the increased second node voltage V _E The resulting second actuation current I _en2 increases accordingly.

The first actuation transistor M _{7 of the} actuation switch M _sw1 has a gate voltage V _g7 , and since the source of the first input transistor M _in1 is electrically connected to the power supply terminal V _DDA , the second input transistor M The source of _in2 is electrically connected to the ground, so that when the second actuation current I _en2 flowing through the second input transistor M _in2 is greater than the first actuation current I _en1 flowing through the first input transistor M _in1 When the second actuating current I _en2 flowing to the ground terminal is greater than the first actuating current I _en1 , the gate voltage V _{g7 is} lowered and the first actuating transistor M _{7 is} thus turned on.

As described above, the drain of the second actuating transistor M ₈ of the actuating switch M _sw1 is electrically connected to the positive power input terminal V _gp , and the gate is electrically connected to the source of the second actuating transistor M ₇ , the source The pole is electrically connected to the voltage output terminal V _out . When the first actuator by the transistor M ₇ gate voltage drop V _g7 turned, so that the second brake actuator transistor M ₈ of voltage increase V _g8, thereby actuating the second transistor M ₈ is turned on, Further, the positive power input terminal V _{gp is} electrically connected to the voltage output terminal V _out .

Furthermore, since the input voltage V _in increases, the voltage V _{gp of the} positive power input terminal decreases, but since the PMOS M _{p is} electrically connected to the power supply terminal V _DDA , the PMOS M _{p is} turned on, and the power supply terminal V _DDA will pass through the PMOS M _p a voltage output terminal V _out of the charge, the output voltage V _out rises.

In other words, the clamping circuit 23 can cause the operational amplifier 2 to increase the voltage (V _gp ) of the positive power input terminal when the input voltage V _{in is} increased, that is, when the operational amplifier 2 is being charged, at the level of the output voltage V _out . As for the phenomenon that the level exceeding the input voltage V _in causes overshoot, that is, the output voltage V _{out of the} voltage rises clamps the voltage of the positive power input terminal V _gp voltage, so that the voltage of the positive power input terminal V _{gp does} not generate A large drop is made so that when the operational amplifier 2 is charged, it can quickly return to the level of the charging voltage (input voltage). Therefore, the time required for the operational amplifier 2 to overshoot due to charging can be reduced by the clamp circuit 23 of the present invention. In addition, the buffer transistor M _{9 is} electrically connected between the ground terminal and the drain of the first actuation transistor M ₇ . In this embodiment, the buffer transistor M ₉ is an NMOS.

Moreover, the clamping circuit 23 can select the size of the second input transistor M _in2 to be larger than the size of the first input transistor M _in1 according to the design requirement, thereby increasing the second actuation current I _en2 by a greater speed than the first actuation. The current I _en1 allows the first actuation transistor M ₇ and the second actuation transistor M _{8 of} the clamp circuit 23 to be turned on more quickly, thus making the overshoot time shorter.

Further, the operational amplifier when the input voltage V _in 2 is maintained constant, the first actuator clamp transistor circuit 23 of the actuation switch _SW1 M M gate voltage of approximately ₇ V _g7 system level power supply terminal V _DDA. Further, the gate voltage V _g7 is equal to the power supply terminal voltage V _DDA minus the turn-on voltage V _gs7 , and therefore, the first actuating transistor M ₇ cannot be turned on. Moreover, the second actuation transistor M ₈ has a _threshold voltage V _{g8 that} approaches the ground terminal voltage in the case where the first actuation transistor M ₇ cannot be turned on. In other words, the gate voltage V _g8 approaches the ground voltage level due to the drain current of the buffer transistor M ₉ flowing to the ground (discharge). Accordingly, the clamp circuit 23 maintains its input voltage V _in constant, that is, when it is in a steady state, its operation is turned off. In other words, after the output buffer circuit 2 described above is charged to a fixed voltage (input voltage), the output buffer circuit 2 will turn off its operation.

Please refer to FIG. 3B, which is a circuit diagram of the discharge of the output buffer circuit 3 of the present invention. The same circuit connection relationship and operation are as described above, and will not be described herein. However, it is worth mentioning that the operation of the operational amplifier on the circuit has positive polarity and negative polarity, which means that the operation of the voltage has two ranges, that is, the positive polarity amplifier and the negative polarity amplifier respectively represent two of the circuits. Channels, and switch between the two channels. Therefore, in practice, the positive polarity amplifier circuit shown in FIG. 3A and the negative polarity amplifier circuit shown in FIG. B are collectively disposed on the circuit, and the main difference between the two is in the actuation. The electrical connections of the switches are not the same.

The actuation switch M _sw2 includes a first actuation transistor M ₁₀ , a second actuation transistor M ₁₁ and a buffer transistor M ₁₂ , wherein the first actuation transistor M ₁₀ is an NMOS, the second actuation The transistor M ₁₁ is a PMOS. The first active transistor M _{10 has} its source electrically connected to the ground, and the gate is electrically connected to the _{drains of the} first input transistor M _in1 and the second input transistor M _in2 to make the first actuating transistor M ₁₀ When the input voltage V _in decreases, the first actuation current I _en1 and the second actuation current I _{en2 are} turned on.

Further, when the input voltage V _in decreases, the n-type differential input of the n-type differential input is reduced by the first current I _c1 of the M _{1 of} the differential transistor (M ₁ , M ₂ ). However, since the first constant current I _c1 supplied from the first current source M ₆ to the n-type differential pair transistor (M ₁ , M ₂ ) is a fixed value, the n-type differential pair transistor (M _{1 is made} The first input current I _in1 of M _{2 of} M ₂ ) increases.

Furthermore, as described above, when the first input current I _in1 increases, the first node voltage V _A on the first current mirror CM ₁ increases accordingly, so that the first input transistor M _{in1 is} increased according to the first node The first actuating current I _en1 generated by the voltage V _A increases accordingly.

Similarly, when the input voltage V _in drops, so that the flow through the p-type rail differential input transistor pair of M (M _{3, M. 4) 3} on which p-type differential circuit of the second rail current I ₂ Increasing, however, since the second constant current I _c2 supplied from the second current source M ₅ to the p-type differential pair transistor (M ₃ , M ₄ ) is a fixed value, thus flowing through the p-type differential pair transistor The second input current I _in2 of M _{4 of} (M ₃ , M ₄ ) decreases.

Moreover, when the second input current I _in2 decreases, the second node voltage V _E on the second current mirror CM ₂ decreases accordingly, so that the second input transistor M _{in2 is} according to the reduced second node voltage V _E The resulting second actuation current I _{en2 is} then reduced.

The first actuation transistor M _{10 of the} actuation switch M _sw2 has a gate voltage V _g10 , and since the source of the first input transistor M _in1 is electrically connected to the power supply terminal V _DDA , the second input transistor M The source of _in2 is electrically connected to the ground, so that the first actuation current I _en1 flowing through the first input transistor M _in1 is greater than the second actuation current I _en2 flowing through the second input transistor M _in2 When the first actuation current I _en1 flowing from the power supply terminal V _{DDA is} greater than the second actuation current I _en2 , the gate voltage V _{g10 is} increased, and the first actuation transistor M _{10 is} thus turned on.

As described above, the second actuation transistor M _{11 of the} actuation switch M _sw2 is electrically connected to the negative power input end (ground), and the gate is electrically connected to the source of the first actuation transistor M ₁₀ . The source is electrically connected to the voltage output terminal V _out . When the first actuator of the transistor M ₁₀ by the gate voltage V _g10 rises turned on, so that the gate of the transistor M of the second actuator ₁₁ to increase the voltage V _g11, thus the second actuator _{11 is} turned on the transistor M, Further, the negative power input terminal V _{gn is} electrically connected to the voltage output terminal V _out .

Further, since the input voltage V _in is reduced, so that the negative power supply input voltage V _gn rises, thus the NMOS M _n turned on, but due to NMOSM _n is electrically connected to the ground terminal, the buffer circuit 3 via the NMOS M _n of the voltage at the output V _out discharge the output voltage V _out decreases.

In other words, the clamping circuit 33 can cause the operational amplifier 3 to clamp the voltage V _{gn of the} negative power input terminal to the level of the output voltage V _out without exceeding the input when the input voltage V _in decreases, that is, when the operational amplifier 3 is discharged. The level of the voltage V _in causes an overshoot phenomenon, that is, the output voltage V _{out of the} voltage drop clamps the voltage of the negative power input terminal V _{gn of the} voltage rise, so that the voltage of the negative power input terminal V _{gn does} not cause a large rise. In order to quickly return to the level of the discharge voltage when the operational amplifier 3 is discharged. Therefore, the time during which the operational amplifier 3 is overshooted by the discharge can be reduced by the clamp circuit 23. In addition, the buffer transistor M _{12 is} electrically connected between the power supply terminal V _DDA and the drain of the first actuation transistor M ₁₀ . In this embodiment, the buffer transistor M ₁₂ is a PMOS.

Moreover, the clamping circuit 33 can select the size of the first input transistor M _in1 to be larger than the size of the second input transistor M _in2 according to the design requirement, thereby increasing the speed of the first actuation current I _en1 by more than the second actuation. The current I _en2 allows the first actuation transistor M ₁₀ and the first actuation transistor M _{11 of} the clamp circuit 33 to be turned on more quickly, thereby making the undershoot time shorter.

Further, the operational amplifier when the input voltage V _in 3 is maintained constant, clamping circuit 33 actuating the first actuator switch transistor M M _SW2 gate voltage of ₁₀ V _g10 ground proximity system level. Further, the gate voltage V _g10 is equal to the ground terminal voltage plus the turn-on voltage V _gs10 , and therefore, the first actuating transistor M ₁₀ cannot be turned on. Moreover, in the case where the first actuation transistor M ₁₀ cannot be turned on, the gate voltage V _g11 of the second actuation transistor M ₁₁ approaches the power supply terminal voltage V _DDA . Further, the gate voltage V _g11 approaches the power supply terminal voltage level V _DDA because the drain current of the buffer transistor M ₁₂ flows out (charges) from the current terminal. Accordingly, the clamp circuit 33 to the input voltage V _in is maintained constant, i.e., closed in a steady state based upon its actuation. In other words, after the output buffer circuit 3 described above is discharged to a fixed voltage (input voltage), the output buffer circuit 3 will turn off its operation.

In summary, the output buffer circuit of the source driver of the present invention can clamp the operating voltage level of the positive and negative power input terminals of the operational amplifier during charging and discharging by the action of the clamping circuit, thereby reducing the overshoot time. The portable electronic product using the output buffer circuit of the present invention can further improve the reaction speed at the time of charging and discharging.

1‧‧‧Operational Amplifier
2, 3‧‧‧ output buffer circuit
21, 31‧‧‧ two-track rail circuit
22, 32‧‧‧Multiple current mirrors
23, 33‧‧‧Clamping circuit
V _in ‧‧‧ input voltage
V _out ‧‧‧voltage output
V _gp , V _gn ‧‧ ‧ gate voltage
V _DDA ‧‧‧ positive power terminal
V _g5 ~ V _g8 ‧‧‧ gate voltage
V _A ‧‧‧first node voltage
V _E ‧‧‧second node voltage
M _p , M _n MOS‧‧‧ transistor
M ₁ ~ M ₁₂ ‧‧‧O crystal
M _in1 ‧‧‧first input transistor
M _in2 ‧‧‧Second input transistor
M _sw1 , M _sw2 ‧‧‧ actuation switch
CM ₁ ~ CM ₄ ‧‧‧current mirror
I ₁ ‧‧‧First current
I ₂ ‧‧‧second current
I _in1 ‧‧‧first input current
I _in2 ‧‧‧second input current
I _c1 ‧‧‧first constant current
I _c2 ‧‧‧second constant current
I _en1 ‧‧‧First actuating current
I _{en2 ‧‧‧second} actuation current

The first A diagram is a circuit diagram of a conventional operational amplifier; the first B diagram is a schematic diagram of the operational amplifier charging the gate voltage; the first C diagram is a schematic diagram of the operational amplifier discharge for the gate voltage; The output buffer circuit diagram of the source driver of the present invention; the third A diagram is a circuit diagram for charging the output buffer circuit of the present invention; and the third B diagram is a circuit diagram of the discharge of the output buffer circuit of the present invention.

2‧‧‧Output buffer circuit

21‧‧‧Two-track rail circuit

22‧‧‧Multiple current mirrors

23‧‧‧Clamping circuit

V _in ‧‧‧ input voltage

V _out ‧‧‧voltage output

V _gp , V _gn ‧‧ ‧ gate voltage

M _p , M _n ‧‧‧MOS transistor

V _DDA ‧‧‧ positive power terminal

Claims (10)

An output buffer circuit of a source driver includes: a two-track rail circuit that receives an input voltage to generate a first input current and a second input current respectively; a plurality of current mirrors, wherein the two current mirrors respectively receive the a first input current and the second input current; and a clamping circuit electrically connected to a voltage output terminal, a positive power input terminal, a negative power input terminal and the second current mirror, comprising: a first input transistor, Electrically connecting the current mirror receiving the first input current to generate a first actuation current according to the first input current; a second input transistor electrically connecting the current mirror receiving the second input current, Generating a second actuation current according to the second input current; and an actuating switch, the voltage output terminal is electrically connected to the positive power input terminal according to the first actuation current and the second actuation current being turned on. The negative power input. The output buffer circuit of claim 1, wherein the two-track rail circuit comprises: an n-type differential input track-to-rail circuit, comprising: an n-type differential pair transistor, receiving the input The voltage is used to generate a first current; and a first current source is electrically connected to the n-type differential pair transistor to provide a first constant current of the n-type differential pair transistor, wherein the first input current The first current is subtracted from the first constant current; and a p-type differential input rail-to-rail circuit includes: a p-type differential pair transistor electrically connected to the n-type differential pair transistor; Receiving the input voltage to generate a second current; and a second current source electrically connecting the p-type differential pair transistor to provide a second constant current of the p-type differential pair transistor, wherein the The two input currents are the second constant current minus the second current. The output buffer circuit of claim 1, wherein the plurality of current mirrors comprise: a first current mirror, receiving the first input current from a first node, wherein the first node has a first node And a second current mirror receiving the second input current from a second node, wherein the second node has a second node voltage. The output buffer circuit of claim 3, wherein the first input transistor is electrically connected to the first node, and the second input transistor is electrically connected to the second node. The output buffer circuit of claim 3, wherein the plurality of current mirrors further comprise a third current mirror and a fourth current mirror electrically connected to each other, and the third current mirror and the fourth The current mirror is electrically connected between the first current mirror and the second current mirror. The output buffer circuit of claim 1, wherein the actuating switch comprises: a first actuating transistor, the gate electrically connecting the first input transistor and the second input transistor, the source An electrically connected terminal, wherein the first actuating transistor is turned on according to the first actuating current and the second actuating current when the input voltage rises; a second actuating transistor having a drain Electrically connecting the positive power input end, the source is electrically connected to the voltage output end, and the gate is electrically connected to the drain of the first actuating transistor, wherein the second actuating transistor is at the first actuating current When the crystal is turned on, the voltage output terminal is electrically connected to the positive power input end; and a buffer transistor is electrically connected between a ground end and a drain of the first actuating transistor. The output buffer circuit of claim 6, wherein the size of the second input transistor is larger than the size of the first input transistor. The output buffer circuit of claim 1, wherein the actuating switch comprises: a first actuating transistor, the gate electrically connecting the first input transistor and the second input transistor, the source a first electrically actuated transistor, wherein the first actuating transistor is turned on according to the first actuating current and the second actuating current when the input voltage drops; and a second actuating transistor having a drain Electrically connecting the negative power input end, the source is electrically connected to the voltage output end, and the gate is electrically connected to the drain of the first actuating transistor, wherein the second actuating transistor is at the first actuating current When the crystal is turned on, the voltage output terminal is electrically connected to the negative power input end; and a buffer transistor is electrically connected between a power supply terminal and the drain of the first actuating transistor. The output buffer circuit of claim 8, wherein the size of the first input transistor is greater than the size of the second input transistor. The output buffer circuit of claim 1, wherein the clamping circuit and the positive power input end are electrically connected to a PMOS, and the clamping circuit and the negative power input end are electrically connected to an NMOS. .