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TW201444040A - Semiconductor package and method of manufacture - Google Patents

Semiconductor package and method of manufacture Download PDF

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Publication number
TW201444040A
TW201444040A TW102115846A TW102115846A TW201444040A TW 201444040 A TW201444040 A TW 201444040A TW 102115846 A TW102115846 A TW 102115846A TW 102115846 A TW102115846 A TW 102115846A TW 201444040 A TW201444040 A TW 201444040A
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Taiwan
Prior art keywords
layer
semiconductor package
encapsulant
electronic component
circuit layer
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TW102115846A
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Chinese (zh)
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TWI541965B (en
Inventor
張翊峰
王隆源
蔡芳霖
劉正仁
陳宏棋
Original Assignee
矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW102115846A priority Critical patent/TWI541965B/en
Priority to CN201310174210.8A priority patent/CN104134641A/en
Publication of TW201444040A publication Critical patent/TW201444040A/en
Application granted granted Critical
Publication of TWI541965B publication Critical patent/TWI541965B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention provides a semiconductor package and a method of manufacturing the same, the semiconductor package including a first encapsulant having opposing first and second surfaces; a plurality of conductors formed in the first encapsulant and having first and second connectors respectively connecting to the first and second surfaces; a plurality of connecting pads formed in the first encapsulant and exposing from the second surface of the first encapsulant; a chip embedded in the first encapsulant and disposed on the connecting pads; and a first circuit layer formed on the first surface of the first encapsulant and electrically connected to the first connector of the conductor, thereby reducing the package thickness and size as a result.

Description

半導體封裝件及其製法 Semiconductor package and its manufacturing method

本發明係關於一種半導體封裝件及其製法，特別是指一種嵌埋晶片於封裝膠體內之半導體封裝件及其製法。 The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package in which a wafer is embedded in a package body and a method of fabricating the same.

隨著半導體技術之日新月異、以及電子產品朝向薄型化之趨勢，半導體封裝件之尺寸或體積亦隨之不斷縮小，藉以使該半導體封裝件達到輕薄短小之目的。 With the ever-changing semiconductor technology and the trend toward thinner electronic products, the size or volume of semiconductor packages has also been shrinking, so that the semiconductor package can be light, thin and short.

第1A圖係繪示習知技術之第201208021號中華民國專利中半導體封裝件1之剖視示意圖。如圖所示，半導體封裝件1係包括：硬質板10、複數第一銲球11、晶片12、包覆層13、介電層14、第三線路層153、第一拒銲層161、第二拒銲層162以及複數第二銲球171。 1A is a cross-sectional view showing a semiconductor package 1 of the Republic of China patent No. 201208021 of the prior art. As shown, the semiconductor package 1 includes a hard board 10, a plurality of first solder balls 11, a wafer 12, a cladding layer 13, a dielectric layer 14, a third wiring layer 153, a first solder resist layer 161, and a first Two solder resist layers 162 and a plurality of second solder balls 171.

該硬質板10係具有相對之第一表面10a與第二表面10b，該第一表面10a與第二表面10b上分別形成有第一線路層151及第二線路層152。該第一線路層151電性連接該第二線路層152，並具有複數連接墊154，該第一銲球 11係設置於該連接墊154上。 The hard plate 10 has a first surface 10a and a second surface 10b opposite to each other, and a first circuit layer 151 and a second circuit layer 152 are formed on the first surface 10a and the second surface 10b, respectively. The first circuit layer 151 is electrically connected to the second circuit layer 152 and has a plurality of connection pads 154, the first solder ball The 11 series is disposed on the connection pad 154.

該晶片12係設置於該硬質板10之第一表面10a上，並具有作用面121與非作用面122。該作用面121上設有複數電極墊123，並以該非作用面122接置於該硬質板10之第一表面10a上。 The wafer 12 is disposed on the first surface 10a of the hard plate 10 and has an active surface 121 and an inactive surface 122. The active surface 121 is provided with a plurality of electrode pads 123, and is attached to the first surface 10a of the hard plate 10 by the non-active surface 122.

該包覆層13係形成於該硬質板10之第一表面10a上，用以包覆該第一銲球11及該晶片12，並外露出該第一銲球11及晶片12之作用面121。該介電層14係形成於該包覆層13上，並具有複數開孔以外露出該第一銲球11及該晶片12之作用面121上之電極墊123。 The cladding layer 13 is formed on the first surface 10a of the hard plate 10 for covering the first solder ball 11 and the wafer 12, and exposing the first solder ball 11 and the active surface 121 of the wafer 12. . The dielectric layer 14 is formed on the cladding layer 13 and has an electrode pad 123 exposed on the first solder ball 11 and the active surface 121 of the wafer 12 in addition to a plurality of openings.

該第三線路層153係形成於該介電層14上以電性連接該第一銲球11及該電極墊123。該第一拒銲層161係形成於該介電層14及第三線路層153上，並外露部分該第三線路層153。該第二拒銲層162係形成於該硬質板10之第二表面10b及第二線路層152上，並外露出部分該第二線路層152。 The third circuit layer 153 is formed on the dielectric layer 14 to electrically connect the first solder ball 11 and the electrode pad 123. The first solder resist layer 161 is formed on the dielectric layer 14 and the third wiring layer 153, and the third wiring layer 153 is exposed. The second solder resist layer 162 is formed on the second surface 10b and the second wiring layer 152 of the hard board 10, and partially exposes the second circuit layer 152.

第1B圖係依據第1A圖繪示習知技術之第201208021號中華民國專利中另一半導體封裝件1'之剖視示意圖。如圖所示，半導體封裝件1'除包括第1A圖之半導體封裝件1外，亦包括半導體裝置18以及複數第三銲球172。該半導體裝置18可為半導體封裝結構，係藉由該第二銲球171接置於該第一拒銲層161所外露之第三線路層153，該第三銲球172係接置於該第二拒銲層162所外露之第二線路層152上。 1B is a cross-sectional view showing another semiconductor package 1' in the Republic of China patent No. 201208021 according to the first embodiment. As shown, the semiconductor package 1' includes a semiconductor device 18 and a plurality of third solder balls 172 in addition to the semiconductor package 1 of FIG. The semiconductor device 18 can be a semiconductor package structure, and the second solder ball 171 is connected to the third circuit layer 153 exposed by the first solder resist layer 161. The third solder ball 172 is connected to the first solder ball 172. The second solder layer 162 is exposed on the second circuit layer 152.

上述半導體封裝件之缺點，在於將包覆於包覆層內之晶片設置於硬質板上，使得該半導體封裝件之整體厚度較厚，導致該半導體封裝件之尺寸或體積較大、材料成本亦較高。 The semiconductor package has the disadvantage that the wafer covered in the cladding layer is disposed on the hard board, so that the overall thickness of the semiconductor package is thick, resulting in a large size or volume of the semiconductor package, and the material cost is also Higher.

因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.

鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝件，其包括：第一封裝膠體，係具有相對之第一表面與第二表面；複數導電體，係形成於該第一封裝膠體內，並具有分別外露於該第一表面與該第二表面之第一連接部及第二連接部；複數連接墊，係形成於該第一封裝膠體內，並外露於該第一封裝膠體之第二表面；晶片，係嵌埋於該第一封裝膠體內，並設置於該連接墊上；以及第一線路層，係形成於該第一封裝膠體之第一表面上，並電性連接該導電體之第一連接部。 In view of the above-mentioned various deficiencies of the prior art, the present invention provides a semiconductor package comprising: a first encapsulant having opposite first and second surfaces; and a plurality of electrical conductors formed on the first encapsulant The body has a first connecting portion and a second connecting portion respectively exposed on the first surface and the second surface; a plurality of connecting pads are formed in the first encapsulating body and exposed to the first encapsulant a second surface; a wafer embedded in the first encapsulant and disposed on the connection pad; and a first circuit layer formed on the first surface of the first encapsulant and electrically connected to the conductive The first connection of the body.

該半導體封裝件可包括：表面處理層，係形成於該第一線路層上。 The semiconductor package may include a surface treatment layer formed on the first wiring layer.

該半導體封裝件可包括：第一拒銲層，係形成於該第一線路層上，並外露出部分該第一線路層；電子元件與複數導電元件，該電子元件係設置於該第一拒銲層上，並藉由該導電元件電性連接該第一線路層；以及第二封裝膠體，係形成於該第一封裝膠體上方，並包覆該第一線路層、第一拒銲層、電子元件及導電元件。 The semiconductor package may include: a first solder resist layer formed on the first circuit layer and exposing a portion of the first circuit layer; an electronic component and a plurality of conductive components, the electronic component being disposed in the first reject And electrically connecting the first circuit layer to the solder layer; and the second encapsulant is formed over the first encapsulant and covering the first circuit layer, the first solder resist layer, Electronic components and conductive components.

該半導體封裝件可包括：第二線路層，係形成於該第一封裝膠體之第二表面上，並電性連接該導電體之第二連接部與該連接墊；第二拒銲層，係形成於該第二線路層上，並外露出部分該第二線路層；電子元件與複數導電元件，該電子元件係設置於該第二拒銲層上，並藉由該導電元件電性連接該第二線路層；以及第二封裝膠體，係形成於該第一封裝膠體上方，並包覆該第二線路層、第二拒銲層、電子元件及導電元件。 The semiconductor package may include: a second circuit layer formed on the second surface of the first encapsulant and electrically connected to the second connection portion of the electrical conductor and the connection pad; the second solder resist layer Forming on the second circuit layer, and exposing a portion of the second circuit layer; the electronic component and the plurality of conductive components, the electronic component is disposed on the second solder resist layer, and electrically connected by the conductive component a second circuit layer; and a second encapsulant formed over the first encapsulant and covering the second circuit layer, the second solder resist layer, the electronic component, and the conductive component.

本發明亦提供一種半導體封裝件之製法，其包括：提供具有金屬層之承載件；形成複數連接墊及複數高於該連接墊之導電體於該金屬層上；設置晶片於該連接墊上；形成第一封裝膠體於該金屬層上，以包覆該連接墊、導電體及晶片，並外露出該導電體之連接部；以及形成第一線路層於該第一封裝膠體上以電性連接該導電體之連接部。 The invention also provides a method for fabricating a semiconductor package, comprising: providing a carrier having a metal layer; forming a plurality of connection pads and a plurality of electrical conductors above the connection pad on the metal layer; and disposing a wafer on the connection pad; forming a first encapsulant on the metal layer to cover the connection pad, the conductor and the wafer, and exposing the connection portion of the conductor; and forming a first circuit layer on the first encapsulant to electrically connect the The connection of the conductors.

形成該連接墊之步驟可包括：形成具有複數第一穿孔之第一阻層於該金屬層上，該第一穿孔係外露出部分該金屬層；形成該連接墊於該第一穿孔內以連接該金屬層；以及移除該第一阻層。 The step of forming the connection pad may include: forming a first resist layer having a plurality of first perforations on the metal layer, the first perforation exposing a portion of the metal layer; forming the connection pad in the first perforation to connect The metal layer; and removing the first resist layer.

形成該導電體之步驟可包括：形成具有複數第二穿孔之第二阻層於該金屬層上，該第二穿孔係高於該連接墊並外露出部分該金屬層；形成該導電體於該第二穿孔內以連接該金屬層；以及移除該第二阻層。 The step of forming the electrical conductor may include: forming a second resist layer having a plurality of second perforations on the metal layer, the second perforation being higher than the connection pad and exposing a portion of the metal layer; forming the electrical conductor a second through hole to connect the metal layer; and remove the second resist layer.

該半導體封裝件之製法可包括：形成表面處理層於該第一線路層上。 The method of fabricating the semiconductor package can include: forming a surface treatment layer on the first circuit layer.

該半導體封裝件之製法可包括：形成第一拒銲層於該第一線路層上並外露出部分該第一線路層；設置電子元件於該第一拒銲層上，並藉由複數導電元件電性連接該第一線路層；以及形成第二封裝膠體於該第一封裝膠體上方，以包覆該第一線路層、第一拒銲層、電子元件及導電元件。 The semiconductor package can be formed by: forming a first solder resist layer on the first circuit layer and exposing a portion of the first circuit layer; providing electronic components on the first solder resist layer and using a plurality of conductive elements Electrically connecting the first circuit layer; and forming a second encapsulant over the first encapsulant to encapsulate the first circuit layer, the first solder resist layer, the electronic component, and the conductive component.

該半導體封裝件之製法可包括：移除該承載件；圖案化該金屬層以形成第二線路層；形成第二拒銲層於該第二線路層上並外露出部分該第二線路層；設置電子元件於該第二拒銲層上，並藉由複數導電元件電性連接該第二線路層；以及形成第二封裝膠體於該第一封裝膠體上方，以包覆該第二線路層、第二拒銲層、電子元件及導電元件。 The method of fabricating the semiconductor package may include: removing the carrier; patterning the metal layer to form a second circuit layer; forming a second solder resist layer on the second circuit layer and exposing a portion of the second circuit layer; An electronic component is disposed on the second solder resist layer, and electrically connected to the second circuit layer by a plurality of conductive elements; and a second encapsulant is formed over the first encapsulant to cover the second circuit layer, The second solder resist layer, the electronic component and the conductive component.

上述之電子元件可為半導體晶片或半導體封裝結構。 The electronic component described above may be a semiconductor wafer or a semiconductor package structure.

由上可知，本發明之半導體封裝件及其製法，主要係將導電體及連接墊分別形成於封裝膠體內，並將晶片嵌埋於該封裝膠體內以設置於該連接墊上，且將該導電體之連接部外露於該封裝膠體之表面，再將線路層形成於該封裝膠體之表面上以電性連接該導電體之連接部。藉此，本發明能降低該半導體封裝件之厚度，以縮小該半導體封裝件之尺寸或體積，進而減少該半導體封裝件之材料成本。 As can be seen from the above, the semiconductor package of the present invention and the manufacturing method thereof are mainly formed by forming a conductor and a connection pad in the encapsulant, and embedding the wafer in the encapsulant to be disposed on the connection pad, and the conductive The connection portion of the body is exposed on the surface of the encapsulant, and a circuit layer is formed on the surface of the encapsulant to electrically connect the connection portion of the electrical conductor. Thereby, the present invention can reduce the thickness of the semiconductor package to reduce the size or volume of the semiconductor package, thereby reducing the material cost of the semiconductor package.

1、1'‧‧‧半導體封裝件 1, 1'‧‧‧ semiconductor package

10‧‧‧硬質板 10‧‧‧hard board

10a‧‧‧第一表面 10a‧‧‧ first surface

10b‧‧‧第二表面 10b‧‧‧second surface

11‧‧‧第一銲球 11‧‧‧First solder ball

12‧‧‧晶片 12‧‧‧ wafer

121‧‧‧作用面 121‧‧‧Action surface

122‧‧‧非作用面 122‧‧‧Non-active surface

123‧‧‧電極墊 123‧‧‧electrode pad

13‧‧‧包覆層 13‧‧‧Cladding

14‧‧‧介電層 14‧‧‧Dielectric layer

151‧‧‧第一線路層 151‧‧‧First line layer

152‧‧‧第二線路層 152‧‧‧Second circuit layer

153‧‧‧第三線路層 153‧‧‧ third circuit layer

154‧‧‧連接墊 154‧‧‧Connecting mat

161‧‧‧第一拒銲層 161‧‧‧First solder mask

162‧‧‧第二拒銲層 162‧‧‧Second solder mask

171‧‧‧第二銲球 171‧‧‧second solder ball

172‧‧‧第三銲球 172‧‧‧ third solder ball

18‧‧‧半導體裝置 18‧‧‧Semiconductor device

2、3、4、5、6‧‧‧半導體封裝件 2, 3, 4, 5, 6‧‧‧ semiconductor packages

20‧‧‧承載件 20‧‧‧Carrier

201‧‧‧金屬層 201‧‧‧metal layer

21‧‧‧第一阻層 21‧‧‧First resistance layer

211‧‧‧第一穿孔 211‧‧‧First perforation

212‧‧‧連接墊 212‧‧‧Connecting mat

22‧‧‧第二阻層 22‧‧‧second resistance layer

221‧‧‧第二穿孔 221‧‧‧Second perforation

222‧‧‧導電體 222‧‧‧Electrical conductor

223‧‧‧第一連接部 223‧‧‧First connection

224‧‧‧第二連接部 224‧‧‧Second connection

23‧‧‧晶片 23‧‧‧ wafer

24‧‧‧第一封裝膠體 24‧‧‧First encapsulant

241‧‧‧第一表面 241‧‧‧ first surface

242‧‧‧第二表面 242‧‧‧ second surface

25‧‧‧第一線路層 25‧‧‧First line layer

251‧‧‧第一開口 251‧‧‧ first opening

26‧‧‧表面處理層 26‧‧‧Surface treatment layer

27‧‧‧第一拒銲層 27‧‧‧First solder mask

271‧‧‧第二開口 271‧‧‧ second opening

28‧‧‧第二線路層 28‧‧‧Second circuit layer

281‧‧‧第三開口 281‧‧‧ third opening

29‧‧‧第二拒銲層 29‧‧‧Second solder mask

291‧‧‧第四開口 291‧‧‧ fourth opening

30、301‧‧‧電子元件 30, 301‧‧‧ Electronic components

31、311‧‧‧銲線 31, 311‧‧‧ welding line

32‧‧‧第二封裝膠體 32‧‧‧Second encapsulant

33‧‧‧銲球 33‧‧‧ solder balls

34‧‧‧導電元件 34‧‧‧Conductive components

第1A圖係繪示習知技術之第201208021號中華民國專利中半導體封裝件之剖視示意圖；第1B圖係依據第1A圖繪示習知技術之第201208021號中華民國專利中另一半導體封裝件之剖視示意圖； 第2A圖至第2O圖係繪示本發明之半導體封裝件及其製法之第一實施例之剖視示意圖，其中，第2K'圖為第2K圖之另一態樣；第3圖係依據第2O圖繪示本發明之半導體封裝件之第二實施例之剖視示意圖；第4圖係依據第2O圖繪示本發明之半導體封裝件之第三實施例之剖視示意圖；第5圖係依據第2O圖繪示本發明之半導體封裝件之第四實施例之剖視示意圖；以及第6圖係依據第2O圖繪示本發明之半導體封裝件之第五實施例之剖視示意圖。 1A is a cross-sectional view showing a semiconductor package in the Republic of China patent No. 201208021 of the prior art; and FIG. 1B is another semiconductor package in the Republic of China patent No. 201208021 according to the first embodiment. A schematic cross-sectional view of the piece; 2A to 2O are schematic cross-sectional views showing a first embodiment of a semiconductor package of the present invention and a method of fabricating the same, wherein the 2K' diagram is another aspect of the 2K diagram; and the 3rd diagram is based on FIG. 2 is a cross-sectional view showing a second embodiment of the semiconductor package of the present invention; FIG. 4 is a cross-sectional view showing a third embodiment of the semiconductor package of the present invention according to FIG. FIG. 2 is a cross-sectional view showing a fourth embodiment of a semiconductor package of the present invention; and FIG. 6 is a cross-sectional view showing a fifth embodiment of the semiconductor package of the present invention according to FIG.

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered.

同時，本說明書中所引用之如「上」、「一」、「第一」、「第二」、「表面」及「連接部」等用語，亦僅為便於敘述 之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 At the same time, the terms "upper", "one", "first", "second", "surface" and "connected" as quoted in this manual are also for convenience only. It is to be understood that the scope of the invention is not limited by the scope of the invention.

第2A圖至第2O圖係繪示本發明之半導體封裝件及其製法之第一實施例之剖視示意圖，其中，第2K'圖為第2K圖之另一態樣。 2A to 2O are cross-sectional views showing a first embodiment of the semiconductor package of the present invention and a method of manufacturing the same, wherein the 2K' is another aspect of the 2Kth.

如第2A圖所示，提供具有金屬層201之承載件20。 As shown in FIG. 2A, a carrier 20 having a metal layer 201 is provided.

如第2B圖所示，形成具有複數第一穿孔211之第一阻層21於該金屬層201上，該第一穿孔211係外露出部分該金屬層201。 As shown in FIG. 2B, a first resist layer 21 having a plurality of first vias 211 is formed on the metal layer 201, and the first vias 211 expose a portion of the metal layer 201.

如第2C圖所示，形成該連接墊212於該第一穿孔211內以連接該金屬層201。 As shown in FIG. 2C, the connection pad 212 is formed in the first through hole 211 to connect the metal layer 201.

如第2D圖所示，移除該第一阻層21，以外露出該連接墊212。 As shown in FIG. 2D, the first resist layer 21 is removed, and the connection pad 212 is exposed.

如第2E圖所示，形成具有複數第二穿孔221之第二阻層22於該金屬層201上，該第二穿孔221之高度係高於該連接墊212之高度並外露出部分該金屬層201。 As shown in FIG. 2E, a second resist layer 22 having a plurality of second vias 221 is formed on the metal layer 201. The height of the second vias 221 is higher than the height of the connection pads 212 and a portion of the metal layer is exposed. 201.

如第2F圖所示，形成具有第一連接部223與第二連接部224之導電體222於該第二穿孔221內以連接該金屬層201。該導電體222可為金屬柱、凸塊、銲球或針腳(pin)等。 As shown in FIG. 2F, an electrical conductor 222 having a first connecting portion 223 and a second connecting portion 224 is formed in the second through hole 221 to connect the metal layer 201. The conductor 222 can be a metal post, a bump, a solder ball or a pin or the like.

如第2G圖所示，移除該第二阻層22，以外露出該連接墊212及該導電體222。 As shown in FIG. 2G, the second resist layer 22 is removed, and the connection pad 212 and the conductor 222 are exposed.

如第2H圖所示，設置晶片23於該連接墊212上。 As shown in FIG. 2H, the wafer 23 is placed on the connection pad 212.

如第2I圖所示，形成第一封裝膠體24於該金屬層201上，以包覆該連接墊212、導電體222及晶片23。 As shown in FIG. 2I, a first encapsulant 24 is formed on the metal layer 201 to cover the connection pad 212, the conductor 222, and the wafer 23.

如第2J圖所示，薄化該第一封裝膠體24之厚度，以外露出該導電體222之第一連接部223。該第一封裝膠體24係具有分別外露出該第一連接部223及該第二連接部224之相對之第一表面241與第二表面242。 As shown in FIG. 2J, the thickness of the first encapsulant 24 is thinned, and the first connection portion 223 of the conductor 222 is exposed. The first encapsulant 24 has a first surface 241 and a second surface 242 respectively exposing the first connecting portion 223 and the second connecting portion 224 .

如第2K圖所示，藉由無電電鍍(electroless plating)等方式，形成第一線路層25於該第一封裝膠體24上，以電性連接該導電體222之第一連接部223。該第一線路層25係具有複數第一開口251以外露出部分該第一封裝膠體24。 As shown in FIG. 2K, the first wiring layer 25 is formed on the first encapsulant 24 by electroless plating or the like to electrically connect the first connection portion 223 of the conductor 222. The first circuit layer 25 has a plurality of first openings 251 exposed to the first encapsulant 24 .

此外，如第2K'圖所示之另一態樣中，亦可形成表面處理層26於第2K圖之第一線路層25上並外露出該第一開口251。該表面處理層26可由鎳、鈀、金(Ni/Pd/Au)所組成群組之合金或多層金屬其中一者所形成。 Further, in another aspect as shown in FIG. 2K', the surface treatment layer 26 may be formed on the first wiring layer 25 of FIG. 2K and the first opening 251 may be exposed. The surface treatment layer 26 may be formed of one of an alloy of nickel, palladium, gold (Ni/Pd/Au), or a plurality of layers of metal.

如第2L圖所示，形成具有複數第二開口271之第一拒銲層27(或絕緣層)於第2K圖之第一線路層25及第一開口251上，該第二開口271係外露出部分該第一線路層25。但在其他實施例中，亦可先形成該第一拒銲層27於第2K'圖之表面處理層26上，使該第二開口271外露出部分該表面處理層26(圖中未繪示)。 As shown in FIG. 2L, a first solder resist layer 27 (or insulating layer) having a plurality of second openings 271 is formed on the first wiring layer 25 and the first opening 251 of FIG. 2K, and the second opening 271 is external. A portion of the first wiring layer 25 is exposed. In other embodiments, the first solder resist layer 27 may be formed on the surface treatment layer 26 of the second K', such that the second opening 271 exposes a portion of the surface treatment layer 26 (not shown). ).

如第2M圖所示，移除該承載件20，以外露出該金屬層201。 As shown in FIG. 2M, the carrier 20 is removed and the metal layer 201 is exposed.

如第2N圖所示，圖案化該金屬層201以形成具有複 數第三開口281之第二線路層28，該第三開口281係外露出部分該第一封裝膠體24之第二表面242。 As shown in FIG. 2N, the metal layer 201 is patterned to form a complex The second circuit layer 28 of the third opening 281 exposes a portion of the second surface 242 of the first encapsulant 24 .

如第2O圖所示，形成具有複數第四開口291之第二拒銲層29(或絕緣層)於該第二線路層28及該第三開口281上，該第四開口291係外露出部分該第二線路層28。 As shown in FIG. 2O, a second solder resist layer 29 (or insulating layer) having a plurality of fourth openings 291 is formed on the second wiring layer 28 and the third opening 281, and the fourth opening 291 is exposed outside. The second circuit layer 28.

本發明另提供一種半導體封裝件2，如第2O圖所示。該半導體封裝件2係包括第一封裝膠體24、複數導電體222、複數連接墊212、晶片23以及第一線路層25。 The present invention further provides a semiconductor package 2 as shown in FIG. The semiconductor package 2 includes a first encapsulant 24, a plurality of conductors 222, a plurality of connection pads 212, a wafer 23, and a first wiring layer 25.

該第一封裝膠體24係具有相對之第一表面241與第二表面242。該導電體222係形成於該第一封裝膠體24內，並具有分別外露於該第一表面241與該第二表面242之第一連接部223及第二連接部224。該連接墊212係形成於該第一封裝膠體24內，並外露於該第一封裝膠體24之第二表面242。該晶片23係嵌埋於該第一封裝膠體24內，並設置於該連接墊212上。 The first encapsulant 24 has an opposite first surface 241 and second surface 242. The conductor 222 is formed in the first encapsulant 24 and has a first connecting portion 223 and a second connecting portion 224 respectively exposed on the first surface 241 and the second surface 242 . The connection pad 212 is formed in the first encapsulant 24 and exposed on the second surface 242 of the first encapsulant 24 . The wafer 23 is embedded in the first encapsulant 24 and disposed on the connection pad 212.

該第一線路層25係形成於該第一封裝膠體24之第一表面241上，並電性連接該導電體222之第一連接部223，且該第一線路層25具有複數第一開口251以外露出部分該第一封裝膠體24之第一表面241。 The first circuit layer 25 is formed on the first surface 241 of the first encapsulant 24 and electrically connected to the first connection portion 223 of the electrical conductor 222, and the first circuit layer 25 has a plurality of first openings 251. A portion of the first surface 241 of the first encapsulant 24 is exposed.

該半導體封裝件2可包括具有複數第二開口271之第一拒銲層27，係形成於該第一線路層25及該第一開口251上，該第二開口271外露出部分該第一線路層25。 The semiconductor package 2 may include a first solder resist layer 27 having a plurality of second openings 271 formed on the first circuit layer 25 and the first opening 251. The second opening 271 exposes a portion of the first line. Layer 25.

該半導體封裝件2可包括具有複數第三開口281之第二線路層28，係形成於該第一封裝膠體24之第二表面242 上，並電性連接該導電體222之第二連接部224與該連接墊212，該第三開口281外露出部分該第一封裝膠體24之第二表面242。 The semiconductor package 2 can include a second circuit layer 28 having a plurality of third openings 281 formed on the second surface 242 of the first encapsulant 24 . The second connecting portion 224 of the electrical conductor 222 is electrically connected to the connecting pad 212. The third opening 281 exposes a portion of the second surface 242 of the first encapsulant 24.

該半導體封裝件2可包括具有複數第四開口291之第二拒銲層29，係形成於該第二線路層28及該第三開口281上，該第四開口291外露出部分該第二線路層28。 The semiconductor package 2 may include a second solder resist layer 29 having a plurality of fourth openings 291 formed on the second circuit layer 28 and the third opening 281. The fourth opening 291 exposes a portion of the second line. Layer 28.

此外，如第2K'圖所示，該半導體封裝件2亦可包括表面處理層26，係形成於該第一線路層25上，並外露出該第一線路層25之第一開口251，而第2L圖之第一拒銲層27也可先形成於該表面處理層26上，使該第二開口271外露出部分該表面處理層26(圖中未繪示)。 In addition, as shown in FIG. 2K', the semiconductor package 2 may further include a surface treatment layer 26 formed on the first circuit layer 25 and exposing the first opening 251 of the first circuit layer 25, and The first solder resist layer 27 of FIG. 2L may also be formed on the surface treatment layer 26 such that the second opening 271 exposes a portion of the surface treatment layer 26 (not shown).

第3圖係依據第2O圖繪示本發明之半導體封裝件之第二實施例之剖視示意圖。如圖所示，半導體封裝件3除包括第2O圖之半導體封裝件2外，亦包括電子元件30、電子元件301、複數銲線31、複數銲線311、第二封裝膠體32以及複數銲球33。 Figure 3 is a cross-sectional view showing a second embodiment of the semiconductor package of the present invention in accordance with Figure 2O. As shown, the semiconductor package 3 includes an electronic component 30, an electronic component 301, a plurality of bonding wires 31, a plurality of bonding wires 311, a second encapsulant 32, and a plurality of solder balls in addition to the semiconductor package 2 of FIG. 33.

該電子元件30與該電子元件301均可為晶片，並依序設置於該第二拒銲層29上。該電子元件30係藉由該銲線31電性連接該第四開口291所外露之第二線路層28，該電子元件301係藉由該銲線311電性連接該電子元件30。 The electronic component 30 and the electronic component 301 can both be wafers and sequentially disposed on the second solder resist layer 29. The electronic component 30 is electrically connected to the second circuit layer 28 exposed by the fourth opening 291 by the bonding wire 31. The electronic component 301 is electrically connected to the electronic component 30 by the bonding wire 311.

該第二封裝膠體32係形成於該第一封裝膠體24上方，並包覆該第二線路層28、第二拒銲層29、電子元件30、電子元件301、銲線31及銲線311。該銲球33係接置於該第二開口271所外露之第一線路層25上。 The second encapsulant 32 is formed over the first encapsulant 24 and covers the second circuit layer 28, the second solder resist layer 29, the electronic component 30, the electronic component 301, the bonding wire 31, and the bonding wire 311. The solder ball 33 is attached to the first circuit layer 25 exposed by the second opening 271.

上述半導體封裝件3之製法，除包括第2A圖至第2O圖之製法外，亦包括依序設置該電子元件30與該電子元件301於該第二拒銲層29上，並藉由該銲線31電性連接該電子元件30與該第四開口291所外露之第二線路層28，且藉由該銲線311電性連接該電子元件301與該電子元件30，再形成該第二封裝膠體32於該第一封裝膠體24上方，以包覆該第二線路層28、第二拒銲層29、電子元件30及電子元件301，另接置該銲球33於該第二開口271所外露之第一線路層25上。 The method for manufacturing the semiconductor package 3 includes, in addition to the methods of FIGS. 2A to 2O, the electronic component 30 and the electronic component 301 are sequentially disposed on the second solder resist layer 29, and the soldering is performed by the soldering The wire 31 is electrically connected to the second circuit layer 28 exposed by the electronic component 30 and the fourth opening 291, and the electronic component 301 and the electronic component 30 are electrically connected by the bonding wire 311 to form the second package. The colloid 32 is over the first encapsulant 24 to cover the second circuit layer 28, the second solder resist layer 29, the electronic component 30 and the electronic component 301, and the solder ball 33 is further connected to the second opening 271. Exposed on the first circuit layer 25.

第4圖係依據第2O圖繪示本發明之半導體封裝件之第三實施例之剖視示意圖。如圖所示，半導體封裝件4除包括第2O圖之半導體封裝件2外，亦包括電子元件30、複數銲球33以及複數導電元件34。 Figure 4 is a cross-sectional view showing a third embodiment of the semiconductor package of the present invention in accordance with Figure 2O. As shown, the semiconductor package 4 includes an electronic component 30, a plurality of solder balls 33, and a plurality of conductive elements 34 in addition to the semiconductor package 2 of FIG.

該電子元件30可為半導體晶片或半導體封裝結構，係設置於該第二拒銲層29上，並藉由該導電元件34電性連接該第四開口291所外露之第二線路層28。該銲球33係接置於該第二開口271所外露之第一線路層25上。該導電元件34可為銲球或凸塊等。 The electronic component 30 can be a semiconductor wafer or a semiconductor package structure, and is disposed on the second solder resist layer 29, and electrically connected to the second circuit layer 28 exposed by the fourth opening 291 by the conductive component 34. The solder ball 33 is attached to the first circuit layer 25 exposed by the second opening 271. The conductive element 34 can be a solder ball or a bump or the like.

上述半導體封裝件4之製法，除包括第2A圖至第2O圖之製法外，亦包括設置該電子元件30於該第二拒銲層29上，並藉由該導電元件34電性連接該電子元件30與該第四開口291所外露之第二線路層28，另接置該銲球33於該第二開口271所外露之第一線路層25上。 The method for fabricating the semiconductor package 4 includes, in addition to the method of the second embodiment to the second embodiment, the electronic component 30 is disposed on the second solder resist layer 29, and the electronic component 34 is electrically connected to the electronic component 34. The element 30 and the second circuit layer 28 exposed by the fourth opening 291 are further connected to the solder ball 33 on the first circuit layer 25 exposed by the second opening 271.

第5圖係依據第2O圖繪示本發明之半導體封裝件之 第四實施例之剖視示意圖。如圖所示，半導體封裝件5除包括第2O圖之半導體封裝件2外，亦包括電子元件30、複數導電元件34、第二封裝膠體32以及複數銲球33。 Figure 5 is a diagram showing the semiconductor package of the present invention according to Figure 2O. A schematic cross-sectional view of a fourth embodiment. As shown, the semiconductor package 5 includes an electronic component 30, a plurality of conductive components 34, a second encapsulant 32, and a plurality of solder balls 33 in addition to the semiconductor package 2 of FIG.

該電子元件30可為半導體晶片或半導體封裝結構，係設置於該第二拒銲層29上，並藉由該導電元件34電性連接該第四開口291所外露之第二線路層28。該導電元件34可為銲球或凸塊等。該第二封裝膠體32係形成於該第一封裝膠體24上方，並包覆該第二線路層28、第二拒銲層29、電子元件30及導電元件34。該銲球33係接置於該第二開口271所外露之第一線路層25上。 The electronic component 30 can be a semiconductor wafer or a semiconductor package structure, and is disposed on the second solder resist layer 29, and electrically connected to the second circuit layer 28 exposed by the fourth opening 291 by the conductive component 34. The conductive element 34 can be a solder ball or a bump or the like. The second encapsulant 32 is formed over the first encapsulant 24 and covers the second wiring layer 28, the second solder resist layer 29, the electronic component 30, and the conductive component 34. The solder ball 33 is attached to the first circuit layer 25 exposed by the second opening 271.

上述半導體封裝件5之製法，除包括第2A圖至第2O圖之製法外，亦包括設置該電子元件30於該第二拒銲層29上，並藉由該導電元件34電性連接該電子元件30與該第四開口291所外露之第二線路層28，再形成該第二封裝膠體32於該第一封裝膠體24上方，以包覆該第二線路層28、第二拒銲層29及電子元件30，另接置該銲球33於該第二開口271所外露之第一線路層25上。 The manufacturing method of the semiconductor package 5 includes, in addition to the method of the second embodiment to the second embodiment, the electronic component 30 is disposed on the second solder resist layer 29, and the electronic component 34 is electrically connected to the electronic component 34. The second circuit layer 28 exposed by the component 30 and the fourth opening 291 is formed over the first encapsulant 24 to cover the second circuit layer 28 and the second solder resist layer 29 . And the electronic component 30 is further connected to the solder ball 33 on the first circuit layer 25 exposed by the second opening 271.

第6圖係依據第2O圖繪示本發明之半導體封裝件之第五實施例之剖視示意圖。如圖所示，半導體封裝件6除包括第20圖之半導體封裝件2並將其上下倒置外，亦包括電子元件30、複數導電元件34、第二封裝膠體32以及複數銲球33。 Figure 6 is a cross-sectional view showing a fifth embodiment of the semiconductor package of the present invention in accordance with Figure 2O. As shown, the semiconductor package 6 includes the electronic component 30, the plurality of conductive elements 34, the second encapsulant 32, and the plurality of solder balls 33 in addition to the semiconductor package 2 of FIG. 20 and upside down.

該電子元件30可為半導體晶片或半導體封裝結構，係設置於該第一拒銲層27上，並藉由該導電元件34電性連 接該第二開口271所外露之第一線路層25。該導電元件34可為銲球或凸塊等。該第二封裝膠體32係形成於該第一封裝膠體24上方，並包覆該第一線路層25、第一拒銲層27、電子元件30及導電元件34。該銲球33係接置於該第四開口291所外露之第二線路層28上。 The electronic component 30 can be a semiconductor wafer or a semiconductor package structure, disposed on the first solder resist layer 27, and electrically connected by the conductive component 34. The first circuit layer 25 exposed by the second opening 271 is connected. The conductive element 34 can be a solder ball or a bump or the like. The second encapsulant 32 is formed over the first encapsulant 24 and covers the first circuit layer 25 , the first solder resist layer 27 , the electronic component 30 , and the conductive component 34 . The solder ball 33 is attached to the second circuit layer 28 exposed by the fourth opening 291.

上述半導體封裝件6之製法，除包括第2A圖至第2O圖之製法並將半導體封裝件2上下倒置外，亦包括設置該電子元件30於該第一拒銲層27上，並藉由該導電元件34電性連接該電子元件30與該第二開口271所外露之第一線路層25，再形成該第二封裝膠體32於該第一封裝膠體24上方，以包覆該第一線路層25、第一拒銲層27、電子元件30及導電元件34，另接置該銲球33於該第四開口291所外露之第二線路層28上。 The method for manufacturing the semiconductor package 6 includes, in addition to the method of FIGS. 2A to 2O and the upside down of the semiconductor package 2, the method further includes disposing the electronic component 30 on the first solder resist layer 27, and The conductive component 34 is electrically connected to the first circuit layer 25 exposed by the electronic component 30 and the second opening 271, and then the second encapsulant 32 is formed over the first encapsulant 24 to cover the first circuit layer. 25, the first solder resist layer 27, the electronic component 30 and the conductive component 34, and the solder ball 33 is further connected to the second circuit layer 28 exposed by the fourth opening 291.

由上可知，本發明之半導體封裝件及其製法，主要係將導電體及連接墊分別形成於封裝膠體內，並將晶片嵌埋於該封裝膠體內以設置於該連接墊上，且將該導電體之連接部外露於該封裝膠體之表面，再將線路層形成於該封裝膠體之表面上以電性連接該導電體之連接部。藉此，本發明可省略習知技術之硬質板，故能降低該半導體封裝件之厚度，以縮小該半導體封裝件之尺寸或體積，進而減少該半導體封裝件之材料成本。 As can be seen from the above, the semiconductor package of the present invention and the manufacturing method thereof are mainly formed by forming a conductor and a connection pad in the encapsulant, and embedding the wafer in the encapsulant to be disposed on the connection pad, and the conductive The connection portion of the body is exposed on the surface of the encapsulant, and a circuit layer is formed on the surface of the encapsulant to electrically connect the connection portion of the electrical conductor. Therefore, the present invention can omit the rigid board of the prior art, so that the thickness of the semiconductor package can be reduced to reduce the size or volume of the semiconductor package, thereby reducing the material cost of the semiconductor package.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Anyone skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. change. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧半導體封裝件 2‧‧‧Semiconductor package

212‧‧‧連接墊 212‧‧‧Connecting mat

222‧‧‧導電體 222‧‧‧Electrical conductor

223‧‧‧第一連接部 223‧‧‧First connection

224‧‧‧第二連接部 224‧‧‧Second connection

23‧‧‧晶片 23‧‧‧ wafer

24‧‧‧第一封裝膠體 24‧‧‧First encapsulant

241‧‧‧第一表面 241‧‧‧ first surface

242‧‧‧第二表面 242‧‧‧ second surface

25‧‧‧第一線路層 25‧‧‧First line layer

251‧‧‧第一開口 251‧‧‧ first opening

27‧‧‧第一拒銲層 27‧‧‧First solder mask

271‧‧‧第二開口 271‧‧‧ second opening

28‧‧‧第二線路層 28‧‧‧Second circuit layer

281‧‧‧第三開口 281‧‧‧ third opening

29‧‧‧第二拒銲層 29‧‧‧Second solder mask

291‧‧‧第四開口 291‧‧‧ fourth opening

Claims (22)

一種半導體封裝件，其包括：第一封裝膠體，係具有相對之第一表面與第二表面；複數導電體，係形成於該第一封裝膠體內，並具有分別外露於該第一表面與該第二表面之第一連接部及第二連接部；複數連接墊，係形成於該第一封裝膠體內，並外露於該第一封裝膠體之第二表面；晶片，係嵌埋於該第一封裝膠體內，並設置於該連接墊上；以及第一線路層，係形成於該第一封裝膠體之第一表面上，並電性連接該導電體之第一連接部。 A semiconductor package comprising: a first encapsulant having opposite first and second surfaces; a plurality of electrical conductors formed in the first encapsulant and having respective exposed surfaces on the first surface a first connecting portion and a second connecting portion of the second surface; a plurality of connecting pads are formed in the first encapsulating body and exposed on the second surface of the first encapsulant; the wafer is embedded in the first The first adhesive layer is formed on the first surface of the first encapsulant and electrically connected to the first connection portion of the electrical conductor. 如申請專利範圍第1項所述之半導體封裝件，復包括表面處理層，係形成於該第一線路層上。 The semiconductor package of claim 1, further comprising a surface treatment layer formed on the first circuit layer. 如申請專利範圍第1項所述之半導體封裝件，復包括第一拒銲層，係形成於該第一線路層上，並外露出部分該第一線路層。 The semiconductor package of claim 1, further comprising a first solder resist layer formed on the first circuit layer and partially exposing the first circuit layer. 如申請專利範圍第3項所述之半導體封裝件，復包括電子元件與複數導電元件，該電子元件係設置於該第一拒銲層上，並藉由該導電元件電性連接該第一線路層。 The semiconductor package of claim 3, further comprising an electronic component and a plurality of conductive components, wherein the electronic component is disposed on the first solder resist layer, and electrically connected to the first line by the conductive component Floor. 如申請專利範圍第4項所述之半導體封裝件，復包括 第二封裝膠體，係形成於該第一封裝膠體上方，並包覆該第一線路層、第一拒銲層、電子元件及導電元件。 Such as the semiconductor package described in claim 4, including The second encapsulant is formed on the first encapsulant and covers the first circuit layer, the first solder resist layer, the electronic component and the conductive component. 如申請專利範圍第1項所述之半導體封裝件，復包括第二線路層，係形成於該第一封裝膠體之第二表面上，並電性連接該導電體之第二連接部與該連接墊。 The semiconductor package of claim 1, further comprising a second circuit layer formed on the second surface of the first encapsulant and electrically connected to the second connection portion of the electrical conductor pad. 如申請專利範圍第6項所述之半導體封裝件，復包括第二拒銲層，係形成於該第二線路層上，並外露出部分該第二線路層。 The semiconductor package of claim 6, further comprising a second solder resist layer formed on the second circuit layer and partially exposing the second circuit layer. 如申請專利範圍第7項所述之半導體封裝件，復包括電子元件與複數導電元件，該電子元件係設置於該第二拒銲層上，並藉由該導電元件電性連接該第二線路層。 The semiconductor package of claim 7, further comprising an electronic component and a plurality of conductive components, wherein the electronic component is disposed on the second solder resist layer, and electrically connected to the second line by the conductive component Floor. 如申請專利範圍第8項所述之半導體封裝件，復包括第二封裝膠體，係形成於該第一封裝膠體上方，並包覆該第二線路層、第二拒銲層、電子元件及導電元件。 The semiconductor package of claim 8, further comprising a second encapsulant formed on the first encapsulant and covering the second circuit layer, the second solder resist layer, the electronic component, and the conductive element. 如申請專利範圍第4項或第8項所述之半導體封裝件，其中，該電子元件係為半導體晶片或半導體封裝結構。 The semiconductor package of claim 4, wherein the electronic component is a semiconductor wafer or a semiconductor package structure. 一種半導體封裝件之製法，其包括：提供具有金屬層之承載件；形成複數連接墊及複數高於該連接墊之導電體於該金屬層上；設置晶片於該連接墊上；形成第一封裝膠體於該金屬層上，以包覆該連接 墊、導電體及晶片，並外露出該導電體之連接部；以及形成第一線路層於該第一封裝膠體上以電性連接該導電體之連接部。 A method of fabricating a semiconductor package, comprising: providing a carrier having a metal layer; forming a plurality of connection pads and a plurality of electrical conductors above the connection pad on the metal layer; and disposing a wafer on the connection pad; forming a first encapsulant On the metal layer to cover the connection a pad, a conductor and a wafer, and exposing a connection portion of the conductor; and forming a connection portion of the first circuit layer on the first encapsulant to electrically connect the conductor. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，形成該連接墊之步驟係包括：形成具有複數第一穿孔之第一阻層於該金屬層上，該第一穿孔係外露出部分該金屬層；形成該連接墊於該第一穿孔內以連接該金屬層；以及移除該第一阻層。 The method of fabricating a semiconductor package according to claim 11, wherein the step of forming the connection pad comprises: forming a first resist layer having a plurality of first vias on the metal layer, the first perforation Exposing a portion of the metal layer; forming the connection pad in the first through hole to connect the metal layer; and removing the first resist layer. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，形成該導電體之步驟係包括：形成具有複數第二穿孔之第二阻層於該金屬層上，該第二穿孔係高於該連接墊並外露出部分該金屬層；形成該導電體於該第二穿孔內以連接該金屬層；以及移除該第二阻層。 The method of fabricating a semiconductor package according to claim 11, wherein the step of forming the electrical conductor comprises: forming a second resist layer having a plurality of second perforations on the metal layer, the second perforation is high Forming a portion of the metal layer on the connection pad; forming the electrical conductor in the second through hole to connect the metal layer; and removing the second resist layer. 如申請專利範圍第11項所述之半導體封裝件之製法，復包括形成表面處理層於該第一線路層上。 The method of fabricating a semiconductor package according to claim 11, further comprising forming a surface treatment layer on the first circuit layer. 如申請專利範圍第11項所述之半導體封裝件之製法，復包括形成第一拒銲層於該第一線路層上並外露出部分該第一線路層。 The method of fabricating a semiconductor package according to claim 11, further comprising forming a first solder resist layer on the first circuit layer and exposing a portion of the first circuit layer. 如申請專利範圍第15項所述之半導體封裝件之製法，復包括設置電子元件於該第一拒銲層上，並藉由複數導電元件電性連接該第一線路層。 The method of fabricating a semiconductor package according to claim 15 further comprising: disposing an electronic component on the first solder resist layer, and electrically connecting the first circuit layer by a plurality of conductive components. 如申請專利範圍第16項所述之半導體封裝件之製法，復包括形成第二封裝膠體於該第一封裝膠體上方，以包覆該第一線路層、第一拒銲層、電子元件及導電元件。 The method for manufacturing a semiconductor package according to claim 16, further comprising forming a second encapsulant over the first encapsulant to encapsulate the first circuit layer, the first solder resist layer, the electronic component, and the conductive element. 如申請專利範圍第11項所述之半導體封裝件之製法，復包括：移除該承載件；以及圖案化該金屬層以形成第二線路層。 The method of fabricating a semiconductor package according to claim 11, further comprising: removing the carrier; and patterning the metal layer to form a second wiring layer. 如申請專利範圍第18項所述之半導體封裝件之製法，復包括形成第二拒銲層於該第二線路層上並外露出部分該第二線路層。 The method of fabricating a semiconductor package according to claim 18, further comprising forming a second solder resist layer on the second wiring layer and exposing a portion of the second wiring layer. 如申請專利範圍第19項所述之半導體封裝件之製法，復包括設置電子元件於該第二拒銲層上，並藉由複數導電元件電性連接該第二線路層。 The method of fabricating a semiconductor package according to claim 19, further comprising: disposing the electronic component on the second solder resist layer, and electrically connecting the second circuit layer by the plurality of conductive components. 如申請專利範圍第20項所述之半導體封裝件之製法，復包括形成第二封裝膠體於該第一封裝膠體上方，以包覆該第二線路層、第二拒銲層、電子元件及導電元件。 The method for manufacturing a semiconductor package according to claim 20, further comprising forming a second encapsulant over the first encapsulant to encapsulate the second circuit layer, the second solder resist layer, the electronic component, and the conductive element. 如申請專利範圍第16項或第20項所述之半導體封裝件之製法，其中，該電子元件係為半導體晶片或半導體封裝結構。 The method of fabricating a semiconductor package according to claim 16 or claim 20, wherein the electronic component is a semiconductor wafer or a semiconductor package structure.
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