TW201443856A - Display device - Google Patents

Abstract

To correct a change in the Vgs-Id characteristics when the pMOS transistor and the nMOS transistor are energized for a long period of time, by using a metal film that acts as a light-blocking layer or a reflective layer. A display device that includes a plurality of pixels and a CMOS circuit, wherein a pMOS transistor on the CMOS circuit includes a first light-blocking layer and a gate electrode on opposing sides of a semiconductor layer, and an nMOS transistor of the CMOS circuit includes a second light-blocking layer and a gate electrode on opposing sides of a semiconductor layer; the first light-blocking layer and the second light-blocking layer composed of a conductive layer to which a predetermined voltage is inputted, include a first component for adjusting the Vgs-Id characteristics of the pMOS transistor by controlling a voltage value inputted to the first light-blocking layer, where Id is a drain current, and Vgs is an inter-gate source voltage; and a second component for adjusting the Vgs-Id characteristics of the nMOS transistor by controlling the voltage value inputted to the second light-blocking layer.

Description

Display device

The present invention relates to a display device, and more particularly to a technique that is effective for use in a display device including a CMOS (Complementary Metal-Oxide Semiconductor) circuit.

A display device such as a liquid crystal display device, an organic EL (Electroluminescence) display device, or an image display device that electrically controls the position of a movable shutter to display an image is known to include a CMOS circuit.

Fig. 9 is a cross-sectional view showing the configuration of a p-type MOS (Metal-Oxide Semiconductor) transistor and an n-type MOS transistor in a CMOS circuit used in the conventional display device.

In Fig. 9, 101-series substrates (glass substrates, etc.), 102p, 102n-based metal films, 103, 104-type insulating films, 105-series wiring, 106-series electrodes, 107-series openings, 108p, 108n-based semiconductor layers, and 109-series Gate electrode, pMOS type p-type MOS transistor, nMOS type n-type MOS transistor.

As shown in FIG. 9, in the p-type MOS transistor (pMOS) and the n-type MOS transistor (nMOS) used in the conventional display device, there are metal films (102p, 102n) configured to function as a light shielding layer or a reflective layer. In the case of preventing leakage current from being increased when the semiconductor layers (108p, 108n) are irradiated with light.

10 and 11 show the CMOS inverter circuit used in the prior display device. A circuit diagram of the circuit.

The CMOS inverter circuit shown in FIG. 10 simultaneously controls the potential of the metal film (102p) of the p-type MOS transistor (pMOS) and the potential of the metal film (102n) of the n-type MOS transistor (nMOS), FIG. The CMOS inverter circuit shown is such that the potential of the metal film (102p) of the p-type MOS transistor (pMOS) and the potential of the metal film (102n) of the n-type MOS transistor (nMOS) are in a floating state.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1]

US 2008/0174532

Fig. 12 is a graph showing changes in Vgs-Id characteristics due to deterioration of a p-type MOS transistor and an n-type MOS transistor.

Fig. 12(a) is a graph showing changes in Vgs-Id characteristics due to deterioration of a p-type MOS transistor, and Fig. 12(b) is a graph showing Vgs-Id characteristics due to deterioration of an n-type MOS transistor. The graph of the change. Furthermore, Vgs is the gate-source voltage and Id is the drain current.

As shown in FIG. 12, the Vgs-Id characteristics of the p-type MOS transistor (pMOS) and the n-type MOS transistor (nMOS) are shifted due to deterioration due to energization over a long period of time.

Here, as shown in FIG. 12(a), the Vgs-Id characteristic of the p-type MOS transistor (pMOS) is shifted to the negative side of Vgs, as shown in FIG. 12(b), the n-type MOS transistor (nMOS). The Vgs-Id characteristic is offset to the positive side of Vgs.

As described above, the Vgs-Id characteristics of the p-type MOS transistor (pMOS) and the n-type MOS transistor (nMOS) are shifted in opposite directions due to deterioration due to energization for a long period of time.

For example, a p-type MOS transistor (pMOS) and an n-type MOS transistor (nMOS) are used in a display device of a pixel circuit, a p-type MOS transistor (pMOS) and an n-type MOS transistor. The deterioration of (nMOS) due to long-time energization deteriorates the display quality of the display image displayed on the display panel.

Therefore, it is necessary to correct the change in the Vgs-Id characteristic when the p-type MOS transistor (pMOS) and the n-type MOS transistor (nMOS) are energized for a long time to the Vgs-Id characteristic before the deterioration.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a technique for correcting a long time to p using a metal film functioning as a light shielding layer or a reflective layer in a display device including a CMOS circuit. The variation of the Vgs-Id characteristic when the MOS transistor and the n-type MOS transistor are energized.

The above and other objects and novel features of the present invention will be apparent from the description of the specification and appended claims.

The outline of a representative part of the invention disclosed in the present invention will be briefly described as follows.

(1) A display device comprising a plurality of pixels and a CMOS circuit, wherein the p-type MOS transistor of the CMOS circuit includes a first light shielding layer on a side opposite to a gate electrode via a semiconductor layer, and an n-type MOS of the CMOS circuit The transistor includes a second light shielding layer on a side opposite to the gate electrode via the semiconductor layer, and the first light shielding layer and the second light shielding layer are formed of a conductive layer to which a specific voltage is input, and the display device includes the mechanism 1 and the mechanism 2 The mechanism 1 adjusts the Vgs-Id characteristic of the p-type MOS transistor by controlling the voltage value input to the first light-shielding layer when the Id is set to the drain current and the Vgs is the gate-source voltage. The mechanism 2 controls the voltage value input to the second light shielding layer to adjust the Vgs-Id characteristic of the n-type MOS transistor.

(2) In (1), the mechanism 1 adjusts the Vgs-Id characteristics of all the p-type MOS transistors of the CMOS circuit, and the mechanism 2 adjusts the Vgs-Id characteristics of all the n-type MOS transistors of the CMOS circuit.

(3) A display device comprising a plurality of pixels each including a mechanical shutter, a signal line for inputting an image signal to each of the pixels, and a scan line for inputting a scan voltage to each of the pixels, and electrically controlling a position of the mechanical shutter to perform image display; wherein each pixel includes electrically controlling a position of the mechanical shutter In the pixel circuit, the pixel circuit includes a CMOS circuit, and the p-type MOS transistor of the CMOS circuit includes a first light shielding layer on a side opposite to a gate electrode via a semiconductor layer, and the n-type MOS transistor of the CMOS circuit is The second light shielding layer is included on the side opposite to the gate electrode via the semiconductor layer, and the first light shielding layer and the second light shielding layer are formed of a conductive layer to which a specific voltage is input. The display device includes the mechanism 1 and the mechanism 2, and the mechanism When the Id is set to the drain current and the Vgs is set to the gate-source voltage, the voltage value of the first light shielding layer input to each of the pixels is controlled to adjust the Vgs-Id of the p-type MOS transistor. The mechanism 2 controls the voltage value of the second light-shielding layer input to each of the pixels to adjust the Vgs-Id characteristic of the n-type MOS transistor.

(4) In (3), the mechanism 1 adjusts the Vgs-Id characteristic of the p-type MOS transistor of all the pixel circuits, and the mechanism 2 adjusts the Vgs-Id characteristic of the n-type MOS transistor of all the pixel circuits. .

(5) (3) or (4) comprising: a planar light source; a transparent substrate provided on the planar light source; and a light shielding film provided on the transparent substrate side of the planar light source, wherein the light shielding film has The optical opening region corresponding to each pixel shields a region other than the optical opening region from the light emitted from the planar light source, and the mechanical shutter is provided on the transparent substrate corresponding to the optical opening region.

(6) In any one of (1) to (5), the p-type MOS transistor and the n-type MOS transistor system semiconductor layer are a transistor formed of a polycrystalline germanium film.

The effect obtained by the representative part of the invention disclosed in the present invention will be briefly described as follows.

According to the present invention, it can be used as a shading in a display device including a CMOS circuit A metal film in which a layer or a reflective layer functions to correct a change in Vgs-Id characteristics when a p-type MOS transistor and an n-type MOS transistor are energized for a long period of time.

2, 14, pMOS, PMT*‧‧‧p type MOS transistor

3, 15, nMOS, NMT*‧‧‧n type MOS transistor

4‧‧‧Signal storage capacitor

5‧‧‧ scan switch

6‧‧‧ signal line

7, 12‧‧‧ power cord

8‧‧‧Update line

10‧‧‧ scan line

11‧‧‧Shutter voltage line

13‧‧‧Signal transmission switch

20‧‧‧Shutter electrode

21, 22‧‧‧Control electrode

23‧‧‧ pixels

24‧‧‧Image signal voltage writing circuit

25‧‧‧Scan circuit

26‧‧‧Control electrode drive circuit

30, 32‧‧‧ Polycrystalline germanium film doped with high concentration of n-type impurities

31‧‧‧Polysilicon film

33‧‧‧gate insulating film

34‧‧‧Insulation protective film

35, 109‧‧‧ gate electrode

37‧‧‧Source electrode

36, 43‧‧‧汲electrode

38‧‧‧Protective film

39‧‧‧ glass substrate

40, 103, 104‧‧‧Insulation film

41‧‧‧Light

42‧‧‧Light source

46, 48‧‧·reflective film

47‧‧‧Light guide

49‧‧‧Black film

101‧‧‧Substrate

102, 102p, 102n‧‧‧ metal film

105‧‧‧Wiring

106‧‧‧Electrode

107‧‧‧ openings

108p, 108n‧‧‧ semiconductor layer

Id‧‧‧汲polar current

T1~t6‧‧‧ moment

Vgs‧‧‧ gate-source voltage

Vp, Vn‧‧‧ potential

1 is a circuit diagram showing a circuit configuration of an example of a CMOS inverter circuit used in a display device according to an embodiment of the present invention.

Fig. 2 is a circuit diagram showing a circuit configuration of another example of a CMOS inverter circuit used in a display device according to an embodiment of the present invention.

3 is a graph showing a change in Vgs-Id characteristics due to a change in potential of a metal film in a p-type MOS transistor, and a change in Vgs-Id characteristics due to a change in potential of a metal film in an n-type MOS transistor. The graph.

4 is a circuit diagram showing a pixel circuit of an image display device of a movable shutter type as an example of a pixel circuit using the CMOS inverter circuit shown in FIGS. 1 and 2.

Fig. 5 is a block diagram showing a schematic configuration of an image display device of a movable shutter type.

6 is a cross-sectional view showing a cross-sectional structure of a pixel portion of an image display device of a movable shutter type.

Fig. 7 is a timing chart showing the operation of the image display device of the movable shutter type (polarity inversion: shutter = low voltage).

Fig. 8 is a timing chart showing the operation of the image display device of the movable shutter type (polarity: shutter = high voltage).

Fig. 9 is a cross-sectional view showing the configuration of a p-type MOS transistor and an n-type MOS transistor in a CMOS circuit used in the prior display device.

Fig. 10 is a circuit diagram showing a circuit configuration of an example of a CMOS inverter circuit used in the prior display device.

Fig. 11 is a circuit diagram showing a circuit configuration of another example of a CMOS inverter circuit used in the prior display device.

Figure 12 is a diagram showing degradation of a p-type MOS transistor and an n-type MOS transistor due to degradation A graph of changes in Vgs-Id characteristics.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the drawings, the same functions are denoted by the same reference numerals, and the description thereof will be omitted. Further, the following examples are not intended to limit the scope of the patent application of the present invention.

3 is a view showing a change in Vgs-Id characteristics due to a potential change of a metal film (102p) in a p-type MOS transistor (pMOS), and a metal film (102n) in an n-type MOS transistor (nMOS). A graph of the change in Vgs-Id characteristics due to the change in potential.

The Vgs-Id characteristic of the p-type MOS transistor (pMOS) changes as shown in Fig. 3(a) in accordance with the potential Vp of the metal film (102p). When the potential Vp of the Vp1 metal film (102p) is 0 V, the higher the potential Vp of the metal film (102p), the more the Vgs-Id characteristic shifts toward the negative side of Vgs, and the lower the potential Vp of the metal film (102p). The more the Vgs-Id characteristic is shifted to the positive side of Vgs.

The Vgs-Id characteristic of the n-type MOS transistor (nMOS) changes as shown in Fig. 3(b) in accordance with the potential Vn of the metal film (102n). When the potential Vn of the Vn1 metal film (102n) is 0 V, the higher the potential Vn of the metal film (102n), the more the Vgs-Id characteristic shifts toward the negative side of Vgs, and the lower the potential Vn of the metal film (102n). The more the Vgs-Id characteristic is shifted to the positive side of Vgs.

1 is a circuit diagram showing a circuit configuration of an example of a CMOS inverter circuit used in a display device according to an embodiment of the present invention.

The CMOS inverter circuit of the present embodiment individually controls the potential of the metal film (102p) of the p-type MOS transistor (pMOS) and the metal film (102n) of the n-type MOS transistor (nMOS) by different wirings. Potential.

Therefore, in the present embodiment, even when the p-type MOS transistor (pMOS) and the n-type MOS transistor (nMOS) are differently deteriorated (change in Vgs-Id characteristics as shown in FIG. 12), It is also possible to restore the potential of the metal film (102p) of the p-type MOS transistor (pMOS) and the potential of the metal film (102n) of the n-type MOS transistor (nMOS) individually. Vgs-Id characteristics before the transformation.

Fig. 2 is a circuit diagram showing a circuit configuration of another example of a CMOS inverter circuit used in a display device according to an embodiment of the present invention.

In the display device shown in FIG. 2, the potential of the metal film (102p) of the p-type MOS transistor (pMOS) in all CMOS inverter circuits is controlled by a control voltage Vp, and is controlled by a control voltage Vn. The potential of the metal film (102n) of the n-type MOS transistor (nMOS) in all CMOS inverter circuits.

The CMOS inverter circuit shown in Figs. 1 and 2 is used for, for example, a pixel circuit of a display device.

4 is a circuit diagram showing a pixel circuit of an image display device of a movable shutter type as an example of a pixel circuit using the CMOS inverter circuit shown in FIGS. 1 and 2.

Hereinafter, an image display device of a movable shutter type will be described with reference to Fig. 4 .

The pixel 23 is composed of a CMOS circuit and includes a p-type MOS transistor (2, 14) and an n-type MOS connected between a power supply line 7 to which a VDD voltage is supplied and a power supply line 12 to which a GND (ground) voltage is supplied. Transistor (3, 15).

A signal line 6 is provided in each of the pixels 23, and the signal line 6 and a signal storage capacitor (hereinafter referred to as a holding capacitor) 4 are connected by a scan switch 5 composed of an n-type MOS transistor.

The holding capacitor 4 is further connected to the source (or drain) of the signal transfer switch 13 composed of an n-type MOS transistor, and the drain (or source) of the signal transfer switch 13 is connected to the p-type MOS transistor 2 and the n-type. The gate of MOS transistor 3. Furthermore, the other end of the holding capacitor 4 is connected to the power supply line 12, and the gate of the scan switch 5 is connected to the update line 8.

Further, the gates of the p-type MOS transistor 2 and the n-type MOS transistor 3 are connected to one of the control electrodes 22 of the mechanical shutter, and the gates of the p-type MOS transistor 14 and the n-type MOS transistor 15 are connected to the mechanical shutter. A control electrode 21. The shutter electrode 20 is connected to the shutter voltage line 11.

Further, the mechanical shutter is disposed opposite to the opening provided on the light shielding surface.

Fig. 5 is a block diagram showing a schematic configuration of an image display device of a movable shutter type.

In the image display device of the movable shutter type, the pixel 23 shown in FIG. 4 is arranged in a two-dimensional shape as one pixel. Here, the scanning line 10 is provided in units of columns and is connected to the scanning circuit 25.

Further, the signal line 6 is provided in each row and connected to the image signal voltage writing circuit 24.

The power supply lines (7, 12), the update line 8, and the shutter voltage line 11 are commonly provided for each pixel, and are connected to the control electrode drive circuit 26.

Further, in order to simplify the illustration, the display area is described in a matrix in which the number of pixels is 4 × 3 pixels in FIG. 5, but it should be understood that the technical idea disclosed in the present invention does not particularly limit the number of pixels.

Further, the CMOS circuit to which the present invention is applied can be applied to the above-described pixel 23 or the circuit shown in Fig. 5 (image signal voltage writing circuit 24, scanning circuit 25 or control electrode driving circuit 26).

Next, a cross-sectional structure of a pixel portion of an image display device of a movable shutter type will be described.

6 is a cross-sectional view showing a cross-sectional structure of a pixel portion of an image display device of a movable shutter type.

As shown in FIG. 6, a metal film 102 is formed on the glass substrate 39. The metal film 102 is covered by an insulating film 40. On the insulating film 40, a polycrystalline germanium film transistor is disposed. The polycrystalline germanium film transistor includes a polycrystalline germanium film 31 and is doped. A polycrystalline silicon thin film (30, 32) having a high concentration of n-type impurities, a gate insulating film 33, and a gate electrode 35 including a high melting point metal, a source electrode 37, and a drain electrode 36.

Further, on the glass substrate 39, a shutter voltage line 11 and a drain electrode 43 (for example, an n-type MOS transistor 15) are formed of an Al wiring layer similar to the source electrode 37 and the drain electrode 36 via the insulating protective film 34. The bucker voltage line 11 and the drain electrode 43 are covered by a protective film 38 including a multilayer film of tantalum nitride and an organic material.

On the protective film 38, a mechanical shutter including two control electrodes of the shutter electrode 20 and the control electrode (21, 22) is formed, and the shutter electrode 20 is connected to the shutter voltage line via the contact hole. 11. The drain electrode 36 is connected to the control electrode 22 via a contact hole, and the drain electrode 43 is connected to the control electrode 21 via a contact hole. Further, the shutter electrodes 20 and the surfaces of the two control electrodes (21, 22) are formed with an insulating film to prevent short circuits when they are in contact with each other.

Here, the position of the shutter electrode 20 is controlled by an electric field based on the relative relationship between the voltage input to the shutter electrode 20 and the voltage input to the control electrode 21 and the control electrode 22, and therefore, in FIG. 6, it is also revealed by a broken line. The movable range of the shutter electrode 20.

Further, other transistors disposed in the pixel 23 also include a polycrystalline silicon transistor transistor. The polycrystalline germanium thin film transistors can be formed using a known excimer laser annealing process or the like.

On the opposite side of the shutter electrode 20 and the glass substrate 39, a light guide plate 47 including a light source 42 including three colors of R (red) G (green) B (blue) and a separate LED (Light Emitting Diode) is disposed. , light-emitting diode) light source.

Reflective films (46, 48) are disposed on both sides of the light guide plate 47, and a black film 49 is further disposed on the reflective film 48. The reflective film (46, 48) is a metal film of Ag or Al, and the black film 49 can be formed by appropriately dispersing pigment particles such as carbon black or titanium black in a metal oxide film or a polyimide resin.

Here, as shown in FIG. 6, the reflection film 48 and the black film 49 are provided with an opening at a position corresponding to the shutter electrode 20, and a part of the light 41 emitted from the light source 42 and propagating along the light guide plate 47 is self-contained. The opening is shot. Further, the black film 49 is provided to prevent reflection of external light.

Next, the operation of the image display device of the movable shutter type will be described.

Fig. 7 is a timing chart showing the operation of the image display device of the movable shutter type (polarity inversion: shutter = low voltage).

Fig. 8 is a timing chart showing the operation of the image display device of the movable shutter type (polarity: shutter = high voltage).

First, use Figure 7 to move the pixel circuit when the polarity is reversed (shutter = low voltage). For explanation.

Before the time (t1), the scanning line 10 is sequentially supplied with the scanning line, and the image storage capacitor 4 is written with the image signal.

Then, at time (t1), the power supply voltage of the power supply line 7 is changed from the voltage of Vdrive (for example, 25 V) to the voltage of 0 V, and the shutter control voltage on the shutter voltage line 11 is changed from the voltage of Vrelease 1 (for example, 10 V) to the voltage of 0 V.

Then, at time (t2), the transfer control signal on the update line 8 becomes a high level (hereinafter referred to as an H level), whereby the signal transfer switch 13 is turned on, and the pair is made of a p-type MOS transistor (2, 14). A signal input is performed by an SRAM (Static Random Access Memory) circuit composed of an n-type MOS transistor (3, 15).

At time (t3), the power supply voltage of the power supply line 7 rises to the voltage of Vlatch, whereby the image signal is latched to the SRAM circuit.

Thereafter, at time (t4), the transfer control signal on the update line 8 becomes a low level (hereinafter referred to as an L level), whereby the signal transfer switch 13 is turned off.

At time (t5), the power supply voltage of the power supply line 7 rises to the voltage of Vdrive (for example, 25 V), whereby the shutter electrode 20 is driven.

The shutter electrode 20 that initially contacts any one of the control electrodes (21, 22) moves to the intermediate point after the time (t1), because the power supply voltage of the power supply line 7 becomes 0 V, and thereafter, at the time (t5), A control electrode (21, 22) moves. At this time, a voltage of 0 V is applied to the shutter electrode 20, a voltage of Vdrive (for example, 25 V) is applied to the control electrode on the high voltage side, and a voltage of 0 V is applied to the control electrode on the low voltage side.

Thereafter, at time (t6), at the timing when the shutter electrode 20 is stopped, the shutter control voltage on the shutter voltage line 11 becomes the voltage of Vrelease1 (for example, 10 V), and the potential difference between the shutter electrode 20 and the control electrode on the high voltage side is made. The potential difference from 25V is reduced to a potential difference of 15V. At this time, since the shutter electrode 20 is stopped, even if the applied voltage is reduced, the shutter characteristics are not affected.

Next, the operation of the pixel circuit in the case of polarity (shutter=high voltage) will be described with reference to FIG.

Before the time (t1), the scanning line 10 is sequentially supplied with the scanning line, and the image signal is written to the holding capacitor 4.

Then, at time (t1), the power supply voltage of the power supply line 7 is changed from the voltage of Vdrive (for example, 25V) to the voltage of 0V, and the shutter control voltage on the shutter voltage line 11 is changed from the voltage of Vrelease2 (for example, 15V) to the voltage of Vdrive (for example, 25V).

Then, at time (t2), the transfer control signal on the update line 8 becomes the H level, whereby the signal transfer switch 13 is turned on, and the pair includes the p-type MOS transistor (2, 14) and the n-type MOS transistor. (3, 15) The SRAM circuit performs signal input.

At time (t3), the power supply voltage of the power supply line 7 rises to the voltage of Vlatch, whereby the image signal is latched to the SRAM circuit.

Thereafter, at time (t4), the transfer control signal on the update line 8 becomes the L level, whereby the signal transfer switch 13 is turned off.

At time (t5), the power supply voltage of the power supply line 7 rises to the voltage of Vdrive (for example, 25 V), whereby the shutter electrode 20 is driven.

The shutter electrode 20 initially in contact with any one of the control electrodes (21, 22) moves toward any of the control electrodes (21, 22) at time (t5). At this time, a voltage of Vdrive (for example, 25 V) is applied to the shutter electrode 20, a voltage of Vdrive (for example, 25 V) is applied to the control electrode on the high voltage side, and a voltage of 0 V is applied to the control electrode on the low voltage side.

Thereafter, at time (t6), at the timing when the shutter electrode 20 is stopped, the shutter control voltage on the shutter voltage line 11 becomes the voltage of Vrelease2 (for example, 15 V), and the potential difference between the shutter electrode 20 and the control electrode on the low voltage side is made. The potential difference from 25V is reduced to a potential difference of 15V. At this time, since the shutter electrode 20 is stopped, even if the applied voltage is reduced, the shutter characteristics are not affected.

As described above, the invention completed by the inventors has been specifically carried out according to the above embodiment. The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit and scope of the invention.

pMOS‧‧‧p type MOS transistor

nMOS‧‧‧n type MOS transistor

102p, 102n‧‧‧ metal film

Vp, Vn‧‧‧ potential

Claims (7)

A display device comprising: a plurality of pixels and a CMOS circuit, wherein the p-type MOS transistor of the CMOS circuit includes a first light shielding layer on a side opposite to a gate electrode via a semiconductor layer, and the n-type of the CMOS circuit The MOS transistor includes a second light shielding layer on a side opposite to the gate electrode via the semiconductor layer, and the first light shielding layer and the second light shielding layer are formed of a conductive layer to which a specific voltage is input, and the display device includes the mechanism 1 When the Id is set to the drain current and the Vgs is set to the gate-source voltage, the voltage value input to the first light shielding layer is controlled to adjust the Vgs-Id characteristic of the p-type MOS transistor; The mechanism 2 controls the voltage value input to the second light shielding layer to adjust the Vgs-Id characteristic of the n-type MOS transistor. A display device according to claim 1, wherein said mechanism 1 adjusts a Vgs-Id characteristic of all p-type MOS transistors of said CMOS circuit, and said mechanism 2 adjusts a Vgs-Id characteristic of all n-type MOS transistors of said CMOS circuit. A display device, comprising: a plurality of pixels respectively including a mechanical shutter; a signal line for inputting an image signal to each of the pixels; and a scan line for inputting a scan voltage to each of the pixels; and the display device Electrically controlling the position of the mechanical shutter to perform image display, and Each of the pixels includes a pixel circuit electrically controlling a position of the mechanical shutter, wherein the pixel circuit includes a CMOS circuit, and the p-type MOS transistor of the CMOS circuit includes a first light shielding layer on a side opposite to a gate electrode via a semiconductor layer The n-type MOS transistor of the CMOS circuit includes a second light-shielding layer on a side opposite to the gate electrode via the semiconductor layer, and the first light-shielding layer and the second light-shielding layer are formed of a conductive layer to which a specific voltage is input. The display device includes a mechanism 1 that controls the voltage value of the first light-shielding layer input to each of the pixels when the Id is set to the drain current and the Vgs is the gate-source voltage. a Vgs-Id characteristic of the p-type MOS transistor; and a mechanism 2 that controls a voltage value of the second light-shielding layer input to each of the pixels to adjust a Vgs-Id characteristic of the n-type MOS transistor. The display device of claim 3, wherein the mechanism 1 adjusts a Vgs-Id characteristic of the p-type MOS transistor of all the pixel circuits, and the mechanism 2 adjusts a Vgs-Id characteristic of the n-type MOS transistor of all the pixel circuits. . The display device of claim 3 or 4, comprising: a planar light source; a transparent substrate disposed on the planar light source; and a light shielding film disposed on the transparent substrate side of the planar light source; the light shielding film having An optical opening region corresponding to each pixel, and a region other than the optical opening region is shielded from light emitted from the planar light source, and the mechanical shutter is provided on the transparent substrate corresponding to the optical opening region. The display device according to any one of claims 1 to 4, wherein the p-type MOS transistor and The above-mentioned n-type MOS transistor system semiconductor layer is a transistor composed of a polycrystalline germanium film. The display device of claim 5, wherein the p-type MOS transistor and the n-type MOS transistor system semiconductor layer are formed of a polycrystalline germanium film.