TW201436004A - Integrated circuit structure and method for manufacturing the same - Google Patents

Abstract

An integrated circuit structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The integrated circuit structure further includes a conductive wiring in the dielectric layer. The integrated circuit structure also includes a first metallic capping layer over the conductive wiring and a second metallic capping layer over the first metallic capping layer. The second metallic capping layer has a width substantially the same as a width of the first metallic capping layer.

Description

Integrated circuit structure and its forming method

The present invention relates to integrated circuit structures, and more particularly to metal cap layers thereof.

A commonly used method for forming metal lines and vias is the so-called damascene method, which typically begins with an opening in the dielectric layer and a dielectric layer that separates the metallization layer in a vertical direction. The method of forming the opening is generally a conventional lithography and etching technique. After the opening is formed, copper or a copper alloy is filled into the opening to form a via or a conductive trench. The excess metallic material on the surface of the dielectric layer is then removed by chemical mechanical polishing (CMP). The retained copper or copper alloy forms through holes and/or metal lines.

The reason why copper replaces aluminum is that the electrical resistance of copper is lower than that of aluminum. However, copper is still facing the problem of electromigration (EM) and stress migration (SM) reliability as the component size shrinks and current density increases.

An integrated circuit structure according to an embodiment of the present invention includes: a substrate; a dielectric layer on the substrate; a conductive wire in the dielectric layer; a first metal cap layer on the conductive wire; and a second metal cap layer Located on the first metal cap layer, wherein the width of the second metal cap layer is substantially the same as the width of the first metal cap layer.

An integrated circuit structure provided by an embodiment of the present invention includes: a half a conductor substrate; a low dielectric constant dielectric layer on the semiconductor substrate; an opening extending from an upper surface of the low dielectric constant dielectric layer to a low dielectric constant dielectric layer; a barrier layer, a pad opening a copper-containing conductive line located in the opening and on the barrier layer; a second metal cap layer on the copper-containing conductive line; and a first metal cap layer between the second metal cap layer and the copper-containing conductive line, wherein The material of the first metal cap layer is different from the material of the second metal cap layer.

A method for forming an integrated circuit structure according to an embodiment of the present invention includes: forming a dielectric layer on a semiconductor substrate; forming a copper line in the dielectric layer; forming a first metal cap layer on the copper line; and forming a second The metal cap layer is on the first metal cap layer, wherein the width of the second metal cap layer is substantially the same as the width of the first metal cap layer.

100‧‧‧ method

102, 104, 106, 108, 110, 112, 114‧ ‧ steps

200‧‧‧Semiconductor device

202‧‧‧Substrate

204‧‧‧First dielectric layer

206‧‧‧First depression

208, 220‧‧‧ barrier layer

210‧‧‧ Conductive layer

212‧‧‧First cover

214‧‧‧ESL

212a, 224a‧‧‧ first metal cover

212b, 224b‧‧‧ second metal cover

216‧‧‧Second dielectric layer

218‧‧‧second depression

218U‧‧‧groove part

218L‧‧‧through hole

222‧‧‧ Conductor

224‧‧‧Second cover

1 is a flow chart of a method of fabricating a semiconductor device in one or more embodiments.

2 through 8 are cross-sectional views of the semiconductor device in different process stages in one or more embodiments.

The present invention provides many different embodiments or examples to implement different features in various embodiments. The following specific examples of components and combinations are used to simplify the invention and are merely by way of example and not limitation. For example, the description of forming the first structure on the second structure includes the case where the first and second structures are in direct contact or are separated by an additional structure. In addition, the various examples of the invention may be repeated with the same reference numerals to simplify the description, but elements having the same reference numbers do not necessarily have the same pair. Should be related.

1 is a flow chart of a method 100 of fabricating a semiconductor device 200 in one or more embodiments. 2-8 are cross-sectional views of the semiconductor device 200 fabricated in accordance with the method 100 of FIG. 1 in one or more embodiments, in various process stages. Semiconductor device 200 can include a microprocessor, a memory unit, and/or other integrated circuits (ICs). It is worth noting that the method of Figure 1 does not form a complete semiconductor device 200. The complete formation of the semiconductor device 200 can be a complementary metal oxide half (CMOS) process technology. In summary, additional processes can be performed before, during, and after the method of Figure 1, and the following is only a brief description of some other processes. Furthermore, the first to eighth figures have been simplified to make the present invention easy to understand. For example, although the drawing is a semiconductor device 200, it should be understood that the IC can include a variety of other devices such as resistors, capacitors, inductors, fuses, or the like.

As shown in FIGS. 1 and 2, step 102 of method 100 forms first recess 206 in first dielectric layer 204. In some embodiments, the first dielectric layer 204 is formed on the substrate 202. In some embodiments, substrate 202 includes a base substrate such as a crystalline germanium substrate (such as a germanium wafer). In other embodiments, substrate 202 includes a top semiconductor layer of a compound wafer, such as a germanium substrate on an insulating layer. In yet another embodiment, the substrate 202 is a top layer of a base substrate or a compound wafer, such as a tantalum, niobium alloy, a III-V material such as gallium arsenide or indium arsenide, a II-VI material such as zinc selenide or Zinc sulphide, or the like, is generally formed by epitaxial growth. The stress properties of Group III-V or Group II-VI materials such as indium arsenide, zinc sulfide, or the like are generally believed to be particularly advantageous for forming devices. The interconnect structure such as the metal wiring/via and its forming method are as follows. In the preferred embodiment of the present invention, the cross-sectional view of the apparatus in the process stage is as shown in Figures 2 through 8, and the changes are also disclosed below.

The first dielectric layer 204 includes a dielectric layer of the same layer or different layers, and the composition may be an inorganic dielectric or an organic dielectric. The first dielectric layer 204 can be a void material or a non-porous material. For example, the first dielectric layer 204 can be, but is not limited to, yttrium oxide, polyhedral sesquioxaxane, carbon doped oxide (such as organic bismuth, which contains bismuth, carbon, oxygen, and Hydrogen), a thermosetting polyarylene ether, or a multilayer structure as described above. The term "polyarylene ether" refers to an aromatic group or an aromatic group substituted with an inert group, and the linkage between these groups includes a bond, a fused ring, or an inert linking group such as oxygen, sulfur, hydrazine, Aachen, carbonyl, or the like.

The first dielectric layer 204 typically has a dielectric constant less than or equal to about 3.5 and is therefore also referred to as a low dielectric constant dielectric layer. In the preferred embodiment, the first dielectric layer 204 has a dielectric constant of less than about 2.5 and is therefore sometimes referred to as an ultra low dielectric constant (ELK) dielectric layer. Low and ultra low dielectric constant dielectrics typically have lower parasitic crosstalk than dielectric materials with dielectric constants above 4.0. The thickness of the first dielectric layer 204 depends on the type of dielectric material and the number of layers of dielectric material. For example, the first dielectric layer 204 for the interconnect structure has a thickness between about 150 nm and about 450 nm. In some embodiments, the first dielectric layer 204 is formed by a deposition process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), evaporation, chemical solution deposition, or spin coating. law.

The first dielectric layer 204 is then patterned to form a first recess 206 in the first dielectric layer 204. In some embodiments, the patterning process includes patterning a process on the first dielectric layer 204 (such as applying a photoresist, exposing the photoresist to a desired pattern, and developing a photoresist after exposure), and then performing the patterning process. An etch process (dry etch, wet etch, or a combination thereof) is performed to remove portions of the first dielectric layer 204, i.e., form a first recess 206 in the first dielectric layer 204. In some embodiments, first The recess 206 is used to form a trench for the metal line. In some embodiments, the stripping process is performed prior to forming the metal lines to remove the patterned photoresist.

As shown in FIGS. 1 and 3, step 104 of method 100 forms conductive layer 210 in first recess 206. In some embodiments, the conductive layer 210 fills the first recess 206 and covers the first conductive layer 204. In some embodiments, the conductive layer 210 can be copper or a copper alloy. In some embodiments, the method of forming the conductive layer 210 includes depositing a thin seed layer of copper or a copper alloy, and filling the first recess 206 with a conductive material such as copper or a copper alloy. In some embodiments, the thin seed layer and the conductive material are formed by physical vapor deposition (PVD) and electroplating, respectively. In other embodiments, conductive layer 210 comprises other conductive materials such as silver, gold, tungsten, aluminum, or the like.

In some embodiments, the barrier layer 208 is formed prior to forming the conductive layer 210. In some embodiments, the barrier layer 208 is formed in the exposed sidewall portion of the first dielectric layer 204 and the first recess 206. In some embodiments, the barrier layer 208 can be titanium, tantalum, tantalum nitride, titanium nitride, tantalum, tantalum nitride, tantalum alloy, tantalum nitride, tungsten, tungsten nitride, or any other A barrier material that prevents conductive material from diffusing through. The thickness of the barrier layer 208 depends on its deposition process and material type. In some embodiments, the barrier layer 208 has a thickness between about 0.5 nm and about 40 nm. In other embodiments, the barrier layer 208 has a thickness between about 0.5 nm and about 20 nm. In some embodiments, the barrier layer 208 is formed by a deposition process such as CVD, PECVD, PVD, atomic layer deposition (ALD), sputtering, chemical solution deposition, or electroplating.

As shown in FIGS. 1 and 4, step 106 of method 100 removes a portion of conductive layer 210. In some embodiments, the method of removing a portion of the conductive layer 210 is chemical mechanical polishing (CMP). In some embodiments, the CMP process removes the first dielectric layer A portion of the conductive layer 210 on the 204 and the underlying barrier layer 208 expose the upper surface of the first dielectric layer 204. In some embodiments, the CMP process removes a portion of the conductive layer 210 on the first recess 206 and retains other portions of the conductive layer 210 in the first dielectric layer 204. In some embodiments, the CMP step retains the conductive layer 210 in the first dielectric layer 204 while the upper surface of the remaining conductive layer 210 is substantially coplanar with the upper surface of the first dielectric layer 204. The structure of the barrier layer 208 and the conductive layer 210 in the first dielectric layer 204 in a single damascene process can be used as the first interconnect layer.

A pre-treatment process can then be performed to treat the surface of the conductive layer 210. In this embodiment, the pretreatment process includes nitrogen-based gas treatment in a production tool, and the production tool can be a PECVD machine. For example, nitrogen-based gases include nitrogen, ammonia, or the like. In other embodiments, the pretreatment is carried out in a hydrogen-based gas environment, and the hydrogen-based gas includes hydrogen, ammonia, or the like. Pre-treatment on the surface of the conductive layer 210 can reduce the primary metal oxide to a metal (such as reducing native copper oxide to copper) and can remove chemical contaminants from the surface of the conductive layer 210.

As shown in FIGS. 1 and 5, step 108 of method 100 forms first cap layer 212 on remaining conductive layer 210. The first cap layer 212 prevents holes from being formed in the interface of successive layers of interconnects, thereby increasing the electron transfer (EM) reliability of the semiconductor device 200. In some embodiments, the first cap layer 212 is formed on the exposed upper surface of the remaining conductive layer 210 (such as the conductive layer 210 in the first dielectric layer 204). In some embodiments, the first cap layer 212 is a two-layer structure that includes a second metal cap layer 212b on the first metal cap layer 212a. In some embodiments, the first cap layer 212 has a total thickness of between about 1 nm and about 70 nm. Although the first cap layer 212 in the drawing only covers the conductive layer 210 without covering the barrier layer 208, the present technology Those of ordinary skill in the art will appreciate that the first cover layer 212 may also extend over the top edge of the barrier layer 208.

The first metal cap layer 212a acts as an adhesive layer to provide sufficient adhesion to the underlying conductive layer 210. In certain embodiments, the first metal cap layer 212a comprises cobalt, tantalum, niobium, or an alloy of the foregoing, and the alloy includes tungsten, boron, phosphorus, molybdenum, and/or niobium. For example, cobalt, ruthenium, or osmium may be alloyed with tungsten, boron, phosphorus, molybdenum, and/or niobium. In this embodiment, the first metal cap layer 212a is a cobalt-containing metal cap layer such as cobalt phosphide. In some embodiments, the first metal cap layer 212a has a thickness between about 0.5 nm and about 20 nm. In other embodiments, the first metal cap layer 212a has a thickness between about 0.5 nm and about 10 nm. In some embodiments, the first metal cap layer 212a is formed by a selective deposition process, such as a catalytic plating process or an electroless plating process. In other embodiments, a non-selective deposition process such as sputtering, ALD, or CVD can be employed.

In some embodiments, the second metal cap layer 212b is selectively formed on the surface of the first metal cap layer 212a, and the width of the second metal cap layer 212b is substantially the same as the width of the first metal cap layer 212a. . In some embodiments, the second metal cap layer 212b is formed by a selective deposition process such as a catalytic plating process or an electroless plating process. In other embodiments, the second metal cap layer 212b may be formed using a non-selective deposition process such as sputtering, ALD, or CVD, such that the width of the second metal cap layer 212b is different than the width of the first metal cap layer 212a.

In this embodiment, the metal contained in the second metal cap layer 212b is different from the metal contained in the first metal cap layer 212a. In some embodiments, the material of the second metal cap layer 212b has a lower resistivity than the material of the first metal cap layer 212a to reduce the total resistance of the first cap layer 212. In other embodiments, The deposition rate of the material of the second metal cap layer 212b is higher than the deposition rate of the material of the first metal cap layer 212a to increase the throughput. In some embodiments, the second metal cap layer 212b comprises tungsten, tantalum, niobium, or an alloy of the foregoing. In some embodiments, the second metal cap layer 212b has a thickness between about 0.5 nm and about 50 nm. In other embodiments, the second metal cap layer 212b has a thickness between about 0.5 nm and about 10 nm.

As shown in FIGS. 1 and 6, a step 110 of method 100 forms a second dielectric layer 216 on the first dielectric layer 204, and a second dielectric layer 216 includes a second recess 218 therein. The second dielectric layer 216 typically has a dielectric constant less than or equal to about 3.5 and is therefore also referred to as a low dielectric constant dielectric layer. In the preferred embodiment, the second dielectric layer 216 has a dielectric constant of less than about 2.5 and is therefore also referred to as an ELK dielectric layer. In some embodiments, the second dielectric layer 216 contains the same dielectric material as the first dielectric layer 204. The process technology and thickness range of the first dielectric layer 204 can also be used for the second dielectric layer 216. In other embodiments, the second dielectric layer 216 contains a different dielectric material than the first dielectric layer 204.

In some embodiments, an ESL (etch stop layer) 214 is formed between the first dielectric layer 204 and the second dielectric layer 216. The second recess 218 is formed in the ESL 214 and the second dielectric layer 216, and the forming method may be the foregoing patterning and etching process. In some embodiments, the material of the ESL 214 is different than the material of the first dielectric layer 204 or the second dielectric layer 216 to provide etch selectivity in the process of forming the second recess 218. In certain embodiments, ESL 214 can be tantalum nitride, tantalum carbide, tantalum oxynitride, or a combination thereof.

In some embodiments, the second recess 218 includes an upper trench portion 218U that can then be used to form a conductive trace. The second recess 218 can be further The lower via portion 218L is included on the upper trench portion 218U and can then be used to form a conductive via. In this embodiment, the lower via portion 218L exposes at least a portion of the upper surface of the first cap layer 212. The conductive lines and the via holes formed by the dual damascene process can serve as the second interconnect layer on the first interconnect layer.

As shown in FIGS. 1 and 7, the step 112 of the method 100 successively forms the barrier layer 220 and the conductive material 222 in the second recess 218. In some embodiments, the barrier layer 220 of the pad second recess 218 is formed by a deposition process such as CVD, PECVD, PVD, atomic layer deposition (ALD), sputtering, chemical solution deposition, or electroplating. In some embodiments, the material of the barrier layer 220 can be the same as the material of the barrier layer 208. In some embodiments, the barrier layer 220 has a thickness range that is the same as the thickness of the barrier layer 208.

In some embodiments, the conductive material 222 is continuously formed on the barrier layer 220, as in the method of forming the conductive layer 210 described above. In some embodiments, the connector 222 fills up and extends beyond the second recess 218. In certain embodiments, the electrical conductor 222 comprises copper or a copper alloy. In some embodiments, the step of forming the conductive material 222 further includes depositing a thin seed layer of copper or a copper alloy prior to forming the copper or copper alloy. In some embodiments, the excess barrier layer 220 and the conductive material 222 on the surface of the second dielectric layer 216 are removed by a CMP process, and the other portions of the barrier layer 220 and the conductive material 222 are retained in the second dielectric layer. In electrical layer 216 and/or in ESL 214. The barrier layer 220 and the conductive material 222 remaining in the second dielectric layer 216 can serve as a second interconnect layer. As shown in FIG. 7, the second interconnect layer can be electrically connected to the underlying first interconnect layer via the first cap layer 212.

As shown in FIGS. 1 and 8, step 114 of method 100 forms second cap layer 224 on conductive 222. The second cover layer 224 prevents the holes from being formed in the interconnect The interface of successive layers of the line layer further increases the electron transfer (EM) reliability of the semiconductor device 200. In some embodiments, the second cap layer 224 is formed by a method of forming the first cap layer 212 as described above. In some embodiments, the second cap layer 224 is a two-layer structure having a second metal cap layer 224b on the first metal cap layer 224a. In some embodiments, the thickness range of the first metal cap layer 224a and the thickness range of the second metal cap layer 224b are each different from the thickness range of the first metal cap layer 212a and the thickness range of the second metal cap layer 212b. the same. Although the second cap layer 224 in the drawing only covers the conductive material 222 without covering the barrier layer 220, it will be understood by those of ordinary skill in the art that the second cap layer 224 may also extend to the top edge of the barrier layer 220. on.

The first metal cap layer 224a acts as an adhesive layer and provides sufficient adhesion to the underlying conductive material 222. In certain embodiments, the first metal cap layer 224a comprises cobalt, tantalum, niobium, or an alloy of the foregoing, and the alloy comprises tungsten, boron, phosphorus, molybdenum, and/or niobium. In some embodiments, the material of the first metal cap layer 224a is the same as the material of the first metal cap layer 212a. In this embodiment, the second metal cap layer 224b includes a metal that is different from the metal included in the first metal cap layer 212a. In some embodiments, the material resistivity of the second metal cap layer 224b is lower than the material resistivity of the first metal cap layer 224a to reduce the total resistivity of the second cap layer 224. In other embodiments, the deposition rate of the material of the second metal cap layer 224b is higher than the deposition rate of the material of the first metal cap layer 224a to increase the productivity of the product. In some embodiments, the second metal cap layer 224b comprises tungsten, tantalum, niobium, or an alloy of the foregoing. In some embodiments, the first metal cap layer 224a and the second metal cap layer 224b are formed by a selective deposition process, such as a catalytic plating process or an electroless plating process. In other embodiments, non-selective deposition processes such as sputtering, ALD, or CVD.

Embodiments of the invention have a number of advantages. The first metal cap layer provides sufficient adhesion to the underlying conductive material to provide a strong mechanical strength between the first metal cap layer and the underlying conductive material. Furthermore, the second metal cap layer has a lower resistivity than the first metal cap layer. In this way, the total resistance of the first metal cap layer and the second metal cap layer can be reduced. Furthermore, the deposition rate of the second metal cap layer is higher than the deposition rate of the first metal cap layer. In summary, the total deposition time of the first and second metal cap layers can be shortened, thereby improving the productivity of the semiconductor device.

In one embodiment, the integrated circuit structure includes a substrate, a dielectric layer on the substrate, a conductive wire in the dielectric layer, a first metal cap layer on the conductive wire, and a first metal cap layer The second metal cover. The width of the second metal cap layer is substantially the same as the width of the first metal cap layer.

In another embodiment, the integrated circuit structure includes: a semiconductor substrate, a low dielectric constant dielectric layer on the semiconductor substrate, and an upper surface extending from a low dielectric constant dielectric layer to a low dielectric constant An opening in the electrical layer, a barrier layer of the pad opening, a copper-containing conductive line in the opening and the barrier layer, a first metal cap layer on the copper-containing conductive line, and a first metal cap layer The second metal cover. The material of the first metal cap layer is different from the material of the second metal cap layer.

In another embodiment, the method includes: forming a dielectric layer on the semiconductor substrate; forming a copper line in the dielectric layer; forming a first metal cap layer on the copper line; and selectively forming the second metal cap layer on On the first metal cover layer.

While the above has been described in detail with reference to the embodiments, it is understood that various modifications can be made without departing from the scope of the application and the spirit of the embodiments. Change, substitution, and change. Further, the scope of the patent application is not limited to the processes, machines, fabrication, compositions, devices, methods, and steps of the specific embodiments described above. As is known to those skilled in the art from the present disclosure, in accordance with the presently available embodiments and corresponding embodiments, it is possible to employ processes, machines, or processes that have substantially the same function or that achieve substantially the same results, either currently or in the future. Production, composition, device, method or procedure. In summary, the scope of the patent application includes the above-described processes, machines, fabrications, compositions, devices, methods, or steps.

200‧‧‧Semiconductor device

202‧‧‧Substrate

204‧‧‧First dielectric layer

208, 220‧‧‧ barrier layer

210‧‧‧ Conductive layer

212‧‧‧First cover

214‧‧‧ESL

212a, 224a‧‧‧ first metal cover

212b, 224b‧‧‧ second metal cover

216‧‧‧Second dielectric layer

222‧‧‧ Conductor

224‧‧‧Second cover

Claims (11)

An integrated circuit structure comprising: a substrate; a dielectric layer on the substrate; a conductive wire in the dielectric layer; a first metal cap layer on the conductive wire; and a second metal a cap layer is disposed on the first metal cap layer, wherein a width of the second metal cap layer is substantially the same as a width of the first metal cap layer. The integrated circuit structure of claim 1, wherein a material resistivity of the second metal cap layer is lower than a material resistivity of the first metal cap layer. The integrated circuit structure of claim 1, wherein the material of the second metal cap layer is different from the material of the first metal cap layer, wherein the first metal cap layer comprises cobalt, lanthanum, cerium, or The above alloy, and wherein the second metal cap layer comprises tungsten, tantalum, niobium, or an alloy thereof. The integrated circuit structure of claim 1, further comprising: an etch stop layer on the second metal cap layer; a low dielectric constant dielectric layer on the etch stop layer; a via plug, located in the low dielectric constant dielectric layer, wherein the via plug passes through an opening in the etch stop layer, and wherein the via plug contacts the second metal cap layer; a metal a line in the dielectric layer of the low dielectric constant and contacting the via plug; and a third metal cap layer on the metal line, wherein the third metal cap layer has a two-layer structure. An integrated circuit structure comprising: a semiconductor substrate; a low dielectric constant dielectric layer on the semiconductor substrate; and an opening extending from the upper surface of the low dielectric constant dielectric layer to the low dielectric a constant dielectric layer; a barrier layer, the opening; a copper-containing conductive line in the opening and the barrier layer; a second metal cap layer on the copper-containing conductive line; A first metal cap layer is disposed between the second metal cap layer and the copper-containing conductive trace, wherein a material of the first metal cap layer is different from a material of the second metal cap layer. The integrated circuit structure of claim 5, wherein the first metal cap layer comprises cobalt, tantalum, niobium, or an alloy thereof, and wherein the second metal cap layer comprises tungsten, tantalum, niobium, or The above alloy. The integrated circuit structure of claim 5, wherein a material resistivity of the second metal cap layer is lower than a material resistivity of the first metal cap layer. The integrated circuit structure of claim 5, wherein the width of the second metal cap layer is substantially the same as the width of the first metal cap layer. A method for forming an integrated circuit structure includes: forming a dielectric layer on a semiconductor substrate; forming a copper line in the dielectric layer; forming a first metal cap layer on the copper line; and forming a A second metal cap layer is disposed on the first metal cap layer, wherein a width of the second metal cap layer is substantially the same as a width of the first metal cap layer. The method for forming an integrated circuit structure according to claim 9, wherein the first metal cap layer is different from the material of the second metal cap layer, and the resistivity of the second metal cap layer is lower than the first The resistivity of a metal cap layer. The method of forming an integrated circuit structure according to claim 9, wherein the first metal cap layer is selectively formed on the copper line.