TW201421590A - Bumping process for improving underfill adhesion - Google Patents

Abstract

Disclosed is a bumping process for improving underfill adhesion to lessen underfill delamination without the demand of an extra coarsening step added in bumping process. A photo-resist type dielectric layer is formed on a passivation layer of a semiconductor substrate and covers the substrate pads. Grayscale exposure and opening exposure are performed on the photo-resist type dielectric layer by one photo mask. After development, the photo-resist type dielectric layer has a plurality of openings exposing the pads and a plurality of dense dimples located above the passivation layer by underexposure. A plurality of bumps are disposed on the pads. Therein, the openings are smaller than the footprints of the corresponding bumps in a manner that the dense dimples are further distributed under the bumps.

Description

Bump process to improve adhesion of primer

The present invention relates to a method of forming bumps on a wafer surface in the fabrication technique of a semiconductor device, and more particularly to a bump process for improving adhesion of a primer.

The bump process is implemented on a wafer, and various protruding bumps are provided on the bonding surface of a semiconductor device such as a wafer or a wafer level wafer package structure to electrically connect the semiconductor device. In general, there is a bonding gap between the semiconductor device having bumps and the substrate to be bonded, so it is necessary to fill the underfill. However, the adhesion of the underfill colloid to the protective layer of a semiconductor device such as a conventional bump wafer is not good, and delamination of the undercoat joint interface is liable to occur.

Figures 1A through 1H illustrate a conventional bump process. As shown in FIG. 1A, a plurality of pads 312 are disposed on a semiconductor substrate 310 and covered with a protective layer 313. As shown in FIG. 1B, an under bump metal layer 350 is formed on the protective layer 313, and the pads 312 are covered via the openings 314 of the protective layer 313. As shown in FIG. 1C, a photosensitive film 360 for electroplating is formed on the under bump metal layer 350, and exposed to develop a portion of the under bump metal layer 350 on the pads 312. As shown in FIG. 1D, a plurality of bumps 340 are formed on the pads 312 by patterning of the photosensitive film 360 for electroplating, wherein each bump 340 may include a columnar body 341 and A solder layer 342. As shown in FIG. 1E, the photosensitive film 360 for electroplating is removed to display The under bump metal layer 350 is not located at the rest of the bumps 340. As shown in FIG. 1F, the remaining portions are removed by etching so that the under bump metal layer 350 is transformed into a plurality of under bump metal sockets 351 that bond the bumps 340. As shown in FIG. 1G, an additional roughening step is added in the bump process and the surface leakage current is reduced, and the residual metal layer 350 on the protective layer 313 can be more effectively removed or formed into an oxide to reduce the surface by plasma etching. The leakage current is generated while the surface 315 is roughened, and the top and side edges of the bumps 340 are also roughened. Finally, as shown in FIG. 1H, a reflow step can be performed to solder the solder layer 342 to the corresponding columnar body 341. The above plasma etching can also be performed after reflow. However, the extent to which the protective layer surface 315 is roughened by plasma etching is limited, and the underfill and the wafer protective layer are not compatible with the properties of the material itself, so that the underfill colloid cannot be The roughened surface of the protective layer 313 forms a stronger bond, and there is still a chance that delamination from the protective layer 313 will occur, resulting in reduced product reliability and yield.

In order to solve the above problems, the main object of the present invention is to improve the adhesion of the primer to improve the adhesion of the primer, and to improve the adhesion of the protective layer of the semiconductor device such as the bumped wafer to the underfill, resulting in the primer being removed. A delamination phenomenon occurs and the bump process does not require an additional coarsening step.

The second object of the present invention is to provide a bump process for improving the adhesion of the primer, and to form a dense pit by omitting the process steps. A photoresist type dielectric layer to improve the adhesion of the primer to the bonding force of the bumps (or metal sockets under the bumps).

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a bump process for improving the adhesion of a primer, comprising the steps of: providing a semiconductor substrate having a plurality of first pads on a bonding surface thereof and covering a first protective layer; forming a a photoresist layer on the first protective layer and covering the first pads; performing gray scale exposure and aperture exposure on the photoresist type dielectric layer by using a gray scale mask, the gray scale mask Having a gray-scale region and a plurality of non-gray-order dot patterns in the gray-scale region, the gray-scale region being aligned with a portion of the photoresist-type dielectric layer on the first protective layer, Aligning the non-gray dot patterns with the first pads; developing the photoresist type dielectric layer while removing portions of the photoresist type dielectric layer on the first pads, so that The photoresist type dielectric layer has a plurality of first openings exposing the first pads, and partially removing the photoresist type dielectric layer on the first protective layer to form a surface thereof a plurality of under-exposed dense pits; and a plurality of bumps on the first pads, wherein the plurality of bumps An opening smaller than the plurality of lines corresponding to the surface coverage of the bumps, so that the plurality of dimples densely distributed more downward of the bumps.

The invention further discloses a bump structure which is improved by the above-mentioned bump process and which improves the adhesion of the primer.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing bump process, the method further includes the steps of: forming a bump underlying metal layer on the photoresist type dielectric layer and bonding to the first pads before the bumps are disposed. The dense pits are covered by the first openings to the first pads for bonding of the bumps; and after the bumps are disposed, the bumps are removed by etching The metal layer is not located at the exposed portion below the bumps. Therefore, the under bump metal layer (ie, the under bump metal socket) remaining under the bumps will have a better bonding force with the photoresist type dielectric layer.

In the foregoing bump process, in the step of disposing the bumps, the under bump metal layer can be used as a plating conductive surface, and the bumps are electroplated to be bonded to the under bump metal layer. The part on the first pad.

In the bump process described above, each of the bumps may comprise a columnar body and a solder layer formed by electroplating a photosensitive film for the same plating.

In the foregoing bump process, the photoresist type dielectric layer may include a positive photoresist, and the non-gray dot dot patterns are light transmission holes.

In the foregoing bump process, the photoresist type dielectric layer may include a negative photoresist, and the non-gray dot patterns are light shielding pads.

In the foregoing bump process, the first protection layer may have a plurality of second openings aligned with the first pads, and the second openings are smaller than the first pads and larger than the The first openings are such that the first protective layer partially covers the periphery of the first pads and is not exposed to the photoresist type The first openings of the dielectric layer.

In the foregoing bump process, the bonding surface of the semiconductor substrate may further comprise a plurality of second pads and covered with a second protective layer under the first protective layer, the first pads The reconfigured circuit layer is connected to the reconfigured circuit layer, and the reconfigurable circuit layer is formed on the first protective layer and connects the first pads to the corresponding second pads. The Wafer Level Chip Scale Package (WLCSP) can be fabricated by the bump process.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

According to a first embodiment of the present invention, a bump process for improving adhesion of a primer is exemplified in a cross-sectional view of an element in the process of FIGS. 2A to 2J.

First, as shown in FIG. 2A, a semiconductor substrate 110 is provided. A plurality of first pads 112 are disposed on a bonding surface 111 of the semiconductor substrate 110 and covered with a first protective layer 113. The semiconductor substrate 110 can be a wafer on which an integrated circuit is fabricated, and the wafer can pass through a crystal back. mill. In this embodiment, the first protective layer 113 may have a plurality of openings 114 aligned with the first pads 112, which are smaller than the first pads 112, so that the first protective layer 113 partially covers the periphery of the first pads 112. The openings 114 of the first protective layer 113 may be substantially the same as the surface coverage area of the plurality of subsequently formed bumps 140 (as shown in FIGS. 2G to 2J). Additionally, this step can include wafer cleaning.

Then, as shown in FIG. 2B, a photoresist type dielectric layer 120 is formed on the first protective layer 113 and covers the first pads 112. The photoresist type dielectric layer 120 may comprise a positive photoresist or a negative photoresist. The main component of the photoresist dielectric layer 120 may be a photosensitive polyimide, polybenzoxazole or polybenzoxazole. , PBO), or benzocyclobutene (BCB). Generally, the thickness of the photoresist type dielectric layer 120 is greater than the thickness of the first protective layer 113.

Then, as shown in FIG. 2C, the photoresist type dielectric layer 120 is subjected to gray scale exposure and aperture exposure using a gray scale mask 130 having a gray scale region 131 and a plurality of a non-gray-order dot pattern 132 in the gray-scale region 131, the gray-scale region 131 being aligned with a portion of the photoresist-type dielectric layer 120 on the first protective layer 113, the non-gray scale The dot pattern 132 is aligned with the first pads 112. In this embodiment, the non-gray-level dot patterns 132 are smaller than the first pads 112 and smaller than the openings 114 of the first protective layer 113, so that the gray-scale regions 131 are partially overlapped to the holes. The first pad 112, and the gray-scale region 131 includes a plurality of fine micro-holes to reduce the light transmittance thereof.

Then, as shown in FIG. 2D, the photoresist type dielectric layer 120 is developed, and the portion of the photoresist type dielectric layer 120 on the first pads 112 is removed to make the photoresist type The electrical layer 120 has a plurality of first openings 121 exposing the first pads 112, and partially removes the photoresist layer 120 on the first protective layer 113 to form a surface thereof. There are a plurality of underexposed dense pits 122. The plurality of dense pits 122 may be dispersed on the first pads 112 due to the non-gray dot patterns 132 located in the gray scale region 131 and having a small size. In this embodiment, the first protective layer 113 is aligned with the first opening 112 of the first pad 112 to be larger than the first opening 121, so that the first protective layer 113 is not exposed to the light. The first openings 121 of the resistive dielectric layer 120. Or in another actual structure, the opening 114 of the first pad 112 may be smaller than the first opening 121 (not shown).

As shown in FIG. 2C, when the photoresist type dielectric layer 120 includes a positive photoresist, the non-gray dot patterns 132 may be transparent holes. Therefore, the portion of the photoresist type dielectric layer 120 that is irradiated with light can be removed by the developer, and the first openings 121 and the dense pits 122 can be simultaneously formed. In a variation of the embodiment, as shown in FIG. 4, when the photoresist type dielectric layer 120 includes a negative photoresist, the non-gray dot patterns 132 may be light shielding pads. Therefore, the portion of the photoresist type dielectric layer 120 that is irradiated with light will remain on the semiconductor substrate 110.

The 2E to 2J drawings are related to specifically setting a plurality of bumps 140 on the first pads 112 and a pre-step thereof. The first openings 121 of the photoresist type dielectric layer 120 may be smaller than the corresponding bumps. The surface coverage area of 140 is such that the dense pits 122 are more distributed below the bumps 140 (as covered by the pits 122A in FIG. 3).

As shown in FIG. 2E, before the bumps 140 are disposed, a bump under metal layer 150 may be formed on the photoresist type dielectric layer 120 by sputtering to be bonded to the pads. The dense pits 122 on the pads 112 are covered by the first openings 121 to the first pads 112 for bonding of the bumps 140.

As shown in FIG. 2F, a photosensitive film 160 for electroplating is formed on the under bump metal layer 150 and exposed to light to expose the under bump metal layer 150 over the first pads 112. The portion, in turn, defines a surface coverage area of the bumps 140.

As shown in FIG. 2G, in the step of providing the bumps 140, the under bump metal layer 150 can be used as a plating conductive surface, and the bumps 140 are electroplated to the under bump metal layer 150. The portions on the first pads 112 are formed in the through holes of the plating photosensitive film 160. As shown in FIG. 2H, the photosensitive film 160 for electroplating is removed to reveal that the under bump metal layer 150 is not located at the exposed portion below the bumps. Each of the bumps 140 may include a columnar body 141 and a solder layer 142 formed by plating the same photosensitive film 160 for electroplating. The columnar body 141 may be a copper post, and the solder layer 142 may be tin silver (Sn-Ag).

As shown in FIG. 2I, after the bumps 140 are disposed, the under bump metal layer 150 is removed from the exposed portions below the bumps, so that the under bump metal layer 150 is converted into a plurality of bumps. Positioned in the convex Below the block 140, the under bump metal socket 151. Therefore, the under bump metal layer 150 remaining under the bumps 140 is formed as the under bump metal socket 151 as shown in FIG. 2I, which will be made due to the presence of the covered pits 122A in FIG. The under bump metal socket 151 has a better bonding force with the photoresist type dielectric layer 120.

The solder layer 142 can be reflowed as shown in FIG. 2J.

Therefore, the bump process system for improving the adhesion of the primer can improve the delamination phenomenon of the undercoat of the protective layer of the semiconductor device such as the conventional bump wafer. And the bump process does not require additional coarsening steps. Moreover, a bump structure for improving the adhesion of the primer as shown in FIG. 2J can be formed by the above-mentioned bump process, and the semiconductor substrate 110 is singulated by a wafer by a single wafer cutting process. Wafers are constructed to form a flip chip structure having stud bumps.

In accordance with a second embodiment of the present invention, another bump process for improving the adhesion of the primer is illustrated in the cross-sectional view of the components in the process of Figures 5A through 5J.

The 5A to 5G drawings relate to the specific provision of another semiconductor substrate 110. As shown in FIG. 5G, a plurality of first pads 112 are disposed on one of the bonding faces 111 of the semiconductor substrate 110 and covered with a first protective layer 113. In this embodiment, the plurality of second pads 215 are further disposed on the bonding surface 111 of the semiconductor substrate 110 and covered with the second protective layer 216 under the first protective layer 113. The first pads 112 can be a plurality of reconfigured pads connected to a reconfigured circuit layer 270, and The reconfigured circuit layer 270 is formed on the first protective layer 113 and connects the first pads 112 to the corresponding second pads 215.

As shown in FIG. 5A, the second pad 215 and the second protective layer 216 may be further disposed on the bonding surface 111 of the semiconductor substrate 110. As shown in FIG. 5B, the first protective layer 113 is formed on the second protective layer 216 and the second pads 215 are exposed. As shown in FIG. 5C, a metal layer 271 such as a titanium/copper (Ti/Cu) material is formed on the first protective layer 113 by sputtering and covers the conductive connection pattern. The second pad 215. As shown in FIG. 5D, a photoresist 280 is formed on the metal layer 271 and patterned such that the metal layer 271 reveals a hollow pattern to form a reconfigured wiring layer. As shown in FIG. 5E, pattern plating is performed according to the hollow pattern of the photoresist 280 to form an embossed wiring structure 272 of a material such as copper/nickel/silver (Cu/Ni/Ag) on the metal layer 271. . As shown in FIG. 5F, the photoresist 280 is removed to reveal a portion of the metal layer 271 that is not covered by the embossed trace structure 272. As shown in FIG. 5G, under the cover protection of the embossed line structure 272, the portion of the metal layer 271 not covered by the embossed line structure 272 may be removed by etching, and the metal layer 271 is covered with the embossing. The remaining portion of the line structure 272 plus the embossed line structure 272 will be converted to the reconfigured wiring layer 270 containing the first pads 112.

As shown in FIG. 5H, a photoresist type dielectric layer 120 is formed on the first protective layer 113 and covers the first pads 112. Thereafter, the gray-scale exposure and opening of the photoresist type dielectric layer 120 is performed by using a gray scale mask 130. The gray scale mask 130 has a gray scale region 131 and a plurality of non-gray dot pattern 132 in the gray scale region 131, and the gray scale region 131 is aligned with the photoresist type dielectric. The layer 120 is located on the first protective layer 113, and the non-gray dot patterns 132 are aligned with the first pads 112.

As shown in FIG. 5I, the photoresist type dielectric layer 120 is developed, and the portion of the photoresist type dielectric layer 120 on the first pads 112 is removed to make the photoresist type dielectric layer. The 120 has a plurality of first openings 121 exposing the first pads 112, and partially removes the photoresist layer 120 on the first protective layer 113 to form a plurality of surfaces thereon. An underexposed dense pit 122. The depth of the dense pits 122 is about 10-40% of the thickness of the photoresist type dielectric layer 120, or between 0.5 and 2.0 micrometers (um). The dense pits 122 may be of any shape, wherein a circle is preferred, and the diameter or length may be between 0.3 and 3.0 micrometers (um). In different embodiments, the transmittance of the dense pits 122 may be 50 to 100% of the thickness of the photoresist type dielectric layer 120, so that the semiconductor substrate 110 is severe. Before the warpage, the photoresist type dielectric layer 120 can be first divided into a plurality of cell blocks to reduce the degree of warpage of the semiconductor substrate 110.

As shown in FIG. 5J, a plurality of bumps 140 are disposed on the first pads 112, wherein the first openings 121 are smaller than the surface coverage areas of the corresponding bumps 140, so as to be dense. The dimples 122 are more distributed below the bumps 140.

Therefore, the present invention provides a bump process for improving the adhesion of the primer. The improvement of the adhesion of the protective layer of the semiconductor device such as the conventional bump wafer to the underfill causes the delamination phenomenon of the primer, and the bump process does not need to add an additional roughening step. The bump structure capable of improving the adhesion of the primer as shown in FIG. 5J can be formed by the above-mentioned bump process, and the semiconductor substrate 110 is singulated into a plurality of wafers by a single wafer process. To form a waiverable Wafer Level Chip Scale Package (WLCSP).

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

110‧‧‧Semiconductor substrate

111‧‧‧ joint surface

112‧‧‧First mat

113‧‧‧First protective layer

114‧‧‧Second opening

120‧‧‧Photoresistive dielectric layer

121‧‧‧First opening

122‧‧‧Dense pits

122A‧‧‧ covered pit

130‧‧‧ Grayscale mask

131‧‧‧ Grayscale area

132‧‧‧Non-gray dot pattern

140‧‧‧Bumps

141‧‧‧ columnar body

142‧‧‧ solder layer

150‧‧‧ under bump metal layer

151‧‧‧Under the metal seat under the bump

160‧‧‧Photosensitive film for electroplating

215‧‧‧second mat

216‧‧‧Second protective layer

270‧‧‧Reconfigured circuit layer

271‧‧‧metal layer

272‧‧‧ embossed line structure

280‧‧‧Light resistance

310‧‧‧Semiconductor substrate

312‧‧‧ pads

313‧‧‧Protective layer

314‧‧‧ openings

315‧‧‧ roughened surface

340‧‧‧Bumps

341‧‧‧ columnar body

342‧‧‧ solder layer

350‧‧‧ under bump metal layer

351‧‧‧Under the metal seat under the bump

360‧‧‧Photosensitive film for electroplating

1A to 1H: A schematic cross-sectional view of an element in a conventional bump process.

2A to 2J are views showing a cross-sectional view of an element in a bump process for improving adhesion of a primer according to a first embodiment of the present invention.

Fig. 3 is a top plan view of Fig. 2J in accordance with a first embodiment of the present invention.

Figure 4 is a cross-sectional view showing the element of a photosensitive dielectric layer exposed to a gray scale exposure by a bump process for improving the adhesion of the primer according to a variation of the first embodiment of the present invention.

5A to 5J are schematic cross-sectional views showing another element in a bump process for improving adhesion of a primer according to a second embodiment of the present invention.

110‧‧‧Semiconductor substrate

111‧‧‧ joint surface

112‧‧‧First mat

113‧‧‧First protective layer

114‧‧‧Second opening

120‧‧‧Photoresistive dielectric layer

130‧‧‧ Grayscale mask

131‧‧‧ Grayscale area

132‧‧‧Non-gray dot pattern

Claims (10)

A bump process for improving the adhesion of a primer, comprising: providing a semiconductor substrate, wherein a plurality of first pads are disposed on a bonding surface of the semiconductor substrate and covered with a first protective layer; forming a photoresist type dielectric Laminating on the first protective layer and covering the first pads; performing gray scale exposure and aperture exposure on the photoresist type dielectric layer by using a gray scale mask, the gray scale mask has a gray scale a region and a plurality of non-gray-order dot patterns in the gray-scale region, the gray-scale region being aligned with a portion of the photoresist-type dielectric layer on the first protective layer, the non-gray-order points Aligning the pattern with the first pads; developing the photoresist type dielectric layer while removing portions of the photoresist type dielectric layer on the first pads, so that the photoresist type is The electric layer has a plurality of first openings exposing the first pads, and partially removing the photoresist type dielectric layer on the first protective layer to form a plurality of underexposures on the surface thereof a dense pit; and a plurality of bumps are disposed on the first pads, wherein the first openings are smaller than corresponding The plurality of coverage of the surface of the bump, so that the plurality of dimples densely distributed more downward of the bumps. According to the bump process for improving the adhesion of the primer according to Item 1 of the patent application, the method further comprises the steps of: forming a sub-bump metal layer on the photoresist dielectric layer and bonding before setting the bumps; The one on the first pads Draw a plurality of recesses, and cover the first pads via the first openings for bonding of the bumps; and after the bumps are disposed, the metal layer under the bumps is removed by etching Located outside the exposed portions of the bumps. The bump process for improving the adhesion of the primer according to the second aspect of the patent application, wherein in the step of providing the bumps, the under bump metal layer is an electroplated conductive surface, and the bumps are electroplated The under bump metal layer is located on the first pads. The bump process for improving the adhesion of the primer according to the third application of the patent application, wherein each of the bumps comprises a columnar body and a solder layer formed by plating the same electroplating photosensitive film. The bump process for improving the adhesion of a primer according to the first aspect of the patent application, wherein the photoresist type dielectric layer comprises a positive photoresist, and the non-gray dot patterns are light-transmitting holes. The bump process for improving the adhesion of a primer according to the first aspect of the patent application, wherein the photoresist type dielectric layer comprises a negative photoresist, and the non-gray dot patterns are light shielding pads. The bump process for improving the adhesion of the primer according to the first aspect of the patent application, wherein the first protective layer has a plurality of second openings aligned with the first pads, and the second openings are Less than the first pads and larger than the first openings, so that the first protective layer partially covers the periphery of the first pads and is not exposed to the first portions of the photoresist type dielectric layer Open the hole. Bumps for improving the adhesion of the primer according to item 1 of the patent application scope The process, wherein the bonding surface of the semiconductor substrate is further provided with a plurality of second pads and covered with a second protective layer under the first protective layer, wherein the first pads are connected to a plurality of The reconfiguration pad is disposed on the first protection layer and the first pads are connected to the corresponding second pads. A bump structure for improving adhesion of a primer, comprising: a semiconductor substrate having a plurality of first pads on a bonding surface thereof and covered with a first protective layer; a photoresist type dielectric layer formed on the substrate On the first protective layer, the photoresist type dielectric layer has a plurality of first openings exposing the first pads, and the surface of the photoresist type dielectric layer on the first protective layer is formed. a plurality of dense pits formed by the gray scale exposure to form an underexposure; and a plurality of bumps disposed on the first pads, wherein the first openings are smaller than the surface coverage areas of the corresponding bumps So that the dense pits are more distributed below the bumps. A bump structure for improving adhesion of a primer according to claim 9 of the patent application scope, further comprising a plurality of under-bump metal sockets formed on the photoresist type dielectric layer and bonded to the first The dense pits on the pad are covered by the first openings to the first pads for bonding of the bumps.