TW201421543A - Epitaxial wafer and its manufacturing method - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 105
- 239000004065 semiconductor Substances 0.000 claims abstract description 337
- 150000004767 nitrides Chemical class 0.000 claims abstract description 243
- 230000002093 peripheral effect Effects 0.000 claims abstract description 86
- 230000007717 exclusion Effects 0.000 claims abstract description 60
- 239000013078 crystal Substances 0.000 claims abstract description 56
- 238000000034 method Methods 0.000 claims description 109
- 229910052594 sapphire Inorganic materials 0.000 claims description 34
- 239000010980 sapphire Substances 0.000 claims description 34
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical group Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 23
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 238000005121 nitriding Methods 0.000 claims description 8
- 239000011800 void material Substances 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 397
- 239000000758 substrate Substances 0.000 description 57
- 239000010408 film Substances 0.000 description 42
- 239000000463 material Substances 0.000 description 41
- 238000000927 vapour-phase epitaxy Methods 0.000 description 26
- 230000003287 optical effect Effects 0.000 description 22
- 239000002994 raw material Substances 0.000 description 22
- 125000002524 organometallic group Chemical group 0.000 description 21
- 239000007789 gas Substances 0.000 description 18
- 238000002407 reforming Methods 0.000 description 18
- 238000011156 evaluation Methods 0.000 description 17
- 238000012545 processing Methods 0.000 description 16
- 238000002441 X-ray diffraction Methods 0.000 description 15
- 230000008569 process Effects 0.000 description 14
- 229910052732 germanium Inorganic materials 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000002452 interceptive effect Effects 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 6
- 229910002704 AlGaN Inorganic materials 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 5
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 5
- 238000001451 molecular beam epitaxy Methods 0.000 description 5
- 238000007740 vapor deposition Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000012159 carrier gas Substances 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000003754 machining Methods 0.000 description 3
- 238000005086 pumping Methods 0.000 description 3
- 238000001878 scanning electron micrograph Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000001771 vacuum deposition Methods 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000032258 transport Effects 0.000 description 2
- 229910017109 AlON Inorganic materials 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910020068 MgAl Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000000275 quality assurance Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N zinc oxide Inorganic materials [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02021—Edge treatment, chamfering
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
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- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
- C30B29/403—AIII-nitrides
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
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- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
- H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
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Abstract
本發明之目的在於提供一種磊晶晶圓,其具備晶圓以及形成於晶圓之一表面側的整個面上的單晶III族氮化物半導體層。III族氮化物半導體層,具有外周部及中央部,該外周部形成於晶圓的周邊部所構成的除外區域,該中央部形成於比晶圓中的除外區域更為內側應用區域。應用區域,係晶圓之除外區域以外的區域。相較於中央部,外周部包含較多空隙或是以晶圓的一表面側作為起點的突起。磊晶晶圓中,中央部之結晶性高於外周部之結晶性。An object of the present invention is to provide an epitaxial wafer comprising a wafer and a single crystal group III nitride semiconductor layer formed on the entire surface side of one surface of the wafer. The group III nitride semiconductor layer has an outer peripheral portion and a central portion, and the outer peripheral portion is formed in an exclusion region formed by a peripheral portion of the wafer, and the central portion is formed in an inner application region than the exclusion region in the wafer. The application area is an area other than the excluded area of the wafer. The outer peripheral portion includes a larger number of voids or a projection having a surface side of the wafer as a starting point as compared with the central portion. In the epitaxial wafer, the crystallinity of the central portion is higher than that of the outer peripheral portion.
Description
本發明係關於一種磊晶晶圓及其製造方法。 The present invention relates to an epitaxial wafer and a method of fabricating the same.
作為使用III族氮化物半導體的半導體裝置,以發光二極體為代表的發光裝置、及以高電子移動率電晶體(HEMT;high electron mobility transistor)為代表的電子裝置等,正在各處研究開發。另外,最近,將III族氮化物半導體的紫外發光裝置,使用於可高效率照射白光的照明領域、必須殺菌及滅菌的衛生領域、醫療領域以及高速處理環境汙染物等的領域,受到莫大的期待。又,作為發出波長為200~360nm之光線(紫外光)的紫外光半導體發光元件所使用的材料,氮化鋁正受到矚目。作為紫外光半導體發光元件,可舉例如,紫外發光二極體或紫外光半導體雷射等。利用使半導體層磊晶成長於基板上的磊晶晶圓,可形成半導體裝置。 As a semiconductor device using a group III nitride semiconductor, a light-emitting device typified by a light-emitting diode and an electronic device represented by a high electron mobility transistor (HEMT) are being researched and developed at various places. . In addition, recently, the III-type nitride semiconductor ultraviolet light-emitting device has been widely used in the field of lighting that can efficiently illuminate white light, in the field of hygiene that must be sterilized and sterilized, in the medical field, and in high-speed treatment of environmental pollutants. . Further, as a material used for an ultraviolet semiconductor light-emitting element that emits light having a wavelength of 200 to 360 nm (ultraviolet light), aluminum nitride is attracting attention. Examples of the ultraviolet semiconductor light-emitting device include an ultraviolet light-emitting diode or an ultraviolet semiconductor laser. A semiconductor device can be formed by using an epitaxial wafer in which a semiconductor layer is epitaxially grown on a substrate.
另外,III族氮化物半導體結晶難以低成本化及大尺寸化,故難以作為可用於磊晶成長之基板的塊材結晶。因此,具有很多將III族氮化物半導體結晶磊晶成長於與III族氮化物半導體結晶相異之材料的基板上的情形。事實上,為了使III族氮化物半導體結晶磊晶成長,大多使用藍寶石基板或碳化矽基板作為不同材料所形成的基板。又,作為使III族氮化物半導體結晶磊晶成長於其上的塊材結晶之基板,具有例如,GaN獨立基板(free standing substrates)及AlN獨立基板。磊晶成長法,可舉例如:有機金屬氣相磊晶 (MOVPE;Metal Organic Vapor Phase Epitaxy)法,氫化物氣相磊晶(HVPE;Hydride Vapor Phase Epitaxy)法,分子束磊晶(MBE;Molecular Beam Epitaxy)法等。 Further, since the group III nitride semiconductor crystal is difficult to be reduced in cost and large in size, it is difficult to form a bulk crystal which can be used for a substrate for epitaxial growth. Therefore, there are many cases in which a group III nitride semiconductor crystal is epitaxially grown on a substrate different from the material of the group III nitride semiconductor crystal. In fact, in order to crystallize and grow the group III nitride semiconductor crystal, a sapphire substrate or a tantalum carbide substrate is often used as a substrate formed of a different material. Further, as a substrate of a bulk crystal in which a group III nitride semiconductor crystal is epitaxially grown, there are, for example, GaN free standing substrates and AlN independent substrates. Epitaxial growth method, for example: organometallic vapor phase epitaxy (MOVPE; Metal Organic Vapor Phase Epitaxy) method, Hydride Vapor Phase Epitaxy (HVPE) method, Molecular Beam Epitaxy (MBE) method, and the like.
然而,磊晶晶圓中,在使III族氮化物半導體層磊晶成長於基板上時,因為基板與III族氮化物半導體層的晶格常數差及線膨脹係數差,而在III族氮化物半導體層中產生缺陷及應變。更進一步,磊晶晶圓中,在III族氮化物半導體層的應變產生於拉伸方向的情況中,具有在III族氮化物半導體層產生裂縫的可能性。 However, in the epitaxial wafer, when the group III nitride semiconductor layer is epitaxially grown on the substrate, the difference in lattice constant and the coefficient of linear expansion of the substrate and the group III nitride semiconductor layer are in the group III nitride. Defects and strains are generated in the semiconductor layer. Further, in the epitaxial wafer, in the case where the strain of the group III nitride semiconductor layer is generated in the stretching direction, there is a possibility that cracks are generated in the group III nitride semiconductor layer.
在使用III族氮化物半導體的半導體裝置中,為了提升其製造良率且提升裝置性能,必須抑制III族氮化物半導體層在成長時所產生的裂縫。至今已有很多人提出各種製造使用III族氮化物半導體的半導體裝置的方法(例如,參照日本特許公開2007-134742號公報及國際公開第2011/161975號)。以下,日本特許公開2007-134742號公報稱為文獻1,國際公開第2011/161975號稱為文獻2。 In a semiconductor device using a group III nitride semiconductor, in order to improve the manufacturing yield and improve device performance, it is necessary to suppress cracks generated when the group III nitride semiconductor layer is grown. Various methods for manufacturing a semiconductor device using a group III nitride semiconductor have been proposed so far (for example, refer to Japanese Laid-Open Patent Publication No. 2007-134742 and International Publication No. 2011/161975). Hereinafter, Japanese Patent Laid-Open Publication No. 2007-134742 is referred to as Document 1, and International Publication No. 2011/161975 is referred to as Document 2.
文獻1中記載一種氮化物半導體結構之製造方法,係在藍寶石基板的表面形成凹部之後,使III族氮化物半導體成長。該氮化物半導體結構之製造方法中,相鄰於凹部兩邊的凸部正上方,結晶成長的氮化物半導體膜於側向上成長並結合,而在凹部形成空洞部。該氮化物半導體結構之製造方法中,藉由在凹部形成空洞部,可緩和形成於藍寶石基板表面側的整個面的厚膜之III族氮化物半導體膜的應力,進而抑制在III族氮化物半導體膜中產生裂縫的情形。 Document 1 describes a method for producing a nitride semiconductor structure in which a group III nitride semiconductor is grown after forming a concave portion on the surface of a sapphire substrate. In the method for fabricating a nitride semiconductor structure, a nitride semiconductor film grown in a crystal grain is grown in the lateral direction and is bonded to the upper side of the convex portion on both sides of the concave portion, and a cavity portion is formed in the concave portion. In the method for producing a nitride semiconductor structure, by forming a cavity in the concave portion, the stress of the group III nitride semiconductor film formed on the entire surface of the surface of the sapphire substrate can be alleviated, and the III nitride semiconductor can be suppressed. A situation in which cracks are formed in the film.
然而,文獻1所記載的技術中,為了在藍寶石基板表面的凹部形成空洞部,必須使III族氮化物半導體側向成長,而具有III族氮化物半導體膜之表面整體的平坦性低落的可能性。 However, in the technique described in Document 1, in order to form a cavity in the concave portion on the surface of the sapphire substrate, it is necessary to laterally grow the group III nitride semiconductor, and the flatness of the entire surface of the group III nitride semiconductor film may be lowered. .
另外,文獻2中記載一種磊晶成長基板,係由單晶矽基板及III族氮化 物半導體所形成,並具備形成於單晶矽基板主面上的緩衝層。該磊晶成長基板的緩衝層,在單晶矽基板主面的中心部上為單晶,在單晶矽基板主面上的中心部周圍的區域為多晶。 In addition, Document 2 describes an epitaxial growth substrate which is a single crystal germanium substrate and a group III nitride. The semiconductor is formed and has a buffer layer formed on the main surface of the single crystal germanium substrate. The buffer layer of the epitaxial growth substrate is a single crystal on the central portion of the main surface of the single crystal germanium substrate, and the region around the central portion of the main surface of the single crystal germanium substrate is polycrystalline.
另外,文獻2中記載一種磊晶成長方法,係在以矽構成的單晶基板的主面上,使以與該單晶基板相異之材料所形成的III族氮化物半導體所構成的成長層進行異質磊晶成長。該磊晶成長方法,係在對單晶基板之主面的中心部進行鏡面加工,並對單晶基板之主面上的中心部周圍的區域進行粗面加工之後,使成長層磊晶成長。 Further, Document 2 describes an epitaxial growth method in which a growth layer composed of a group III nitride semiconductor formed of a material different from the single crystal substrate is formed on a main surface of a single crystal substrate made of tantalum. Perform heterogeneous epitaxial growth. In the epitaxial growth method, the center portion of the main surface of the single crystal substrate is mirror-finished, and the region around the central portion on the main surface of the single crystal substrate is subjected to rough surface processing, and then the growth layer is epitaxially grown.
接著,文獻2中所記載之主旨,係可在單晶矽基板上使III族氮化物半導體異質磊晶成長的情況中,抑制產生於晶圓端部的裂縫。 Next, in the case of the case where the group III nitride semiconductor is heteroepitaxially grown on the single crystal germanium substrate, the crack generated in the end portion of the wafer can be suppressed.
文獻2中所揭示的磊晶成長基板中,關於形成於單晶矽基板之主面的III族氮化物半導體所構成的緩衝層,藉由使單晶矽基板之主面上的中心部周圍的區域為多晶來緩和應力,而可抑制裂縫產生於單晶矽基板之主面上的中心部的單晶。 In the epitaxial growth substrate disclosed in Document 2, the buffer layer formed of the group III nitride semiconductor formed on the main surface of the single crystal germanium substrate is surrounded by the central portion on the main surface of the single crystal germanium substrate. The region is polycrystalline to alleviate the stress, and it is possible to suppress the crack from being generated in the single crystal at the central portion of the main surface of the single crystal germanium substrate.
然而,文獻2所記載的磊晶成長方法中,根據緩衝層的形成條件,中心部周圍的區域並不一定會形成多晶,而具有抑制裂縫產生的效果不充分的可能。 However, in the epitaxial growth method described in Document 2, depending on the formation conditions of the buffer layer, the region around the center portion does not necessarily form polycrystals, and the effect of suppressing the occurrence of cracks may be insufficient.
於是,本發明之目的係提供一種磊晶晶圓及其製造方法,該磊晶晶圓中,可謀求III族氮化物半導體層之中央部表面之平坦性的提升,且可抑制裂縫的產生。 Accordingly, an object of the present invention is to provide an epitaxial wafer and a method of manufacturing the same, which can improve the flatness of the surface of the central portion of the group III nitride semiconductor layer and suppress the occurrence of cracks.
本發明之磊晶晶圓,具備晶圓及形成於該晶圓之一表面側的整個面上的單晶III族氮化物半導體層。該III族氮化物半導體層,具有外周部及中 央部;該外周部形成於該晶圓之周邊部所構成的除外區域,該中央部形成於比該晶圓的該除外區域更內側之應用區域。該外周部具有下述特徵:與該中央部相比,包含較多空隙或是以晶圓之該一表面側作為起點的突起。本發明之磊晶晶圓因此具有下述效果:可謀求III族氮化物半導體層之中央部表面之平坦性的提升,且可抑制在III族氮化物半導體層之成長時所產生的裂縫。 The epitaxial wafer of the present invention includes a wafer and a single crystal group III nitride semiconductor layer formed on the entire surface side of one surface of the wafer. The group III nitride semiconductor layer has a peripheral portion and a middle portion a central portion; the outer peripheral portion is formed in an exclusion region formed by a peripheral portion of the wafer, and the central portion is formed in an application region further inside the exclusion region of the wafer. The outer peripheral portion has a feature that includes a larger number of voids or a projection having the one surface side of the wafer as a starting point as compared with the central portion. The epitaxial wafer of the present invention has an effect of improving the flatness of the surface of the central portion of the group III nitride semiconductor layer and suppressing cracks generated when the group III nitride semiconductor layer is grown.
該磊晶晶圓中,該晶圓宜為藍寶石晶圓,而該III族氮化物半導體層宜為氮化鋁層。 In the epitaxial wafer, the wafer is preferably a sapphire wafer, and the group III nitride semiconductor layer is preferably an aluminum nitride layer.
本發明之磊晶晶圓的製造方法,係具備晶圓及形成於該晶圓之一表面側的整個面之單晶的III族氮化物半導體層的磊晶晶圓之製造方法。磊晶晶圓之製造方法中,在使該III族氮化物半導體層成長於該晶圓的該一表面側時,該III族氮化物半導體層具有外周部及中央部;該外周部形成於該晶圓之周邊部所構成的除外區域,該中央部形成於比該晶圓之該除外區域更內側的應用區域。磊晶晶圓之製造方法的特徵,係以使相較於該中央部,該外周部包含較多空隙或是以該晶圓之該一表面側作為起點而成長的突起的方法,使該III族氮化物半導體層成長。藉此,本發明之磊晶晶圓之製造方法可具有下述效果:可提供一種磊晶晶圓,其可謀求III族氮化物半導體層的中央部表面之平坦性的提升,且抑制III族氮化物半導體層在成長時所產生的裂縫。 The method for producing an epitaxial wafer according to the present invention is a method for producing an epitaxial wafer having a wafer and a single-crystal group III nitride semiconductor layer formed on the entire surface side of the wafer. In the method of manufacturing an epitaxial wafer, when the group III nitride semiconductor layer is grown on the one surface side of the wafer, the group III nitride semiconductor layer has an outer peripheral portion and a central portion; the outer peripheral portion is formed in the The exclusion region formed by the peripheral portion of the wafer is formed in an application region that is further inside than the exclusion region of the wafer. The method of manufacturing an epitaxial wafer is characterized in that the outer peripheral portion includes a plurality of voids or a protrusion that grows on the one surface side of the wafer as a starting point, and the III is made. The group nitride semiconductor layer grows. Thereby, the method for manufacturing an epitaxial wafer of the present invention can have the effect of providing an epitaxial wafer which can improve the flatness of the central portion surface of the group III nitride semiconductor layer and suppress the group III A crack generated when a nitride semiconductor layer grows.
該磊晶晶圓之製造方法中,在使該III族氮化物半導體層成長之前,宜在該晶圓之該除外區域中,於該晶圓的另一表面側形成凹部。 In the method of manufacturing an epitaxial wafer, before the growth of the group III nitride semiconductor layer, it is preferable to form a concave portion on the other surface side of the wafer in the exclusion region of the wafer.
該磊晶晶圓之製造方法中,在該III族氮化物半導體層成長之前,宜在該晶圓之該除外區域中該晶圓的另一表面側,形成越靠近該晶圓的邊緣,該除外區域之厚度尺寸越小的推拔面。 In the method for manufacturing the epitaxial wafer, before the growth of the group III nitride semiconductor layer, it is preferable that the other surface side of the wafer in the exclusion region of the wafer is formed closer to the edge of the wafer. The smaller the thickness of the exclusion zone, the smaller the push surface.
該磊晶晶圓之製造方法中,在該III族氮化物半導體層成長之前,宜在 該晶圓之該除外區域中的該晶圓之該一表面側進行改質處理。 In the method for manufacturing the epitaxial wafer, before the growth of the group III nitride semiconductor layer, The one surface side of the wafer in the exclusion region of the wafer is subjected to a modification process.
該磊晶晶圓之製造方法中,該處理宜為氧化處理。 In the method of manufacturing the epitaxial wafer, the treatment is preferably an oxidation treatment.
該磊晶晶圓之製造方法中,該處理宜為氮化處理。 In the method of manufacturing the epitaxial wafer, the treatment is preferably a nitriding treatment.
該磊晶晶圓之製造方法中,該晶圓宜為藍寶石晶圓,該III族氮化物半導體層宜為氮化鋁層。 In the method for manufacturing the epitaxial wafer, the wafer is preferably a sapphire wafer, and the group III nitride semiconductor layer is preferably an aluminum nitride layer.
1、101‧‧‧磊晶晶圓 1, 101‧‧‧ epitaxial wafer
10‧‧‧晶圓 10‧‧‧ wafer
10aa、10ab、30aa‧‧‧表面 10aa, 10ab, 30aa‧‧‧ surface
10a‧‧‧支持基板 10a‧‧‧Support substrate
11‧‧‧應用區域 11‧‧‧Application area
12‧‧‧除外區域 12‧‧‧Excluded areas
13‧‧‧凹部 13‧‧‧ recess
14‧‧‧推拔面 14‧‧‧ pushed face
15‧‧‧改質層 15‧‧‧Modified layer
20、20a‧‧‧III族氮化物半導體層 20, 20a‧‧‧III nitride semiconductor layer
21‧‧‧中央部 21‧‧‧Central Department
22‧‧‧外周部 22‧‧‧The outer part
23、123‧‧‧裂縫 23, 123‧‧‧ crack
24‧‧‧突起 24‧‧‧ Protrusion
3‧‧‧紫外光半導體發光元件 3‧‧‧Ultraviolet semiconductor light-emitting elements
30a‧‧‧第1氮化物半導體層 30a‧‧‧1st nitride semiconductor layer
40a‧‧‧活性層 40a‧‧‧active layer
50a‧‧‧電子區塊層 50a‧‧‧Electronic block layer
60a‧‧‧第2氮化物半導體層 60a‧‧‧2nd nitride semiconductor layer
70a‧‧‧p形接觸層 70a‧‧‧p-shaped contact layer
80a‧‧‧第1電極 80a‧‧‧1st electrode
90a‧‧‧第2電極 90a‧‧‧2nd electrode
110‧‧‧藍寶石晶圓 110‧‧‧Sapphire wafer
120‧‧‧氮化鋁層 120‧‧‧Aluminum nitride layer
以下更詳細說明本發明之較佳實施態樣。藉由以下詳述及添附圖式,能更清楚理解本發明之其他特徵及優點。 Preferred embodiments of the invention are described in more detail below. Other features and advantages of the present invention will be apparent from the description and appended claims.
【圖1】圖1A係實施態樣之磊晶晶圓的基本構成之示意俯視圖,圖1B係該基本構成的示意剖面圖。 Fig. 1A is a schematic plan view showing a basic configuration of an epitaxial wafer according to an embodiment, and Fig. 1B is a schematic cross-sectional view showing the basic configuration.
【圖2】圖2係實施態樣之磊晶晶圓的示意剖面圖。 Fig. 2 is a schematic cross-sectional view showing an epitaxial wafer of an embodiment.
【圖3】圖3係實施態樣之磊晶晶圓的另一構成例之示意剖面圖。 Fig. 3 is a schematic cross-sectional view showing another configuration example of an epitaxial wafer of an embodiment.
【圖4】圖4係實施態樣之磊晶晶圓的其他構成例的示意剖面圖。 Fig. 4 is a schematic cross-sectional view showing another configuration example of an epitaxial wafer of an embodiment.
【圖5】圖5係比較例1之磊晶晶圓的示意俯視圖。 Fig. 5 is a schematic plan view showing an epitaxial wafer of Comparative Example 1.
【圖6】圖6係實施態樣中的紫外發光二極體之概略剖面。 Fig. 6 is a schematic cross-sectional view showing an ultraviolet light emitting diode in an embodiment.
【圖7】圖7係實施例3之磊晶晶圓中的III族氮化物半導體層之外周部的俯視SEM影像。 Fig. 7 is a plan view SEM image of the outer peripheral portion of the group III nitride semiconductor layer in the epitaxial wafer of the third embodiment.
【圖8】圖8係實施例4之磊晶晶圓中的III族氮化物半導體層之外周部的剖面SEM影像。 Fig. 8 is a cross-sectional SEM image of the outer peripheral portion of the group III nitride semiconductor layer in the epitaxial wafer of the fourth embodiment.
以下,就本實施態樣之磊晶晶圓1,根據圖1AA至圖4進行說明。 Hereinafter, the epitaxial wafer 1 of the present embodiment will be described with reference to FIGS. 1AA to 4.
磊晶晶圓1包含:晶圓10,具有一表面10aa與另一表面10ab;及單晶III族氮化物半導體層20,形成於晶圓10之一表面10aa側的整個面。III族氮化物半導體層20包含:外周部22,形成於晶圓10之周邊部所構成的除外區域12;及中央部21,形成於比晶圓10的除外區域12更內側的應用區域11。晶圓10的應用區域11,係晶圓10之除外區域12以外的區域。 The epitaxial wafer 1 includes a wafer 10 having a surface 10aa and another surface 10ab, and a single crystal III-nitride semiconductor layer 20 formed on the entire surface of one surface 10aa of the wafer 10. The group III nitride semiconductor layer 20 includes an outer peripheral portion 22, an exclusion region 12 formed on a peripheral portion of the wafer 10, and a central portion 21 formed in an application region 11 that is inside the exclusion region 12 of the wafer 10. The application area 11 of the wafer 10 is an area other than the exclusion area 12 of the wafer 10.
外周部22,相較於中央部21,包含較多空隙或是以晶圓10的一表面10aa側作為起點的突起。接著,中央部21,其結晶性高於外周部22。結晶性高,係指X光搖擺曲線(其為結晶性評價之一例)的半值寬較窄。本實施態樣之磊晶晶圓1中,外周部22,相較於中央部21,包含較多空隙或是突起,該突起係以為一表面10aa作為起點,而該一表面10aa係晶圓10與III族氮化物半導體層20的界面。 The outer peripheral portion 22 includes a plurality of voids or a projection having a surface 10aa side of the wafer 10 as a starting point as compared with the central portion 21. Next, the central portion 21 has higher crystallinity than the outer peripheral portion 22. The high crystallinity means that the X-ray rocking curve (which is an example of crystallinity evaluation) has a narrow half-value width. In the epitaxial wafer 1 of the present embodiment, the outer peripheral portion 22 includes a plurality of voids or protrusions compared to the central portion 21, and the protrusions are a surface 10aa as a starting point, and the surface 10aa is a wafer 10 Interface with the group III nitride semiconductor layer 20.
晶圓10的除外區域12,如圖2所示,可作為在晶圓10的另一表面10ab側中凹部13形成的區域。凹部13,係沿著成為晶圓10之外周緣的邊緣形成。凹部13,宜在晶圓10的另一表面10ab側,形成於晶圓10的整個圓周上。 The exclusion region 12 of the wafer 10, as shown in FIG. 2, can serve as a region where the concave portion 13 is formed on the other surface 10ab side of the wafer 10. The recess 13 is formed along the edge which becomes the outer periphery of the wafer 10. The recess 13 is preferably formed on the entire circumference of the wafer 10 on the other surface 10ab side of the wafer 10.
另外,晶圓10的除外區域12,如圖3所示,可為晶圓10的另一表面10ab側中形成推拔面14的區域。推拔面14,係沿著晶圓10的邊緣形成。推拔面14,宜以使晶圓10的厚度隨著靠近晶圓10的邊緣逐漸變薄的方式形成。推拔面14,宜形成於晶圓10之另一表面10ab側之晶圓10的整個圓周上。又,晶圓10,在將矽晶圓用於晶圓10的情況中,可將品質保證區(FQA;Fixed Quality Area)作為應用區域11,並可將邊緣除外區域(edge exclusion)作為除外區域12。 Further, as shown in FIG. 3, the exclusion region 12 of the wafer 10 may be a region in which the push surface 14 is formed on the other surface 10ab side of the wafer 10. The push-out face 14 is formed along the edge of the wafer 10. The push surface 14 is preferably formed such that the thickness of the wafer 10 becomes thinner as it approaches the edge of the wafer 10. The push-out surface 14 is preferably formed on the entire circumference of the wafer 10 on the other surface 10ab side of the wafer 10. Moreover, in the case where the wafer 10 is used for the wafer 10, a quality assurance area (FQA) can be used as the application area 11, and edge exclusion can be used as an exclusion area. 12.
另外,晶圓10的除外區域12,如圖4所示,可為晶圓10的一表面10aa側形成改質層15的區域。改質層15,宜在晶圓10的一表面10aa側,形成於晶圓10的整個圓周上。 Further, as shown in FIG. 4, the exclusion region 12 of the wafer 10 may be a region where the reforming layer 15 is formed on one surface 10aa side of the wafer 10. The reforming layer 15 is preferably formed on the entire circumference of the wafer 10 on one surface 10aa side of the wafer 10.
晶圓10,可使用圓板狀的單晶基板。晶圓10宜為定向平面(OF)。晶圓10的厚度,宜為例如,數100μm~數mm,較宜為200μm~1mm。晶圓10的直徑,宜為例如,50.8mm~300mm。晶圓10中,並未限定晶圓10的厚度及直徑。 As the wafer 10, a disk-shaped single crystal substrate can be used. Wafer 10 is preferably an oriented plane (OF). The thickness of the wafer 10 is preferably, for example, several hundred μm to several mm, and more preferably 200 μm to 1 mm. The diameter of the wafer 10 is preferably, for example, 50.8 mm to 300 mm. In the wafer 10, the thickness and diameter of the wafer 10 are not limited.
除外區域12,在晶圓10的俯視下,宜為從晶圓10之邊緣的外周線往內側2mm~5mm左右的部分。 The exclusion region 12 is preferably a portion from the outer circumference of the edge of the wafer 10 to the inner side of about 2 mm to 5 mm in a plan view of the wafer 10.
晶圓10的材料中,磊晶成長於該晶圓10的一表面10aa側的III族氮化物半導體層20的組成及結構,宜對應III族氮化物半導體層20上所形成的層等,進行適當選擇。簡而言之,晶圓10,可與使用磊晶晶圓1而製造的半導體裝置之種類等對應,而進行適當選擇。因此,作為晶圓10的材料,可使用例如,氧化物、IV族半導體、IV-IV族化合物半導體、III-V族化合物半導體等。晶圓10的材料中,作為氧化物,可使用例如,藍寶石、ZnO、MgO、MgAl2O4等。晶圓10的材料中,作為IV族半導體,可使用例如,Si、Ge等。晶圓10的材料中,作為IV-IV族化合物半導體,可使用例如,SiC、SiGe等。晶圓10的材料中,作為III-V族化合物半導體,可使用例如,GaN、AlN等。 In the material of the wafer 10, the composition and structure of the group III nitride semiconductor layer 20 which is epitaxially grown on one surface 10aa side of the wafer 10 is preferably made to correspond to a layer formed on the group III nitride semiconductor layer 20, and the like. Appropriate choice. In short, the wafer 10 can be appropriately selected in accordance with the type of the semiconductor device manufactured using the epitaxial wafer 1 or the like. Therefore, as the material of the wafer 10, for example, an oxide, a group IV semiconductor, a group IV-IV compound semiconductor, a group III-V compound semiconductor, or the like can be used. Among the materials of the wafer 10, for example, sapphire, ZnO, MgO, MgAl 2 O 4 or the like can be used as the oxide. Among the materials of the wafer 10, as the group IV semiconductor, for example, Si, Ge, or the like can be used. Among the materials of the wafer 10, as the group IV-IV compound semiconductor, for example, SiC, SiGe, or the like can be used. Among the materials of the wafer 10, as the group III-V compound semiconductor, for example, GaN, AlN, or the like can be used.
磊晶晶圓1,可用於使用III族氮化物半導體的半導體裝置之製造。磊晶晶圓1中,根據應用區域11的平面尺寸及半導體裝置的晶片尺寸,可製造複數半導體裝置。其中,本實施態樣之磊晶晶圓1中,可提升形成於磊晶晶圓1之上的III族氮化物半導體結晶的結晶性。作為半導體裝置,可舉例如,以發光二極體為代表的發光裝置,及高電子移動率電晶體等。作為發光二極體,具有作為紫外光半導體發光元件之一的紫外發光二極體等。紫外發光二極體,可以例如形成發光波長為200~360nm的紫外波長區域的方式,適當地構成。 The epitaxial wafer 1 can be used for the fabrication of a semiconductor device using a group III nitride semiconductor. In the epitaxial wafer 1, a plurality of semiconductor devices can be manufactured according to the planar size of the application region 11 and the wafer size of the semiconductor device. In the epitaxial wafer 1 of the present embodiment, the crystallinity of the group III nitride semiconductor crystal formed on the epitaxial wafer 1 can be improved. As the semiconductor device, for example, a light-emitting device typified by a light-emitting diode, a high electron mobility transistor, and the like can be given. As the light-emitting diode, there is an ultraviolet light-emitting diode or the like which is one of ultraviolet light-emitting semiconductor light-emitting elements. The ultraviolet light emitting diode can be suitably formed, for example, in such a manner as to form an ultraviolet wavelength region having an emission wavelength of 200 to 360 nm.
在使用磊晶晶圓1所製造的半導體裝置為紫外光半導體發光元件的情況中,宜使用例如藍寶石晶圓作為晶圓10。晶圓10,宜依據例如,符合日 本電子工業振興協會(JEIDA),及國際半導體製造裝置材料協會(SEMI;Semicondutor Equipment and Materials International)等規格。藍寶石晶圓,例如,宜依據下述規格:符合以SEMI M65-0306規格化的化合物半導體磊晶晶圓所使用的藍寶石基板之規格。另外,在將藍寶石晶圓使用為晶圓10的情況中,可將例如c面、m面、a面、R面等作為一表面10aa使用。藍寶石晶圓,宜使為c面的(0001)面作為晶圓10的一表面10aa側。另外,藍寶石晶圓中,來自(0001)面的傾斜角宜為0~0.3°。 In the case where the semiconductor device manufactured using the epitaxial wafer 1 is an ultraviolet semiconductor light-emitting device, for example, a sapphire wafer is preferably used as the wafer 10. Wafer 10, preferably based on, for example, The Electronics Industry Promotion Association (JEIDA), and the International Semiconductor Manufacturing Equipment Materials Association (SEMI; Semicondutor Equipment and Materials International) and other specifications. The sapphire wafer, for example, should be based on the following specifications: The specifications of the sapphire substrate used in the compound semiconductor epitaxial wafer standardized by SEMI M65-0306. Further, in the case where the sapphire wafer is used as the wafer 10, for example, a c-plane, an m-plane, an a-plane, an R-plane, etc. can be used as one surface 10aa. The sapphire wafer should preferably have a (0001) plane on the c-plane as a surface 10aa side of the wafer 10. Further, in the sapphire wafer, the inclination angle from the (0001) plane is preferably 0 to 0.3.
III族氮化物半導體層20的材料,可以例如,BxAlyGazIn1-x-y-zN(0≦x、0≦y、0≦z、x+y+z≦1)的組成表示。III族氮化物半導體層20,亦可存在於該III族氮化物半導體層20形成時,不可避免地混入的H、C、O、Si、Fe等雜質。另外,III族氮化物半導體層20,亦可含有為了控制導電性而蓄意導入的Si、Ge、Be、Mg、Zn、C等雜質。 The material of the group III nitride semiconductor layer 20 can be expressed, for example, as a composition of B x Al y Ga z In 1-xyz N (0≦x, 0≦y, 0≦z, x+y+z≦1). The group III nitride semiconductor layer 20 may be present in an impurity such as H, C, O, Si, or Fe which is inevitably mixed when the group III nitride semiconductor layer 20 is formed. Further, the group III nitride semiconductor layer 20 may contain impurities such as Si, Ge, Be, Mg, Zn, and C which are intentionally introduced to control conductivity.
將以一表面10aa為(0001)面的藍寶石晶圓作為晶圓10使用的情況中,從抑制裂縫23產生於該III族氮化物半導體層20的觀點來看,III族氮化物半導體層20的材料,宜為藍寶石晶圓與III族氮化物半導體層20之表面晶格常數的差值較小的材料。因此,例如在半導體裝置為紫外光半導體發光元件的情況中,III族氮化物半導體層20的材料中,Al的組成比較高者為較佳,而從高溫下之結晶結構的穩定性及對於紫外光之穿透率的觀點來看,AlN最為合適。 In the case where a sapphire wafer having a surface 10aa (0001) plane is used as the wafer 10, the group III nitride semiconductor layer 20 is formed from the viewpoint that the crack 23 is generated in the group III nitride semiconductor layer 20. The material is preferably a material having a small difference in surface lattice constant between the sapphire wafer and the group III nitride semiconductor layer 20. Therefore, for example, in the case where the semiconductor device is an ultraviolet semiconductor light-emitting element, among the materials of the group III nitride semiconductor layer 20, the composition of Al is relatively high, and the stability of the crystal structure from a high temperature and the ultraviolet From the standpoint of light transmittance, AlN is most suitable.
另外,在半導體裝置為紫外光半導體發光元件的情況中,適合使用c面藍寶石基板作為相對發光波長為透明的支持基板。而在半導體裝置為紫外光半導體發光元件的情況中,適合使用AlN作為III族氮化物半導體層20的材料。 Further, in the case where the semiconductor device is an ultraviolet semiconductor light-emitting device, a c-plane sapphire substrate is suitably used as a support substrate having a transparent light-emitting wavelength. On the other hand, in the case where the semiconductor device is an ultraviolet semiconductor light-emitting element, AlN is suitably used as the material of the group III nitride semiconductor layer 20.
因此,磊晶晶圓1,在於晶圓10上製造複數紫外光半導體發光元件的情況中,宜使用藍寶石晶圓作為晶圓10,而宜使用氮化鋁層(AlN層)作為III族氮化物半導體層20。 Therefore, in the case of the epitaxial wafer 1 in which a plurality of ultraviolet semiconductor light-emitting elements are fabricated on the wafer 10, a sapphire wafer is preferably used as the wafer 10, and an aluminum nitride layer (AlN layer) is preferably used as the group III nitride. Semiconductor layer 20.
作為III族氮化物半導體層20的磊晶成長法,可使用例如,有機金屬氣相磊晶(MOVPE;Metal Organic Vapor Phase Epitaxy)法、分子束磊晶(MBE;Molecular Beam Epitaxy)法、氫化物氣相磊晶(HVPE;Hydride Vapor Phase Epitaxy)法、濺鍍法等。有機金屬氣相磊晶法,可使用例如:同時供給III族原料與V族原料以使III族氮化物半導體結晶成長的成長方法,或是使III族原料與V族原料的供給時機交錯以使III族氮化物半導體結晶成長的成長方法。以下,將同時供給III族原料與V族原料以使III族氮化物半導體結晶成長的成長方法,稱為同時供給成長法。另外,將III族原料與V族原料的供給時機交錯以使III族氮化物半導體結晶成長的成長方法,稱為交互供給成長法。而關於分子束磊晶法,可使用與有機金屬氣相磊晶法相同的同時供給成長法及交互供給成長法。有機金屬氣相磊晶法與分子束磊晶法中,可精準地控制薄膜的膜厚,且能夠進行高品質的結晶成長。另一方面,氫化物氣相磊晶法中,因為可大量供給原料,故適用於在短時間內成長為厚膜的情況。III族氮化物半導體層20的製作中,可將該等方法組合。例如,有機金屬氣相磊晶法中,藉由將同時供給成長法與交互供給成長法時序性地組合,可提升結晶性。另外,有機金屬氣相磊晶法中,可使用連續供給III族原料且間歇性供給V族原料以進行成長的成長方法,亦可將同時供給成長法與脈衝供給成長法時序性組合。以下,將連續供給III族原料且間歇性地供給V族原料以進行成長的成長方法稱作脈衝供給成長法。 As the epitaxial growth method of the group III nitride semiconductor layer 20, for example, a metal organic vapor phase epitaxy (MOVPE) method, a molecular beam epitaxy (MBE) method, or a hydride can be used. HVPE (Hydride Vapor Phase Epitaxy) method, sputtering method, and the like. In the organometallic vapor phase epitaxy method, for example, a growth method in which a group III raw material and a group V raw material are simultaneously supplied to crystallize a group III nitride semiconductor can be used, or a supply timing of a group III raw material and a group V raw material can be interleaved so that A method of growing a group III nitride semiconductor crystal. Hereinafter, a growth method in which a group III raw material and a group V raw material are simultaneously supplied to grow a group III nitride semiconductor crystal is referred to as a simultaneous supply growth method. Further, a method of growing a group III raw material and a supply timing of a group V raw material to grow a group III nitride semiconductor crystal is called an alternate supply growth method. As for the molecular beam epitaxy method, the same simultaneous supply growth method and interactive supply growth method as the organometallic vapor phase epitaxy method can be used. In the organometallic vapor phase epitaxy method and the molecular beam epitaxy method, the film thickness of the film can be precisely controlled, and high-quality crystal growth can be performed. On the other hand, in the hydride vapor phase epitaxy method, since a large amount of raw material can be supplied, it is suitable for the case where it grows into a thick film in a short time. In the production of the group III nitride semiconductor layer 20, these methods can be combined. For example, in the organometallic vapor phase epitaxy method, crystallinity can be improved by sequentially combining the simultaneous supply growth method and the interactive supply growth method. Further, in the organometallic vapor phase epitaxy method, a growth method in which a group III raw material is continuously supplied and a group V raw material is intermittently supplied for growth can be used, and the simultaneous supply growth method and the pulse supply growth method can be combined in a time series. Hereinafter, a method of continuously supplying a group III raw material and intermittently supplying a group V raw material to grow is referred to as a pulse supply growth method.
表示III族原料與V族原料之莫耳比的V/III比,在同時供給成長法、交互供給成長法、脈衝供給成長法的任一情況中,皆宜為1以上5000以下。基板溫度、V/III比、III族原料之供給量及成長壓力等雖被認為是影響III族氮化物半導體層20之結晶性的參數,但基板溫度被認為是最根本的參數。 The V/III ratio indicating the molar ratio of the group III raw material to the group V raw material is preferably 1 or more and 5000 or less in any of the simultaneous supply growth method, the interactive supply growth method, and the pulse supply growth method. The substrate temperature, the V/III ratio, the supply amount of the group III raw material, the growth pressure, and the like are considered to be parameters affecting the crystallinity of the group III nitride semiconductor layer 20, but the substrate temperature is considered to be the most fundamental parameter.
另外,本案發明人製作如圖5所示的比較例1之磊晶晶圓101,以作為用以實現紫外光半導體發光元件,特別是高效率的深紫外發光元件之研究的一環。磊晶晶圓101,係在藍寶石晶圓110上使單晶氮化鋁層120磊晶成長。接著,本案發明人,對於該磊晶晶圓101,以光學顯微鏡對氮化鋁層 120表面進行評價。 Further, the inventors of the present invention produced the epitaxial wafer 101 of Comparative Example 1 as shown in FIG. 5 as a part for realizing research on ultraviolet light semiconductor light-emitting elements, particularly high-efficiency deep ultraviolet light-emitting elements. The epitaxial wafer 101 is epitaxially grown on the sapphire wafer 110 by the single crystal aluminum nitride layer 120. Next, the inventor of the present invention, for the epitaxial wafer 101, an aluminum nitride layer by an optical microscope 120 surface was evaluated.
結果,在氮化鋁層120中,觀察到如圖5所示的示意圖中,從氮化鋁層120之外周部往中心部延伸的大量裂縫123。接著,本案發明人發現,在這種磊晶晶圓101上形成的紫外發光二極體中,光輸出率低且良率亦低。另外,本案發明人確認,在氮化鋁層120包含產生裂縫123之處的情況下所形成的紫外發光二極體,其漏電流較大,且元件特性及可靠度拙劣。 As a result, in the aluminum nitride layer 120, a large number of cracks 123 extending from the outer peripheral portion of the aluminum nitride layer 120 toward the center portion were observed in the schematic view shown in FIG. Next, the inventors of the present invention found that the ultraviolet light-emitting diode formed on the epitaxial wafer 101 has a low light output rate and a low yield. Further, the inventors of the present invention confirmed that the ultraviolet light-emitting diode formed in the case where the aluminum nitride layer 120 contains the crack 123 has a large leakage current and is inferior in element characteristics and reliability.
相對於此,本實施態樣之磊晶晶圓1中,可抑制裂縫23產生於III族氮化物半導體層20之外周部22及中央部21。亦即,磊晶晶圓1中,外周部22,相較於中央部21,包含較多空隙或是以晶圓10的一表面10aa側作為起點的突起,藉此,如圖1A之示意圖所示,可抑制裂縫23產生於外周部22。另外,磊晶晶圓1中,藉由抑制裂縫23產生於外周部22,可降低從外周部22往中央部21延伸的裂縫23。因此,在磊晶晶圓1中,可抑制裂縫23產生於III族氮化物半導體層20。作為抑制裂縫23產生的理由,推論係因為在III族氮化物半導體層20成長時,藉由在外周部22形成空隙或是突起,緩和外周部22的應力,進而抑制裂縫23的產生。更進一步推論,在磊晶晶圓1中,藉由空隙或是突起,可直接阻斷裂縫23往中央部21延伸。磊晶晶圓1,即使是在以一表面10aa為(0001)面的藍寶石晶圓作為晶圓10,且以III族氮化物半導體層20作為氮化鋁層的情況中,亦可抑制裂縫23產生於III族氮化物半導體層20。 On the other hand, in the epitaxial wafer 1 of the present embodiment, the crack 23 can be prevented from being generated in the outer peripheral portion 22 and the central portion 21 of the group III nitride semiconductor layer 20. That is, in the epitaxial wafer 1, the outer peripheral portion 22 includes a plurality of voids or a projection starting from the one surface 10aa side of the wafer 10 as compared with the central portion 21, whereby the schematic view of FIG. 1A is used. It is shown that the crack 23 can be suppressed from being generated in the outer peripheral portion 22. Further, in the epitaxial wafer 1, since the crack 23 is generated in the outer peripheral portion 22, the crack 23 extending from the outer peripheral portion 22 toward the central portion 21 can be reduced. Therefore, in the epitaxial wafer 1, the occurrence of the crack 23 in the group III nitride semiconductor layer 20 can be suppressed. As a reason for suppressing the occurrence of the cracks 23, it is inferred that when the group III nitride semiconductor layer 20 is grown, voids or protrusions are formed in the outer peripheral portion 22, and the stress of the outer peripheral portion 22 is alleviated, thereby suppressing the occurrence of the cracks 23. It is further inferred that in the epitaxial wafer 1, the crack 23 can be directly blocked from extending toward the central portion 21 by voids or protrusions. The epitaxial wafer 1 can suppress the crack 23 even in the case where the sapphire wafer having the (0001) surface of the surface 10aa is the wafer 10 and the group III nitride semiconductor layer 20 is used as the aluminum nitride layer. It is produced in the group III nitride semiconductor layer 20.
另外,相較於以文獻1之氮化物半導體結構之製造方法所形成者,本發名之磊晶晶圓1可謀求III族氮化物半導體層20的中央部21表面之平坦性的提升。關於III族氮化物半導體層20表面的平坦性,係以光學顯微鏡及掃描式電子顯微鏡(SEM;Scanning Electron Microscope)進行評價。 Further, the epitaxial wafer 1 of the present invention can improve the flatness of the surface of the central portion 21 of the group III nitride semiconductor layer 20 as compared with the method for fabricating the nitride semiconductor structure of Document 1. The flatness of the surface of the group III nitride semiconductor layer 20 was evaluated by an optical microscope and a scanning electron microscope (SEM; Scanning Electron Microscope).
接著,進一步說明上述之磊晶晶圓1的製造方法。 Next, a method of manufacturing the epitaxial wafer 1 described above will be further described.
磊晶晶圓1之製造方法中,在III族氮化物半導體層20於晶圓10的一 表面10aa側成長時,III族氮化物半導體層20具有外周部22、中央部21,以相較於中央部21,使外周部22包含較多空隙或是以晶圓10的一表面10aa側與III族氮化物半導體層20之界面為起點的突起的方式,使III族氮化物半導體層20成長。 In the manufacturing method of the epitaxial wafer 1 , one of the group III nitride semiconductor layer 20 is on the wafer 10 When the surface 10aa side is grown, the group III nitride semiconductor layer 20 has the outer peripheral portion 22 and the central portion 21, so that the outer peripheral portion 22 includes a larger number of voids or the surface 10aa side of the wafer 10 than the central portion 21. The group III nitride semiconductor layer 20 is grown in such a manner that the interface of the group III nitride semiconductor layer 20 is a protrusion at the starting point.
以這種方式使III族氮化物半導體層20成長,只要在III族氮化物半導體層20成長之前,對晶圓10進行適當處理即可。在磊晶晶圓1之製造方法中,在III族氮化物半導體層20成長之前,對晶圓10之除外區域12進行適當處理。磊晶晶圓1之製造方法中,藉由對晶圓10的除外區域12進行適當處理,可使III族氮化物半導體層20的實際成長條件,在晶圓10之除外區域12中不同於晶圓10之應用區域11。藉此,在磊晶晶圓1之製造方法中,即使III族氮化物半導體層20之中央部21及外周部22皆為單晶,亦可使III族氮化物半導體層20的結晶性,在中央部21與外周部22不同。此處,磊晶晶圓1之製造方法中,宜使III族氮化物半導體層20之中央部21的結晶性高於外周部22的結晶性,故宜考慮中央部21的結晶性,來決定III族氮化物半導體層20的成長條件,。 The III-nitride semiconductor layer 20 is grown in this manner, and the wafer 10 may be appropriately processed before the III-nitride semiconductor layer 20 is grown. In the method of manufacturing the epitaxial wafer 1, the exclusion region 12 of the wafer 10 is appropriately processed before the growth of the group III nitride semiconductor layer 20. In the method of manufacturing the epitaxial wafer 1, the actual growth conditions of the group III nitride semiconductor layer 20 can be made different from the crystal in the exclusion region 12 of the wafer 10 by appropriately treating the exclusion region 12 of the wafer 10. Application area 11 of circle 10. Therefore, in the method of manufacturing the epitaxial wafer 1, even if the central portion 21 and the outer peripheral portion 22 of the group III nitride semiconductor layer 20 are single crystals, the crystallinity of the group III nitride semiconductor layer 20 can be made. The central portion 21 is different from the outer peripheral portion 22. Here, in the method of manufacturing the epitaxial wafer 1, it is preferable that the crystallinity of the central portion 21 of the group III nitride semiconductor layer 20 is higher than the crystallinity of the outer peripheral portion 22. Therefore, it is preferable to consider the crystallinity of the central portion 21. The growth conditions of the group III nitride semiconductor layer 20 are as follows.
磊晶晶圓1之製造方法中,以使III族氮化物半導體層20的外周部22,相較於中央部21,包含較多空隙或是以晶圓10的一表面10aa為起點而成長之突起的方式,使III族氮化物半導體層20成長。藉此,在磊晶晶圓1之製造方法中,可緩和施加於III族氮化物半導體層20之外周部22的應力,而能夠有效率地抑制裂縫23的產生。另外,在磊晶晶圓1之製造方法中,在III族氮化物半導體層20成長時,可以外周部22的空隙或突起來防止於外周部22產生的裂縫23往中央部21延伸。 In the method of manufacturing the epitaxial wafer 1, the outer peripheral portion 22 of the group III nitride semiconductor layer 20 is formed to have a larger number of voids than the central portion 21 or to grow from the surface 10aa of the wafer 10. The group III nitride semiconductor layer 20 is grown in a manner of protrusions. Thereby, in the method of manufacturing the epitaxial wafer 1, the stress applied to the outer peripheral portion 22 of the group III nitride semiconductor layer 20 can be alleviated, and the occurrence of the crack 23 can be effectively suppressed. Further, in the method of manufacturing the epitaxial wafer 1, when the group III nitride semiconductor layer 20 is grown, the cracks 23 at the outer peripheral portion 22 can be prevented from extending toward the central portion 21 by the voids or protrusions of the outer peripheral portion 22.
磊晶晶圓1之製造方法中,因為III族氮化物半導體層20中產生空隙,故縱向上的成長速率提升。此處,縱向上的成長速率,係晶圓10之厚度方向上的成長速率。 In the method of manufacturing the epitaxial wafer 1, since the voids are formed in the group III nitride semiconductor layer 20, the growth rate in the vertical direction is increased. Here, the growth rate in the longitudinal direction is the growth rate in the thickness direction of the wafer 10.
本案發明人詳細研究的結果,得到下述實驗結果:作為提升縱向上的 成長速率而成長的方法,相較於被認為最適合用以使結晶性高的單晶成長的最佳成長條件,降低成長溫度、提高表示V族原料與III族原料之供給比的V/III比,對於提高成長速率而言為較佳。 The results of the detailed study by the inventor of the present invention gave the following experimental results: as an elevation in the vertical direction The method of growing at a growth rate is lower than the optimum growth conditions for growing a single crystal having high crystallinity, lowering the growth temperature, and increasing the V/III ratio indicating the supply ratio of the group V raw material to the group III raw material. It is better for increasing the growth rate.
於是,本案發明人認為,即使是以最佳成長條件,使III族氮化物半導體層20成長的情況,亦以使晶圓10之除外區域12上的縱向成長速率,高於應用區域11上之縱向成長速率的方式,對晶圓10之除外區域12進行適當處理。 Therefore, the inventors of the present invention considered that even if the group III nitride semiconductor layer 20 is grown under the optimum growth conditions, the longitudinal growth rate on the exclusion region 12 of the wafer 10 is higher than that on the application region 11. The manner in which the growth rate is longitudinally is appropriately treated for the exclusion region 12 of the wafer 10.
作為對晶圓10之除外區域12所進行的適當處理,可舉例如:對晶圓10的另一表面10ab側中的除外區域12進行加工的處理,及對晶圓10的一表面10aa側除外區域12進行改質處理等。在對晶圓10的另一表面10ab側中的除外區域12進行加工的處理中,宜使其形成例如凹部13(參照圖2),或是越靠近晶圓10的邊緣,除外區域12之厚度尺寸越小的推拔面14(參照圖3)。 As an appropriate treatment for the exclusion region 12 of the wafer 10, for example, a process of processing the exclusion region 12 on the other surface 10ab side of the wafer 10, and excluding the one surface 10aa side of the wafer 10 The area 12 is subjected to a reforming process or the like. In the process of processing the exclusion region 12 on the other surface 10ab side of the wafer 10, it is preferable to form, for example, the concave portion 13 (refer to FIG. 2), or the closer to the edge of the wafer 10, the thickness of the exclusion region 12 The push surface 14 having a smaller size is smaller (refer to FIG. 3).
對除外區域12進行加工的處理,可使用半導體微細加工技術及機械加工技術等來進行。對除外區域12進行加工的處理,在使用半導體微細加工技術的情況中,例如,在晶圓10的另一表面10ab側形成遮罩材料層之後,以使晶圓10的另一表面10ab中除外區域12露出的方式,將遮罩材料層圖案化。在對除外區域12進行加工的處理中,只要藉由乾式蝕刻從另一表面10ab側對晶圓10進行蝕刻加工即可。此處,在該遮罩材料層的材料為金屬材料的情況中,可以例如,真空蒸鍍法、濺鍍法、CVD法等形成遮罩材料層。又,真空蒸鍍法,可舉例如,電阻加熱真空蒸鍍法、電子束真空蒸鍍法、高頻感應加熱真空蒸鍍法等。另外,在遮罩材料層的材料為無機絶緣材料的情況中,可以例如CVD法等形成遮罩材料層。另外,在該遮罩材料層的材料為光阻材料的情況中,可以例如,旋轉塗佈法等塗佈法形成遮罩材料層。另外,對除外區域12進行加工的處理,在晶圓10為藍寶石晶圓的情況中,可使用氯系氣體作為進行乾式蝕刻時的蝕刻氣體。對除外區域12進行加工的處理,在以半導體微細加工技術形成推拔面14的情況中,只 要在將遮罩材料層圖案化時使用灰階光罩即可。 The processing for processing the exclusion region 12 can be performed using a semiconductor microfabrication technique, a machining technique, or the like. The processing for processing the exclusion region 12, in the case of using the semiconductor microfabrication technique, for example, after the mask material layer is formed on the other surface 10ab side of the wafer 10, except for the other surface 10ab of the wafer 10. The mask material layer is patterned in such a manner that the region 12 is exposed. In the process of processing the exclusion region 12, the wafer 10 may be etched from the other surface 10ab side by dry etching. Here, in the case where the material of the mask material layer is a metal material, the mask material layer may be formed, for example, by a vacuum deposition method, a sputtering method, a CVD method, or the like. Further, examples of the vacuum deposition method include a resistance heating vacuum vapor deposition method, an electron beam vacuum vapor deposition method, and a high frequency induction heating vacuum vapor deposition method. Further, in the case where the material of the mask material layer is an inorganic insulating material, the mask material layer may be formed by, for example, a CVD method or the like. Further, in the case where the material of the mask material layer is a photoresist material, the mask material layer may be formed by a coating method such as a spin coating method. Further, in the process of processing the exclusion region 12, when the wafer 10 is a sapphire wafer, a chlorine-based gas can be used as the etching gas for dry etching. In the process of processing the exclusion region 12, in the case where the push surface 14 is formed by the semiconductor microfabrication technique, only A gray scale mask can be used when patterning the mask material layer.
對除外區域12進行加工的處理,在使用機械加工技術的情況中,可藉由例如,附有鑽石研磨顆粒的工具,對晶圓10的另一表面10ab中的除外區域12進行切削或研磨。 In the process of processing the exclusion zone 12, in the case of using a machining technique, the exclusion zone 12 in the other surface 10ab of the wafer 10 can be cut or ground by, for example, a tool with diamond abrasive particles.
磊晶晶圓1之製造方法中,例如,在III族氮化物半導體層20成長之前,於晶圓10之除外區域12中,在晶圓10的另一表面10ab側形成凹部13或是推拔面14。藉此,在磊晶晶圓1之製造方法中,於III族氮化物半導體層20成長時,將熱從位於晶圓10之另一表面10ab側的晶圓支持體,傳遞至晶圓10的時候,在應用區域11與除外區域12就有所不同。晶圓支持體,係III族氮化物半導體層20的成長條件中,決定成長溫度的元件之一,在以有機金屬氣相磊晶裝置作為使III族氮化物半導體層20磊晶成長的磊晶成長裝置的情況中為載置台,而在分子束磊晶裝置的情況中為基板載具。因此,在磊晶晶圓1之製造方法中,於III族氮化物半導體層20在晶圓10的一表面10aa側成長時,III族氮化物半導體層20之中,成長於晶圓10之除外區域12上的外周部22之成長溫度,實際上低於中央部21的成長溫度。藉此推論,磊晶晶圓1之製造方法中,在III族氮化物半導體層20於晶圓10的一表面10aa側成長時,與中央部21相比,外周部22在縱向上成長的傾向變強,故較容易產生空隙。 In the method of manufacturing the epitaxial wafer 1, for example, before the growth of the group III nitride semiconductor layer 20, in the exclusion region 12 of the wafer 10, the recess 13 is formed or pushed on the other surface 10ab side of the wafer 10. Face 14. Thereby, in the method of manufacturing the epitaxial wafer 1, when the group III nitride semiconductor layer 20 is grown, heat is transferred from the wafer support on the other surface 10ab side of the wafer 10 to the wafer 10. At the time, the application area 11 and the exclusion area 12 are different. In the wafer support, one of the elements determining the growth temperature in the growth condition of the group III nitride semiconductor layer 20 is an epitaxial crystal grown by epitaxial growth of the group III nitride semiconductor layer 20 by an organic metal vapor phase epitaxy apparatus. In the case of a growth device, it is a mounting table, and in the case of a molecular beam epitaxy device, it is a substrate carrier. Therefore, in the method of manufacturing the epitaxial wafer 1, when the group III nitride semiconductor layer 20 is grown on the surface 10aa side of the wafer 10, among the group III nitride semiconductor layers 20, the wafer 10 is grown. The growth temperature of the outer peripheral portion 22 on the region 12 is actually lower than the growth temperature of the central portion 21. In this way, in the method of manufacturing the epitaxial wafer 1, when the group III nitride semiconductor layer 20 is grown on the surface 10aa side of the wafer 10, the tendency of the outer peripheral portion 22 to grow in the longitudinal direction is higher than that of the central portion 21. It becomes stronger, so it is easier to create voids.
凹部13的深度尺寸,宜在0.5μm~10μm左右的範圍。凹部13的深度尺寸,並非僅限於0.5μm~10μm左右的範圍。然而,在凹部13的深度尺寸未滿0.5μm的情況中,於晶圓10之除外區域12上,亦形成與應用區域11同等緻密的薄膜結構,而難以形成空隙,故具有應力難以緩和的傾向。另外,在凹部13的深度尺寸大於10μm的情況中,III族氮化物半導體層20之外周部22的成長溫度降得太低,使得外周部22變成非單晶的可能性提高。另外,在凹部13的深度尺寸大於10μm的情況中,具有形成凹部13時的加工時間過長的傾向。 The depth of the concave portion 13 is preferably in the range of about 0.5 μm to 10 μm. The depth dimension of the recessed portion 13 is not limited to a range of about 0.5 μm to 10 μm. However, when the depth dimension of the concave portion 13 is less than 0.5 μm, a thin film structure which is denser than the application region 11 is formed on the exclusion region 12 of the wafer 10, and it is difficult to form a void, so that the stress tends to be relaxed. . In addition, in the case where the depth dimension of the concave portion 13 is larger than 10 μm, the growth temperature of the outer peripheral portion 22 of the group III nitride semiconductor layer 20 is lowered too low, so that the possibility that the outer peripheral portion 22 becomes non-single crystal is increased. Further, in the case where the depth dimension of the concave portion 13 is larger than 10 μm, the processing time when the concave portion 13 is formed tends to be too long.
推拔面14,在晶圓10的另一表面10ab中,於推拔面14之寬度在2~5mm左右的範圍內,宜將晶圓10邊緣的深度尺寸設於0.5~10μm左右的範圍。在晶圓10邊緣的推拔面14的深度尺寸未滿0.5μm的情況中,於晶圓10之除外區域12上之外周部22,以含有空隙之方式形成的區域變窄,具有抑制裂縫23之產生或抑制其延伸的效果降低的傾向。另外,在晶圓10邊緣的推拔面14的深度尺寸大於10μm的情況中,III族氮化物半導體層20之外周部22的成長溫度降得太低,而使得外周部22變成非單晶中的可能性提高。另外,在晶圓10邊緣的推拔面14的深度尺寸大於10μm的情況中,具有形成推拔面14時的加工時間變長的傾向。 In the push surface 14, in the other surface 10ab of the wafer 10, the width of the edge of the wafer 10 is preferably in the range of about 0.5 to 10 μm in the range of the width of the push surface 14 in the range of about 2 to 5 mm. In the case where the depth dimension of the push-out surface 14 at the edge of the wafer 10 is less than 0.5 μm, the region formed by the void-containing portion 22 on the outer peripheral portion 22 of the wafer 10 is narrowed, and the crack 23 is suppressed. The tendency to produce or inhibit the effect of its extension is reduced. In addition, in the case where the depth dimension of the push-out surface 14 at the edge of the wafer 10 is larger than 10 μm, the growth temperature of the outer peripheral portion 22 of the group III nitride semiconductor layer 20 is lowered too low, so that the outer peripheral portion 22 becomes non-single crystal. The possibility of improvement. Further, in the case where the depth dimension of the push surface 14 at the edge of the wafer 10 is larger than 10 μm, the processing time when the push surface 14 is formed tends to be long.
加工處理,並不限於藉由半導體微細加工技術或機械加工技術的處理,亦可為例如,使用雷射加工技術的處理。 The processing is not limited to the processing by the semiconductor microfabrication technique or the machining technique, and may be, for example, a treatment using a laser processing technique.
對晶圓10的一表面10aa側的除外區域12所進行的改質處理,係例如,氧化處理或氮化處理。以下,將除外區域12改質的處理稱為改質化處理。 The reforming treatment performed on the exclusion region 12 on the one surface 10aa side of the wafer 10 is, for example, an oxidation treatment or a nitridation treatment. Hereinafter, the process of modifying the exclusion zone 12 is referred to as a reformation process.
氧化處理中,例如,亦可將晶圓10的一表面10aa側的除外區域12在O2氣氛圍或大氣氛圍中退火,亦可對晶圓10的一表面10aa側的除外區域12照射O2電漿。在O2氣體氛圍中或是大氣中將晶圓10退火的氧化處理的情況中,退火溫度可在例如,400~900℃左右的範圍內適當地設定。對晶圓10照射O2電漿以作為氧化處理的情況中,晶圓10的溫度,只要在例如,室溫~600℃左右的範圍內適當設定即可。晶圓10為藍寶石晶圓,改質化處理為氧化處理的情況中,改質層15,相較於Al2O3,係氧含量較多的層。亦即,改質層15,係組成比偏離Al2O3之化學計量的層。該改質層15的厚度,從使形成於該改質層15上的III族氮化物半導體層20之外周部22為單晶的觀點來看,宜設定於數Å~10Å左右的範圍內。 In the oxidation treatment, for example, the exclusion region 12 on the one surface 10aa side of the wafer 10 may be annealed in an O 2 atmosphere or an atmosphere, or the exclusion region 12 on the one surface 10aa side of the wafer 10 may be irradiated with O 2 . Plasma. In the case of an oxidation treatment in which the wafer 10 is annealed in an O 2 gas atmosphere or in the atmosphere, the annealing temperature can be appropriately set within a range of, for example, about 400 to 900 °C. In the case where the wafer 10 is irradiated with the O 2 plasma as the oxidation treatment, the temperature of the wafer 10 may be appropriately set within a range of, for example, room temperature to 600 ° C. The wafer 10 is a sapphire wafer, and in the case where the reforming treatment is an oxidation treatment, the modified layer 15 is a layer having a larger oxygen content than Al 2 O 3 . That is, the reforming layer 15 is a layer having a stoichiometric ratio deviating from Al 2 O 3 . The thickness of the reforming layer 15 is preferably set in a range of about Å to 10 Å from the viewpoint of making the outer peripheral portion 22 of the group III nitride semiconductor layer 20 formed on the reforming layer 15 a single crystal.
氮化處理中,可將例如,晶圓10的一表面10aa側的除外區域12曝露於NH3中,亦可對晶圓10的一表面10aa側的除外區域12照射N2電漿。作為氮化處理,在除外區域12曝露於NH3的情況中,晶圓10的溫度,只 要在例如,900~1100℃左右的範圍內適當設定即可。對晶圓10照射N2電漿以進行氮化處理的情況,晶圓10的溫度,只要在室溫~600℃左右的範圍內適當設定即可。晶圓10為藍寶石晶圓,改質化處理為氮化處理的情況中,改質層15係以其組成式以AlON所表示之物質的層。該改質層15的厚度,從使形成於該改質層15上之III族氮化物半導體層20的外周部22為單晶的觀點來看,宜設定於5Å~30Å左右的範圍內。 In the nitriding treatment, for example, the exclusion region 12 on the one surface 10aa side of the wafer 10 may be exposed to NH 3 , or the exclusion region 12 on the one surface 10aa side of the wafer 10 may be irradiated with N 2 plasma. In the case where the exclusion region 12 is exposed to NH 3 as the nitriding treatment, the temperature of the wafer 10 may be appropriately set within a range of, for example, about 900 to 1100 °C. When the wafer 10 is irradiated with N 2 plasma to perform nitriding treatment, the temperature of the wafer 10 may be appropriately set within a range of from room temperature to 600 ° C. The wafer 10 is a sapphire wafer, and in the case where the reforming treatment is a nitriding treatment, the modified layer 15 is a layer of a substance represented by AlON in a compositional formula. The thickness of the modified layer 15 is preferably set in a range of about 5 Å to 30 Å from the viewpoint of making the outer peripheral portion 22 of the group III nitride semiconductor layer 20 formed on the modified layer 15 a single crystal.
磊晶晶圓1之製造方法中,對晶圓10照射N2電漿,以進行氮化處理的情況中,可使用例如,電子迴旋加速器共振(ECR;Electron Cyclotron Resonance)電漿裝置。另外,磊晶晶圓1之製造方法,在將晶圓10曝露於NH3中以進行氮化處理的情況中,可使用例如有機金屬氣相磊晶裝置。在使用有機金屬氣相磊晶裝置的情況中,藉由提升基板溫度,促進藍寶石晶圓與NH3的化學反應,而可縮短氮化處理所需要的時間。另外,在形成改質層15時,作為保護應用區域11的遮罩層的材料,可使用例如,Si3N4、SiO2、光阻等。然而,關於改質化處理的溫度,在遮罩層的材料為光阻的情況中宜為150℃以下,在SiO2的情況中宜為1000℃以下。另外,磊晶晶圓1之製造方法中,在形成SiO2層的遮罩層之後,於有機金屬氣相磊晶裝置中,在基板溫度未滿900℃的條件下進行氮化處理。之後,磊晶晶圓1之製造方法中,在晶圓10設置於有機金屬氣相磊晶裝置內的狀態下,將基板溫度上升至1300℃左右,藉此可自動地去除遮罩層。藉此,磊晶晶圓1之製造方法中,以NH3所進行的氮化處理,及之後的III族氮化物半導體層20的形成,皆可在有機金屬氣相磊晶裝置內進行,故具有製造製程簡化的優點。 In the method of manufacturing the epitaxial wafer 1, when the wafer 10 is irradiated with N 2 plasma to perform nitriding treatment, for example, an Electron Cyclotron Resonance (ECR) plasma apparatus can be used. Further, in the method of manufacturing the epitaxial wafer 1, in the case where the wafer 10 is exposed to NH 3 for nitriding treatment, for example, an organometallic vapor phase epitaxy apparatus can be used. In the case of using an organometallic vapor phase epitaxy device, the time required for the nitridation treatment can be shortened by increasing the substrate temperature and promoting the chemical reaction of the sapphire wafer with NH 3 . Further, when forming the reforming layer 15, as a material for protecting the mask layer of the application region 11, for example, Si 3 N 4 , SiO 2 , photoresist, or the like can be used. However, the temperature of the reforming treatment is preferably 150 ° C or less in the case where the material of the mask layer is photoresist, and preferably 1000 ° C or less in the case of SiO 2 . Further, in the method of manufacturing the epitaxial wafer 1, after the mask layer of the SiO 2 layer is formed, the nitridation treatment is performed in the organic metal vapor phase epitaxy apparatus under the condition that the substrate temperature is less than 900 °C. Thereafter, in the method of manufacturing the epitaxial wafer 1, the mask layer is automatically removed by raising the substrate temperature to about 1300 ° C in a state where the wafer 10 is placed in the organometallic vapor phase epitaxy apparatus. Therefore, in the method of manufacturing the epitaxial wafer 1, the nitridation treatment by NH 3 and the subsequent formation of the group III nitride semiconductor layer 20 can be performed in the organometallic vapor phase epitaxy apparatus. It has the advantage of simplifying the manufacturing process.
磊晶晶圓1之製造方法中,藉由在III族氮化物半導體層20成長前進行改質化處理,可在晶圓10之除外區域12中的晶圓10的一表面10aa側形成改質層15。藉此,磊晶晶圓1之製造方法中,III族氮化物半導體層20成長時,III族氮化物半導體層20中,與中央部21相比,可在外周部22形成大量的突起。磊晶晶圓1中,在III族氮化物半導體層20之中央部21之突起數量亦可為零,從提升形成於中央部21之裝置之產量的觀點來看,突 起的數量宜為較少。 In the method of manufacturing the epitaxial wafer 1, the reforming process before the growth of the group III nitride semiconductor layer 20 can be performed on the surface 10aa side of the wafer 10 in the exclusion region 12 of the wafer 10. Layer 15. As a result, in the method of manufacturing the epitaxial wafer 1, when the group III nitride semiconductor layer 20 is grown, a large number of protrusions can be formed in the outer peripheral portion 22 of the group III nitride semiconductor layer 20 as compared with the central portion 21. In the epitaxial wafer 1, the number of protrusions in the central portion 21 of the group III nitride semiconductor layer 20 can also be zero, from the viewpoint of increasing the yield of the device formed in the central portion 21, The number should be less.
本案發明人得到下述實驗結果:例如,在晶圓10為藍寶石晶圓,III族氮化物半導體層20為氮化鋁層的情況中,相較於控制III族氮化物半導體層20的成長條件,將晶圓10的一表面10aa改質化較易形成突起。於是,在III族氮化物半導體層20的外周部22形成突起的情況中,於III族氮化物半導體層20的成長之前,宜在晶圓10之除外區域12中的晶圓10的一表面10aa側形成改質層15。藉此,磊晶晶圓1之製造方法中,可在III族氮化物半導體層20的外周部22,相較於中央部21,形成大量的突起。磊晶晶圓1之製造方法中,在使用晶圓10的一表面10aa為(0001)面的藍寶石晶圓,以氮化鋁層作為III族氮化物半導體層20,並藉由有機金屬氣相磊晶裝置使III族氮化物半導體層20成長的情況中,形成如圖7及圖8的突起24。該等的突起24,具有倒六角錐狀的結構。突起24,在III族氮化物半導體層20中,具有在突起24與突起24之周圍的平坦表面的邊界形成間隙的情形。突起24,比突起24周圍的平坦表面突出數100nm~數μm左右。突起24的結晶方位,與III族氮化物半導體層20中之突起24的周圍不同。 The inventors of the present invention obtained the following experimental results: for example, in the case where the wafer 10 is a sapphire wafer and the group III nitride semiconductor layer 20 is an aluminum nitride layer, the growth conditions of the group III nitride semiconductor layer 20 are controlled. It is easier to form a protrusion by modifying one surface 10aa of the wafer 10. Then, in the case where the protrusions are formed on the outer peripheral portion 22 of the group III nitride semiconductor layer 20, before the growth of the group III nitride semiconductor layer 20, a surface 10aa of the wafer 10 in the exclusion region 12 of the wafer 10 is preferable. The modified layer 15 is formed on the side. Thereby, in the method of manufacturing the epitaxial wafer 1, a large number of protrusions can be formed in the outer peripheral portion 22 of the group III nitride semiconductor layer 20 as compared with the central portion 21. In the method of manufacturing the epitaxial wafer 1, a sapphire wafer having a (0001) plane on one surface 10aa of the wafer 10, a group III nitride semiconductor layer 20 as an aluminum nitride layer, and an organic metal vapor phase are used. In the case where the epitaxial device grows the group III nitride semiconductor layer 20, the protrusions 24 as shown in FIGS. 7 and 8 are formed. These protrusions 24 have a hexagonal pyramid shape. The protrusion 24 has a case where a gap is formed in the boundary of the flat surface around the protrusion 24 and the protrusion 24 in the group III nitride semiconductor layer 20. The projection 24 protrudes by about 100 nm to several μm from the flat surface around the projection 24. The crystal orientation of the protrusions 24 is different from the periphery of the protrusions 24 in the group III nitride semiconductor layer 20.
例如,在使用一表面10aa為(0001)面的藍寶石晶圓作為晶圓10,以氮化鋁層作為III族氮化物半導體層20,並藉由有機金屬氣相磊晶裝置進行成長的情況中,III族氮化物半導體層20的成長條件如下所述。 For example, in the case where a sapphire wafer having a surface 10aa of a (0001) plane is used as the wafer 10, and an aluminum nitride layer is used as the group III nitride semiconductor layer 20, and grown by an organometallic vapor phase epitaxy apparatus, The growth conditions of the group III nitride semiconductor layer 20 are as follows.
鋁的原料氣體,宜使用三甲基鋁(Trimethyl Aluminum;以下以TMA表示)。TMA的載體氣體,宜使用H2氣體。另外,氮的原料氣體,宜使用NH3。 As the raw material gas of aluminum, trimethyl aluminum (hereinafter referred to as TMA) is preferably used. For the carrier gas of TMA, H 2 gas is preferably used. Further, as the raw material gas of nitrogen, NH 3 is preferably used.
氮化鋁層的成長溫度,宜設在1200℃以上1400℃以下,更宜設在1250~1350℃的溫度範圍內。氮化鋁層的成長溫度,係以基板溫度來設定。該基板溫度為載置台的溫度。晶圓10之應用區域11的溫度,可視為與基板溫度相同的溫度。在上述凹部13與推拔面14形成的情況中,晶圓10之除外區域12的溫度低於應用區域11的溫度。 The growth temperature of the aluminum nitride layer should be set to be 1200 ° C or higher and 1400 ° C or lower, and more preferably set at a temperature range of 1250 to 1350 ° C. The growth temperature of the aluminum nitride layer is set based on the substrate temperature. The substrate temperature is the temperature of the mounting table. The temperature of the application region 11 of the wafer 10 can be regarded as the same temperature as the substrate temperature. In the case where the concave portion 13 and the push-out surface 14 are formed, the temperature of the exclusion region 12 of the wafer 10 is lower than the temperature of the application region 11.
氮化鋁層的成長壓力,宜在例如1kPa~40kPa左右的範圍內設定。氮化鋁層的成長壓力,為有機金屬氣相磊晶裝置的反應爐內之壓力。 The growth pressure of the aluminum nitride layer is preferably set within a range of, for example, about 1 kPa to 40 kPa. The growth pressure of the aluminum nitride layer is the pressure in the reaction furnace of the organometallic vapor phase epitaxy apparatus.
氮化鋁層的成長方法,可使用同時供給成長法,或是交互供給成長法。另外,氮化鋁層的成長方法,亦可時序性地組合同時供給成長法與交互供給成長法。另外,氮化鋁層的成長方法,亦可使用脈衝供給成長法,亦可時序性地組合同時供給成長法與脈衝供給成長法。 The method of growing the aluminum nitride layer may be a simultaneous supply growth method or an interactive supply growth method. In addition, the method of growing the aluminum nitride layer may be combined with the simultaneous supply growth method and the interactive supply growth method in a time series. Further, as a method of growing the aluminum nitride layer, a pulse supply growth method may be used, and a simultaneous supply growth method and a pulse supply growth method may be combined in a sequential manner.
表示III族原料與V族原料的莫耳比的V/III比,在同時供給成長法、交互供給成長法、脈衝供給成長法的任一情況中,皆宜為1以上5000以下。 The V/III ratio indicating the molar ratio of the group III raw material to the group V raw material is preferably 1 or more and 5,000 or less in any of the simultaneous supply growth method, the interactive supply growth method, and the pulse supply growth method.
又,磊晶晶圓1之製造方法中,在使III族氮化物半導體層20於晶圓10的一表面10aa側成長時,亦可在晶圓10與III族氮化物半導體層20之間,形成低溫緩衝層。低溫緩衝層的膜厚,係以避免III族氮化物半導體層20的結晶性降低的方式設定。另外,磊晶晶圓1之製造方法中,在使III族氮化物半導體層20成長於晶圓10的一表面10aa側時,亦可在晶圓10與III族氮化物半導體層20的界面,形成晶圓10與III族氮化物半導體層20之中間組成的反應產生物。反應產生物,可舉例如,數Å左右的極薄的膜層。亦即,磊晶晶圓1中,亦可使III族氮化物半導體層20直接形成於晶圓10上,亦可使III族氮化物半導體層20間接地形成於晶圓10上。 Further, in the method of manufacturing the epitaxial wafer 1, when the group III nitride semiconductor layer 20 is grown on one surface 10aa side of the wafer 10, it may be between the wafer 10 and the group III nitride semiconductor layer 20. A low temperature buffer layer is formed. The film thickness of the low temperature buffer layer is set so as to prevent the crystallinity of the group III nitride semiconductor layer 20 from being lowered. Further, in the method of manufacturing the epitaxial wafer 1, when the group III nitride semiconductor layer 20 is grown on the surface 10aa side of the wafer 10, the interface between the wafer 10 and the group III nitride semiconductor layer 20 may be A reaction product composed of the intermediate portion of the wafer 10 and the group III nitride semiconductor layer 20 is formed. The reaction product may, for example, be an extremely thin film layer of about several Å. That is, in the epitaxial wafer 1, the group III nitride semiconductor layer 20 may be formed directly on the wafer 10, or the group III nitride semiconductor layer 20 may be formed indirectly on the wafer 10.
如上所述,磊晶晶圓1,可用於使用III族氮化物半導體之半導體裝置的製造,例如,可用於紫外光半導體發光元件3(參照圖6)等的製造。亦即,磊晶晶圓1,可根據晶圓10的應用區域11的尺寸及紫外光半導體發光元件3的晶片尺寸,形成複數紫外光半導體發光元件3。其中,在磊晶晶圓1中,可提升形成於該磊晶晶圓1上之III族氮化物半導體積層膜的結晶性。圖6的例中,形成於磊晶晶圓1上的III族氮化物半導體積層膜,係由第1氮化物半導體層30a、活性層40a、電子區塊層50a、第2氮化物半導體層60a及p形接觸層70a所構成。圖6係顯示相當於磊晶晶圓1中所形成的複數紫外光半導體發光元件3中的1個的部分概略剖面圖。磊晶晶圓1中,在 切割為個別的紫外光半導體發光元件3之後,藍寶石晶圓所形成的晶圓10,成為晶片尺寸的支持基板10a,III族氮化物半導體層20成為晶片尺寸的III族氮化物半導體層20a。III族氮化物半導體層20a,具有作為磊晶晶圓1上所形成的III族氮化物半導體積層膜之緩衝層的功能。 As described above, the epitaxial wafer 1 can be used for the fabrication of a semiconductor device using a group III nitride semiconductor, and can be used, for example, for the fabrication of an ultraviolet semiconductor light-emitting device 3 (see FIG. 6). That is, the epitaxial wafer 1 can form the plurality of ultraviolet semiconductor light-emitting elements 3 in accordance with the size of the application region 11 of the wafer 10 and the wafer size of the ultraviolet semiconductor light-emitting element 3. Among them, in the epitaxial wafer 1, the crystallinity of the group III nitride semiconductor laminated film formed on the epitaxial wafer 1 can be improved. In the example of FIG. 6, the group III nitride semiconductor laminated film formed on the epitaxial wafer 1 is composed of the first nitride semiconductor layer 30a, the active layer 40a, the electron block layer 50a, and the second nitride semiconductor layer 60a. And the p-shaped contact layer 70a is formed. FIG. 6 is a partial schematic cross-sectional view showing one of the plurality of ultraviolet semiconductor light-emitting elements 3 formed in the epitaxial wafer 1. In epitaxial wafer 1, in After the individual ultraviolet light semiconductor light-emitting elements 3 are cut, the wafer 10 formed of the sapphire wafer becomes the wafer-sized support substrate 10a, and the group III nitride semiconductor layer 20 becomes the wafer-sized group III nitride semiconductor layer 20a. The group III nitride semiconductor layer 20a has a function as a buffer layer of a group III nitride semiconductor laminated film formed on the epitaxial wafer 1.
圖6所示之構成的紫外光半導體發光元件3,具備:第1導電形的第1氮化物半導體層30a,形成於III族氮化物半導體層20a上;活性層40a,形成於第1氮化物半導體層30a上;及第2氮化物半導體層60a,形成在與活性層40a中的第1氮化物半導體層30a側的相反側。該紫外光半導體發光元件3,係在210nm~360nm的紫外波長區域具有發光波長(發光峰值波長)的紫外發光二極體。紫外光半導體發光元件3中,使用AlGaN系材料作為活性層40a的材料。以下,亦將活性層40a稱為發光層40a。 The ultraviolet semiconductor light-emitting device 3 having the configuration shown in FIG. 6 includes a first nitride semiconductor layer 30a of a first conductivity type formed on the group III nitride semiconductor layer 20a, and an active layer 40a formed of a first nitride. The semiconductor layer 30a and the second nitride semiconductor layer 60a are formed on the opposite side of the first nitride semiconductor layer 30a side of the active layer 40a. The ultraviolet light-emitting semiconductor light-emitting element 3 is an ultraviolet light-emitting diode having an emission wavelength (emission peak wavelength) in an ultraviolet wavelength region of 210 nm to 360 nm. In the ultraviolet semiconductor light-emitting device 3, an AlGaN-based material is used as the material of the active layer 40a. Hereinafter, the active layer 40a is also referred to as a light-emitting layer 40a.
另外,紫外光半導體發光元件3更包含:第1電極80a,與第1氮化物半導體層30a電性連接;及第2電極90a,與第2氮化物半導體層60a電性連接。 Further, the ultraviolet semiconductor light emitting element 3 further includes a first electrode 80a electrically connected to the first nitride semiconductor layer 30a, and a second electrode 90a electrically connected to the second nitride semiconductor layer 60a.
另外,紫外光半導體發光元件3中,使第1導電形為n形,第2導電形為p形。紫外光半導體發光元件3,在與第2氮化物半導體層60a中的發光層40a側的相反側上,具有p形接觸層70a。紫外光半導體發光元件3中,第2電極90a,形成於p形接觸層70a的一部分之上。簡而言之,紫外光半導體發光元件3中,第2電極90a透過p形接觸層70a與第2氮化物半導體層60a電性連接。此處,紫外光半導體發光元件3中,發光層40a與第2氮化物半導體層60a之間宜設有電子區塊層50a。另外,紫外光半導體發光元件3為台面(mesa)結構。紫外光半導體發光元件3,在第1氮化物半導體層30a中的發光層40a側中,在使第1氮化物半導體層30a露出的表面30aa的一部分之上,具有第1電極80a。 Further, in the ultraviolet semiconductor light-emitting device 3, the first conductive shape is made n-shaped, and the second conductive shape is p-shaped. The ultraviolet-light semiconductor light-emitting element 3 has a p-type contact layer 70a on the side opposite to the light-emitting layer 40a side of the second nitride semiconductor layer 60a. In the ultraviolet semiconductor light-emitting element 3, the second electrode 90a is formed on a part of the p-type contact layer 70a. In short, in the ultraviolet semiconductor light-emitting device 3, the second electrode 90a is electrically connected to the second nitride semiconductor layer 60a through the p-type contact layer 70a. Here, in the ultraviolet semiconductor light-emitting device 3, an electron block layer 50a is preferably provided between the light-emitting layer 40a and the second nitride semiconductor layer 60a. Further, the ultraviolet light semiconductor light emitting element 3 has a mesa structure. The ultraviolet-light semiconductor light-emitting device 3 has a first electrode 80a on a portion of the surface 30aa on which the first nitride semiconductor layer 30a is exposed on the light-emitting layer 40a side of the first nitride semiconductor layer 30a.
發光層40a,宜具有量子井結構。量子井結構,可為多重量子井結構,亦可為單一量子井結構。發光層40a,只要以發出期望之發光波長的紫外光 的方式,適當地設定井層中Al的組成比即可。AlGaN系材料的發光層40a中,可藉由改變Al的組成比,在發光波長為210~360nm的範圍內,任意地設定發光波長。紫外光半導體發光元件3中,例如,在期望的發光峰值波長為265nm附近的情況下,只要將Al的組成比設為0.50即可。另外,紫外光半導體發光元件3,亦可以雙異質結構形成。紫外光半導體發光元件3中,可使發光層40a為單層結構,並使用發光層40a與發光層40a之厚度方向的兩側的層,作為雙異質結構。發光層40a的厚度方向之兩側的層,可使用例如,n形氮化物半導體層及p形氮化物半導體層。 The light-emitting layer 40a preferably has a quantum well structure. The quantum well structure can be a multiple quantum well structure or a single quantum well structure. The luminescent layer 40a is only required to emit ultraviolet light having a desired illuminating wavelength In a manner, the composition ratio of Al in the well layer can be appropriately set. In the light-emitting layer 40a of the AlGaN-based material, the emission wavelength can be arbitrarily set in the range of the emission wavelength of 210 to 360 nm by changing the composition ratio of Al. In the ultraviolet-light semiconductor light-emitting device 3, for example, when the desired emission peak wavelength is around 265 nm, the composition ratio of Al may be set to 0.50. Further, the ultraviolet semiconductor light-emitting element 3 may be formed in a double heterostructure. In the ultraviolet-light semiconductor light-emitting device 3, the light-emitting layer 40a can have a single-layer structure, and a layer on both sides in the thickness direction of the light-emitting layer 40a and the light-emitting layer 40a can be used as a double heterostructure. For the layers on both sides in the thickness direction of the light-emitting layer 40a, for example, an n-type nitride semiconductor layer and a p-type nitride semiconductor layer can be used.
又,紫外光半導體發光元件3,並不限於紫外發光二極體,亦可為紫外雷射二極體。 Further, the ultraviolet light semiconductor light emitting element 3 is not limited to the ultraviolet light emitting diode, and may be an ultraviolet laser diode.
以下,就紫外光半導體發光元件3之各構成要件詳細說明。 Hereinafter, each constituent element of the ultraviolet light-emitting semiconductor light-emitting element 3 will be described in detail.
III族氮化物半導體層20a,例如在紫外光半導體發光元件3中,可作為緩衝層使用,其用以減少第1氮化物半導體層30a之穿透式差排,同時減少第1氮化物半導體層30a的殘留應變。 The group III nitride semiconductor layer 20a, for example, in the ultraviolet semiconductor light-emitting device 3, can be used as a buffer layer for reducing the transmission difference of the first nitride semiconductor layer 30a while reducing the first nitride semiconductor layer. Residual strain of 30a.
發光層40a,係將注入的載體轉換為光者,可作為量子井結構。此處,載體為電子與電洞。量子井結構,係由障壁層與井層所形成。量子井結構,可為多重量子井結構,亦可為單一量子井結構。另外,紫外光半導體發光元件3中,井層及障壁層各別的膜厚並未特限定。然而,發光層40a中,若井層的膜厚過厚,則注入井層的電子及電洞,會因為量子井結構中的晶格不匹配所引起的壓電場,而導致空間上的分離,使得紫外光半導體發光元件3的發光效率低落。另外,發光層40a中,在井層的膜厚過薄的情況中,載體的封閉效果低落,使得紫外光半導體發光元件3的發光效率低落。因此,井層的膜厚,宜為1~5nm左右,較宜為1.3~3nm左右。另外,障壁層的膜厚,宜設定於例如,5~15nm左右的範圍內。本實施態樣中的紫外光半導體發光元件3中,作為一例,將井層的膜厚設為2nm,障壁層的膜厚設為10nm,但並非限定於該等膜厚。 The light-emitting layer 40a converts the injected carrier into a light and can be used as a quantum well structure. Here, the carrier is an electron and a hole. The quantum well structure is formed by the barrier layer and the well layer. The quantum well structure can be a multiple quantum well structure or a single quantum well structure. Further, in the ultraviolet-light semiconductor light-emitting device 3, the film thickness of each of the well layer and the barrier layer is not particularly limited. However, in the light-emitting layer 40a, if the film thickness of the well layer is too thick, the electrons and holes injected into the well layer may cause spatial separation due to the piezoelectric field caused by the lattice mismatch in the quantum well structure. The luminous efficiency of the ultraviolet semiconductor light-emitting element 3 is made low. Further, in the case where the film thickness of the well layer is too thin in the light-emitting layer 40a, the sealing effect of the carrier is lowered, so that the light-emitting efficiency of the ultraviolet-light semiconductor light-emitting element 3 is lowered. Therefore, the film thickness of the well layer should preferably be about 1 to 5 nm, preferably about 1.3 to 3 nm. Further, the film thickness of the barrier layer is preferably set to, for example, about 5 to 15 nm. In the ultraviolet-light semiconductor light-emitting device 3 of the present embodiment, as an example, the film thickness of the well layer is 2 nm, and the thickness of the barrier layer is 10 nm, but the film thickness is not limited thereto.
發光層40a中,係以發出期望之發光波長的紫外光的方式,設定井層中Al的組成比。紫外光半導體發光元件3中,使用AlGaN系材料的發光層40a的情況中,藉由改變Al的組成比,可在發光波長為210~360nm的範圍內,任意地設定發光波長。例如,AlGaN系材料的發光層40a中,在期望的發光波長為265nm附近的情況下,只要將Al的組成比設為0.50即可。另外,紫外光半導體發光元件3中,亦可使發光層40a為單層結構,並利用發光層40a與發光層40a的厚度方向的兩側的層,來形成雙異質結構。發光層40a的厚度方向的兩側的層,可使用例如,n形氮化物半導體層及p形氮化物半導體層。 In the light-emitting layer 40a, the composition ratio of Al in the well layer is set so as to emit ultraviolet light of a desired light-emitting wavelength. In the case of using the light-emitting layer 40a of an AlGaN-based material in the ultraviolet-light semiconductor light-emitting device 3, by changing the composition ratio of Al, the light-emitting wavelength can be arbitrarily set in the range of the light-emitting wavelength of 210 to 360 nm. For example, in the light-emitting layer 40a of the AlGaN-based material, when the desired light-emitting wavelength is around 265 nm, the composition ratio of Al may be set to 0.50. Further, in the ultraviolet-light semiconductor light-emitting device 3, the light-emitting layer 40a may have a single-layer structure, and a double heterostructure may be formed by the layers on both sides in the thickness direction of the light-emitting layer 40a and the light-emitting layer 40a. For the layers on both sides in the thickness direction of the light-emitting layer 40a, for example, an n-type nitride semiconductor layer and a p-type nitride semiconductor layer can be used.
第1氮化物半導體層30a中,第1導電形為n形的情況下,形成n形氮化物半導體層。n形氮化物半導體層對發光層40a輸送電子。雖將n形氮化物半導體層的膜厚設為1μm以作為一例,但其膜厚並未特限定。另外,n形氮化物半導體層,可使用n形AlxGa1-xN(0<x<1)層。此處,n形AlxGa1-xN(0<x<1)層中的Al的組成比x,只要可抑制在發光層40a中所發出的紫外光被吸收的情形,則該組成比x並未特別限定。例如,如上所述,在發光層40a中的井層的Al的組成比為0.5,障壁層的Al的組成比0.70的情況下,n形AlxGa1-xN(0<x<1)層的Al的組成比x,可為與障壁層的Al的組成比相同的0.70。亦即,發光層40a的井層為Al0.5Ga0.5N層的情況中,n形氮化物半導體層,可為n形Al0.70Ga0.30N層。又,n形氮化物半導體層的材料,並不限於AlGaN,只要可抑制在發光層40a中所發出之紫外光被吸收的情形即可。n形氮化物半導體層的材料,亦可為例如,AlInN、AlGaInN等。n形氮化物半導體層的施體雜質宜為Si。另外,n形氮化物半導體層的電子濃度,只要在例如,1×1018~1×1019cm-3左右的範圍內設定即可。本實施態樣中的紫外光半導體發光元件3中,將n形氮化物半導體層的電子濃度設為8×1018cm-3以作為一例。 In the first nitride semiconductor layer 30a, when the first conductive shape is an n-type, an n-type nitride semiconductor layer is formed. The n-type nitride semiconductor layer transports electrons to the light-emitting layer 40a. Although the film thickness of the n-type nitride semiconductor layer is set to 1 μm as an example, the film thickness is not particularly limited. Further, as the n-type nitride semiconductor layer, an n-type Al x Ga 1-x N (0 < x < 1) layer can be used. Here, the composition ratio x of Al in the n-type Al x Ga 1-x N (0<x<1) layer is as long as the ultraviolet light emitted in the light-emitting layer 40a is suppressed from being absorbed. x is not particularly limited. For example, as described above, the composition ratio of Al of the well layer in the light-emitting layer 40a is 0.5, and the composition ratio of Al of the barrier layer is In the case of 0.70, the composition ratio x of Al of the n-type Al x Ga 1-x N (0 < x < 1) layer may be 0.70 which is the same as the composition ratio of Al of the barrier layer. That is, in the case where the well layer of the light-emitting layer 40a is an Al 0.5 Ga 0.5 N layer, the n-type nitride semiconductor layer may be an n-type Al 0.70 Ga 0.30 N layer. Further, the material of the n-type nitride semiconductor layer is not limited to AlGaN as long as it is possible to suppress absorption of ultraviolet light emitted from the light-emitting layer 40a. The material of the n-type nitride semiconductor layer may be, for example, AlInN, AlGaInN or the like. The donor impurity of the n-type nitride semiconductor layer is preferably Si. Further, the electron concentration of the n-type nitride semiconductor layer may be set within a range of, for example, about 1 × 10 18 to 1 × 10 19 cm -3 . In the ultraviolet-light semiconductor light-emitting device 3 of the present embodiment, the electron concentration of the n-type nitride semiconductor layer is set to 8 × 10 18 cm -3 as an example.
第2氮化物半導體層60a,在第2導電形為p形的情況中,形成p形氮化物半導體層。p形氮化物半導體層對發光層40a輸送電洞。另外,p形氮 化物半導體層,可使用p形AlyGa1-yN(0<y<1)層。此處,p形AlyGa1-yN(0<y<1)層中的Al的組成比y,只要可抑制在發光層40a中所發出光之紫外光被吸收的情形,則該組成比y並未特別限定。如上所述發光層40a中的井層的Al的組成比為0.5,且障壁層的Al的組成比為0.70的情況中,p形AlyGa1-yN(0<y<1)層的Al的組成比y,可為例如,與障壁層的Al的組成比相同的0.70。亦即,發光層40a的井層為Al0.5Ga0.5N層的情況中,p形氮化物半導體層,可為p形Al0.70Ga0.30N層。p形氮化物半導體層的受體雜質宜為Mg。 In the case where the second conductivity type is p-shaped, the second nitride semiconductor layer 60a forms a p-type nitride semiconductor layer. The p-type nitride semiconductor layer transports holes to the light-emitting layer 40a. Further, as the p-type nitride semiconductor layer, a p-type Al y Ga 1-y N (0 < y < 1) layer can be used. Here, the composition ratio y of Al in the p-type Al y Ga 1-y N (0 < y < 1) layer is as long as the ultraviolet light of the light emitted from the light-emitting layer 40a is suppressed from being absorbed. The ratio y is not particularly limited. As described above, in the case where the composition ratio of Al of the well layer in the light-emitting layer 40a is 0.5, and the composition ratio of Al of the barrier layer is 0.70, the layer of p-type Al y Ga 1-y N (0 < y < 1) The composition ratio y of Al may be, for example, 0.70 which is the same as the composition ratio of Al of the barrier layer. That is, in the case where the well layer of the light-emitting layer 40a is an Al 0.5 Ga 0.5 N layer, the p-type nitride semiconductor layer may be a p-type Al 0.70 Ga 0.30 N layer. The acceptor impurity of the p-type nitride semiconductor layer is preferably Mg.
另外,p形氮化物半導體層的電洞濃度,並未特別限定,在不使p形氮化物半導體層的膜質劣化的範圍內,宜為較高的電洞濃度。然而,紫外光半導體發光元件3中,因為p形AlyGa1-yN(0<y<1)層的電洞濃度低於n形AlxGa1-xN(0<x<1)層的電子濃度,故若p形氮化物半導體層的膜厚過厚,則具有紫外光半導體發光元件3的電阻變大的傾向。因此,p形氮化物半導體層的膜厚宜為200nm以下,較宜為100nm以下。又,本實施態樣中的紫外光半導體發光元件3中,將p形氮化物半導體層的膜厚設定為25nm以作為一例。 Further, the hole concentration of the p-type nitride semiconductor layer is not particularly limited, and a high hole concentration is preferable insofar as the film quality of the p-type nitride semiconductor layer is not deteriorated. However, in the ultraviolet-light semiconductor light-emitting element 3, since the p-type Al y Ga 1-y N (0 < y < 1) layer has a hole concentration lower than that of the n-type Al x Ga 1-x N (0 < x < 1) When the thickness of the p-type nitride semiconductor layer is too thick, the electric resistance of the ultraviolet semiconductor light-emitting element 3 tends to increase. Therefore, the thickness of the p-type nitride semiconductor layer is preferably 200 nm or less, and more preferably 100 nm or less. In the ultraviolet-light semiconductor light-emitting device 3 of the present embodiment, the film thickness of the p-type nitride semiconductor layer is set to 25 nm as an example.
另外,紫外光半導體發光元件3中,為了抑制注入發光層40a的電子中,未於發光層40a中與電洞再結合的電子,漏出(Overflow)至p形氮化物半導體層側,發光層40a與第2氮化物半導體層60a之間,宜設有電子區塊層50a。又,本實施態樣中的紫外光半導體發光元件3中,第2氮化物半導體層60a為p形氮化物半導體層。電子區塊層50a,可藉由p形AlzGa1-zN(0<z<1)層構成。該p形AlzGa1-zN(0<z<1)層的Al的組成比z,雖可為例如0.9,但並未特別限定。電子區塊層50a中的Al的組成比z,宜以使電子區塊層50a的能帶間隙能量,高於p形氮化物半導體層或是障壁層的能帶間隙能量的方式設定。另外,電子區塊層50a的電洞濃度並未特別限定。另外,關於電子區塊層50a的膜厚,雖並未特別限定,但若膜厚過薄,則抑制溢流(overflow)的效果減少;若膜厚過厚,則紫外光半導體發光元件3的電阻變大。此處,關於電子區塊層50a的膜厚,雖因為根據Al的組成比z 與電洞濃度等的值適當改變而無法一概而論,但宜設定於1~50nm的範圍內,較宜設定於5~25nm的範圍內。 Further, in the ultraviolet-light semiconductor light-emitting device 3, in order to suppress electrons injected into the light-emitting layer 40a, electrons that are not recombined with the holes in the light-emitting layer 40a are overflowed to the side of the p-type nitride semiconductor layer, and the light-emitting layer 40a An electron block layer 50a is preferably provided between the second nitride semiconductor layer 60a and the second nitride semiconductor layer 60a. Further, in the ultraviolet semiconductor light-emitting device 3 of the present embodiment, the second nitride semiconductor layer 60a is a p-type nitride semiconductor layer. The electron block layer 50a can be composed of a p-type Al z Ga 1-z N (0 < z < 1) layer. The composition ratio z of Al of the p-type Al z Ga 1-z N (0 < z < 1) layer may be, for example, 0.9, but is not particularly limited. The composition ratio z of Al in the electron block layer 50a is preferably set such that the band gap energy of the electron block layer 50a is higher than the band gap energy of the p-type nitride semiconductor layer or the barrier layer. Further, the hole concentration of the electron block layer 50a is not particularly limited. Further, although the film thickness of the electron block layer 50a is not particularly limited, if the film thickness is too thin, the effect of suppressing overflow is reduced, and if the film thickness is too thick, the ultraviolet semiconductor light-emitting element 3 is thick. The resistance becomes larger. Here, the film thickness of the electron block layer 50a cannot be generalized because the composition ratio z of the Al and the hole concentration are appropriately changed, but it is preferably set in the range of 1 to 50 nm, and is preferably set to 5 ~25nm range.
p形接觸層70a,係為了使與第2電極90a的接觸電阻下降,並得到與第2電極90a之良好的歐姆接觸而設置。p形接觸層70a,可藉由p形GaN層構成。此處,構成p形接觸層70a的p形GaN層的電洞濃度,宜高於p形氮化物半導體層。構成p形接觸層70a的p形GaN層中,藉由使p形GaN層的電洞濃度為例如,1×1018cm-3左右,可得到與第2電極90a的良好的電性接觸。然而,p形GaN層的電洞濃度並未特別限定,亦可在可得到與第2電極90a之良好的電性接觸的電洞濃度之範圍內,進行適當變更。p形接觸層70a的膜厚雖設為50nm,但並不僅限於此,只要設定在例如,30~150nm左右的範圍內即可。 The p-type contact layer 70a is provided in order to reduce the contact resistance with the second electrode 90a and obtain good ohmic contact with the second electrode 90a. The p-type contact layer 70a can be formed by a p-type GaN layer. Here, the p-type GaN layer constituting the p-type contact layer 70a preferably has a hole concentration higher than that of the p-type nitride semiconductor layer. In the p-type GaN layer constituting the p-type contact layer 70a, good electrical contact with the second electrode 90a can be obtained by setting the hole concentration of the p-type GaN layer to, for example, about 1 × 10 18 cm -3 . However, the hole concentration of the p-type GaN layer is not particularly limited, and may be appropriately changed within a range of a hole concentration at which good electrical contact with the second electrode 90a is obtained. Although the film thickness of the p-type contact layer 70a is 50 nm, it is not limited thereto, and may be set to, for example, a range of about 30 to 150 nm.
另外,紫外光半導體發光元件3中,在為n電極的第1電極80a上,形成有例如Au膜所構成的第1平板電極(圖中未顯示)。另外,紫外光半導體發光元件3中,在為p電極的第2電極90a上,形成有例如Au膜所構成的第2平板電極(圖中未顯示)。 Further, in the ultraviolet-light semiconductor light-emitting device 3, a first plate electrode (not shown) made of, for example, an Au film is formed on the first electrode 80a which is an n-electrode. Further, in the ultraviolet-light semiconductor light-emitting device 3, a second plate electrode (not shown) made of, for example, an Au film is formed on the second electrode 90a which is a p-electrode.
紫外光半導體發光元件3之製造方法中,例如,在磊晶晶圓1上形成第1氮化物半導體層30a之後,在與第1氮化物半導體層30a中的磊晶晶圓1側的相反側,形成發光層40a。之後,紫外光半導體發光元件3之製造方法中,例如,在發光層40a中與第1氮化物半導體層30a側的相反側,依序形成電子區塊層50a、第2氮化物半導體層60a、p形接觸層70a。第1氮化物半導體層30a、發光層40a、電子區塊層50a、第2氮化物半導體層60a及p形接觸層70a,可藉由同一減壓有機金屬氣相磊晶裝置形成。紫外光半導體發光元件3之製造方法中,在p形接觸層70a的形成結束後,使基板溫度降溫至室溫附近,並將磊晶晶圓1從有機金屬氣相磊晶裝置取出。磊晶晶圓1中,形成有第1氮化物半導體層30a、發光層40a、電子區塊層50a、第2氮化物半導體層60a及p形接觸層70a的堆疊薄膜所構成的III族氮化物半導體積層膜。 In the method of manufacturing the ultraviolet semiconductor light-emitting device 3, for example, after the first nitride semiconductor layer 30a is formed on the epitaxial wafer 1, the opposite side of the epitaxial wafer 1 side of the first nitride semiconductor layer 30a is formed. A light-emitting layer 40a is formed. Then, in the method of manufacturing the ultraviolet-light semiconductor light-emitting device 3, for example, the electron block layer 50a and the second nitride semiconductor layer 60a are sequentially formed on the side opposite to the first nitride semiconductor layer 30a side in the light-emitting layer 40a. P-shaped contact layer 70a. The first nitride semiconductor layer 30a, the light-emitting layer 40a, the electron block layer 50a, the second nitride semiconductor layer 60a, and the p-type contact layer 70a can be formed by the same reduced-pressure organic metal vapor phase epitaxy apparatus. In the method of manufacturing the ultraviolet semiconductor light-emitting device 3, after the formation of the p-type contact layer 70a is completed, the substrate temperature is lowered to near room temperature, and the epitaxial wafer 1 is taken out from the organometallic vapor phase epitaxy apparatus. In the epitaxial wafer 1 , a group III nitride formed of a stacked thin film of the first nitride semiconductor layer 30a, the light-emitting layer 40a, the electron block layer 50a, the second nitride semiconductor layer 60a, and the p-type contact layer 70a is formed. Semiconductor laminated film.
之後,在紫外光半導體發光元件3之製造方法中,III族氮化物半導體積層膜中,在與台面結構的頂面對應的區域上形成光阻層,將該光阻層作為遮罩,從III族氮化物半導體積層膜中的p形接觸層70a的表面側至第1氮化物半導體層30a的途中,進行蝕刻。紫外光半導體發光元件3之製造方法中,在形成台面結構之後,去除光阻層。 Thereafter, in the method of manufacturing the ultraviolet semiconductor light-emitting device 3, in the group III nitride semiconductor laminated film, a photoresist layer is formed on a region corresponding to the top surface of the mesa structure, and the photoresist layer is used as a mask from III. The surface side of the p-type contact layer 70a in the group nitride semiconductor laminated film is etched in the middle of the first nitride semiconductor layer 30a. In the method of manufacturing the ultraviolet semiconductor light-emitting device 3, after the mesa structure is formed, the photoresist layer is removed.
之後,紫外光半導體發光元件3之製造方法中,形成與第1氮化物半導體層30a電性連接的第1電極80a,及與第2氮化物半導體層60a電性連接的第2電極90a,接著,形成第1平板電極及第2平板電極。第1電極80a及第2電極90a,可使用例如,蒸鍍裝置等形成。另外,第1平板電極及第2平板電極,可使用例如,蒸鍍裝置等形成。 After that, in the method of manufacturing the ultraviolet semiconductor light-emitting device 3, the first electrode 80a electrically connected to the first nitride semiconductor layer 30a and the second electrode 90a electrically connected to the second nitride semiconductor layer 60a are formed, and then The first plate electrode and the second plate electrode are formed. The first electrode 80a and the second electrode 90a can be formed using, for example, a vapor deposition device or the like. Further, the first plate electrode and the second plate electrode can be formed using, for example, a vapor deposition device or the like.
到形成第1平板電極及第2平板電極的步驟為止,結束紫外光半導體發光元件3之製造方法,藉此完成形成有複數紫外光半導體發光元件3的裝置晶圓。之後,紫外光半導體發光元件3之製造方法中,進行以切割鋸或雷射等將裝置晶圓分割的切割步驟。紫外光半導體發光元件3之製造方法中,藉由進行切割步驟,可各別形成晶片狀紫外光半導體發光元件3。亦即,紫外光半導體發光元件3之製造方法中,可從1個裝置晶圓得到複數紫外光半導體發光元件3。 The method of manufacturing the ultraviolet light semiconductor light-emitting device 3 is completed until the steps of forming the first plate electrode and the second plate electrode, thereby completing the device wafer on which the plurality of ultraviolet light semiconductor light-emitting elements 3 are formed. Thereafter, in the method of manufacturing the ultraviolet semiconductor light-emitting device 3, a cutting step of dividing the device wafer by a dicing saw or a laser is performed. In the method of manufacturing the ultraviolet semiconductor light-emitting device 3, the wafer-shaped ultraviolet semiconductor light-emitting device 3 can be formed separately by performing the dicing step. That is, in the method of manufacturing the ultraviolet semiconductor light-emitting device 3, the plurality of ultraviolet semiconductor light-emitting elements 3 can be obtained from one device wafer.
(實施例1) (Example 1)
本實施例中,根據上述實施態樣中所說明的磊晶晶圓1之製造方法,製造磊晶晶圓1。 In the present embodiment, the epitaxial wafer 1 is manufactured according to the method of manufacturing the epitaxial wafer 1 described in the above embodiment.
磊晶晶圓1的製造中,首先,準備一表面10aa為(0001)面,直徑為50.8mm的藍寶石晶圓作為晶圓10。 In the manufacture of the epitaxial wafer 1, first, a sapphire wafer having a surface 10aa of a (0001) plane and a diameter of 50.8 mm is prepared as the wafer 10.
之後,磊晶晶圓1之製造方法中,藉由電阻加熱真空蒸鍍法,在晶圓10的另一表面10ab上形成作為遮罩材料層的Ni層。之後,在磊晶晶圓1 之製造方法中,使用光微影技術及蝕刻技術,進行遮罩材料層的圖案化,藉此形成以遮罩材料層的一部分所構成的遮罩層。該圖案化中,晶圓10的另一表面10ab之中,從晶圓10的邊緣露出約2mm的區域。 Thereafter, in the method of manufacturing the epitaxial wafer 1, a Ni layer as a mask material layer is formed on the other surface 10ab of the wafer 10 by a resistance heating vacuum deposition method. After the epitaxial wafer 1 In the manufacturing method, the mask layer is patterned by using a photolithography technique and an etching technique, thereby forming a mask layer composed of a part of the mask material layer. In the patterning, an area of about 2 mm is exposed from the edge of the wafer 10 among the other surface 10ab of the wafer 10.
之後,磊晶晶圓1之製造方法中,藉由使用Cl2氣體的乾式蝕刻,於晶圓10的另一表面10ab,形成深度尺寸約3μm的凹部13。蝕刻速率為60~80nm/分左右。 Thereafter, in the method of manufacturing the epitaxial wafer 1, a recess 13 having a depth of about 3 μm is formed on the other surface 10ab of the wafer 10 by dry etching using Cl 2 gas. The etching rate is about 60 to 80 nm/min.
之後,以王水蝕刻去除形成於晶圓10的另一表面10ab上的遮罩層。 Thereafter, the mask layer formed on the other surface 10ab of the wafer 10 is removed by aqua regia etching.
之後,在磊晶晶圓1之製造方法中,將晶圓10導入有機金屬氣相磊晶裝置的反應爐內,並將晶圓10的另一表面10ab設置於載置台。在將晶圓10導入反應爐前,宜以藥品對晶圓10進行前處理,將晶圓10的表面潔淨化。 Thereafter, in the method of manufacturing the epitaxial wafer 1, the wafer 10 is introduced into a reactor of an organometallic vapor phase epitaxy apparatus, and the other surface 10ab of the wafer 10 is placed on a mounting table. Before the wafer 10 is introduced into the reaction furnace, the wafer 10 is preferably pretreated with a chemical to clean the surface of the wafer 10.
在將晶圓10設於載置台之後,進行反應爐內部的真空抽氣。 After the wafer 10 is placed on the mounting table, vacuum evacuation inside the reaction furnace is performed.
磊晶晶圓1之製造方法中,在進行反應爐的真空抽氣之後,將作為載體氣體的H2氣體供給至反應爐內,一邊使反應爐內的壓力保持於規定壓力,一邊將基板溫度升溫至1300℃。此處,規定壓力為10kPa。磊晶晶圓1之製造方法中,在基板溫度升溫至1300℃後,藉由同時供給TMA與NH3的同時供給成長法,使III族氮化物半導體層20在晶圓10上成長。在磊晶晶圓1之製造方法中所形成的磊晶晶圓1,係在晶圓10上形成以膜厚為4μm的AlN層所構成的III族氮化物半導體層20。TMA的流量在標準狀態下為0.2L/min。亦即,TMA的流量為200SCCM(standard cc per minute)。作為載體氣體之H2氣體的流量,在標準狀態下為100L/min。亦即,H2氣體的流量為100SLM(standard liter per minute)。NH3的流量在標準狀態下為1L/min。亦即,NH3的流量為1SLM。 In the manufacturing method of the epitaxial wafer 1, after performing vacuum evacuation of the reactor, H 2 gas as a carrier gas is supplied into the reaction furnace, and the substrate temperature is maintained while maintaining the pressure in the reactor at a predetermined pressure. The temperature was raised to 1300 °C. Here, the predetermined pressure is 10 kPa. In the method of manufacturing the epitaxial wafer 1, after the substrate temperature is raised to 1300 ° C, the group III nitride semiconductor layer 20 is grown on the wafer 10 by simultaneously supplying the TMA and NH 3 while supplying the growth method. In the epitaxial wafer 1 formed in the method of manufacturing the epitaxial wafer 1, a group III nitride semiconductor layer 20 composed of an AlN layer having a film thickness of 4 μm is formed on the wafer 10. The flow rate of the TMA is 0.2 L/min under standard conditions. That is, the flow rate of the TMA is 200 SCCM (standard cc per minute). The flow rate of the H 2 gas as the carrier gas was 100 L/min in a standard state. That is, the flow rate of the H 2 gas is 100 SLM (standard liter per minute). The flow rate of NH 3 was 1 L/min under standard conditions. That is, the flow rate of NH 3 is 1 SLM.
在將基板溫度降溫至室溫附近後,從有機金屬氣相磊晶裝置取出磊晶 晶圓1。 After the substrate temperature is lowered to near room temperature, the epitaxial crystal is taken out from the organometallic vapor phase epitaxy device. Wafer 1.
本案發明人,以光學顯微鏡觀察本實施例之磊晶晶圓1中的III族氮化物半導體層20的表面。根據以光學顯微鏡觀察的評價中,可得知,在III族氮化物半導體層20的外周部22中,在數μm~10μm左右的平面尺寸中產生空隙。外周部22中的空隙密度,約為10~100個/mm2左右。另外,根據以光學顯微鏡觀察的評價可確認,與晶圓10中未形成凹部13的比較例1相比,外周部22中的裂縫23的數量減少。根據以光學顯微鏡觀察的評價可確認,未觀察到從III族氮化物半導體層20的外周部22往中央部21延伸的裂縫23,裂縫23停止於空隙的位置。根據以光學顯微鏡觀察的評價可確認,III族氮化物半導體層20之中央部21的表面為鏡面。 The inventors of the present invention observed the surface of the group III nitride semiconductor layer 20 in the epitaxial wafer 1 of the present embodiment with an optical microscope. According to the evaluation by the optical microscope, it is found that voids are formed in the outer peripheral portion 22 of the group III nitride semiconductor layer 20 in a plane size of several μm to 10 μm. The void density in the outer peripheral portion 22 is about 10 to 100 / mm 2 . Moreover, it was confirmed from the evaluation by the optical microscope that the number of the cracks 23 in the outer peripheral portion 22 was smaller than that of Comparative Example 1 in which the concave portion 13 was not formed in the wafer 10. As a result of observation by an optical microscope, it was confirmed that the crack 23 extending from the outer peripheral portion 22 of the group III nitride semiconductor layer 20 toward the central portion 21 was not observed, and the crack 23 was stopped at the position of the void. From the evaluation by observation with an optical microscope, it was confirmed that the surface of the central portion 21 of the group III nitride semiconductor layer 20 was a mirror surface.
另外,本案發明人,以SEM觀察本實施例之磊晶晶圓1的剖面。從剖面的SEM影像來看,本案發明人判斷,III族氮化物半導體層20的外周部22,與中央部21相比,在縱向上的成長速率較快,於橫方向上的成長速率較慢。 Further, the inventors of the present invention observed the cross section of the epitaxial wafer 1 of the present embodiment by SEM. From the SEM image of the cross section, the inventors of the present invention judged that the outer peripheral portion 22 of the group III nitride semiconductor layer 20 has a faster growth rate in the longitudinal direction and a slower growth rate in the lateral direction than the central portion 21. .
另外,本案發明人,對於III族氮化物半導體層20,以X光繞射法,分別評價中央部21與外周部22的結晶結構。在根據X光繞射法的結晶結構的評價中,得到「中央部21與外周部22皆為單晶」的結果。 Further, the inventors of the present invention evaluated the crystal structures of the central portion 21 and the outer peripheral portion 22 by the X-ray diffraction method for the group III nitride semiconductor layer 20, respectively. In the evaluation of the crystal structure by the X-ray diffraction method, "the central portion 21 and the outer peripheral portion 22 were both single crystals" were obtained.
另外,本案發明人,對於III族氮化物半導體層20,為了分別評價中央部21與外周部22的結晶性,對AlN的(10-12)面進行X光繞射的ω掃描。此處,X光繞射的ω掃描,係顯示結晶在c軸方向上波動之程度的指標。X光繞射的ω掃描,所得到的X光搖擺曲線(XRC;X-ray Rocking Curve)的半值寬,其外周部22的半值寬約小於中央部21的半值寬50arcsec左右,外周部22及中央部21的結晶性皆為良好。 Further, in the case of the group III nitride semiconductor layer 20, in order to evaluate the crystallinity of the central portion 21 and the outer peripheral portion 22, respectively, the (10-12) plane of AlN is subjected to X-ray diffraction of X-ray diffraction. Here, the ω scan of the X-ray diffraction is an index indicating the degree of crystallization of the crystal in the c-axis direction. The ω scan of the X-ray diffraction has a half-value width of the X-ray Rocking Curve (XRC), and the half-value width of the outer peripheral portion 22 is smaller than the half-value width of the central portion 21 by about 50 arcsec. Both the portion 22 and the central portion 21 have good crystallinity.
根據X光搖擺曲線所得到的III族氮化物半導體層20的(0002)面及(10-12)面的半值寬,分別約為200arcsec及400~500arcsec。又,本案發明 人在實驗上確認,從形成於磊晶晶圓1中的紫外光半導體發光元件3的光輸出率的觀點來看,只要(10-12)面的半值寬在500arcsec以下,就具有足夠的結晶性。 The half value widths of the (0002) plane and the (10-12) plane of the group III nitride semiconductor layer 20 obtained from the X-ray rocking curve are about 200 arcsec and 400 to 500 arcsec, respectively. Also, the invention of the present invention It has been experimentally confirmed that from the viewpoint of the light output rate of the ultraviolet semiconductor light-emitting element 3 formed in the epitaxial wafer 1, as long as the half value width of the (10-12) plane is 500 arcsec or less, it is sufficient. Crystallinity.
(實施例2) (Example 2)
本實施例中,根據上述的實施態樣中所說明的磊晶晶圓1之製造方法,製造磊晶晶圓1。 In the present embodiment, the epitaxial wafer 1 is manufactured according to the method of manufacturing the epitaxial wafer 1 described in the above embodiment.
在製造磊晶晶圓1時,首先,準備一表面10aa為(0001)面,直徑為50.8mm的藍寶石晶圓,作為晶圓10。 When the epitaxial wafer 1 is manufactured, first, a sapphire wafer having a surface 10aa of a (0001) plane and a diameter of 50.8 mm is prepared as the wafer 10.
之後,磊晶晶圓1之製造方法中,以旋轉塗佈機將光阻塗佈於晶圓10的另一表面10ab上,並藉由使用灰階光罩的光微影技術,形成圓錐台狀地圖案化的光阻層。 Thereafter, in the method of manufacturing the epitaxial wafer 1, a photoresist is applied to the other surface 10ab of the wafer 10 by a spin coater, and a truncated cone is formed by photolithography using a gray scale mask. A patterned photoresist layer.
之後,在磊晶晶圓1之製造方法中,進行使用Cl2氣體的乾式蝕刻,藉此在晶圓10的另一表面10ab上形成推拔面14。此時,推拔面14中,使晶圓10的邊緣寬度約為5mm,並使晶圓10的邊緣的深度尺寸為約3μm。 Thereafter, in the method of manufacturing the epitaxial wafer 1, dry etching using a Cl 2 gas is performed, whereby the push surface 14 is formed on the other surface 10ab of the wafer 10. At this time, in the push surface 14, the edge width of the wafer 10 is made approximately 5 mm, and the depth of the edge of the wafer 10 is about 3 μm.
之後,在磊晶晶圓1之製造方法中,於去除光阻層之後洗淨晶圓10,接著使晶圓10乾燥。 Thereafter, in the method of manufacturing the epitaxial wafer 1, the wafer 10 is cleaned after the photoresist layer is removed, and then the wafer 10 is dried.
之後,在磊晶晶圓1之製造方法中,將晶圓10導入有機金屬氣相磊晶裝置的反應爐內,並將晶圓10的另一表面10ab設於載置台。 Thereafter, in the method of manufacturing the epitaxial wafer 1, the wafer 10 is introduced into a reactor of an organometallic vapor phase epitaxy apparatus, and the other surface 10ab of the wafer 10 is placed on a mounting table.
在將晶圓10設於載置台後,進行反應爐內部的真空抽氣。 After the wafer 10 is placed on the mounting table, vacuum evacuation inside the reaction furnace is performed.
磊晶晶圓1之製造方法,在進行反應爐的真空抽氣之後,將作為載體的H2氣體供給至反應爐內,一邊使反應爐內的壓力保持於規定壓力,一邊將基板溫度升溫至1300℃。此處,規定壓力為10kPa。磊晶晶圓1之製造 方法中,在將基板溫度升溫至1300℃之後,藉由同時供給TMA與NH3的同時供給成長法,使III族氮化物半導體層20在晶圓10上成長。磊晶晶圓1之製造方法中所形成的磊晶晶圓1,係在晶圓10上形成有以膜厚為4μm的AlN層所構成的III族氮化物半導體層20。TMA的流量為200SCCM。載體的H2氣體的流量為100SLM。NH3的流量為1SLM。 In the method for producing the epitaxial wafer 1, after the vacuum pumping of the reactor is performed, the H 2 gas as a carrier is supplied into the reactor, and the temperature of the substrate is raised while maintaining the pressure in the reactor at a predetermined pressure. 1300 ° C. Here, the predetermined pressure is 10 kPa. In the method of manufacturing the epitaxial wafer 1, after the substrate temperature is raised to 1300 ° C, the group III nitride semiconductor layer 20 is grown on the wafer 10 by simultaneously supplying a growth method of TMA and NH 3 simultaneously. In the epitaxial wafer 1 formed in the method of manufacturing the epitaxial wafer 1, a group III nitride semiconductor layer 20 composed of an AlN layer having a film thickness of 4 μm is formed on the wafer 10. The flow rate of the TMA is 200 SCCM. The flow rate of the H 2 gas of the carrier was 100 SLM. The flow rate of NH 3 is 1 SLM.
在將基板溫度降溫至室溫附近後,從有機金屬氣相磊晶裝置取出磊晶晶圓1。 After the substrate temperature is lowered to near room temperature, the epitaxial wafer 1 is taken out from the organometallic vapor phase epitaxy apparatus.
本案發明人,以光學顯微鏡觀察本實施例之磊晶晶圓1中的III族氮化物半導體層20的表面。根據以光學顯微鏡觀察的評價可得知,與實施例1相同,III族氮化物半導體層20的外周部22中,在數μm~10μm左右的平面尺寸中產生空隙。外周部22中的空隙密度,約為10~100個/mm2左右。另外,根據以光學顯微鏡觀察的評價可確認,與晶圓10中未形成推拔面14的比較例1相比,外周部22中的裂縫23的數量減少。根據以光學顯微鏡觀察的評價可確認,並未觀察到從III族氮化物半導體層20的外周部22往中央部21延伸的裂縫23,且裂縫23停止於空隙的位置。根據以光學顯微鏡觀察的評價可確認,中央部21的表面為鏡面。 The inventors of the present invention observed the surface of the group III nitride semiconductor layer 20 in the epitaxial wafer 1 of the present embodiment with an optical microscope. According to the evaluation by the optical microscope, it is found that, as in the first embodiment, the outer peripheral portion 22 of the group III nitride semiconductor layer 20 has voids in a planar size of about several μm to 10 μm. The void density in the outer peripheral portion 22 is about 10 to 100 / mm 2 . In addition, it was confirmed from the evaluation by the optical microscope that the number of the cracks 23 in the outer peripheral portion 22 was smaller than that of Comparative Example 1 in which the push surface 14 was not formed in the wafer 10. As a result of observation by an optical microscope, it was confirmed that the crack 23 extending from the outer peripheral portion 22 of the group III nitride semiconductor layer 20 toward the central portion 21 was not observed, and the crack 23 was stopped at the position of the void. From the evaluation by observation with an optical microscope, it was confirmed that the surface of the central portion 21 was a mirror surface.
另外,在藉由X光繞射法的結晶結構的評價中,與實施例1相同,中央部21與外周部22皆為單晶。 Further, in the evaluation of the crystal structure by the X-ray diffraction method, the central portion 21 and the outer peripheral portion 22 were all single crystals as in the first embodiment.
另外,本案發明人,對AlN的(10-12)面進行X光繞射的ω掃描。藉由X光繞射的ω掃描所得到的X光搖擺曲線的半值寬中,外周部22的半值寬雖比中央部21的半值寬低50arcsec左右,但外周部22及中央部21的結晶性皆為良好。 Further, the inventors of the present invention performed ω scanning of X-ray diffraction on the (10-12) plane of AlN. In the half value width of the X-ray rocking curve obtained by the ω scanning of the X-ray diffraction, the half value width of the outer peripheral portion 22 is lower than the half value width of the central portion 21 by about 50 arcsec, but the outer peripheral portion 22 and the central portion 21 are The crystallinity is good.
另外,根據X光搖擺曲線所得到的III族氮化物半導體層20的(0002)面及(10-12)面的半值寬,分別約為200arcsec及400~500arcsec。 Further, the half value widths of the (0002) plane and the (10-12) plane of the group III nitride semiconductor layer 20 obtained from the X-ray rocking curve are about 200 arcsec and 400 to 500 arcsec, respectively.
(實施例3) (Example 3)
本實施例中,根據上述實施態樣中所說明的磊晶晶圓1之製造方法,製造磊晶晶圓1。 In the present embodiment, the epitaxial wafer 1 is manufactured according to the method of manufacturing the epitaxial wafer 1 described in the above embodiment.
在製造磊晶晶圓1時,首先,準備一表面10aa為(0001)面,直徑為50.8mm的藍寶石晶圓作為晶圓10。 When manufacturing the epitaxial wafer 1, first, a sapphire wafer having a surface 10aa of a (0001) plane and a diameter of 50.8 mm is prepared as the wafer 10.
之後,在磊晶晶圓1之製造方法中,以高頻濺鍍裝置在晶圓10的一表面10aa上形成氮化矽膜。之後,在磊晶晶圓1之製造方法中,使用光微影技術及蝕刻技術,以使晶圓10的一表面10aa中從晶圓10的邊緣約4mm處的除外區域12露出的方式,使氮化矽膜圖案化。 Thereafter, in the method of manufacturing the epitaxial wafer 1, a tantalum nitride film is formed on one surface 10aa of the wafer 10 by a high-frequency sputtering apparatus. Thereafter, in the method of manufacturing the epitaxial wafer 1, a photolithography technique and an etching technique are used to expose one surface 10aa of the wafer 10 from the exclusion region 12 at an edge of the wafer 10 of about 4 mm. The tantalum nitride film is patterned.
之後,在磊晶晶圓1之製造方法中,進行改質化處理。該改質化處理中,於ECR電漿裝置中產生N2電漿,並在晶圓10的一表面10aa側的除外區域12形成改質層15。 Thereafter, in the method of manufacturing the epitaxial wafer 1, a reforming process is performed. In the reforming process, N 2 plasma is generated in the ECR plasma apparatus, and the reforming layer 15 is formed on the exclusion region 12 on the one surface 10aa side of the wafer 10.
之後,在磊晶晶圓1之製造方法中,以蝕刻去除氮化矽膜。 Thereafter, in the method of manufacturing the epitaxial wafer 1, the tantalum nitride film is removed by etching.
之後,在磊晶晶圓1之製造方法中洗淨晶圓10,接著使晶圓10乾燥。 Thereafter, the wafer 10 is cleaned in the method of manufacturing the epitaxial wafer 1, and then the wafer 10 is dried.
之後,在磊晶晶圓1之製造方法中,將晶圓10導入有機金屬氣相磊晶裝置的反應爐內,並將晶圓10的另一表面10ab設於載置台。 Thereafter, in the method of manufacturing the epitaxial wafer 1, the wafer 10 is introduced into a reactor of an organometallic vapor phase epitaxy apparatus, and the other surface 10ab of the wafer 10 is placed on a mounting table.
在將晶圓10設於載置台之後,進行反應爐內部的真空抽氣。 After the wafer 10 is placed on the mounting table, vacuum evacuation inside the reaction furnace is performed.
磊晶晶圓1之製造方法中,在進行反應爐的真空抽氣之後,將載體的H2氣體供給至反應爐內,一邊使反應爐內的壓力保持於規定壓力,一邊將基板溫度升溫至1300℃。此處,規定壓力為10kPa。磊晶晶圓1之製造方法中,在將基板溫度升溫至1300℃後,將同時供給TMA與NH3的「同時供給成長法」,與連續供給TMA且間歇性地供給NH3以使其成長的「脈衝 供給成長法」組合,以使III族氮化物半導體層20於晶圓10上成長。磊晶晶圓1之製造方法中所形成的磊晶晶圓1,係在晶圓10上形成有以膜厚為4μm的AlN層所構成的III族氮化物半導體層20。TMA的流量為200SCCM。載體的H2氣體的流量為100SLM。NH3的流量為1SLM。 In the method of manufacturing the epitaxial wafer 1, after the vacuum pumping of the reactor is performed, the carrier H 2 gas is supplied into the reactor, and the substrate temperature is raised while maintaining the pressure in the reactor at a predetermined pressure. 1300 ° C. Here, the predetermined pressure is 10 kPa. In the method of manufacturing the epitaxial wafer 1, after the temperature of the substrate is raised to 1300 ° C, the simultaneous supply of TMA and NH 3 is simultaneously supplied, and TMA is continuously supplied and NH 3 is intermittently supplied to grow. The "pulse supply growth method" is combined to grow the group III nitride semiconductor layer 20 on the wafer 10. In the epitaxial wafer 1 formed in the method of manufacturing the epitaxial wafer 1, a group III nitride semiconductor layer 20 composed of an AlN layer having a film thickness of 4 μm is formed on the wafer 10. The flow rate of the TMA is 200 SCCM. The flow rate of the H 2 gas of the carrier was 100 SLM. The flow rate of NH 3 is 1 SLM.
在基板溫度降溫至室溫附近後,從有機金屬氣相磊晶裝置取出磊晶晶圓1。 After the substrate temperature is lowered to near room temperature, the epitaxial wafer 1 is taken out from the organometallic vapor phase epitaxy apparatus.
本案發明人,以光學顯微鏡觀察本實施例之磊晶晶圓1中的III族氮化物半導體層20的表面。根據以光學顯微鏡觀察的評價可得知,III族氮化物半導體層20的外周部22中,產生平面尺寸為數μm的突起24(參照圖7)。外周部22中的突起24的密度,約為100~1000個/mm2左右。另外,根據以光學顯微鏡觀察的評價可確認,與晶圓10中未形成改質層15的比較例1相比,外周部22中的裂縫23的數量減少。根據以光學顯微鏡觀察的評價可確認,未觀察到從III族氮化物半導體層20的外周部22往中央部21延伸的裂縫23,且裂縫23停止於突起24的位置。根據以光學顯微鏡觀察的評價可確認,中央部21的表面為鏡面。 The inventors of the present invention observed the surface of the group III nitride semiconductor layer 20 in the epitaxial wafer 1 of the present embodiment with an optical microscope. According to the evaluation by the optical microscope, it is found that the protrusions 24 having a planar size of several μm are formed in the outer peripheral portion 22 of the group III nitride semiconductor layer 20 (see FIG. 7). The density of the projections 24 in the outer peripheral portion 22 is about 100 to 1000 pieces/mm 2 . Moreover, it was confirmed from the evaluation by the optical microscope that the number of the cracks 23 in the outer peripheral portion 22 was smaller than that of Comparative Example 1 in which the modified layer 15 was not formed in the wafer 10. As a result of observation by an optical microscope, it was confirmed that the crack 23 extending from the outer peripheral portion 22 of the group III nitride semiconductor layer 20 toward the central portion 21 was not observed, and the crack 23 was stopped at the position of the projection 24. From the evaluation by observation with an optical microscope, it was confirmed that the surface of the central portion 21 was a mirror surface.
另外,藉由X光繞射法的結晶結構的評價中,與實施例1相同,可得到「中央部21與外周部22皆為單晶」的結果。 In addition, in the evaluation of the crystal structure of the X-ray diffraction method, as in the first embodiment, the result of "the central portion 21 and the outer peripheral portion 22 are single crystals" can be obtained.
另外,本案發明人,對AlN的(10-12)面進行X光繞射的ω掃描。藉由X光繞射的ω掃描所得到的X光搖擺曲線的半值寬中,外周部22的半值寬雖比中央部21的半值寬低50arcsec左右,但外周部22及中央部21的結晶性皆為良好。 Further, the inventors of the present invention performed ω scanning of X-ray diffraction on the (10-12) plane of AlN. In the half value width of the X-ray rocking curve obtained by the ω scanning of the X-ray diffraction, the half value width of the outer peripheral portion 22 is lower than the half value width of the central portion 21 by about 50 arcsec, but the outer peripheral portion 22 and the central portion 21 are The crystallinity is good.
另外,藉由X光搖擺曲線所得到的III族氮化物半導體層20的(0002)面及(10-12)面的半值寬,分別約為200arcsec及400~500arcsec。 Further, the half value widths of the (0002) plane and the (10-12) plane of the group III nitride semiconductor layer 20 obtained by the X-ray rocking curve are about 200 arcsec and 400 to 500 arcsec, respectively.
(實施例4) (Example 4)
本實施例中,根據上述的實施態樣中所說明的磊晶晶圓1之製造方法,製造磊晶晶圓1。 In the present embodiment, the epitaxial wafer 1 is manufactured according to the method of manufacturing the epitaxial wafer 1 described in the above embodiment.
在製造磊晶晶圓1時,首先,準備一表面10aa為(0001)面,直徑為50.8mm的藍寶石晶圓,作為晶圓10。 When the epitaxial wafer 1 is manufactured, first, a sapphire wafer having a surface 10aa of a (0001) plane and a diameter of 50.8 mm is prepared as the wafer 10.
之後,在磊晶晶圓1之製造方法中,以高頻濺鍍裝置,在晶圓10的一表面10aa上形成氮化矽膜。之後,磊晶晶圓1之製造方法中,使用光微影技術及蝕刻技術,以在晶圓10的一表面10aa中,以使從晶圓10的邊緣約4mm處之除外區域12露出的方式,將氮化矽膜圖案化。 Thereafter, in the method of manufacturing the epitaxial wafer 1, a tantalum nitride film is formed on one surface 10aa of the wafer 10 by a high-frequency sputtering apparatus. Thereafter, in the method of manufacturing the epitaxial wafer 1, a photolithography technique and an etching technique are employed to expose the exclusion region 12 at about 4 mm from the edge of the wafer 10 on one surface 10aa of the wafer 10. The tantalum nitride film is patterned.
之後,磊晶晶圓1之製造方法中,進行改質化處理。該改質化處理中,在大氣氛圍下,以900℃進行退火1小時,藉此在晶圓10的一表面10aa側的除外區域12上形成改質層15。 Thereafter, in the method of manufacturing the epitaxial wafer 1, a reforming process is performed. In the reforming treatment, the modified layer 15 is formed on the exclusion region 12 on the one surface 10aa side of the wafer 10 by annealing at 900 ° C for 1 hour in an air atmosphere.
之後,在磊晶晶圓1之製造方法中,以蝕刻去除氮化矽膜。 Thereafter, in the method of manufacturing the epitaxial wafer 1, the tantalum nitride film is removed by etching.
之後,在磊晶晶圓1之製造方法中,將晶圓10洗淨,接著使晶圓10乾燥。 Thereafter, in the method of manufacturing the epitaxial wafer 1, the wafer 10 is washed, and then the wafer 10 is dried.
之後,在磊晶晶圓1之製造方法中,將晶圓10導入有機金屬氣相磊晶裝置的反應爐內,並將晶圓10的另一表面10ab設於載置台。 Thereafter, in the method of manufacturing the epitaxial wafer 1, the wafer 10 is introduced into a reactor of an organometallic vapor phase epitaxy apparatus, and the other surface 10ab of the wafer 10 is placed on a mounting table.
在將晶圓10設於載置台後,進行反應爐內部的真空抽氣。 After the wafer 10 is placed on the mounting table, vacuum evacuation inside the reaction furnace is performed.
磊晶晶圓1之製造方法中,在進行反應爐的真空抽氣之後,將作為載體的H2氣體供給至反應爐內,一邊使反應爐內的壓力保持於規定壓力,一邊將基板溫度上升至1300℃。此處,規定壓力為10kPa。磊晶晶圓1之製造方法中,在基板溫度升溫至1300℃之後,將TMA與NH3同時供給的「同時供給成長法」,及連續供給TMA且間歇性供給NH3以使其成長的「脈衝 供給成長法」組合,以使III族氮化物半導體層20在晶圓10上成長。磊晶晶圓1之製造方法中所形成的磊晶晶圓1,係在晶圓10上形成有以膜厚為4μm的AlN層所構成之III族氮化物半導體層20。TMA的流量為200SCCM。載體的H2氣體的流量為100SLM。NH3的流量為1SLM。 In the method of manufacturing the epitaxial wafer 1, after the vacuum pumping of the reactor is performed, the H 2 gas as a carrier is supplied into the reactor, and the substrate temperature is raised while maintaining the pressure in the reactor at a predetermined pressure. To 1300 ° C. Here, the predetermined pressure is 10 kPa. In the method of manufacturing the epitaxial wafer 1, after the temperature of the substrate is raised to 1300 ° C, the "simultaneous supply growth method" in which TMA and NH 3 are simultaneously supplied, and the continuous supply of TMA and the intermittent supply of NH 3 are allowed to grow. The pulse supply growth method is combined to grow the group III nitride semiconductor layer 20 on the wafer 10. In the epitaxial wafer 1 formed in the method of manufacturing the epitaxial wafer 1, a group III nitride semiconductor layer 20 composed of an AlN layer having a film thickness of 4 μm is formed on the wafer 10. The flow rate of the TMA is 200 SCCM. The flow rate of the H 2 gas of the carrier was 100 SLM. The flow rate of NH 3 is 1 SLM.
在基板溫度降溫至室溫附近後,從有機金屬氣相磊晶裝置取出磊晶晶圓1。 After the substrate temperature is lowered to near room temperature, the epitaxial wafer 1 is taken out from the organometallic vapor phase epitaxy apparatus.
本案發明人,以光學顯微鏡觀察本實施例之磊晶晶圓1中的III族氮化物半導體層20的表面。根據以光學顯微鏡觀察的評價可得知,III族氮化物半導體層20的外周部22中,產生平面尺寸為數μm的突起24(參照圖8)。III族氮化物半導體層20中,在圖8的紙面上,向上的方向中,無突起24部分之面方位為<0002>,相對於此,突起24部分的面方位為<11-20>。簡而言之,突起24部分的面方位,與無突起24部分的面方位係為不同的方位。 The inventors of the present invention observed the surface of the group III nitride semiconductor layer 20 in the epitaxial wafer 1 of the present embodiment with an optical microscope. According to the evaluation by the optical microscope, it is found that the protrusions 24 having a planar size of several μm are formed in the outer peripheral portion 22 of the group III nitride semiconductor layer 20 (see FIG. 8). In the group III nitride semiconductor layer 20, the plane orientation of the portion having no protrusions 24 in the upward direction on the paper surface of Fig. 8 is <0002>, whereas the plane orientation of the portion of the protrusions 24 is <11-20>. In short, the plane orientation of the portion of the protrusion 24 is different from the plane orientation of the portion without the protrusion 24.
外周部22中的突起24的密度,約為100~1000個/mm2左右。另外,根據以光學顯微鏡觀察的評價可確認,與晶圓10中未形成改質層15的比較例1相比,外周部22中的裂縫23的數量減少。根據以光學顯微鏡觀察的評價可確認,未觀察到從III族氮化物半導體層20的外周部22往中央部21延伸的裂縫23,且裂縫23停止於突起24的位置。根據以光學顯微鏡觀察的評價可確認,中央部21的表面為鏡面。 The density of the projections 24 in the outer peripheral portion 22 is about 100 to 1000 pieces/mm 2 . Moreover, it was confirmed from the evaluation by the optical microscope that the number of the cracks 23 in the outer peripheral portion 22 was smaller than that of Comparative Example 1 in which the modified layer 15 was not formed in the wafer 10. As a result of observation by an optical microscope, it was confirmed that the crack 23 extending from the outer peripheral portion 22 of the group III nitride semiconductor layer 20 toward the central portion 21 was not observed, and the crack 23 was stopped at the position of the projection 24. From the evaluation by observation with an optical microscope, it was confirmed that the surface of the central portion 21 was a mirror surface.
另外,藉由X光繞射法之結晶結構的評價中,與實施例1相同,可得到「中央部21與外周部22皆為單晶」的結果。 In addition, in the evaluation of the crystal structure of the X-ray diffraction method, as in the first embodiment, the result of "the central portion 21 and the outer peripheral portion 22 are single crystals" can be obtained.
另外,本案發明人,對AlN的(10-12)面進行X光繞射的ω掃描。藉由X光繞射的ω掃描所得到的X光搖擺曲線的半值寬中,外周部22的半值寬雖比中央部21的半值寬低50arcsec左右,但外周部22及中央部21的結晶性皆為良好。 Further, the inventors of the present invention performed ω scanning of X-ray diffraction on the (10-12) plane of AlN. In the half value width of the X-ray rocking curve obtained by the ω scanning of the X-ray diffraction, the half value width of the outer peripheral portion 22 is lower than the half value width of the central portion 21 by about 50 arcsec, but the outer peripheral portion 22 and the central portion 21 are The crystallinity is good.
另外,藉由X光搖擺曲線所得到的III族氮化物半導體層20的(0002)面及(10-12)面的半值寬,分別約為200arcsec及400~500arcsec。 Further, the half value widths of the (0002) plane and the (10-12) plane of the group III nitride semiconductor layer 20 obtained by the X-ray rocking curve are about 200 arcsec and 400 to 500 arcsec, respectively.
又,本實施例中,以在O2氣體氛圍中退火的氧化處理,及以O2電漿照射進行氧化處理,代替在大氣氛圍中退火的氧化處理,以作為改質化處理的情況中,亦得到同樣的結果。 Further, in the present embodiment, in the case where the oxidation treatment is performed by annealing in an O 2 gas atmosphere and the oxidation treatment is performed by irradiation with O 2 plasma instead of the oxidation treatment which is annealed in an atmospheric atmosphere, as a reforming treatment, The same result was obtained.
1‧‧‧磊晶晶圓 1‧‧‧ epitaxial wafer
10‧‧‧晶圓 10‧‧‧ wafer
10aa、10ab‧‧‧表面 10aa, 10ab‧‧‧ surface
11‧‧‧應用區域 11‧‧‧Application area
12‧‧‧除外區域 12‧‧‧Excluded areas
20‧‧‧III族氮化物半導體層 20‧‧‧III nitride semiconductor layer
21‧‧‧中央部 21‧‧‧Central Department
22‧‧‧外周部 22‧‧‧The outer part
23‧‧‧裂縫 23‧‧‧ crack
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