TW201414146A - Power conversion control chip and device thereof - Google Patents

Abstract

A power conversion control chip and a device thereof are disclosed, the device being a primary control flyback conversion circuit. The chip comprises a monitoring unit, a peak value sensing unit, an analyzing unit, and a driving unit. A D-type flip flop of the monitoring unit is used to monitor the output voltage variation of the device and output a monitoring signal or a reset signal. The peak value sensing unit is used to sense the input peak flow of the device and output a peak value signal. A multiplier of the analyzing unit multiplies the monitoring signal or the reset signal with the peak value signal, and forms a driving signal or an initial signal after comparing and contrasting a reference value with the analyzing unit so as to drive the driving unit for conducting or stopping a current switch of the device and adjust the voltage input conducting time of the device to ensure current output.

Description

Power conversion control chip and device thereof

The present invention relates to the technical field of switching power supply equipment, and more particularly to a power conversion control chip and a device thereof using a primary side control flyback conversion circuit as an architecture, so as to improve the frequency cut time and further improve the power conversion efficiency, and Reduce virtual power consumption and reduce noise.

Switch Power Supply (SPS) commonly has fly-back, forward and push-pull conversion control circuit architectures, and has high efficiency and volume. Small, lightweight, easy to assemble and large output voltage range, it can improve the quality of work and is widely used in various electronic devices. For example, the flyback architecture is taken as an example, as shown in FIG. 1 , which is a circuit diagram of a conventional primary side control flyback power conversion control device. The device 1 is provided with a rectifier 10 , a control chip 12 , and a control chip 12 . The coupling transformer 11 is provided with a primary side coil (N _P ), a secondary side coil (N _S ) and an auxiliary coil ( _{A A} ), and the primary side coil is connected in series with a current switch 120 and a current resistor. The control coil 12 is coupled to the auxiliary coil in series with a voltage dividing resistor 122. After the rectifier 10 receives and rectifies one of the AC currents of the mains, the primary side coil stores an initial current (I _P ), and the secondary side coil and the auxiliary coil respectively form an output current (I _O And a monitoring current (I _D ). In this manner, the control chip 12 senses the peak voltage value of the primary side current by the current resistor 121, and monitors the peak value of the output current by the voltage dividing resistor 122, and then analyzes the peak pressure value and the variation value to switch. The current switch 120 operates to increase or decrease the on-current of the primary side current to adjust the output voltage value to reduce the virtual power consumption and improve the conversion efficiency of the overall circuit.

In view of this, the primary side control flyback power conversion control device 1 adjusts the power switching frequency by the control chip 12, so how to further accurately analyze the operation result and improve the output time of the cut frequency signal by changing the internal circuit thereof. Control parameters such as voltage value and conduction period to further reduce noise, Total Harmonic Distortion (THD) and overall circuit virtual power consumption to improve the power factor (Power Factor), which is the solution of the present invention. The subject.

In view of the problems of the prior art, the present invention aims to provide a power conversion control chip and a device thereof, which can reduce the virtual power consumption of the whole circuit by adjusting the frequency cut time by the primary side control, thereby further improving the power conversion efficiency and reducing the noise. It is suitable for light-emitting diode lighting equipment and LCD TV backlight module.

According to the purpose of the present invention, the power conversion control chip is used in a Primary Side Control for Flyback Converter (Discontinuous Conduction Mode) (DCM) for control output. The power flow improves the power factor, and the conversion circuit has a coupling transformer provided with a primary side coil (N _P ), a secondary side coil (N _S ) and an auxiliary coil (N _A ), and the primary side The coil is connected in series with a current switch and a current resistor (R _CS ) to form a primary current (I _P ) after receiving the compressive energy, and a voltage drop is formed across the current resistor, and the secondary side The coil and the auxiliary coil respectively induce an output current (I _O ) and a monitoring current (I _D ), and the auxiliary coil is connected in series with a voltage dividing resistor to form a voltage drop (V _D ) at both ends thereof. The power conversion control chip includes a monitoring unit, a peak sensing unit, an analyzing unit and a driving unit. The monitoring unit is provided with a D-type flip-flop, and the signal input pin is electrically connected to the primary side coil and the reset signal. The pin is connected to the voltage dividing resistor to monitor and compare the voltage drop across the voltage dividing resistor with a threshold value. When the voltage drop across the voltage dividing resistor is greater than the threshold, the D type The flip-flop generates a monitoring signal, and vice versa generates a reset signal.

The peak sensing unit is connected to the primary side coil through a current resistance of the conversion circuit to sense and compare a voltage drop formed by the primary side current across the current resistance and a peak voltage limit to generate a peak value. Signal. The analyzing unit is provided with a multiplier for receiving the reset signal, the monitoring signal and the peak signal by the telecommunication connection of the monitoring unit and the output end of the peak sensing unit, and the output end of the analyzing unit is telecommunicationally connected to the D type The clock pin of the flip-flop, and after the reset signal and the monitor signal respectively multiply the peak signal, the reference value (V _ref ) is compared and amplified to form a differential pressure value, and when the differential pressure value is less than a lower limit A drive signal is output when the value is output, and an initial signal is output when the differential pressure value is greater than an upper limit value. The driving unit is connected to the analyzing unit and is connected to the primary side coil through a current switch of the conversion circuit. The driving unit receives the initial signal to turn off the current switch, or receives the driving signal and turns on the current switch to adjust The on-time of the primary side current adjusts the magnitude of the output current.

The monitoring unit is provided with a high voltage low drop out linear regulator (HV LDO) and an inverse comparator. The high voltage linear regulator is coupled to the input end of the primary side coil and the type D The signal input pin of the flip-flop is used to regulate the input power. After the current is output to the D-type flip-flop; the positive input terminal of the reverse comparator is coupled to the voltage dividing resistor, the negative input terminal inputs the threshold value, and the output terminal is coupled to the reset signal of the D-type flip-flop device Feet. The analyzing unit is provided with a first comparator, a certain frequency wave generator and an RS flip-flop. The first comparator is connected to the multiplier by the first comparator, and the negative input terminal receives the differential pressure value and a compensation value. The input end is coupled to the fixed frequency wave generator to receive a triangular wave to form the upper limit value and the lower limit value, compare the compensated differential pressure value, and output the driving signal or the initial signal to the RS forward and reverse device Reset the input pin. The output pin of the RS flip-flop is coupled to the clock pin of the D-type flip-flop through an inverter, and the set input pin is coupled to the fixed-wave generator to receive a square wave and a positive edge Trigger the D-type flip-flop.

Moreover, the peak sensing unit is provided with a signal generator and a sample and hold (SAH) device, and the signal generator is configured to generate a sampling signal having a frequency of 1/2 of the primary side current conducting period. Counting, and the sample holder is coupled to the current resistor and the signal generator, and sampling the voltage drop across the current resistor at each time point according to the sampling signal triggering, so that the conversion circuit operates in a continuous conduction mode (Continuous Conduction) Mode, CCM). The sample holder is sampled at the center of the primary side current cutoff period, or is sampled at the beginning and end of the primary side current cutoff period.

In this embodiment, the power conversion control chip further includes a current limiting unit, which is connected to the monitoring unit, the voltage dividing resistor, the current resistor and the analyzing unit, and when the current switch is turned on, the monitoring unit is reversely discharged. One of the values of the current limiting current forms a current limiting value across the voltage dividing resistor, so that the current limiting unit compares the current limiting value with the voltage across the current resistor When the primary current is greater than the allowable current limit value, the analyzing unit outputs the initial signal, and the voltage dividing resistor is a variable resistor to adjust the current limiting current.

In addition, according to a second object of the present invention, a primary side control flyback conversion circuit architecture is connected to one of the external power sources to output a stable output current to drive at least one light emitting diode group, which includes a rectifier module. , an energy storage module, a control module and an output module. The rectifier module is coupled to the power source and receives and rectifies a variable one of the alternating currents. The energy storage module is provided with a coupling transformer. The coupling transformer is provided with a primary side coil, a secondary side coil and an auxiliary coil. The primary side coil is coupled to the output end of the rectifier module to receive the rectified alternating current. After the storage energy forms a primary current, the secondary coil and the auxiliary coil respectively induce an output current and a monitoring current.

The control module is provided with a power conversion control chip, a voltage dividing resistor, a current switch and a current resistor, and the voltage dividing resistor is coupled to the auxiliary coil and the monitoring unit, and the monitoring unit is coupled to the storage capacitor And the input end of the primary side coil; the current switch is an N-type MOSFET, the drain is coupled to the output end of the primary side coil, and the source is coupled to the current resistor and the peak sensing unit The control module is coupled to the driving unit through the monitoring unit, and the amount of change of the monitoring current is obtained by the monitoring unit, and the amount of change of the primary current is obtained through the peak sensing unit, and is calculated by the analyzing unit. The driving unit is turned on or off to compensate or bleed the primary side current to maintain the output current in a constant current state. The output module is provided with a diode and an output capacitor. The diode is connected in series with the secondary coil, and the output capacitor and the LED are connected to the LED. Rectification The output capacitor is filtered and output to the light emitting diode.

In summary, the peak value of the output current (I _OP ) of the present invention is the peak of the primary side current (I _PP ) and the product of the primary side coil and the secondary side coil, and when the primary side current works The period is T, where the on period is T _ON and the off period is T _OFF , the average value of the output current I _O(avg) = (1/2) ^* (N _P /N _S ) ^* (V _ref /R _CS ) ^* (1/T). Since T and V _ref are constant values, and V _ref is the T main design parameter, I _O(avg) is not changed by the parameter change of the control wafer, and is in a completely constant current state.

In DCM mode, when I _P completely releases energy at T _OFF , I _{O is} weakened, and below the threshold voltage of the diode, there is no I _O output, and the voltage drop across the voltage dividing resistor ( V _D ) will exhibit a period of jitter, and I _{O will be} weaker than the critical pressure of the diode before T _OFF1 , then T _OFF2 , I _O(avg) = (1/2) ^* I _PP ^* (T _OFF1 /T) ^* (N _P /N _S ). Furthermore, in the CCM mode, since the I _{P does} not completely release the energy, the next cycle is started, so the I _P at the start of the next T _ON has a first-class value (I _P1 ), so that I _O(avg) = ( 1/2) ^* (I _PP +I _P1 ) ^* (T _OFF /T) ^* (N _P /N _S ), so that problems such as T _OFF1 and T _OFF2 are not generated, and electromagnetic interference and THD can be improved, and the flow is improved. The peak current through the current switch and the diode will be half of the operating capacitor in DCM mode without large capacitance to reduce the circuit volume and reduce the virtual power consumption.

In order for your review board to have a clear understanding of the contents of the present invention, please refer to the following description for matching drawings.

2 to 5 are respectively a circuit diagram of a device according to a preferred embodiment of the present invention, a block diagram of an embodiment, and a schematic diagram of a wafer circuit and a waveform diagram of the next embodiment. As shown in the figure, the power conversion control device 2 is a primary side control flyback conversion circuit architecture suitable for the DCM operation mode, and is configured to drive at least one light emitting diode 4 to emit light by connecting an external power source (not shown). . The control device 2 includes a rectifier module 20, an energy storage module 21, a control module 22, and an output module 23. The rectifier module 20 is a bridge rectifier circuit coupled to the power supply and rectified. An alternating current forms a variable direct current. The energy storage module 21 is provided with a storage capacitor 210 and a coupling transformer 211. The coupling transformer 211 has a primary side coil (N _P ), a secondary side coil (N _S ) and an auxiliary coil (N _A ). And the primary side coil is coupled to one end of the storage capacitor 210 and the output end of the rectifier module 20, so that the storage capacitor 210 receives the rectified variable DC and forms an input voltage (V _DC ) at both ends. A primary side current (I _P ) is formed by the primary side coil energy storage, and the secondary side coil senses the fluctuation of the primary side current to form an output current (I _O ), and the auxiliary coil is further A monitoring current (I _D ) is induced due to the variation of the current value of the output current. The output module 23 is provided with a diode 230 and an output capacitor 231. The diode 230 is connected in series with the secondary coil, and is connected to the output capacitor 231 and the LED 4 to make the output current pass through. The diode 230 is rectified and filtered by the output capacitor 231 and output to the LED 2 to improve the performance of the overall circuit.

The control module 22 is provided with a voltage dividing resistor 220, a current switch 221 and a current resistor 222, and a power conversion control chip 3. The control chip 3 includes a monitoring unit 30, a peak sensing unit 31, and an analyzing unit. 32 and a driving unit 33, and are provided with seven pins such as VDD, HV, DET, GATE, CS, GND and COMP. The voltage dividing resistor 220 is connected in series with the auxiliary coil, so that the monitoring current forms a voltage drop (V _D ) across the voltage dividing resistor 220. The current switch 221 is an N-type MOSFET, and the drain is coupled to the output end of the primary side coil and the source is coupled to the current resistor 222 to make the primary side current at both ends of the current resistor 222. Form a pressure drop. The monitoring unit 30 is provided with a D-type flip-flop 300, a high-voltage linear regulator 301 and an inverting comparator 302. The positive input terminal of the inverting comparator 302 is coupled to the voltage dividing resistor 220 through the DET pin. The negative input terminal inputs a threshold value (V _th ), and the output terminal is coupled to the reset signal pin of the D-type flip-flop 300 to monitor and compare the voltage drop across the voltage dividing resistor 220 with the threshold. The signal input pin of the D-type flip-flop 300 is coupled to the high-voltage linear regulator 301, and is connected to the primary side coil and the storage capacitor 210 through the HV pin to obtain stable working pressure and work quality. Service life. When the voltage drop across the voltage dividing resistor 220 is greater than the threshold, the inverse comparator 302 outputs a low level voltage value, so that the D-type flip-flop 300 generates a monitoring signal 3000. Conversely, the inverse comparator 302 outputs a high level voltage value to trigger the D-type flip-flop 300 to generate a reset signal 3001.

The peak sensing unit 31 is coupled to the current resistor 222 through the CS pin to sense and compare the voltage drop across the current resistor 222 with a peak voltage limit to generate a peak signal 310. The analyzing unit 32 is provided with a multiplier 320, a filter 321, a difference amplifier 322, a first comparator 323, a fixed wave generator 324, an RS flip flop 325 and an inverter 326. The multiplier The input end of the 320 is coupled to the output of the monitoring unit 30 and the peak sensing unit 31 to receive the reset signal 3001, the monitoring signal 3000 and the peak signal 310, and the output end of the 320 is coupled to the filter 321 . The negative input terminal of the difference amplifier 322 is coupled to the filter 321 to receive the filtered product of the reset signal 3001 and the monitoring signal 3000 and the peak signal 310, respectively, to input a reference value with the positive input terminal ( V _ref ) is _aligned and amplified to form a differential pressure value. The negative input terminal of the first comparator 323 is coupled to the output terminal of the difference amplifier 322 and the COMP pin to receive the differential voltage value and a compensation value, and the positive input terminal is coupled to the fixed frequency wave generator 324. Forming an upper limit value and a lower limit value by receiving a triangular wave, and the first comparator 323 compares the compensated differential pressure values with the upper and lower limit values, respectively, so that when the differential pressure value is less than the lower limit value, a output is output. The driving signal 3250 is greater than the upper limit value and an initial signal 3251 is output. Thus, when the response of the difference amplifier 322 is slow, the differential voltage of the output will be a stable value and the circuit will be in a constant on-time control mode to form a high-power control structure.

The set input pin of the RS flip-flop 325 is coupled to the fixed-frequency wave generator 324 to receive a square wave, and the reset input pin is coupled to the output end of the first comparator 323, and the output pin is coupled to the output pin. The input end of the driving unit 33 and the clock pin of the D-type flip-flop 300 are coupled through the inverter 326, and the D-type flip-flop 300 is activated by the positive edge. The input end of the driving unit 33 is coupled to the gate of the current switch 221 through the GATE pin, so that when the RS flip-flop 325 receives the driving signal 3250, the current switch 221 is turned on, and the RS flip-flop 325 is turned on. The current switch 221 is turned off when the initial signal 3251 is received. In this way, the primary side current can be compensated or bleed to adjust the magnitude of the output current to increase the luminous efficiency of the light emitting diode 4 by the current working state.

It is to be noted that, in order to improve the adaptability, the peak sensing unit 31 can be shown in FIGS. 6-8, which is a schematic diagram and waveform of a wafer circuit according to still another embodiment of the preferred embodiment of the present invention. A signal generator 311 and a sample holder 312 are provided. The signal generator 311 is configured to generate a sampling signal having a frequency of 1/2 of the reciprocal of the primary side current conducting period (T _on ), and the sampling is maintained. The current transformer 222 is coupled to the current resistor 222 and the signal generator 311 to sample the voltage drop across the current resistor 222 at each time point according to the sampling signal trigger. The sample holder 312 is sampled at the start time and the end point of the primary side current off period (T _off ), or after sampling at the center of the primary side current cutoff period, the analysis obtains an average peak value, so that the sample is obtained. When the primary current gradually decreases below the average peak, the analyzing unit 32 triggers the driving unit 33 to turn on the current switch 221 to start the next duty cycle. In this way, the control device 2 is allowed to operate in the CCM mode, and when the current switch 221 is turned off, that is, in the off period of the primary side current, the monitoring current is switched from the high level to the low level, and no residual wave is generated. The control chip 3 is prevented from malfunctioning to improve the working quality and stability of the overall circuit.

On the other hand, the control chip 3 is further shown in FIG. 9 , which is a circuit diagram of a wafer according to still another embodiment of the preferred embodiment of the present invention, comprising a current limiting unit 34 electrically connected to the monitoring unit 30 . The voltage dividing resistor 220, the current resistor 222, and the analyzing unit 32. The current limiting unit 34 is provided with a second comparator 340 and an OR gate 341. The positive input terminal of the second comparator 340 is coupled to the DET pin and the negative input terminal is coupled to the CS pin. The input end of the OR gate 341 is coupled to the output end of the second comparator 340, and the other input end is coupled to the reset input pin of the RS flip-flop 325, so that when the current switch 221 is turned on, The monitoring unit 30 reverses a current limiting current due to the voltage source of the HV and VDD pin inputs, so that a current limiting value is formed across the voltage dividing resistor 220, and the current limiting unit 34 is formed. The current limit value and the voltage drop across the current resistor 220 are compared. When the primary current is greater than the allowable current limit value, the analyzing unit 32 outputs the initial signal 3251 to compensate or bleed the first secondary current to adjust the input working voltage of the control device 2 to avoid the circuit. Problems such as burnout damage or abnormal work occur. Moreover, the voltage dividing resistor 220 is a variable resistor for the user to select the resistance value to adjust the current limiting current. In this way, the single DET pin of the control chip 3 can simultaneously have the dual function of sensing the variation of the output current and detecting the magnitude of the input voltage, thereby reducing the volume of the chip and facilitating miniaturization of the product while allowing the user to be flexible. Use to enhance practicality. Moreover, the voltage outputted by the output module 23 can also be known through the voltage drop waveform across the voltage dividing resistor 220, so as to facilitate the user to add an output overvoltage and short circuit protection mechanism.

The above description is only illustrative of preferred embodiments and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.

Traditional skill

1‧‧‧ device

10‧‧‧Rectifier

11‧‧‧Coupling transformer

12‧‧‧Control chip

120‧‧‧current switch

121‧‧‧current resistance

122‧‧‧voltage resistor

this invention

2‧‧‧Control device

20‧‧‧Rectifier Module

21‧‧‧ Energy storage module

210‧‧‧ storage capacitor

211‧‧‧Coupling transformer

22‧‧‧Control Module

220‧‧‧voltage resistor

221‧‧‧current switch

222‧‧‧current resistance

23‧‧‧Output module

230‧‧ ‧ diode

231‧‧‧ Output Capacitor

3‧‧‧Control chip

30‧‧‧Monitoring unit

300‧‧‧D type flip-flop

3000‧‧‧Monitor signal

3001‧‧‧Reset signal

301‧‧‧High Voltage Linear Regulator

302‧‧‧Inverse comparator

31‧‧‧peak sensing unit

310‧‧‧ Peak signal

311‧‧‧Signal Generator

312‧‧‧Sampling holder

32‧‧‧Analysis unit

320‧‧‧Multiplier

321‧‧‧ filter

322‧‧‧Differential amplifier

323‧‧‧First comparator

324‧‧‧ fixed frequency wave generator

325‧‧‧RS forward and reverse

3250‧‧‧Drive Signal

3251‧‧‧ initial signal

326‧‧‧ reverser

33‧‧‧ drive unit

34‧‧‧ Current limiting unit

340‧‧‧Second comparator

341‧‧‧ or gate

4‧‧‧Lighting diode

Fig. 1 is a circuit diagram of a conventional primary side control flyback power conversion control device.

Figure 2 is a circuit diagram of a device in accordance with a preferred embodiment of the present invention.

Figure 3 is a block diagram of a wafer in accordance with an embodiment of the preferred embodiment of the present invention.

Figure 4 is a schematic diagram of a wafer circuit of a second embodiment of the preferred embodiment of the present invention.

Figure 5 is a waveform diagram of a wafer according to a second embodiment of the preferred embodiment of the present invention.

Figure 6 is a schematic diagram of a wafer circuit in accordance with still another embodiment of the preferred embodiment of the present invention.

Figure 7 is a schematic diagram of a wafer circuit in accordance with another embodiment of the preferred embodiment of the present invention.

Figure 8 is a waveform diagram of a wafer according to another embodiment of the preferred embodiment of the present invention.

Figure 9 is a schematic diagram of a wafer circuit in accordance with still another embodiment of the preferred embodiment of the present invention.

3‧‧‧Control chip

30‧‧‧Monitoring unit

300‧‧‧D type flip-flop

301‧‧‧High Voltage Linear Regulator

302‧‧‧Inverse comparator

31‧‧‧peak sensing unit

32‧‧‧Analysis unit

320‧‧‧Multiplier

321‧‧‧ filter

322‧‧‧Differential amplifier

323‧‧‧First comparator

324‧‧‧ fixed frequency wave generator

325‧‧‧RS forward and reverse

326‧‧‧ reverser

33‧‧‧ drive unit

Claims (10)

A power conversion control chip is used in a primary side control flyback conversion circuit of a discontinuous conduction mode for controlling an output current amount to improve a power factor, the conversion circuit having a coupling transformer, the coupling transformer being provided with a a primary side coil, a secondary side coil and an auxiliary coil, and the primary side coil is connected in series with a current switch and a current resistor to form a primary side current after receiving the compressive energy, and at both ends of the current resistor Forming a voltage drop, and the secondary side coil and the auxiliary coil respectively induce an output current and a monitoring current, and the auxiliary coil is connected in series with a voltage dividing resistor to form a voltage drop at both ends thereof, and the power conversion control is performed. The chip comprises: a monitoring unit, which is provided with a D-type flip-flop, wherein the signal input pin is connected to the primary side coil and the reset signal pin is connected to the voltage dividing resistor to monitor and compare the monitoring current to the point. The voltage drop across the voltage resistor and a threshold value, when the voltage drop across the voltage divider resistor is greater than the threshold value, the D-type flip-flop generates a monitoring signal, and vice versa a peak sensing unit is connected to the primary side coil through a current resistance of the conversion circuit to sense and compare a voltage drop and a peak pressure limit formed by the primary current across the current resistance And generating a peak signal; an analyzing unit is provided with a multiplier for receiving the reset signal, the monitoring signal and the peak signal by the telecommunication connection of the monitoring unit and the output of the peak sensing unit, the analyzing unit The output terminal is connected to the clock pin of the D-type flip-flop, and the reset signal and the monitoring signal are respectively multiplied by the peak signal, And a driving voltage is outputted when a differential pressure value is less than a lower limit value, and an initial signal is output when the differential pressure value is greater than an upper limit value; and a driving unit is The telecommunication device is connected to the analysis unit and is connected to the primary side coil through a current switch of the conversion circuit. The driving unit receives the initial signal and turns off the current switch, or receives the driving signal to turn on the current switch to adjust the primary side. The current is turned on to adjust the magnitude of the output current. The power conversion control chip of claim 1, wherein the monitoring unit is provided with a high voltage linear regulator and an inverse comparator, wherein the high voltage linear regulator is coupled to the input end of the primary side coil and The signal input pin of the D-type flip-flop is output to the D-type flip-flop after the input current is stabilized; the positive input end of the reverse comparator is coupled to the voltage dividing resistor, and the negative input terminal inputs the threshold The output is coupled to the reset signal pin of the D-type flip-flop. The power conversion control chip of claim 2, wherein the analysis unit is provided with a frequency wave generator, a first comparator and an RS flip-flop, the first comparator is telecommunicationally connected to the multiplier The negative input terminal receives the differential pressure value and a compensation value, and the positive input terminal is coupled to the fixed frequency wave generator to receive a triangular wave to form the upper limit value and the lower limit value, and compare the compensation The differential voltage value is output and the driving signal or the initial signal is output to the reset input pin of the RS flip-flop. The power conversion control chip of claim 3, wherein an output pin of the RS flip-flop is coupled to a clock pin of the D-type flip-flop through an inverter, and the input pin is set. Coupling The fixed-frequency wave generator is connected to receive a square wave and the D-type flip-flop is triggered by a positive edge. The power conversion control chip of claim 4, wherein the peak sensing unit is provided with a signal generator and a sample holder, the signal generator is configured to generate a sampling signal having a frequency of 1/2. Reversing the primary side current conducting period, and the sampling holder is coupled to the current resistor and the signal generator, and sampling the voltage drop across the current resistor at each time point according to the sampling signal triggering, so that the converting circuit works In continuous conduction mode. The power conversion control wafer of claim 5, wherein the sample holder is sampled at a point in time of the center of the primary side current cutoff period. The power conversion control chip of claim 5, wherein the sample holder is sampled at a start point and an end point of the primary side current cutoff period. The power conversion control chip of claim 4, further comprising a current limiting unit electrically connected to the monitoring unit, the voltage dividing resistor, the current resistor and the analyzing unit, when the current switch is turned on, The monitoring unit reverses out one of the set current limiting currents to form a current limiting value across the voltage dividing resistor, so that the current limiting unit compares the current limiting value with the voltage drop across the current resistor, when the primary side current The analysis unit outputs the initial signal when the current limit value is allowed. The power conversion control chip of claim 8, wherein the voltage dividing resistor is a variable resistor to adjust the current limiting current. The utility model relates to a power conversion control device, which is a primary side control flyback conversion circuit structure, which is connected with one external power supply and outputs one output current to drive at least one light emitting diode group, which comprises: a rectifier module, a coupling Connecting the power source, and receiving and rectifying a variable one of the alternating currents; an energy storage module is provided with a coupling transformer, the coupling transformer is provided with a primary side coil, a secondary side coil and an auxiliary coil, the primary side coil The output end of the rectifying module is coupled to receive the rectified alternating current to store a primary side current, and the secondary side coil and the auxiliary coil respectively sense an output current and a monitoring current; The module is provided with a power conversion control chip, a voltage dividing resistor, a current switch and a current resistor as described in claim 1, wherein the voltage dividing resistor is coupled to the auxiliary coil and the monitoring unit, and the monitoring unit The unit is coupled to the storage capacitor and the input end of the primary side coil; the current switch is an N-type gold-oxygen half-field effect transistor crystal, and the drain is coupled to the input of the primary side coil The source is coupled to the current resistor and the peak sensing unit, and the gate is coupled to the driving unit. The control module obtains the magnitude of the monitored current through the monitoring unit and learns through the peak sensing unit. The amount of change of the primary side current, and after the calculation unit is operated, the driving unit turns on or off the current switch to compensate or bleed the primary side current to maintain the output current as a constant current state; and an output mode The group is provided with a diode and an output capacitor, and the diode is connected in series with the secondary coil and connected to the output capacitor and The light-emitting diode is rectified by the diode and filtered by the output capacitor and output to the light-emitting diode.