TW201405298A - Memory device and control method therefore - Google Patents

Abstract

A memory device and a control method therefore are provided. The memory device includes a processing unit, a non-volatile memory module, a volatile memory module and a power control module. The processing unit connects a computer system through a computer bus. The non-volatile memory module and the volatile memory module respectively receive a first power and a second power to access data. The power control module provides the first power and the second power to the non-volatile memory module and the volatile memory module respectively. When the computer system transmits a device sleep signal to the processing unit, the processing unit provides a power-saving signal by judging a power situation of the computer system. The power control module determines whether to continue to provide the first power or the second power according to the device sleep signal and the power-saving signal.

Description

Memory device and control method thereof

The present invention relates to a control technique for a memory device, and more particularly to a memory device and a method of controlling the memory device.

In recent years, the research and development technology and demand of consumer electronic products (such as smart phones, tablets, digital cameras, etc.) have been very rapid, which has led to a rapid increase in demand for storage media. Because Flash memory has the characteristics of non-volatile data, power saving, small size and no mechanical structure, it is suitable for many applications of portable devices, so it is most suitable for battery-powered handheld products. Solid-state hard drives are an emerging device that uses NAND flash memory as a storage medium.

At present, a tablet or a notebook computer usually uses a computer bus interface (for example, a serial advanced technology attachment (SATA) interface) that is commonly used in a computer system to transmit data to a solid state hard disk, so there is currently no data transfer. Optimized for the unique structure of solid state drives, it uses the same power-saving mode as the old mechanical hard drives. Since the mechanical hard disk has a structure such as a head and a robot arm, and the structure of the flash memory in the solid state hard disk is completely different from reading and writing, it is necessary to develop a corresponding power management for the read and write mode of the solid state hard disk. Technology allows the computer system to strike a balance between power savings and data access performance.

The invention provides a memory device and a control method of the memory device, which additionally adds a power control module to the memory device (for example, a solid state hard disk), thereby improving the speed of the memory device from the power saving mode to the normal mode. .

The invention provides a memory device, which comprises a processing unit, a non-volatile memory module, a volatile memory module and a power control module. The processing unit is connected to the computer system through a computer bus. The non-volatile memory module is coupled to and controlled by the processing unit, and receives the first power source to access the data. The volatile memory module is coupled to and controlled by the processing unit, and receives a second power source to access data. The power control module is coupled to the processing unit, the non-volatile memory module, and the volatile memory module. The power control module provides the first power source and the second power source to the non-volatile memory module and the volatile memory module, respectively. When the computer system passes the sleep signal of the computer bus to the processing unit, the processing unit determines the power supply condition of the computer system to determine whether to back up the data of the non-volatile memory module to the volatile The memory module generates a power saving mode signal, and the power control module determines whether to continue to provide the first power source or the second power source according to the device sleep signal and the power saving mode signal.

In an embodiment of the present invention, when the computer system transmits the device sleep signal to the processing unit, and the processing unit determines that the computer system is in an AC power supply situation, the processing unit sets the power saving mode signal to be the first A power saving mode. When the computer system transmits the device sleep signal to the processing unit, and the processing unit determines that the computer system is in a DC power supply situation, the processing unit sets the power saving mode signal to the first power saving mode After the computer system does not wake up the memory device within a predetermined time, the computer system transmits the power saving mode signal to the second power saving mode through the processing unit.

In an embodiment of the invention, the power saving mode signal includes a first input output signal and a second input output signal. And, when the power saving mode signal is the first power saving mode, the processing unit backs up the data in the non-volatile memory module to the volatile memory module, and disables the An input and output signal and the second input and output signals are enabled.

From another point of view, the present invention provides a method of controlling a memory device, the memory device comprising a non-volatile memory module receiving a first power source and a volatile memory module receiving a second power source. The control method includes the following steps. Connected to a computer system through a computer bus. Determining, by the computer system, the power supply condition of the computer system to determine whether to back up the data of the non-volatile memory module to the volatile memory module, and generating the sleep signal of the computer system A power saving mode signal. And determining, according to the device sleep signal and the power saving mode signal, whether to continue to provide the first power source or the second power source.

For the remaining implementation details of the control method of the memory device, please refer to the above description, and no further details are provided herein.

Based on the above, the power control module is additionally added to the memory device (for example, a solid state drive), so that when the memory device enters the power saving mode, the processing unit causes the memory device according to the power supply of the computer system. The internal volatile memory module (eg, random access memory) maintains or temporarily maintains the power-on state, and non-volatile memory before shutting down the processing unit and the main non-volatile memory module The internal data part of the body module is backed up to the volatile memory module. When the computer system needs to read the data in the memory device, the volatile memory module that has not been powered off can be read by the computer system with the backup data, and the memory device is re-powered to the processing unit and the volatile at this time. The memory module is re-operated, so that the speed of the memory device from the power saving mode to the normal mode can be improved, and the computer system performance and power saving are achieved.

The above described features and advantages of the present invention will be more apparent from the following description.

DETAILED DESCRIPTION OF THE INVENTION Reference will now be made in detail to the exemplary embodiments embodiments In addition, wherever possible, the elements and/

Please refer to FIG. 1. FIG. 1 is a block diagram of a memory device 100 and a computer system 110 according to an embodiment of the invention. As shown in FIG. 1, the computer system 110 is provided with a computer bus interface (in the embodiment, the computer bus interface is, for example, a SATA interface 120), and through the SATA interface 120. It is connected to the memory device 100 for data transmission. The computer system 110 is, for example, a tablet computer, a notebook computer, a desktop computer, or the like.

The memory device 100 is a main data storage memory of the computer system 110, such as a solid state hard disk. The memory device 100 includes a processing unit 130, a non-volatile memory module 140, a volatile memory module 150, and a power control module 160. It can be seen from the block structure shown in the memory device 100 of FIG. 1 that the memory device 100 is not an old mechanical hard disk, and does not have a structure such as a disk array, a head, and a robot arm. Therefore, this embodiment Take the solid state drive as an example.

In FIG. 1, processing unit 130 is coupled to computer system 110 via computer bus 132, SATA interfaces 120, and 136. In detail, the processing unit 130 is a control module for accessing the non-volatile memory module 140 and the volatile memory module 150 in the memory device 100, which can be implemented by using an embedded system chip (SOC). The processing unit 130 includes a microprocessor 134, a SATA interface 136, and a general purpose input/output (GPIO) interface 138, and the microprocessor 134 is coupled to the SATA interface 136 and the GPIO interface 138, respectively. Specifically, the processing unit 130 in this embodiment receives the first power source VP1 to maintain operation, and when the first power source VP1 is turned off, the processing unit 130 will be turned off to stop operating.

The non-volatile memory module 140 and the volatile memory module 150 are respectively coupled to the processing unit 130 through different data busses, so that the computer system 110 can pass through the processing unit 130 from the non-volatile memory module 140 or The volatile memory module 150 accesses the data. In other words, non-volatile The memory module 140 and the volatile memory module 150 are respectively coupled and controlled by the processing unit 130, so that the computer system 110 accesses the data therein.

The non-volatile memory module 140 receives the first power source VP1 to maintain operation. When the non-volatile memory module 140 does not receive the first power source VP1, although the data in the non-volatile memory module 140 does not disappear, it still takes a period of time to access the data therein. In this embodiment, the non-volatile memory module 140 is, for example, a flash memory (FLASH) memory module built with a NAND gate group.

The volatile memory module 150 receives the second power source VP2 to maintain operation. When the non-volatile memory module 150 does not receive the second power source VP2, based on the characteristics of the volatile memory module 150, the data in the volatile memory module 150 will disappear, so to save the volatile memory For the data of the body module 150, the second power source VP2 needs to be continuously provided to continuously refresh the data. In the present embodiment, the volatile memory module 150 is composed, for example, of a dynamic random access memory (DRAM), and is used as a cache memory block of the memory device 100.

In this embodiment, the memory device 100 further includes a power converter 170 coupled to the computer bus bar 132 to receive the power supply voltage VDD from its power supply pin and convert the power supply voltage VDD into a voltage required by other devices. Therefore, if the voltages required in the memory device 100 are all the same, the power converter 170 may not be needed.

As can be seen from the above, the processing unit 130, the non-volatile memory module 140, and the volatile memory module 150 are the main functional structures of the memory device 100 (solid state hard disk), so that the computer system 110 is in the memory device 100. Has After entering the power saving mode, the data can still be read and written quickly from the memory device 100. In addition to modifying part of the power saving processing judgment mechanism in the processing unit 130, the power control module 160 is also added to control the non-volatile memory. The power supply of the module 140 and the volatile memory module 150.

The power control module 160 is coupled to the processing unit 130, the non-volatile memory module 140, and the volatile memory module 150. The power control module 160 obtains the power supply voltage VDD from the power supply pin of the computer bus bar 132, and converts the power supply voltage VDD into the first power source VP1 and the second power source VP2 to provide the first power source VP1 and the second power source VP2, respectively. The non-volatile memory module 140 and the volatile memory module 150. In addition, the power control module 160 receives the device sleep signal DEVSLP transmitted by the computer system 110 in the computer bus bar 132 and the power saving mode signal 139 transmitted by the processing unit 130 via the GPIO interface 138 to determine whether to continue to provide the first power source VP1. Or the second power source VP2.

In view of this, when the computer system 110 determines that there will be a period of time that does not require access to the memory device 100, or the memory device 100 is in a light load state, the computer system 110 will follow the SATA power management protocol to pass through the computer. The bus bar 132 transmits/enables the device sleep signal DEVSLP to the processing unit 130, causing the memory device 100 to enter the power saving mode by itself.

When the device sleep signal DEVSLP is transmitted to the processing unit 130, the processing unit 130 can determine the power supply condition of the computer system 110 through the computer bus 132 to determine whether to back up the data of the non-volatile memory module 140 to the volatile memory. Module 150, and generates a power save mode signal 139. The power control module 160 is based on the device sleep signal DEVSLP and the province. The electrical mode signal 139 determines whether to continue to provide the first power source VP1 and the second power source VP2, thereby stopping the operation of the processing unit 130 and the non-volatile memory module 140, and further stopping the operation of the volatile memory module 140.

In detail, in the embodiment, when the processing unit 130 receives the device sleep signal DEVSLP, it first determines the power supply situation of the computer system 110. If the computer system 110 is in an AC power supply situation, that is, when the computer system 110 is connected to a stable power source such as a commercial power supply, the processing unit 130 sets the power saving mode signal 139 to the first power saving mode, or is referred to as a slumber mode. . That is, when the power saving mode signal 139 is set to the first power saving mode, considering the performance of the computer system 110 and the memory device 100, the processing unit 130 will back up the data in the non-volatile memory module 140. To the volatile memory module 150, the power control module 160 then stops supplying the first power source VP1 to turn off the processing unit 130 and the non-volatile memory module 140 to save power. On the other hand, the power control module 160 reserves and continues to provide the second power source VP2 to cause the volatile memory module 150 to continuously refresh its internal data.

In this way, when the computer system 110 wishes to access the data of the memory device 100, the computer system 110 can quickly access the backup data in the volatile memory module 150, thereby improving the computer system 110 in the memory device 100. Data access speed when switching from power saving mode to normal mode.

On the other hand, when the processing unit 130 receives the device sleep signal DEVSLP and the computer system 110 is in the DC power supply situation, that is, When the computer system 110 is powered by the built-in battery, since the power supply is tight and the power consumption of the power supply is reduced, it is more important than the operating efficiency. Therefore, the processing unit 130 first sets the power saving mode signal 139 to the above. A power saving mode prevents the computer system 110 from accessing the memory device 100 immediately after transmitting/enabling the device sleep signal DEVSLP. Thereafter, if the computer system 100 does not wake up the memory device 100 for a predetermined time (eg, 10 seconds) (ie, the memory device 100 is not switched from the first power saving mode to the normal operating mode), the computer System 110 adjusts power save mode signal 139 to a second power save mode via GPIO interface 138 in processing unit 130. When the power saving mode signal 139 is in the second power saving mode, the power control module 160 stops supplying the first power source VP1 and the second power source VP2 to turn off the processing unit 130, the non-volatile memory module 140, and volatilize. The memory module 150 achieves power saving effect.

FIG. 2 is a detailed block diagram of a memory device 100 according to an embodiment of the invention. That is, FIG. 2 illustrates the circuit structure of the power control module 160 in detail. The other components of FIG. 2 are the same as those of FIG. 1, and are not described herein. The power control module 160 includes a logic unit 210, a first power controller 220, and a second power controller 230. The power saving mode signal 139 includes a first input and output signal GPIO1 and a second input and output signal GPIO2.

The logic unit 210 receives the device sleep signal DEVSLP and the power saving mode signal 139 to generate a first enable signal EN1 and a second enable signal EN2. In detail, the logic unit 210 includes a first reverse gate 212 and a second reverse gate 214. The first input end of the first anti-gate 212 receives the first input/output signal GPIO1, and the second input end of the first anti-gate 212 receives the device to sleep. The signal DEVSLP, and the output of the first AND gate 212 generates a first enable signal EN1. The first input end of the second anti-gate 214 receives the second input/output signal GPIO2, the second input of the first anti-gate 214 receives the device sleep signal DEVSLP, and the output of the first anti-gate 214 produces the second Can signal EN2. The power converter 170 receives and converts the supply voltage VPP to a logic voltage to supply power to the first AND gate 212 and the second AND gate 214 in the logic unit 210. In this embodiment, the logic unit 210 further includes a resistor R1 coupled between the output end of the power converter 170 and the pin of the carrier sleep signal DEVSLP, and an output coupled to the power converter 170. A resistor R2 between the pins of the input and output signals GPIO1.

The first power controller 220 is coupled to the logic unit 210 to receive the first enable signal EN1 and the supply voltage VDD. The first power controller 220 is converted into the first power source VP1 through the power supply voltage VDD. When the first enable signal EN1 is turned from disabled to disabled, the first power controller 220 stops providing the first power source VP1. The second power controller 230 is coupled to the logic unit 220 to receive the second enable signal EN2 and the supply voltage VDD. The second power controller 230 is converted into the second power source VP2 through the power supply voltage VDD. And when the second enable signal EN2 is turned from disabled to disabled, the second power controller 230 stops providing the second power source VP2.

Therefore, the present embodiment combines the power supply of the computer system 110, the operation mode of the computer device 100 (for example, the normal operation mode, the first power saving mode or the second power saving mode), the device sleep signal DEVSLP, and the first input/output signal GPIO1. , the first enable signal EN1 and the second enable signal EN2, In order to form the table (a), the spirit of the embodiment of the present invention can be more fully understood by those skilled in the art.

In Table (1), the "power supply situation" of the first field indicates that the power supply of the computer system 100 is DC power or AC power. The "mode" indicates the signal state of the power saving mode signal 139 in the memory device 100, and is represented by the first input/output signal GPIO1 and the second input/output signal GPIO2.

Therefore, please refer to FIG. 2 and Table (1) at the same time, when the memory device 100 is in the normal mode (whether the computer system is in the AC power supply situation or the DC power supply situation), the device sleep signal DEVSLP, the first input and output signal GPIO1 and the first The two input and output signals GPIO2 are disabled (logical "0", so that the first enable signal EN1 and the second enable signal EN2 are both enabled (logic "1"), so the first power controller 220 and the second power controller 230 continue to supply the first power VP1 and second power supply VP2.

When the computer system is in the AC power supply situation and the memory device 100 is in the first power saving mode, the device sleep signal DEVSLP and the first input and output signal GPIO1 are enabled (logic "1"), and the second input and output signal GPIO2 is disabled. The logic controller can stop (providing the first power source VP1 to turn off the processing unit 130 and the non-volatile memory module 140. In addition, the second power controller 230 continues to supply the second power source VP2 to enable the volatile memory module 150 to automatically refresh the data. If the memory device 100 is switched from the first power saving mode to the normal mode, the device sleep signal DEVSLP and the first input/output signal GPIO1 are all disabled (logic "0"), so that the first enable signal EN1 is converted to The first power supply controller 220 is enabled to provide the first power supply VP1 to enable the processing unit 130 and the non-volatile memory module 140.

When the computer system is in the DC power supply situation and the memory device 100 is in the first power saving mode, similar to the above description, the device sleep signal DEVSLP and the first input and output signal GPIO1 are enabled (logic "1"), and the second input The output signal GPIO2 is disabled (logic "0") such that the first enable signal EN1 is disabled (logic "0") and the second enable signal EN2 remains enabled (logic "1"). However, since the power consumption of the power supply is more important than the data access performance, the computer system will confirm the time when the memory device 100 enters the first power saving mode (that is, the predetermined time mentioned above) to determine whether to turn off. The power of the volatile memory module 150. The above predetermined time can be The length of time is arbitrarily adjusted by applying the needs of the embodiment, and is not limited to the above examples.

Therefore, in the embodiment, after the computer system 110 is in the DC power supply situation and the memory device 100 is in the first power saving mode for more than a predetermined time (10 seconds), the computer system adjusts the power saving through the GPIO interface 138 of the processing unit 130. The mode signal 139 causes the device sleep signal DEVSLP, the first input/output signal GPIO1, and the second input/output signal GPIO2 to be enabled (logic "1"), so that the first enable signal E1 and the second enable signal EN2 are both Disable (logic "0"). Therefore, the first power controller 220 and the second power controller 230 stop supplying the first power source VP1 and the second power source VP2 to turn off the processing unit 130, the non-volatile memory module 140, and the volatile memory module 150.

In contrast, when the computer system needs to return the memory device 100 from the second power saving mode to the normal mode, the device sleep signal DEVSLP and the first input/output signal GPIO1 are disabled (logic "0"). The first smart signal EN1 and the second enable signal EN2 are turned into enable (logic "1"), so that the power control module 160 provides the first power source VP1 and the second power source VP2.

The embodiment of the present invention can also be described from another perspective by the embodiment. For example, referring to FIG. 1 , an embodiment of the present invention provides a method for controlling a memory device 100 . The memory device 100 includes a non-volatile memory module 140 that receives the first power source VP1 and a volatile memory module 150 that receives the second power source VP2. The control method of the memory device 100 includes the following steps. First, the memory device 100 is connected to the computer system 110 through the computer bus 132. When the computer system 110 transmits through the computer bus 132 When the sleep signal DEVSLP is set, the processing unit 130 determines the power supply condition of the computer system 110 to generate the power save mode signal 139. And, the power control module 160 determines whether to continue to provide the first power source VP1 or the second power source VP2 according to the device sleep signal DEVSLP and the power saving mode signal 139.

In summary, the embodiment of the present invention additionally adds a power control module to a memory device (eg, a solid state drive), so that the processing unit causes the volatile memory module in the memory device according to the power supply of the computer system. (eg, random access memory) maintains or temporarily maintains the power-on state, causing the memory device to enter the first power-saving mode, and before shutting down the processing unit and the main non-volatile memory module, The internal data portion of the volatile memory module is backed up to the volatile memory module.

If the memory device is in the first power saving mode and the computer system is to read the data in the memory device, the volatile memory module that has not stopped supplying power may be first read by the computer system with the backup data, and the memory device is At this time, the power supply unit and the volatile memory module are re-powered to re-operate, thereby improving the speed of the memory device from the power saving mode to the normal mode, and achieving a win-win situation between the computer system performance and the power saving.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ memory device

110‧‧‧ computer system

120, 136‧‧‧Sequence Advanced Technology Connection (SATA) interface

130‧‧‧Processing unit

132‧‧‧Computer Bus

134‧‧‧Microprocessor

138‧‧‧General purpose output/input (GPIO) interface

139‧‧‧Power saving mode signal

140‧‧‧Non-volatile memory module

150‧‧‧Volatile Memory Module

160‧‧‧Power Control Module

170‧‧‧Power Converter

210‧‧‧Logical unit

212, 214‧‧‧ anti-gate

220‧‧‧First power controller

230‧‧‧Second power controller

DEVSLP‧‧‧ device sleep signal

VDD‧‧‧ supply voltage

VP1, VP2‧‧‧ first power supply, second power supply

GPIO1, GPIO2‧‧‧ input and output signals

EN1, EN2‧‧‧ enable signal

R1, R2‧‧‧ resistance

1 is a block functional diagram of a memory device and a computer system according to an embodiment of the invention.

2 is a detailed block diagram of a memory device in accordance with an embodiment of the invention.

100‧‧‧ memory device

110‧‧‧ computer system

120, 136‧‧‧Sequence Advanced Technology Connection (SATA) interface

130‧‧‧Processing unit

132‧‧‧Computer Bus

134‧‧‧Microprocessor

138‧‧‧General purpose output/input (GPIO) interface

139‧‧‧Power saving mode signal

140‧‧‧Non-volatile memory module

150‧‧‧Volatile Memory Module

160‧‧‧Power Control Module

170‧‧‧Power Converter

DEVSLP‧‧‧ device sleep signal

VDD‧‧‧ supply voltage

VP1, VP2‧‧‧ first power supply, second power supply

Claims (10)

A memory device includes: a processing unit connected to a computer system through a computer bus; a non-volatile memory module coupled to and controlled by the processing unit to receive a first power source for accessing data a volatile memory module coupled to and controlled by the processing unit to receive a second power source for accessing data; and a power control module coupled to the processing unit and the non-volatile memory module And the volatile memory module, the power control module respectively providing the first power source and the second power source to the non-volatile memory module and the volatile memory module, wherein when the computer system transmits the When the computer bus transmits a device sleep signal to the processing unit, the processing unit determines a power supply condition of the computer system to determine whether to back up the non-volatile memory module data to the volatile memory module, and generate a And saving the mode signal, and the power control module determines whether to continue to provide the first power source or the second power source according to the device sleep signal and the power saving mode signal. The memory device of claim 1, wherein the power control module comprises: a logic unit, receiving the sleep signal of the device and the power saving mode signal to generate a first enable signal and a second a first power controller coupled to the logic unit to receive the first enable signal, and when the first enable signal is turned from disabled to disabled, the first power controller stops providing the signal First power source; a second power controller coupled to the logic unit to receive the second enable signal, and when the second enable signal is disabled from being enabled, the second power controller stops providing the second power source . The memory device of claim 2, wherein the power saving mode signal comprises a first input and output signal and a second input and output signal, and the logic unit comprises: a first reverse gate, The first input end receives the first input and output signal, the second input end of the first anti-gate receives the sleep signal of the device, and the output of the first anti-gate generates the first enable signal; a second input gate receives the second input and output signal, the second input end of the first anti-gate receives the sleep signal of the device, and the output of the first anti-gate generates the second Can signal. The memory device of claim 1, wherein the processing unit sets the power saving when the computer system transmits the device sleep signal to the processing unit, and the processing unit determines that the computer system is in an AC power supply situation. The mode signal is a first power saving mode, and when the computer system transmits the device sleep signal to the processing unit, and the processing unit determines that the computer system is in a DC power supply situation, the processing unit sets the power saving mode signal After the first power saving mode, and the computer system does not wake up the memory device within a predetermined time, the computer system transmits the power saving mode signal to the second power saving mode through the processing unit. The memory device of claim 4, wherein the power saving mode signal comprises a first input and output signal and a second input and output signal, and when the power saving mode signal is the first power saving mode The processing unit backs up the data in the non-volatile memory module to the volatile memory module, disables the first input and output signals, and enables the second input and output signals. The memory device of claim 5, wherein when the power saving mode signal is the second power saving mode, the computer system transmits the first input/output signal and the second input through the processing unit. output signal. The memory device of claim 1, wherein the memory device is a solid state hard disk, the computer bus is a serial advanced technology connection interface, and the non-volatile memory module is a flash memory module. And the volatile memory module is a dynamic random access memory. A method of controlling a memory device, comprising: a non-volatile memory module receiving a first power source; and a volatile memory module receiving a second power source, wherein the control method comprises: transmitting a The computer bus is connected to a computer system; when the computer system transmits a device sleep signal through the computer bus, determining the power supply condition of the computer system to determine whether to back up the non-volatile memory module data to the volatile a memory module and generating a power saving mode signal; Determining whether to continue providing the first power source or the second power source according to the device sleep signal and the power saving mode signal, respectively. The method for controlling a memory device according to claim 8, wherein determining the power supply condition of the computer system to generate the power saving mode signal comprises the following steps: determining that the computer system is located in an AC power supply situation, setting the power saving The mode signal is a first power saving mode; determining that the computer system is in a DC power supply mode, setting the power saving mode signal to the first power saving mode, and the computer system does not wake up the memory within a predetermined time After the device, the power saving mode signal is set to the second power saving mode. The method for controlling a memory device according to claim 9 further includes the following steps: when the power saving mode signal is the first power saving mode, backing up the data in the non-volatile memory module to The volatile memory module stops supplying the first power source and continues to provide the second power source; and when the power saving mode signal is the second power saving mode, stopping providing the first power source and the second power source.