TW201401434A - Through silicon via structure and method of fabricating the same - Google Patents

Abstract

The present invention provides a method of fabricating a through silicon via structure, in which, a first dielectric layer is formed on the substrate, the first dielectric layer is patterned to have at least one first opening, a via hole is formed in the first dielectric layer and the substrate, a second dielectric layer is conformally formed on the first dielectric layer, the second dielectric layer has at least one second opening corresponding to the at least one first opening, the second dielectric layer covers a sidewall of the via hole. Thereafter, a conductive material layer is formed to fill the via hole and the at least one second opening. The conductive material layer is planarized to form a through silicon via within the via hole. A through silicon via structure is also provided, in which, the second dielectric layer is disposed within the at least one first opening and on the sidewall of the via hole.

Description

Piercing conductor structure and its preparation method

The invention relates to a method for manufacturing a through silicon via (TSV) and a structure thereof.

In the semiconductor technology, the TSV structure is used to electrically connect the stacked crystal grains and the layer components between the crystal grains, thereby significantly reducing the connection distance of the components on the wafer, thereby effectively increasing the overall operation speed. In addition, in the package structure of the die, there are various ways to vertically integrate the wafer, such as a hybrid technique such as wire bonding or flip chip bonding. In recent years, TSV's silicon interposer (or "intermediate interposer") connection technology has been used to provide high wiring density and allow extremely small interconnect spacing.

In the current TSV practice, a via hole is drilled on the front side of the wafer by etching or laser, and a conductive material such as polysilicon, copper, tungsten or the like is filled into the via holes to form a conductive layer. Channel (that is, an interconnect structure that connects internal and external). Finally, the wafer or die back is thinned to expose the vias.

However, the via holes are formed on the front surface of the wafer. After the conductive material is filled into the via holes, the excess conductive layer on the interlayer dielectric layer is usually removed by a chemical-mechanical polishing (CMP) process. Material, but due to the loading problem of grinding in the CMP step, the area with higher pattern density and the area with lower pattern density The inconsistent grinding speeds result in the fact that the two regions where the conductive material should be removed and electrically separated cannot be separated smoothly. After grinding, the metal top surface of the TSV is prone to bridging, which affects the manufacturing yield or product quality.

Therefore, there is still a need for a novel TSV manufacturing method to solve the above problems.

It is an object of the present invention to provide a method of fabricating a TSV structure and a TSV structure that solves the above problems.

In accordance with an embodiment of the present invention, a method of fabricating a TSV structure is provided that includes the following steps. First, a substrate is provided. A first dielectric layer is formed on the substrate. The first dielectric layer is patterned to have at least one first opening. A via hole is formed in the first dielectric layer and the substrate. Forming a second dielectric layer on the first dielectric layer in conformity with the shape of the first dielectric layer, the second dielectric layer having at least one second opening corresponding to the at least one first opening, and the second dielectric layer The electrical layer covers the sidewall of the via. Then, a conductive material layer is respectively filled in the via hole and the at least one second opening. The layer of conductive material is planarized to form a TSV in the via.

According to another embodiment of the present invention, a TSV structure is provided, including: a substrate, a first dielectric layer, a via, a second dielectric layer, and a conductive layer. The first dielectric layer is disposed on the substrate and has at least one first opening. The via hole passes through the first dielectric layer and the substrate. The second dielectric layer is disposed in the at least one first opening and On the side wall of the via. The conductive layer is disposed in the via hole formed on the sidewall with the second dielectric layer to form a TSV.

According to a specific embodiment of the present invention, since a space such as an interlayer dielectric-level zero (ILD-0) is used, one or a plurality of openings are provided in the vicinity of the via holes, and the conductive holes are filled in the same manner as the via holes. The material, therefore, during the planarization (eg, CMP) process, because the metal distribution of the surface is relatively uniform, significant loading differences do not occur, so bridging problems can be avoided or mitigated.

Specific embodiments of the present invention will be described in detail below with reference to Figures 1 through 8. 1 shows a flow chart of a method of fabricating a TSV structure in accordance with an embodiment of the present invention. Figures 2, 3, 5 to 7A show schematic cross-sectional views of an embodiment of the invention. Figures 7B and 7C also show several variations. Figure 4 shows a specific embodiment in accordance with another aspect of the present invention. Figure 8 is a plan view showing an embodiment of the present invention. It should be noted that the dimensions of the various figures herein are not to be construed as a true

Referring to Figures 1 and 2, first, step 101 is performed to provide a substrate 10. Substrate 10 can be a single crystal germanium. Step 102 is performed to form a first dielectric layer, such as dielectric layer 12, on substrate 10. Dielectric layer 12 may also be referred to as a zeroth interlayer dielectric layer. Generally, the dielectric layer between the active device on the substrate and the first metal layer of the metal interconnect structure is referred to as an interlayer dielectric-level one (ILD-1). Zeroth floor The dielectric layer is the dielectric layer between the substrate and the first interlayer dielectric layer. The dielectric layer 12 may be, for example, an oxide layer, but may be produced by, for example, a chemical vapor deposition (CVD) process, but is not limited thereto.

Then, referring to FIGS. 1 and 3, in step 103, the dielectric layer 12 is patterned to have at least one first opening, such as an opening 14 and a plurality of openings 16, respectively located in the vicinity of a predetermined TSV position. The purpose of manufacturing the opening is to form a dummy TSV in a subsequent process, so that when the conductive material layer (for example, metal layer) of the TSV is planarized (for example, CMP), the metal distribution density on the polished surface can be relatively uniform to reduce uneven load. There is no particular limitation on the position, size, shape, and number of the openings. As long as it is disposed near the TSV, the metal distribution density of the polishing surface is relatively uniform when performing CMP. Patterning of the dielectric layer 12 can be performed using, for example, lithography and an etching process. As shown in FIG. 3, the etching of the dielectric layer 12 is stopped on the substrate 10. Therefore, the bottoms of the openings 14 and 16 are the original surfaces of the substrate 10 (the original surface refers to the surface of the original substrate 10 in contact with the dielectric layer 12); However, it is not limited thereto, and may also be stopped in the dielectric layer 12, at which time the bottoms of the openings 14 and 16 are higher than the original surface of the substrate 10; or another embodiment as shown in Fig. 4, stopped at In the substrate 10, at this time, the bottoms of the openings 14 and 16 are lower than the original surface of the substrate 10.

Then, referring to FIGS. 1 and 5, in step 104, a via hole 20 is formed in the dielectric layer 12 and the substrate 10. The step of forming the via hole 20 may include, for example, forming a photoresist layer 18 on the dielectric layer 12 and filling the openings; patterning the photoresist layer 18 by, for example, a lithography process to have an opening to expose the underside Dielectric layer 12 and substrate 10; The patterned photoresist layer 18 is used as a mask through which the dielectric layer 12 and the substrate 10 are partially removed to form the via holes 20. The aperture of the via may be approximately the same or similar to the aperture of the opening 14, for example. The aperture of the opening 16 can be made smaller, for example, than the aperture of the via.

Then, referring to FIGS. 1 and 6, a step 105 is performed to form a second dielectric layer, such as dielectric layer 22, on the dielectric layer 12 in accordance with the shape of the dielectric layer 12. Since the dielectric layer 22 is formed conformally, the dielectric layer 22 has openings 15 and 17 corresponding to the openings 14 and 16, and the dielectric layer 22 covers the sidewalls and the bottom of the via 20, and Can be used as a liner for TSV. The aperture sizes of the openings 15 and 17 may be different from each other. Since the size of the opening 16 is relatively small, the dielectric layer 22 may fill the opening 16 and form an opening 17 above the original opening 16. But it is not limited to this. The aperture sizes of the respective openings 17 are not particularly limited to be the same as each other, but may be different. When the size of the opening 16 is relatively large, the dielectric layer 22 may not fill the opening 16, such that the bottom of the opening 17 may also be located in the dielectric layer 12, with the bottom as shown by the opening 15 being in the dielectric layer 12. situation. Dielectric layer 22 can be formed using, for example, a thermal oxidation process or a CVD process. In particular, the dielectric layer 22 formed by compliance does not mean that the thickness of each layer will be the same, and its thickness depends on the actual shape, and is generally related to the shape of the deposited surface, for example, in the via hole 20 The thickness of the sidewalls is thinner than the thickness above the dielectric layer 12, which can be referred to known deposition techniques.

Then, referring to FIGS. 1 and 7A, in step 106, a conductive material layer 26 is filled in the via hole 20 and the openings 15 and 17, respectively. The conductive material layer 26 can include an example Such as copper, tungsten, aluminum, or other suitable conductive materials. It can be produced by, for example, electroplating, sputtering or chemical vapor deposition (CVD), electro-less plating/electro-less grabbing. Before the conductive material layer 26 is filled, for example, a barrier layer 24 may be formed, that is, a barrier layer 24 is formed between the conductive material layer 26 and the dielectric layer 22. The barrier layer 24 may include, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or a combination thereof. A seed layer (not shown) may also be formed before filling the conductive material layer 26.

Then, in step 107, the conductive material layer 26 is planarized. For example, the conductive material layer 26 on the surface of the substrate 10 is polished by a CMP process to planarize, and the TSVs 28 are formed in the via holes, and the dummy TSVs 30 and 32 can be formed in the openings 15 and 17, respectively, as shown in FIG. 7A. Shown. In another embodiment, as shown in FIG. 7C, the conductive material layer 26 in the openings 15 and 17 can be completely removed during planarization, and therefore, only TSV can exist in the obtained TSV structure. 28, but not the virtual TSV. Alternatively, since the bottom of the opening 15 is lower, the bottom of the opening 17 is relatively higher, so after planarization, only the dummy TSV 32 can be removed, leaving the remaining dummy TSV 30 as shown in FIG. 7B. In the present invention, whether or not the dummy TSV is left is not important, and may be determined as desired; more importantly, when flattening is performed, it is ground together with the TSV due to the setting of the dummy TSV, avoiding the conventional knowledge. The bridging problem. Then, the back surface of the substrate can be further thinned, for example, by a CMP process to expose the conductive material layer 26 in the via holes.

The configuration of the dummy TSV relative to the TSV can be as desired, without any limitation. Figure 8 is a plan view showing a specific embodiment near the periphery of each TSV 28. One or more dummy TSVs are formed, and the shape and size are not particularly limited. For example, the dummy TSV 30 may be one or plural, which may be the same or similar to the TSV 28 cross-sectional diameter, for example, the diameter is also about 10 micrometers ( But not limited to this; or, for example, a smaller dummy TSV 32, which may be one or more, due to the smaller diameter or area of the cross-section, such as 4 microns or 0.4 microns in diameter or between However, it is not limited to this, and is particularly suitable for a small area of metal distribution sparse outside the TSV 28 and the dummy TSV 30. As shown in Fig. 8, an isolation structure 34 is formed, and an alignment mark structure 36 is formed in the zeroth interlayer dielectric layer on the substrate 10 outside the isolation structure 34 for subsequent processing requiring alignment.

In the present invention, in the TSV structure, the substrate may further include a semiconductor element, which is, for example, a TSV structure in a wafer, in other words, the present invention can be applied to the electric power of each layer of the stacked die and the die. Alternatively, the TSV structure can be a TSV structure in a 矽 adapter plate, in other words, the invention can be applied to a 矽 adapter plate.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Base

12, 22‧‧‧ dielectric layer

14, 15, 16, 17‧ ‧ openings

18‧‧‧ photoresist layer

20‧‧‧through holes

24‧‧‧Barrier layer

26‧‧‧ Conductive material layer

28‧‧‧TSV

30, 32‧‧‧Virtual TSV

34‧‧‧Isolation structure

36‧‧‧ alignment mark structure

101, 102, 103, 104, 105, 106, 107‧ ‧ steps

1 is a flow chart of a method of fabricating a TSV structure in accordance with an embodiment of the present invention.

2 through 6, 7A, 7B, and 7C are cross-sectional views illustrating a method of fabricating a TSV structure in accordance with several embodiments of the present invention.

Figure 8 is a plan view showing an embodiment of the present invention.

10‧‧‧Base

12, 22‧‧‧ dielectric layer

15, 17‧‧‧ openings

20‧‧‧through holes

Claims (20)

A method of fabricating a through-conductor via structure includes: providing a substrate; forming a first dielectric layer on the substrate; patterning the first dielectric layer to have at least one first opening; Forming a via hole in the dielectric layer and the substrate; forming a second dielectric layer on the first dielectric layer in conformity with the shape of the first dielectric layer, the second dielectric layer having a first dielectric layer corresponding to the at least one first At least one second opening of the opening, and the second dielectric layer covers the sidewall of the via hole; a conductive material layer is respectively filled in the via hole and the at least one second opening; and the conductive material layer is The planarization is performed to form a through-conducting via in the via hole. The method of claim 1, wherein the forming the via hole in the first dielectric layer and the substrate comprises: forming a photoresist layer on the first dielectric layer; and patterning the photoresist layer And having a third opening; and removing the first dielectric layer and the substrate portion via the third opening to form the via hole. The method of claim 1, wherein a barrier layer is formed between the conductive material layer and the second dielectric layer. The method of claim 1, wherein a bottom of the at least one first opening is higher than the base An original surface of the bottom, or a portion of the original surface. The method of claim 1, wherein a bottom of the at least one first opening is lower than an original surface of the substrate. The method of claim 1, wherein the second dielectric layer is formed using a thermal oxidation process or a chemical vapor deposition process. The method of claim 1, wherein the second dielectric layer comprises a plurality of second openings, the second openings having different aperture sizes. The method of claim 7, wherein in the step of planarizing the layer of conductive material, the layer of conductive material in at least one of the second openings is completely removed. The method of claim 7, wherein the step of planarizing the layer of conductive material is followed by leaving the remaining second openings and the layer of conductive material therein. The method of claim 1, wherein the first dielectric layer has a plurality of first openings of a plurality of aperture sizes, and one of the first openings has an aperture size that is the same as an aperture size of the via. The method of claim 1 wherein the substrate comprises a semiconductor component. The method of claim 1, wherein the through-conductor structure is a 矽 adapter plate The through-conductor structure in the middle. A through-conductor via structure includes: a substrate; a first dielectric layer disposed on the substrate and having at least one first opening; a via hole passing through the first dielectric layer and the substrate; a second dielectric layer disposed in the at least one first opening and the sidewall of the via hole; and a conductive layer disposed on the sidewall having the via hole formed by the second dielectric layer to form a through hole Conductor. The through-conductor via structure of claim 13, further comprising: a barrier layer between the conductive layer and the second dielectric layer. The through-conductor via structure of claim 13, wherein the bottom of the at least one first opening is higher than an original surface of the substrate or a portion of the original surface. The through-conductor via structure of claim 13, wherein a bottom of the at least one first opening is lower than an original surface of the substrate. The through-conductor via structure of claim 13, wherein the second dielectric layer has at least one second opening corresponding to the at least one first opening, and the conductive layer is further disposed on the at least one second opening Forming at least one dummy through conductor. The through-conductor via structure of claim 17, wherein the aperture of the through-turn via is the same as the aperture size of the at least one dummy through-conductor. The through-conductor via structure of claim 13, wherein the first dielectric layer has a plurality of first openings, and the second dielectric layer has a plurality of second openings corresponding to the plurality of first openings, And the conductive layer is further disposed in the plurality of second openings to form a plurality of dummy through-conductors. The through-conductor via structure of claim 13, wherein the substrate comprises a semiconductor component.