TW201328445A - Embedded interposer carrier structure and fabricating method thereof, and flip chip structure and fabricating method thereof - Google Patents
Embedded interposer carrier structure and fabricating method thereof, and flip chip structure and fabricating method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
本發明是有關於一種封裝用構件,且特別是有關於一種中介層內埋基板結構。The present invention relates to a package member, and more particularly to an interposer buried substrate structure.
近年來,隨著電子技術的日新月異,高科技電子產業的相繼問世,使得更人性化、功能更佳的電子產品不斷地推陳出新,並朝向輕、薄、短、小的趨勢設計。目前在半導體封裝製程中,線路基板(circuit substrate)是經常使用的構裝元件之一,其中線路基板主要由多層圖案化線路層(patterned circuit layer)及多層圖案化介電層(patterned dielectric layer)交替疊合而成,由於線路基板具有佈線細密、組裝緊湊及性能良好等優點,使得線路基板已經成為晶片尺寸封裝(chip scale package,CSP)與倒裝晶片封裝(flip chip package)之主流。In recent years, with the rapid development of electronic technology, the high-tech electronics industry has come out one after another, making more humanized and better-functioning electronic products constantly innovating and designing towards light, thin, short and small trends. Currently, in a semiconductor packaging process, a circuit substrate is one of the commonly used component components, wherein the circuit substrate is mainly composed of a plurality of patterned circuit layers and a patterned dielectric layer. Alternately stacked, the circuit substrate has become the mainstream of the chip scale package (CSP) and the flip chip package because of the advantages of fine wiring, compact assembly, and good performance.
在主動元件已利用晶片尺寸封裝或倒裝晶片技術,甚至更進一步以3D堆疊技術縮小所有元件所佔據之體積的發展下,為了解決現今或未來可能發生於構裝上的問題,進一步使用矽中介層內埋基板結構概念,以達到面積縮小化的整合需求,對電性的考量亦可有更進一步的提升。In the development of active components using wafer size packaging or flip chip technology, and even further reducing the volume occupied by all components by 3D stacking technology, in order to solve the problems that may occur in the structure today or in the future, further use of the intermediary The concept of embedded substrate structure in the layer can meet the integration requirements of area reduction, and the electrical considerations can be further improved.
然而,在進行增層製程、組裝製程或模封製程時,常會造成矽中介層位置移動,而使得後續製程的對位精度變差,因而無法應用於具有高密度連接需求之產品。However, when the build-up process, the assembly process, or the mold-sealing process is performed, the position of the inter-layer is often caused to move, and the alignment accuracy of subsequent processes is deteriorated, so that it cannot be applied to products having high-density connection requirements.
本發明的目的是提供一種中介層內埋基板結構,其可有效地固定中介層的位置。It is an object of the present invention to provide an interposer embedded substrate structure that effectively positions the interposer.
本發明的另一目的是提供一種中介層內埋基板結構的製造方法,其可避免中介層產生偏移。Another object of the present invention is to provide a method of fabricating an interposer embedded substrate structure that avoids offset of the interposer.
本發明的另一目的是提供一種倒裝晶片結構,其具有較佳的可靠度。Another object of the present invention is to provide a flip chip structure that has better reliability.
本發明的另一目的是提供一種倒裝晶片結構的製造方法,其可提升組裝時的對準精度。Another object of the present invention is to provide a method of fabricating a flip chip structure that improves alignment accuracy during assembly.
本發明提出一種中介層內埋基板結構,包括中介層、聚合物層、至少一增層膜及至少一接點。聚合物層覆蓋中介層。增層膜設置於聚合物層上。接點穿過增層膜,且與中介層電性連接。The invention provides an interposer embedded substrate structure, comprising an interposer, a polymer layer, at least one buildup film and at least one contact. The polymer layer covers the interposer. The buildup film is disposed on the polymer layer. The joint passes through the buildup film and is electrically connected to the interposer.
依照本發明的一實施例所述,在上述之中介層內埋基板結構中,中介層包括基材及至少一矽通孔。矽通孔設置於基材中。According to an embodiment of the present invention, in the buried substrate structure, the interposer includes a substrate and at least one through hole. The through hole is disposed in the substrate.
依照本發明的一實施例所述,在上述之中介層內埋基板結構中,中介層更包括重佈線層,設置於基材的表面上,且與矽通孔電性連接。According to an embodiment of the present invention, in the buried substrate structure, the interposer further includes a redistribution layer disposed on the surface of the substrate and electrically connected to the through via.
依照本發明的一實施例所述,在上述之中介層內埋基板結構中,聚合物層的材料例如是高分子感光材料。According to an embodiment of the present invention, in the buried substrate structure of the interposer, the material of the polymer layer is, for example, a polymer photosensitive material.
依照本發明的一實施例所述,在上述之中介層內埋基板結構中,高分子感光材料例如是聚亞醯胺(polyimide,PI)、苯環丁烯(benzocyclobutene,BCB)、SU-8(環氧樹脂)、矽膠或聚苯噁唑(polybenzoxazole,PBO)。According to an embodiment of the present invention, in the interposer substrate structure, the polymer photosensitive material is, for example, polyimide (PI), benzocyclobutene (BCB), SU-8. (epoxy resin), silicone or polybenzoxazole (PBO).
依照本發明的一實施例所述,在上述之中介層內埋基板結構中,增層膜的材料例如是ABF(Ajinomoto build-up film)、背膠銅箔(resin coated copper,RCC)、聚丙烯(polypropylene,PP)或樹脂(resin)。According to an embodiment of the present invention, in the buried substrate structure, the material of the build-up film is, for example, ABF (Ajinomoto build-up film), resin coated copper (RCC), and poly Propylene (PP) or resin (resin).
依照本發明的一實施例所述,在上述之中介層內埋基板結構中,更包括載板,中介層貼附於載板上,且聚合物層覆蓋載板。According to an embodiment of the present invention, in the buried substrate structure, the carrier layer further includes a carrier, the interposer is attached to the carrier, and the polymer layer covers the carrier.
依照本發明的一實施例所述,在上述之中介層內埋基板結構中,更包括銲墊,設置於聚合物層中,且電性連接於中介層與接點。According to an embodiment of the present invention, the buried substrate structure further includes a solder pad disposed in the polymer layer and electrically connected to the interposer and the contact.
依照本發明的一實施例所述,在上述之中介層內埋基板結構中,更包括晶種層,設置於增層膜與接點之間。According to an embodiment of the present invention, in the buried substrate structure, the seed layer further includes a seed layer disposed between the buildup film and the contact.
依照本發明的一實施例所述,在上述之中介層內埋基板結構中,更包括銲球,設置於接點上。According to an embodiment of the present invention, in the buried substrate structure of the interposer, a solder ball is further disposed on the contact.
本發明提出一種中介層內埋基板結構的製造方法,包括下列步驟。首先,將中介層貼附於載板上。接著,形成覆蓋中介層與載板的聚合物層。然後,於聚合物層上形成至少一增層膜。接下來,形成穿過增層膜的至少一接點,且接點與中介層電性連接。The invention provides a method for manufacturing an interposer embedded substrate structure, comprising the following steps. First, the interposer is attached to the carrier. Next, a polymer layer covering the interposer and the carrier is formed. Then, at least one buildup film is formed on the polymer layer. Next, at least one contact is formed through the buildup film, and the contact is electrically connected to the interposer.
依照本發明的一實施例所述,在上述之中介層內埋基板結構的製造方法中,聚合物層的形成方法例如是狹縫式塗布法(slot die coating)或網版印刷法(screen printing)。According to an embodiment of the present invention, in the method of fabricating the interposer substrate structure, the method of forming the polymer layer is, for example, slot die coating or screen printing. ).
依照本發明的一實施例所述,在上述之中介層內埋基板結構的製造方法中,於形成增層膜之前,更包括進行下列步驟。首先,於聚合物層中形成至少一第一開口,且第一開口暴露出中介層。接著,於第一開口中形成銲墊,且銲墊電性連接至中介層。According to an embodiment of the present invention, in the method of fabricating the interposer substrate structure, the following steps are further included before the formation of the buildup film. First, at least one first opening is formed in the polymer layer, and the first opening exposes the interposer. Next, a solder pad is formed in the first opening, and the solder pad is electrically connected to the interposer.
依照本發明的一實施例所述,在上述之中介層內埋基板結構的製造方法中,第一開口的形成方法例如是雷射直接成像法(laser direct image,LDI)。According to an embodiment of the present invention, in the method of fabricating the interposer substrate structure, the method of forming the first opening is, for example, a laser direct image (LDI).
依照本發明的一實施例所述,在上述之中介層內埋基板結構的製造方法中,增層膜的形成方法例如是壓合法(lamination)。According to an embodiment of the present invention, in the method of fabricating the interposer substrate structure, the method of forming the buildup film is, for example, lamination.
依照本發明的一實施例所述,在上述之中介層內埋基板結構的製造方法中,穿過增層膜的接點的形成方法包括下列步驟。首先,形成貫穿增層膜的開口。接著,於增層膜上形成晶種層。然後,於晶種層上形乾膜,乾膜暴露出部分晶種層。接下來,於乾膜所暴露出的晶種層上形成接點,且接點填滿開口。According to an embodiment of the present invention, in the method of fabricating a buried substrate structure, the method of forming a contact through the build-up film includes the following steps. First, an opening is formed through the buildup film. Next, a seed layer is formed on the buildup film. Then, a dry film is formed on the seed layer, and the dry film exposes a portion of the seed layer. Next, a contact is formed on the seed layer exposed by the dry film, and the contact fills the opening.
依照本發明的一實施例所述,在上述之中介層內埋基板結構的製造方法中,開口的形成方法例如是雷射鑽孔法(laser drilling)。According to an embodiment of the present invention, in the method of manufacturing a buried substrate structure, the method of forming the opening is, for example, laser drilling.
依照本發明的一實施例所述,在上述之中介層內埋基板結構的製造方法中,晶種層的形成方法例如是無電鍍法(electroless plating)。According to an embodiment of the present invention, in the method of fabricating the interposer substrate structure, the method of forming the seed layer is, for example, electroless plating.
依照本發明的一實施例所述,在上述之中介層內埋基板結構的製造方法中,接點的形成方法例如是電鍍法(electroplating)。According to an embodiment of the present invention, in the method of fabricating the interposer substrate structure, the method of forming the contacts is, for example, electroplating.
依照本發明的一實施例所述,在上述之中介層內埋基板結構的製造方法中,更包括於接點上形成銲球。According to an embodiment of the present invention, in the method for fabricating a buried substrate structure in the interposer, a solder ball is further formed on the contact.
本發明提出一種倒裝晶片結構,包括上述之中介層內埋基板結構及晶片。晶片接合到中介層內埋基板結構中的中介層。The present invention provides a flip chip structure comprising the above-described interposer buried substrate structure and a wafer. The wafer is bonded to the interposer in the interposer to embed the interposer in the substrate structure.
本發明提出一種倒裝晶片結構的製造方法,包括下列步驟。首先,提供上述之中介層內埋基板結構。接著,將晶片接合到中介層內埋基板結構中的中介層。The present invention provides a method of fabricating a flip chip structure comprising the following steps. First, the interposer substrate structure described above is provided. Next, the wafer is bonded to the interposer in the interposer buried substrate structure.
基於上述,在本發明所提出的中介層內埋基板結構中,由於聚合物層覆蓋中介層,所以可藉由聚合物層固定中介層的位置。此外,在本發明所提出的中介層內埋基板結構的製造方法中,由於聚合物層固定中介層,所以可避免中介層在後續增層製程、組裝製程或模封製程等加壓製程中產生偏移,因此在後續製程中具有較佳的對位精度。Based on the above, in the interposer substrate structure proposed by the present invention, since the polymer layer covers the interposer, the position of the interposer can be fixed by the polymer layer. In addition, in the manufacturing method of the interposer substrate structure in the present invention, since the interposer is fixed by the polymer layer, the interposer can be prevented from being generated in a pressurization process such as a subsequent build-up process, an assembly process, or a molding process. Offset, so it has better alignment accuracy in subsequent processes.
另一方面,在本發明所提出之倒裝晶片結構及其製造方法中,由於是使用中介層內埋基板結構進行組裝,因此具有較佳的對準精度及可靠度。On the other hand, in the flip chip structure and the manufacturing method thereof according to the present invention, since the interposer is embedded in the substrate structure, it has better alignment accuracy and reliability.
為讓本發明之上述和其他目的和特徵能更明顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下。The above and other objects and features of the present invention will become more apparent from the description of the appended claims.
圖1A至圖1N所繪示為本發明之一實施例的中介層內埋基板結構的製造流程剖面圖。圖1O所繪示為本發明之一實施例的倒裝晶片組裝的示意圖。1A to FIG. 1N are cross-sectional views showing a manufacturing process of an interposer substrate structure in accordance with an embodiment of the present invention. FIG. 10 is a schematic diagram of a flip chip assembly according to an embodiment of the present invention.
首先,請參照圖1A,將中介層102貼附於載板100上。其中,中介層102例如是藉由如黏晶膠膜(die attach film,DAF)等黏著劑貼附於載板100上。載板100的材料包括玻璃、FR4(玻璃纖維布)或銅箔(Cu foil)等。First, referring to FIG. 1A, the interposer 102 is attached to the carrier 100. The interposer 102 is attached to the carrier 100 by, for example, an adhesive such as a die attach film (DAF). The material of the carrier 100 includes glass, FR4 (glass fiber cloth) or copper foil (Cu foil) or the like.
中介層102包括基材104及至少一矽通孔106。矽通孔106設置於基材104中。基材104的材料例如是矽或玻璃等。矽通孔106的材料例如是銅(Cu)或鎳(Ni)等。此外,中介層102更可包括重佈線層108,設置於基材104面向載板100的表面上,且與矽通孔106電性連接。重佈線層108包括介電層110與金屬線路112。其中,金屬線路112設置於介電層110中,且與矽通孔106電性連接。介電層110的材料例如是高分子感光材料或氧化矽(SiO2)等。金屬線路112的材料例如是銅或鋁(Al)等。The interposer 102 includes a substrate 104 and at least one through via 106. The through hole 106 is disposed in the substrate 104. The material of the substrate 104 is, for example, tantalum or glass. The material of the through hole 106 is, for example, copper (Cu) or nickel (Ni). In addition, the interposer layer 102 may further include a redistribution layer 108 disposed on the surface of the substrate 104 facing the carrier 100 and electrically connected to the through via 106. The redistribution layer 108 includes a dielectric layer 110 and a metal line 112. The metal line 112 is disposed in the dielectric layer 110 and electrically connected to the through hole 106. The material of the dielectric layer 110 is, for example, a polymer photosensitive material or cerium oxide (SiO 2 ). The material of the metal line 112 is, for example, copper or aluminum (Al) or the like.
接著,形成覆蓋中介層102與載板100的聚合物層114。聚合物層114的材料例如是高分子感光材料等,而高分子感光材料例如是聚亞醯胺(polyimide,PI)、苯環丁烯(benzocyclobutene,BCB)、SU-8(環氧樹脂)、矽膠或聚苯噁唑(polybenzoxazole,PBO)等。聚合物層114的形成方法例如是狹縫式塗布法或網版印刷法等。Next, a polymer layer 114 covering the interposer 102 and the carrier 100 is formed. The material of the polymer layer 114 is, for example, a polymer photosensitive material, and the polymer photosensitive material is, for example, polyimide (PI), benzocyclobutene (BCB), SU-8 (epoxy resin), Silicone or polybenzoxazole (PBO) and the like. The method of forming the polymer layer 114 is, for example, a slit coating method or a screen printing method.
然後,請參照圖1B,可選擇性地於聚合物層114中形成至少一開口116,且開口116暴露出中介層102及矽通孔106。開口116的形成方法例如是雷射直接成像法等。Then, referring to FIG. 1B, at least one opening 116 may be selectively formed in the polymer layer 114, and the opening 116 exposes the interposer 102 and the through hole 106. The method of forming the opening 116 is, for example, a laser direct imaging method or the like.
接下來,請參照圖1C,可選擇性地於開口116中形成銲墊118,且銲墊118電性連接至中介層102之矽通孔106。銲墊118的材料例如是銅、鎳、鎳/金(Ni/Au)、鎳/鈀/金(Ni/Pd/Au)或金等。銲墊118的形成方法例如是進行沉積製程與圖案化製程等而形成。Next, referring to FIG. 1C , a pad 118 may be selectively formed in the opening 116 , and the pad 118 is electrically connected to the through hole 106 of the interposer 102 . The material of the pad 118 is, for example, copper, nickel, nickel/gold (Ni/Au), nickel/palladium/gold (Ni/Pd/Au) or gold. The formation method of the pad 118 is formed, for example, by performing a deposition process, a patterning process, or the like.
之後,請參照圖1D,於聚合物層114上形成增層膜120。增層膜120的材料例如是ABF、背膠銅箔(resin coated copper,RCC)、聚丙烯(polypropylene,PP)或樹脂(resin)等。增層膜120的形成方法例如是壓合法等。Thereafter, referring to FIG. 1D, a buildup film 120 is formed on the polymer layer 114. The material of the buildup film 120 is, for example, ABF, resin coated copper (RCC), polypropylene (PP), or resin. The method of forming the buildup film 120 is, for example, a press method or the like.
再者,請參照圖1E,形成貫穿增層膜120的開口122並露出銲墊118。開口122的形成方法例如是雷射鑽孔法等。Furthermore, referring to FIG. 1E, an opening 122 is formed through the buildup film 120 to expose the pad 118. The method of forming the opening 122 is, for example, a laser drilling method or the like.
繼之,請參照圖1F,於增層膜120上形成晶種層124,使晶種層124形成於增層膜120的表面與開口122內的增層膜120之膜壁上及銲墊118上。晶種層124的材料例如是銅、鈦/鋁(Ti/Al)或鈦/銅(Ti/Cu)等。晶種層124的形成方法例如是無電鍍法或濺鍍等。Then, referring to FIG. 1F, a seed layer 124 is formed on the build-up film 120, so that the seed layer 124 is formed on the surface of the build-up film 120 and the film wall of the build-up film 120 in the opening 122 and the pad 118. on. The material of the seed layer 124 is, for example, copper, titanium/aluminum (Ti/Al) or titanium/copper (Ti/Cu). The method of forming the seed layer 124 is, for example, electroless plating or sputtering.
隨後,請參照圖1G,於晶種層124上形乾膜126,乾膜126圖案化後暴露出部分晶種層124。乾膜126的材料例如是正型光阻或負型光阻等光阻材料。乾膜126的形成方法例如是進行微影製程等而形成。Subsequently, referring to FIG. 1G, a dry film 126 is formed on the seed layer 124, and the dry film 126 is patterned to expose a portion of the seed layer 124. The material of the dry film 126 is, for example, a photoresist material such as a positive photoresist or a negative photoresist. The method of forming the dry film 126 is formed, for example, by performing a lithography process or the like.
接著,請參照圖1H,於乾膜126所暴露出的晶種層124上形成至少一接點128,且接點128填滿開口122。其中,接點128穿過增層膜120,且例如是經由晶種層124、銲墊118與中介層102的矽通孔106電性連接。接點128的材料例如是銅等。接點128的形成方法例如是電鍍法等。雖然,接點128是藉由上述方法所形成,但並不用以限制本發明。Next, referring to FIG. 1H, at least one contact 128 is formed on the seed layer 124 exposed by the dry film 126, and the contact 128 fills the opening 122. The contact point 128 passes through the build-up film 120 and is electrically connected to the through-hole 106 of the interposer 102 via the seed layer 124 and the pad 118 , for example. The material of the contact 128 is, for example, copper or the like. The method of forming the contact 128 is, for example, an electroplating method or the like. Although the contact 128 is formed by the above method, it is not intended to limit the present invention.
然後,請參照圖1I,移除乾膜126。乾膜126的移除方法例如是乾式去光阻法等。Then, referring to FIG. 1I, the dry film 126 is removed. The method of removing the dry film 126 is, for example, a dry de-resist method or the like.
接下來,請參照圖1J,以接點128為罩幕,移除部分晶種層124,而形成最基本的中介層內埋基板結構10。部分晶種層124的移除方法例如是回蝕刻法等。Next, referring to FIG. 1J, a portion of the seed layer 124 is removed with the contact 128 as a mask to form the most basic interposer buried substrate structure 10. The method of removing the partial seed layer 124 is, for example, an etch back method or the like.
之後,請參照圖1K,可重複進行圖1D至圖1J的步驟,而於聚合物層114上形成四層增層膜120,且於增層膜120中形成多個接點128。在此實施例中,雖然是以形成四層增層膜120為例進行說明,但並不用以限制本發明。亦即,只要於聚合物層114上形成至少一增層膜120,且於至少一增層膜120中形成至少一接點128即屬於本發明所保護的範圍。Thereafter, referring to FIG. 1K, the steps of FIG. 1D to FIG. 1J may be repeated, and four build-up films 120 are formed on the polymer layer 114, and a plurality of contacts 128 are formed in the build-up film 120. In this embodiment, although the formation of the four-layer build-up film 120 is described as an example, it is not intended to limit the present invention. That is, it is within the scope of the present invention to form at least one buildup film 120 on the polymer layer 114 and to form at least one contact 128 in at least one buildup film 120.
再者,請參照圖1L,可選擇性地於最上層的增層膜120中形成暴露出接點128的開口130。開口130的形成方法例如是對增層膜120進行圖案化製程而形成。Furthermore, referring to FIG. 1L, an opening 130 exposing the contact 128 may be selectively formed in the uppermost buildup film 120. The method of forming the opening 130 is formed, for example, by patterning the build-up film 120.
繼之,請參照圖1M,可選擇性地於開口130所暴露的接點128上形成銲球132。銲球132的材料例如是錫、錫銀(SnAg)或錫銀銅(SnAgCu)等。銲球132的形成方法例如進行浸錫製程(dip soldering process)、錫膏印刷製程(solder printing process)、植球製程、電鍍製程或無電鍍製程等而形成。Next, referring to FIG. 1M, solder balls 132 may be selectively formed on the contacts 128 exposed by the openings 130. The material of the solder ball 132 is, for example, tin, tin silver (SnAg) or tin silver copper (SnAgCu). The method of forming the solder balls 132 is formed by, for example, a dip soldering process, a solder printing process, a ball bonding process, an electroplating process, or an electroless plating process.
隨後,請參照圖1N,可選擇性地移除載板100。載板100的移除方法例如是照光剝離、機械力剝離或溶劑溶解剝離等。Subsequently, referring to FIG. 1N, the carrier 100 can be selectively removed. The removal method of the carrier 100 is, for example, photographic peeling, mechanical force peeling, solvent dissolution peeling, or the like.
接著,請參照圖1O,進行倒裝晶片組裝製程,以將晶片200接合到中介層內埋基板結構10中的中介層102,而形成倒裝晶片結構400。倒裝晶片組裝製程例如是藉由銲球202將晶片200接合到重佈線層108的金屬線路112,而使得晶片200與中介層102進行接合。Next, referring to FIG. 10, a flip chip assembly process is performed to bond the wafer 200 to the interposer 102 in the interposer buried substrate structure 10 to form a flip chip structure 400. The flip chip assembly process, for example, is to bond the wafer 200 to the metal lines 112 of the redistribution layer 108 by solder balls 202, thereby bonding the wafer 200 to the interposer 102.
圖2A至圖2B所繪示為本發明之另一實施例的倒裝晶片組裝流程剖面圖。圖2A為接續圖1M之後所進行的圖式說明。圖2A至圖2B與圖1A至圖1M中相同的標號表示相似的構件,且具有相似的材料、配置方式、形成方法及功效,故於此不再贅述。2A-2B are cross-sectional views showing a process of assembling a flip chip according to another embodiment of the present invention. Fig. 2A is a schematic illustration of the following description taken after Fig. 1M. The same reference numerals in FIGS. 2A to 2B denote the same members as those in FIGS. 1A to 1M, and have similar materials, configurations, formation methods, and effects, and thus will not be described again.
首先,請參照圖2A,於載板100上形成開口134,且開口134暴露出重佈線層108的金屬線路112。開口134的形成方法例如是對載板100進行圖案化製程而形成。First, referring to FIG. 2A, an opening 134 is formed in the carrier 100, and the opening 134 exposes the metal line 112 of the redistribution layer 108. The method of forming the opening 134 is formed, for example, by performing a patterning process on the carrier 100.
接著,請參照圖2B,進行倒裝晶片組裝製程,以將晶片300接合到中介層內埋基板結構10中的中介層102,而形成倒裝晶片結構400'。倒裝晶片組裝製程例如是藉由銲球302將晶片300接合到由開口134所暴露的重佈線層108的金屬線路112,而使得晶片300與中介層102進行接合。Next, referring to FIG. 2B, a flip chip assembly process is performed to bond the wafer 300 to the interposer 102 in the interposer buried substrate structure 10 to form a flip chip structure 400'. The flip chip assembly process, for example, is to bond the wafer 300 to the metal lines 112 of the redistribution layer 108 exposed by the openings 134 by solder balls 302, thereby bonding the wafer 300 to the interposer 102.
基於上述實施例可知,在中介層內埋基板結構10的製造方法中,由於聚合物層114覆蓋中介層102,所以可藉由聚合物層114固定中介層102的位置,因此可避免中介層102在後續增層製程、組裝製程或模封製程等加壓製程中產生偏移,進而提升後續製程的對位精度。此外,在倒裝晶片結構400、400'的製造方法中,由於是使用中介層內埋基板結構10進行組裝,因此可提升組裝時的對準精度。Based on the above embodiments, in the manufacturing method of the interposer substrate structure 10, since the polymer layer 114 covers the interposer 102, the position of the interposer 102 can be fixed by the polymer layer 114, so that the interposer 102 can be avoided. The offset is generated in a pressurization process such as a subsequent build-up process, an assembly process, or a mold-sealing process, thereby improving the alignment accuracy of subsequent processes. Further, in the method of manufacturing the flip-chip structures 400 and 400', since the interposer-embedded substrate structure 10 is used for assembly, the alignment accuracy during assembly can be improved.
以下,藉由圖1J、圖1M與圖1N來說明上述實施例所提出之中介層內埋基板結構10。Hereinafter, the interposer buried substrate structure 10 proposed in the above embodiment will be described with reference to FIGS. 1J, 1M, and 1N.
首先,請參照圖1J,中介層內埋基板結構10包括中介層102、聚合物層114、增層膜120及至少一接點128。中介層102可包括基材104及至少一矽通孔106,且矽通孔設置於基材104中。中介層102更可選擇性地包括重佈線層108,且重佈線層108設置於基材104的表面上,且與矽通孔106電性連接。聚合物層114覆蓋中介層102。增層膜120設置於聚合物層114上。接點128穿過增層膜120,且與中介層102電性連接。另外,中介層內埋基板結構10更可選擇性地包括銲墊118、晶種層124與載板100中的至少一者。銲墊118設置於聚合物層114中,且電性連接於中介層102的矽通孔106與接點128。晶種層124設置於增層膜120與接點128之間。中介層102貼附於載板100上,且聚合物層114覆蓋載板100。First, referring to FIG. 1J, the interposer buried substrate structure 10 includes an interposer 102, a polymer layer 114, a build-up film 120, and at least one contact 128. The interposer 102 can include a substrate 104 and at least one through via 106, and the via is disposed in the substrate 104. The interposer 102 further includes a redistribution layer 108, and the redistribution layer 108 is disposed on the surface of the substrate 104 and electrically connected to the via via 106. The polymer layer 114 covers the interposer 102. The buildup film 120 is disposed on the polymer layer 114. The contact 128 passes through the build-up film 120 and is electrically connected to the interposer 102. In addition, the interposer buried substrate structure 10 more selectively includes at least one of the pad 118, the seed layer 124, and the carrier 100. The pad 118 is disposed in the polymer layer 114 and electrically connected to the through hole 106 of the interposer 102 and the contact 128. The seed layer 124 is disposed between the buildup film 120 and the contact 128. The interposer 102 is attached to the carrier 100 and the polymer layer 114 covers the carrier 100.
相較於圖1J中的中介層內埋基板結構10,圖1M中的中介層內埋基板結構10更包括銲球132,且具有較多的增層膜120及接點128。銲球132例如是設置於由開口130所暴露的接點128上。The interposer buried substrate structure 10 of FIG. 1M further includes solder balls 132 and has more buildup films 120 and contacts 128. Solder balls 132 are disposed, for example, on contacts 128 exposed by openings 130.
相較於圖1M中的中介層內埋基板結構10,圖1N中的中介層內埋基板結構10不具有載板100。The interposer buried substrate structure 10 of FIG. 1N does not have the carrier 100 as compared to the interposer buried substrate structure 10 of FIG. 1M.
於此技術領域具有通常知識者可依照產品設計需求而自行選擇圖1J、圖1M或圖1N中的中介層內埋基板結構10,以進行後續製程。此外,中介層內埋基板結構10中各構件的材料、特性、配置方式、形成方法及功效已於上述實施例中進行詳盡地說明,故於此不再贅述。Those skilled in the art can select the interposer buried substrate structure 10 in FIG. 1J, FIG. 1M or FIG. 1N according to product design requirements for subsequent processes. In addition, the materials, characteristics, arrangement, formation method and efficacy of each component in the interposer substrate structure 10 have been described in detail in the above embodiments, and thus will not be described again.
基於上述實施例可知,在中介層內埋基板結構10中,由於聚合物層114覆蓋中介層102,所以可藉由聚合物層114固定中介層102的位置,而可防止中介層102在後續增層製程、組裝製程或模封製程中產生偏移。Based on the above embodiments, in the interposer substrate structure 10, since the polymer layer 114 covers the interposer 102, the position of the interposer 102 can be fixed by the polymer layer 114, thereby preventing the interposer 102 from increasing in the subsequent stage. An offset occurs in the layer process, assembly process, or molding process.
以下,藉由圖1O與圖2B來說明上述實施例所提出之倒裝晶片結構400、400'。Hereinafter, the flip chip structures 400, 400' proposed in the above embodiments will be described with reference to FIGS. 10 and 2B.
請參照圖1O,倒裝晶片結構400包括中介層內埋基板結構10及晶片200。晶片200接合到中介層內埋基板結構10中的中介層102。此外,倒裝晶片結構400更包括銲球202,用以將晶片200接合到重佈線層108的金屬線路112,而使得晶片200與中介層102進行接合。Referring to FIG. 10, the flip chip structure 400 includes an interposer buried substrate structure 10 and a wafer 200. The wafer 200 is bonded to the interposer 102 in the interposer buried substrate structure 10. In addition, the flip chip structure 400 further includes solder balls 202 for bonding the wafer 200 to the metal lines 112 of the redistribution layer 108 to bond the wafer 200 with the interposer 102.
此外,請參照圖2B,倒裝晶片結構400'包括中介層內埋基板結構10及晶片300。晶片300接合到中介層內埋基板結構10中的中介層102。此外,倒裝晶片結構400'更包括銲球302,用以將晶片300接合到重佈線層108的金屬線路112,而使得晶片300與中介層102進行接合。In addition, referring to FIG. 2B, the flip chip structure 400' includes an interposer buried substrate structure 10 and a wafer 300. The wafer 300 is bonded to the interposer 102 in the interposer buried substrate structure 10. In addition, the flip chip structure 400' further includes solder balls 302 for bonding the wafer 300 to the metal lines 112 of the redistribution layer 108 to bond the wafer 300 with the interposer 102.
基於上述實施例可知,由於倒裝晶片結構400、400'是使用中介層內埋基板結構10進行組裝,因此可避免中介層102產生偏移,而具有較佳的可靠度。Based on the above embodiments, since the flip chip structures 400, 400' are assembled using the interposer buried substrate structure 10, the interposer 102 can be prevented from shifting and has better reliability.
綜上所述,上述實施例至少具有下列特徵:In summary, the above embodiment has at least the following features:
1. 上述實施例所提出的中介層內埋基板結構可有效地固定中介層的位置。1. The interposer buried substrate structure proposed in the above embodiment can effectively fix the position of the interposer.
2. 藉由上述實施例所提出的中介層內埋基板結構的製造方法可避免中介層產生偏移,進而提升後續製程的對位精度。2. The manufacturing method of the interposer substrate structure proposed by the above embodiment can avoid the offset of the interposer, thereby improving the alignment accuracy of the subsequent process.
3. 上述實施例所提出的倒裝晶片結構具有較佳的可靠度。3. The flip chip structure proposed in the above embodiments has better reliability.
4. 藉由上述實施例所提出的倒裝晶片結構的製造方法,可提升組裝時的對準精度。4. With the manufacturing method of the flip chip structure proposed in the above embodiment, the alignment accuracy during assembly can be improved.
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
10...中介層內埋基板結構10. . . Buried substrate structure
100...載板100. . . Carrier board
102...中介層102. . . Intermediary layer
104...基材104. . . Substrate
106...矽通孔106. . .矽 through hole
108...重佈線層108. . . Redistribution layer
110...介電層110. . . Dielectric layer
112...金屬線路112. . . Metal line
114...聚合物層114. . . Polymer layer
116、122、130、134...開口116, 122, 130, 134. . . Opening
118...銲墊118. . . Solder pad
120...增層膜120. . . Additive film
124...晶種層124. . . Seed layer
126...乾膜126. . . Dry film
128...接點128. . . contact
132...銲球132. . . Solder ball
200、300...晶片200, 300. . . Wafer
202、302...銲球202, 302. . . Solder ball
400、400'...倒裝晶片結構400, 400'. . . Flip chip structure
圖1A至圖1N所繪示為本發明之一實施例的中介層內埋基板結構的製造流程剖面圖。1A to FIG. 1N are cross-sectional views showing a manufacturing process of an interposer substrate structure in accordance with an embodiment of the present invention.
圖1O所繪示為本發明之一實施例的倒裝晶片組裝的示意圖。FIG. 10 is a schematic diagram of a flip chip assembly according to an embodiment of the present invention.
圖2A至圖2B所繪示為本發明之另一實施例的倒裝晶片組裝流程剖面圖。2A-2B are cross-sectional views showing a process of assembling a flip chip according to another embodiment of the present invention.
10...中介層內埋基板結構10. . . Buried substrate structure
102...中介層102. . . Intermediary layer
104...基材104. . . Substrate
106...矽通孔106. . .矽 through hole
108...重佈線層108. . . Redistribution layer
110...介電層110. . . Dielectric layer
112...金屬線路112. . . Metal line
114...聚合物層114. . . Polymer layer
116、122、130...開口116, 122, 130. . . Opening
118...銲墊118. . . Solder pad
120...增層膜120. . . Additive film
124...晶種層124. . . Seed layer
128...接點128. . . contact
132...銲球132. . . Solder ball
Claims (22)
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI611547B (en) * | 2015-01-14 | 2018-01-11 | 鈺橋半導體股份有限公司 | Wiring board with interposer and dual wiring structures integrated together and method of making the same |
TWI622151B (en) * | 2016-12-07 | 2018-04-21 | 矽品精密工業股份有限公司 | Carrier substrate for semiconductor packaging and package structure thereof, and method for fabricating semiconductor package |
TWI644408B (en) * | 2016-12-05 | 2018-12-11 | 美商美光科技公司 | Interposer and semiconductor package |
CN111128948A (en) * | 2019-12-30 | 2020-05-08 | 上海先方半导体有限公司 | Structure for realizing coplanarity of embedded adapter plate and substrate and manufacturing method thereof |
CN111128949A (en) * | 2019-12-30 | 2020-05-08 | 上海先方半导体有限公司 | Embedded adapter plate and manufacturing method of packaging structure thereof |
-
2011
- 2011-12-27 TW TW100148928A patent/TWI437932B/en not_active IP Right Cessation
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI611547B (en) * | 2015-01-14 | 2018-01-11 | 鈺橋半導體股份有限公司 | Wiring board with interposer and dual wiring structures integrated together and method of making the same |
TWI644408B (en) * | 2016-12-05 | 2018-12-11 | 美商美光科技公司 | Interposer and semiconductor package |
TWI622151B (en) * | 2016-12-07 | 2018-04-21 | 矽品精密工業股份有限公司 | Carrier substrate for semiconductor packaging and package structure thereof, and method for fabricating semiconductor package |
CN111128948A (en) * | 2019-12-30 | 2020-05-08 | 上海先方半导体有限公司 | Structure for realizing coplanarity of embedded adapter plate and substrate and manufacturing method thereof |
CN111128949A (en) * | 2019-12-30 | 2020-05-08 | 上海先方半导体有限公司 | Embedded adapter plate and manufacturing method of packaging structure thereof |
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TWI437932B (en) | 2014-05-11 |
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