TW201324788A - Manufacturing method of embossed structure, thin film transistor, film capacitor, actuator, piezoelectric inkjet head and optical component - Google Patents
Manufacturing method of embossed structure, thin film transistor, film capacitor, actuator, piezoelectric inkjet head and optical component Download PDFInfo
- Publication number
- TW201324788A TW201324788A TW101140727A TW101140727A TW201324788A TW 201324788 A TW201324788 A TW 201324788A TW 101140727 A TW101140727 A TW 101140727A TW 101140727 A TW101140727 A TW 101140727A TW 201324788 A TW201324788 A TW 201324788A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- embossed structure
- precursor composition
- composition layer
- structure according
- Prior art date
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/135—Nozzles
- B41J2/16—Production of nozzles
- B41J2/1607—Production of print heads with piezoelectric elements
- B41J2/161—Production of print heads with piezoelectric elements of film type, deformed by bending and disposed on a diaphragm
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/135—Nozzles
- B41J2/16—Production of nozzles
- B41J2/1621—Manufacturing processes
- B41J2/1623—Manufacturing processes bonding and adhesion
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/135—Nozzles
- B41J2/16—Production of nozzles
- B41J2/1621—Manufacturing processes
- B41J2/1626—Manufacturing processes etching
- B41J2/1628—Manufacturing processes etching dry etching
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/135—Nozzles
- B41J2/16—Production of nozzles
- B41J2/1621—Manufacturing processes
- B41J2/164—Manufacturing processes thin film formation
- B41J2/1645—Manufacturing processes thin film formation thin film formation by spincoating
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/02—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition
- C23C18/06—Coating on selected surface areas, e.g. using masks
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/02—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition
- C23C18/08—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition characterised by the deposition of metallic material
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/02—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition
- C23C18/12—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition characterised by the deposition of inorganic material other than metallic material
- C23C18/1204—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition characterised by the deposition of inorganic material other than metallic material inorganic material, e.g. non-oxide and non-metallic such as sulfides, nitrides based compounds
- C23C18/1208—Oxides, e.g. ceramics
- C23C18/1216—Metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
- H10D86/0241—Manufacture or treatment of multiple TFTs using liquid deposition, e.g. printing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
- H10N30/074—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing
- H10N30/077—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing by liquid phase deposition
- H10N30/078—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing by liquid phase deposition by sol-gel deposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/08—Shaping or machining of piezoelectric or electrostrictive bodies
- H10N30/081—Shaping or machining of piezoelectric or electrostrictive bodies by coating or depositing using masks, e.g. lift-off
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/20—Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators
- H10N30/204—Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators using bending displacement, e.g. unimorph, bimorph or multimorph cantilever or membrane benders
- H10N30/2047—Membrane type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/031—Manufacture or treatment of data-storage electrodes
- H10D64/033—Manufacture or treatment of data-storage electrodes comprising ferroelectric layers
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Thermal Sciences (AREA)
- Organic Chemistry (AREA)
- Metallurgy (AREA)
- Mechanical Engineering (AREA)
- Materials Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dispersion Chemistry (AREA)
- Ceramic Engineering (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Inorganic Chemistry (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Memories (AREA)
- Particle Formation And Scattering Control In Inkjet Printers (AREA)
- Micromachines (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
本發明的課題為提供一種可使用遠少於以往的原料及製造能量,且以比以往還短的製程製造之功能元件的製造方法。本發明的解決手段為一種壓花構造體的製造方法,包含如下的順序之製程:製備藉由進行熱處理而成為金屬氧化物或金屬的液體材料之第一製程;藉由在基材上塗佈液體材料形成由金屬氧化物或金屬的前驅物組成物構成的前驅物組成物層之第二製程;藉由對前驅物組成物層使用凹凸模施以壓花加工,形成在前驅物組成物層包含殘膜的壓花構造之第三製程;藉由對形成有壓花構造的前驅物組成物層施以利用大氣壓電漿或低壓電漿的灰化處理而處理殘膜之第四製程;藉由對前驅物組成物層進行熱處理,由前驅物組成物形成由金屬氧化物或金屬構成的壓花構造體之第五製程。An object of the present invention is to provide a method for producing a functional element which can be manufactured by a process which is much smaller than the conventional materials and manufacturing energy, and which is shorter than the prior art. The solution of the present invention is a method for manufacturing an embossed structure, comprising the following process: preparing a first process for forming a liquid material of metal oxide or metal by heat treatment; by coating on a substrate The liquid material forms a second process of the precursor composition layer composed of the metal oxide or metal precursor composition; the precursor composition layer is formed by embossing the precursor composition layer using a concave-convex mold a third process of embossing the structure comprising a residual film; a fourth process for treating the residual film by applying a ashing treatment of atmospheric piezoelectric slurry or low-pressure plasma to the precursor composition layer formed with the embossed structure; The fifth process of forming an embossed structure composed of a metal oxide or a metal from the precursor composition by heat-treating the precursor composition layer.
Description
本發明是關於壓花構造體的製造方法、薄膜電晶體、薄膜電容器、致動器、壓電式噴墨頭及光學元件。
The present invention relates to a method of manufacturing an embossed structure, a thin film transistor, a film capacitor, an actuator, a piezoelectric inkjet head, and an optical element.
圖27是為了說明習知的薄膜電晶體900而顯示之圖。
習知的薄膜電晶體900如圖27所示包含:源電極(source electrode)950及汲電極(drain electrode)960;位於源電極950與汲電極960之間的通道層(channel layer)940;控制通道層940的導通狀態之閘電極(gate electrode)920;形成於閘電極920與通道層940之間,由鐵電材料(ferroelectric material)構成之閘絕緣層(gate insulating layer)930。此外,在圖27中符號910是表示絕緣性基板。
在習知的薄膜電晶體900中,構成閘絕緣層930的材料使用鐵電材料(例如BLT((Bi4-xLaxTi3O12)、PZT(Pb(Zrx, Ti1-x)O3)),構成通道層940的材料使用氧化物導體材料(例如銦錫氧化物(ITO:Indium Tin Oxide))。
依照習知的薄膜電晶體900,因構成通道層的材料使用氧化物導體材料,故可提高載子濃度(carrier concentration),而且構成閘絕緣層的材料使用鐵電材料,故能以低的驅動電壓(drive voltage)高速地進行切換(switching),其結果,能以低的驅動電壓高速地控制大的電流。
習知的薄膜電晶體可藉由圖28所示的習知的薄膜電晶體的製造方法製造。圖28是用以說明習知的薄膜電晶體的製造方法而顯示之圖。圖28(a)~圖28(e)為各製程圖,圖28(f)是薄膜電晶體900之俯視圖。
首先,如圖28(a)所示,於由在表面形成有SiO2層的Si基板構成的絕緣性基板910上藉由電子束蒸鍍法(electronbeam evaporation method)形成由Ti(10nm)及Pt(40nm)的積層膜構成的閘電極920。
其次,如圖28(b)所示,由閘電極920的上方藉由溶膠凝膠法(sol-gel method)形成由BLT(Bi3.25La0.75Ti3O12)或PZT(Pb(Zr0.4Ti0.6)O3)構成的閘絕緣層930(200nm)。
其次,如圖28(c)所示,在閘絕緣層930上藉由RF濺鍍法(Radio Frequency sputtering method:射頻濺鍍法)形成由ITO構成的通道層940(5nm~15nm)。
其次,如圖28(d)所示,在通道層940上藉由電子束蒸鍍法真空蒸鍍Ti(30nm)及Pt(30nm)形成源電極950及汲電極960。
其次,藉由RIE法(Reactive Ion Etching method:反應性離子蝕刻法)及濕式蝕刻法(wet etching method)(HF:HCl混合液),由其他的元件區域將元件區域分離。
據此,可製造如圖28(e)及圖28(f)所示的薄膜電晶體900。
圖29是用以說明習知的薄膜電晶體900的電氣特性而顯示之圖。此外,圖29中符號940a是表示通道,符號940b是表示空乏層。
在習知的薄膜電晶體900中,如圖29所示閘電壓(gate voltage)為3V(VG=3V)時的導通狀態電流(ON-state current)得到約10-4A,開關比(on/off ratio)得到1×104,場效遷移率(field-effect mobility)μFE得到10cm2/Vs,記憶體視窗(memory window)得到約2V的值。
[專利文獻1] 日本國特開2006-121029號公報FIG. 27 is a view for explaining a conventional thin film transistor 900.
A conventional thin film transistor 900 includes a source electrode 950 and a drain electrode 960 as shown in FIG. 27; a channel layer 940 between the source electrode 950 and the germanium electrode 960; A gate electrode 920 of an on state of the channel layer 940; a gate insulating layer 930 formed of a ferroelectric material formed between the gate electrode 920 and the channel layer 940. Further, reference numeral 910 in Fig. 27 denotes an insulating substrate.
In the conventional thin film transistor 900, a material constituting the gate insulating layer 930 is made of a ferroelectric material (for example, BLT ((Bi 4-x La x Ti 3 O 12 ), PZT (Pb(Zr x , Ti 1-x )) O 3 )), the material constituting the channel layer 940 is an oxide conductor material (for example, Indium Tin Oxide (ITO).
According to the conventional thin film transistor 900, since the oxide conductor material is used as the material constituting the channel layer, the carrier concentration can be increased, and the material constituting the gate insulating layer is made of a ferroelectric material, so that it can be driven at a low level. The drive voltage is switched at a high speed, and as a result, a large current can be controlled at a high speed with a low drive voltage.
A conventional thin film transistor can be manufactured by a conventional method for manufacturing a thin film transistor shown in FIG. Fig. 28 is a view for explaining a method of manufacturing a conventional thin film transistor. 28(a) to 28(e) are plan views, and Fig. 28(f) is a plan view of the film transistor 900.
First, as shown in FIG. 28(a), Ti (10 nm) and Pt are formed by an electron beam evaporation method on an insulating substrate 910 composed of a Si substrate having an SiO 2 layer formed on the surface thereof. A gate electrode 920 composed of a laminated film of (40 nm).
Next, as shown in Fig. 28(b), BLT (Bi 3.25 La 0.75 Ti 3 O 12 ) or PZT (Pb (Zr 0.4 Ti) is formed by the sol-gel method from above the gate electrode 920. A gate insulating layer 930 (200 nm) composed of 0.6 )O 3 ).
Next, as shown in FIG. 28(c), a channel layer 940 (5 nm to 15 nm) made of ITO is formed on the gate insulating layer 930 by a radio frequency sputtering method (Radio Frequency sputtering method).
Next, as shown in FIG. 28(d), a source electrode 950 and a germanium electrode 960 are formed by vacuum-depositing Ti (30 nm) and Pt (30 nm) on the channel layer 940 by electron beam evaporation.
Next, the element region is separated from the other element regions by the RIE method (Reactive Ion Etching method) and the wet etching method (HF: HCl mixed solution).
According to this, the thin film transistor 900 shown in Figs. 28(e) and 28(f) can be manufactured.
Fig. 29 is a view for explaining the electrical characteristics of a conventional thin film transistor 900. Further, reference numeral 940a in Fig. 29 denotes a channel, and symbol 940b denotes a depletion layer.
In the conventional thin film transistor 900, when the gate voltage is 3V (V G = 3V) as shown in FIG. 29, the ON-state current is about 10 -4 A, and the switching ratio ( On/off ratio) obtained 1×10 4 , field-effect mobility μ FE obtained 10 cm 2 /Vs, and memory window (m e m o r y window ) obtained about 2V Value.
[Patent Document 1] Japanese Patent Laid-Open Publication No. 2006-121029
但是,習知的薄膜電晶體900由於是藉由如上述的方法製造,故有如下的問題:在形成閘電極920、通道層940、源電極950及汲電極960的過程中,需使用高真空製程及/或微影製程(photolithography process),原料或製造能量的使用效率低,且製造需要長時間。
此外,這種問題不僅是見於製造上述的薄膜電晶體的方法之問題,也是見於製造薄膜電容器、致動器、壓電式噴墨頭、光學元件等的功能元件(functional device)的方法全般之問題。
因此,本發明是為了解決上述的問題所進行的創作,其目的為提供一種可使用遠少於以往的原料及製造能量,且以比以往還短的製程製造如上述優良的以薄膜電晶體為首的各種功能元件之壓花構造體的製造方法。
[1]、本發明的壓花構造體的製造方法,其特徵包含如下的順序之製程:製備含有含金屬化合物,藉由進行熱處理而成為金屬氧化物或金屬的液體材料之第一製程;藉由在基材(substrate)上塗佈前述液體材料形成由前述金屬氧化物或前述金屬的前驅物組成物(precursor composition)構成的前驅物組成物層之第二製程;藉由對前述前驅物組成物層使用凹凸模施以壓花加工(embossing),形成在前述前驅物組成物層包含殘膜的壓花構造之第三製程;藉由對形成有前述壓花構造的前述前驅物組成物層施以利用大氣壓電漿(atmospheric pressure plasma)或低壓電漿(low pressure plasma)的灰化處理(ashing treatment)而處理前述殘膜之第四製程;藉由對前述前驅物組成物層進行熱處理,由形成有前述壓花構造的前述前驅物組成物層形成由前述金屬氧化物或前述金屬構成的壓花構造體之第五製程。
依照本發明的壓花構造體的製造方法,因可藉由在基材上塗佈液體材料形成前驅物組成物層,對該前驅物組成物層施以壓花加工形成壓花構造,進而藉由以高溫對前驅物組成物層進行熱處理,形成壓花構造體,且因可藉由使用具有次微米級(submicron order)的微細的圖案(pattern)的模施以壓花加工,形成具有次微米級的微細的圖案的壓花構造體,故可使用遠少於以往的原料及製造能量,且以比以往還短的製程製造如上述優良的以薄膜電晶體為首的各種功能元件。
而且,依照本發明的壓花構造體的製造方法,因更包含藉由對前驅物組成物層施以灰化處理而處理殘膜之第四製程,故可形成無殘膜的影響之壓花構造體。此處[無殘膜的影響之壓花構造體]是指具有透過存在殘膜的部位分裂的構造之壓花構造體。包含在存在殘膜的部位完全不殘留殘膜的情形,與在存在殘膜的部位殘留海島狀的殘膜的情形的兩方。
而且,依照本發明的壓花構造體的製造方法,因擬對前驅物組成物層施以利用大氣壓電漿或低壓電漿的灰化處理,在實施第四製程時無須高真空的環境,故可不需要昂貴的高真空的設備,而且可縮短實施第四製程所需的時間。
此外,無須高真空的環境而能形成壓花構造體的技術有各種印刷技術(活版印刷(letterpress)、凹版印刷(gravure printing)、平版印刷(offset printing)、網版印刷(screen printing method)、利用噴墨(ink-jet)進行的印刷等)。但是,依照該等印刷技術,因最多只能形成具有數十微米級(micron order)的圖案的壓花構造體,故無法形成具有次微米級的微細的圖案的壓花構造體。相對於此,依照本發明的壓花構造體的製造方法,無須高真空的環境而能形成具有次微米級的微細的圖案的壓花構造體。
在本發明的壓花構造體的製造方法中,液體材料可適合使用[含有金屬烷氧化物(metal alkoxide)的溶膠-凝膠溶液(sol-gel solution)]、[含有有機金屬化合物的MOD(Metal Organic Decomposition:金屬有機分解)溶液]、[含有金屬鹽(metal salt)(例如金屬氯化物(metal chloride)、金屬氧氯化物(metaloxychloride)、金屬硝酸鹽(metal nitrate)、金屬醋酸鹽(metalacetate)等)的金屬鹽溶液]、[混合上述溶膠-凝膠溶液、上述MOD溶液及上述金屬鹽溶液的至少兩種的溶液]等的液體材料。
在本發明的壓花構造體的製造方法中,殘膜是指在第三製程中對前驅物組成物層使用凹凸模施以壓花加工時,殘留於在凹凸模中最突出的凸面與基材表面之間的前驅物組成物層。而且,在本發明的壓花構造體的製造方法中,殘膜除了[在各個殘膜形成區域內連續的膜]之外,還包含有[在各個殘膜形成區域內不連續的膜](例如採取海島構造的膜)。
此外,[壓花]有時也被稱為[奈米壓印(nanoimprint)]。
[2]、在本發明的壓花構造體的製造方法中,在前述第四製程中,完全除去前述殘膜較佳。
藉由以這種方法,可形成無殘膜的影響之壓花構造體。亦即在第五製程中,前驅物組成物層被分裂成複數個區域的結果,因前驅物組成物層可不勉強地收縮於面內方向(in-plane direction),故能以高的精度形成所需的壓花構造。
完全除去殘膜的方法可適合使用[施以灰化僅由藉由灰化處理進行之前驅物組成物層的蝕刻速率(etching rate)與殘膜的厚度的關係算出的第一時間之方法(藉由時間管理進行的灰化方法)]、[施以灰化超過上述第一時間的時間之方法(藉由過度蝕刻(over etching)進行的灰化方法,此情形有時基材會被蝕刻)]、[製備由成為蝕刻中止層(etching stopper)的材料構成的基材或至少在表面具備由成為蝕刻中止層的材料構成的層的基材當作基材,並且施以灰化超過上述第一時間的時間之方法(藉由並用蝕刻中止層進行的灰化方法)]等。
[3]、在本發明的壓花構造體的製造方法中,在前述第四製程中,使前述殘膜變薄直到成為藉由實施接著該第四製程的前述第五製程而使前述殘膜採取海島構造的薄度較佳。
藉由以這種方法,可形成無殘膜的影響之壓花構造體。亦即在第五製程中,前驅物組成物層被分裂成複數個區域的結果,因前驅物組成物層可不勉強地收縮於面內方向,故能以高的精度形成所需的壓花構造。
[4]、在本發明的壓花構造體的製造方法中,在前述第四製程中,對形成有前述壓花構造的前述前驅物組成物層施以利用大氣壓電漿的灰化處理較佳。
藉由以這種方法,因可不使用真空製程而製造壓花構造體,故可使用遠少於以往的製造能量,且以比以往還短的製程製造無殘膜的影響之壓花構造體。
[5]、在本發明的壓花構造體的製造方法中,在前述第四製程中,對形成有前述壓花構造的前述前驅物組成物層施以利用低壓電漿的灰化處理較佳。
藉由以這種方法,因可不使用高真空製程而製造壓花構造體,故可使用遠少於以往的製造能量,且以比以往還短的製程製造無殘膜的影響之壓花構造體。
[6]、在本發明的壓花構造體的製造方法中,在0.1Pa以上的壓力之下實施前述第四製程較佳。
擬在0.1Pa以上的壓力之下實施第四製程乃因當在未滿0.1Pa的壓力之下實施第四製程時,為了形成壓力環境很費時且生產性降低,或者需要大規模的減壓裝置,有使製造成本增大等的情形。若由這種觀點來說的話,在本發明的壓花構造體的製造方法中,在1Pa以上的壓力之下實施第四製程較佳,在10Pa以上的壓力之下實施第四製程更佳。
另一方面,在本發明的壓花構造體的製造方法中,在1000Pa~100000Pa左右的壓力之下實施第四製程較佳。乃因若是這種壓力範圍,則能以短時間形成壓力環境。而且乃因若是這種壓力範圍,則可一邊運送處於大氣壓環境的工作件(work),一邊連續投入到壓力環境。而且,在本發明的壓花構造體的製造方法中,在1000Pa以下的壓力之下實施第四製程也較佳。乃因當在1000Pa以下的壓力之下實施第四製程時,如後述,可在施加了偏壓(bias voltage)的狀態下穩定地實施第四製程。若由這種觀點來說的話,在本發明的壓花構造體的製造方法中,在100Pa以下的壓力之下實施第四製程更佳。
[7]、在本發明的壓花構造體的製造方法中,在施加了偏壓的狀態下實施第四製程較佳。
在減壓條件下,即使是施加了偏壓的狀態,也能引起穩定的輝光放電(glow discharge)。因此,如上述藉由在施加了偏壓的狀態下實施第四製程,能以高的蝕刻速率實施灰化製程,進而能以高的生產性製造壓花構造體。
而且,因在減壓條件下使用於灰化的氣體(灰化氣體)的平均自由路徑(mean free path)比在大氣壓條件下長,且灰化氣體的飛翔方向在一方向一致,故如上述藉由在施加了偏壓的狀態下實施第四製程,可降低對壓花構造的側面部分的蝕刻(側向蝕刻(side etching))的比例,進而可製造具有高的形狀精度的壓花構造體。
[8]、在本發明的壓花構造體的製造方法中,使用反應性氣體(reactive gas)實施前述第四製程較佳。
藉由以這種方法,能以高的蝕刻速率實施灰化製程,進而能以高的生產性製造壓花構造體。此情形,反應性氣體使用能與構成前驅物組成物層的成分引起化學反應並可將前驅物組成物層蝕刻的反應性氣體較佳。
[9]、在本發明的壓花構造體的製造方法中,使用含鹵素元素氣體當作前述反應性氣體實施前述第四製程較佳。
如此,可藉由對各式各樣的種類的金屬使用反應性高的含鹵素元素氣體實施第四製程,由各式各樣的種類的前驅物組成物層製造無殘膜的影響之壓花構造體。
[10]、在本發明的壓花構造體的製造方法中,使用含鹵素元素氣體及含Ar氣體的混合氣體當作前述反應性氣體實施前述第四製程較佳。
如此,可藉由對各式各樣的種類的金屬使用反應性高的含鹵素元素氣體及研磨性(milling characteristics)高的Ar氣體實施第四製程,由各式各樣的種類的前驅物組成物層以高的生產性形成無殘膜的影響之壓花構造體。
此外,在本發明的壓花構造體的製造方法(記載於上述[9]或[10]的任一項之壓花構造體的製造方法)中,含鹵素元素氣體可適合使用含氟氣體、含氯氣體、含溴氣體等。具體上在前驅物組成物層由含有Si的物質構成的情形下,可適合使用例如CF4、CF4/O2、CF4/H2、CHF3、C2F6、C3F8、SF6、SF6/O2、NF3、SiF4/O2、Cl2、BCl3、CCl4、CF3Br、HBr、HBr/NF3、HBr/O2、BCl3/CCl4、BCl3/CF4等,在前驅物組成物層由含有Al的物質構成的情形下,可適合使用例如Cl2、BCl3、CCl4、SiCl4、BCl3/Cl2/Ar等,在前驅物組成物層由含有W、Mo、Ta及Ti之中至少一種的物質構成的情形下,可適合使用例如CF4、CF4/O2、NF3、CCl4/O2等,在前驅物組成物層由含有Cr的物質構成的情形下,可適合使用例如Cl2、Cl2/O2、CCl4/O2等,在前驅物組成物層由含有Au及Pt之中至少一種的物質構成的情形下,可適合使用例如Cl2、Cl2/Ar等。
在本發明的壓花構造體的製造方法中,載體氣體(carrier gas)使用He氣體或N2氣體較佳。
[11]、在本發明的壓花構造體的製造方法中,在前述第二製程與前述第三製程之間更包含藉由將前述前驅物組成物層加熱到位於80℃~200℃的範圍內的溫度,預先降低前述前驅物組成物層的流動性之預備加熱製程,在前述第三製程中,藉由在將前述前驅物組成物層加熱到位於80℃~300℃的範圍內的溫度的狀態下,且使用加熱到位於80℃~300℃的範圍內的溫度的模對前述前驅物組成物層施以壓花加工,在前述前驅物組成物層形成壓花構造較佳。
藉由以這種方法,因擬藉由加熱到位於80℃~200℃的範圍內的溫度某種程度地進行前驅物組成物層的固化反應(solidification reaction)而預先降低前驅物組成物層的流動性,並且對透過藉由加熱到位於80℃~300℃的範圍內的溫度降低前驅物組成物層的硬度而得到高的塑性變形能力(plastic deformation capacity)的前驅物組成物層施以壓花加工,故能以高的精度形成所需的壓花構造,其結果,可製造具有所需的性能的壓花構造體。
但是,與使用高分子材料進行壓花加工的通常的壓花加工技術的情形不同,有在使用藉由進行熱處理而成為金屬氧化物或金屬的液體材料進行壓花加工的壓花加工技術的情形下在室溫進行壓花加工的報告例。但是,因據此產生為了賦予規定的塑性變形能力而含有有機成分或溶媒等的必要,故起因於此點而使燒成時的形狀劣化變的激烈。
但是,透過本發明的發明者們的研究,若將前驅物組成物層加熱到位於80℃~300℃的範圍內的溫度,則前驅物組成物層的塑性變形能力變高很明顯。而且,可除去主溶媒很明顯。因此,在本發明的壓花構造體的製造方法中,擬對藉由加熱到位於80℃~300℃的範圍內的溫度得到高的塑性變形能力,並且燒成時的形狀劣化少的前驅物組成物層施以壓花加工。
此處設前驅物組成物層的加熱溫度為[80℃~300℃]的範圍內乃因當上述的加熱溫度未滿80℃時,因前驅物組成物層未充分軟化,故無法充分提高前驅物組成物層的塑性變形能力,當上述的加熱溫度超過300℃時,前驅物組成物層的固化反應過度進行且前驅物組成物層的塑性變形能力再度降低。
若由上述觀點來說的話,在將前驅物組成物層加熱到位於100℃~200℃的範圍內的溫度的狀態下對前驅物組成物層施以壓花加工更佳。
而且如上述,因擬使用加熱到位於80℃~300℃的範圍內的溫度的模對前驅物組成物層施以壓花加工,故正在施以壓花加工的時候,前驅物組成物層的塑性變形能力不會降低,故能以更高的精度形成所需的壓花構造。
此處設上述的模的加熱溫度為[80℃~300℃]的範圍內乃因當上述的加熱溫度未滿80℃時,有起因於前驅物組成物層的溫度降低,使得前驅物組成物層的塑性變形能力降低的情形,當上述的加熱溫度超過300℃時,起因於前驅物組成物層的脫水縮合反應(dehydration-condensation reaction)過度進行,使得前驅物組成物層的塑性變形能力降低。
若由上述觀點來說的話,在上述的第三製程中,使用加熱到位於100℃~200℃的範圍內的溫度的模施以壓花加工更佳。
在本發明的壓花構造體的製造方法中,在上述的第三製程中,以位於1MPa~20MPa的範圍內的壓力施以壓花加工較佳。
依照本發明的壓花構造體的製造方法,如上述因擬對得到高的塑性變形能力的前驅物組成物層施以壓花加工,即使將施以壓花加工時施加的壓力降低到1MPa~20MPa,前驅物組成物層也會仿照模的表面形狀而變形,能以高的精度形成所需的壓花構造。而且,藉由將施以壓花加工時施加的壓力降低到1MPa~20MPa,使得在施以壓花加工時模很難受到損傷。
此處,設上述壓力為[1MPa~20MPa]的範圍內乃因當上述的壓力未滿1MPa時,有壓力過低而無法對前驅物組成物進行壓花的情形,上述的壓力若有20MPa,則可充分地對前驅物組成物進行壓花,故無須施加20Mpa以上的壓力。
若由上述觀點來說的話,在第三製程中以位於2MPa~10MPa的範圍內的壓力施以壓花加工更佳。
[12]、在本發明的壓花構造體的製造方法中,在前述第五製程中,藉由以含氧環境進行熱處理,形成由金屬氧化物構成的壓花構造體較佳。
藉由以這種方法,如後述可製造以壓花構造體當作[薄膜電晶體中的閘電極層、閘絕緣層、源極層、汲極層、通道層或配線層]、[薄膜電容器中的第一電極層、介電質層(dielectric layer)、第二電極層或配線層]、[致動器中的壓電層(piezoelectric layer)、電極層或配線層]、[壓電式噴墨頭中的壓電層或空腔構件(cavity member)]、[光學元件中的晶格層(lattice layer)(金屬陶瓷製晶格層)]而具備的各種功能元件。
此情形,可製造的金屬氧化物可舉例說明:各種順電材料(paraelectric material)(例如BZN(Bi1.5Zn1.0Nb1.5O7)或BST(BaxSr1-x)Ti3O12)、SiO2、SrTiO3、LaAlO3、HfO2)、各種鐵電材料(例如PZT(Pb(Zrx, Ti1-x)O3)、BLT(Bi4-xLaxTi3O12)、Nb摻雜PZT(Nb doped PZT)、La摻雜PZT、鈦酸鋇(barium titanate)(BaTiO3)、鈦酸鉛(lead titanate)(PbTiO3)、BTO(Bi4Ti3O12)、SBT(SrBi2Ta2O9)、BZN(Bi1.5Zn1.0Nb1.5O7)、鐵酸鉍(bismuth ferrite)(BiFeO3))、各種半導體材料或各種導體材料(例如銦錫氧化物(ITO)、氧化銦(indium oxide)(In2O3)、銻摻雜氧化錫(antimony doped tin oxide)(Sb-SnO2)、氧化鋅(zinc oxide)(ZnO)、鋁摻雜氧化鋅(aluminium doped zinc oxide)(Al-ZnO)、鎵摻雜氧化鋅(gallium doped zinc oxide)(Ga-ZnO)、氧化釕(ruthenium oxide)(RuO2)、氧化銥(iridium oxide)(IrO2)、氧化錫(tin oxide)(SnO2)、一氧化錫(tin monoxide)(SnO)、鈮摻雜二氧化鈦(niobium doped titanium dioxide)(Nb-TiO2)等的氧化物導體材料、銦鎵鋅複合氧化物(indium gallium zinc complex oxide)(IGZO)、鎵摻雜氧化銦(gallium doped indium oxide)(In-Ga-O(IGO))、銦摻雜氧化鋅(indium doped zinc oxide)(In-Zn-O(IZO))等的非晶質導電氧化物(amorphous conducting oxide)、鈦酸鍶(strontium titanate)(SrTiO3)、鈮摻雜鈦酸鍶(niobium doped strontium titanate)(Nb-SrTiO3)、鍶鋇複合氧化物(strontium barium complex oxide)(SrBaO3)、鍶鈣複合氧化物(strontium calcium complex oxide)(SrCaO3)、釕酸鍶(strontium ruthenate)(SrRuO3)、鎳酸鑭(lanthanum nickelate)(LaNiO3)、鈦酸鑭(lanthanum titanate)(LaTiO3)、銅酸鑭(lanthanum copper oxide)(LaCuO3)、鎳酸釹(neodymium nickelate)(NdNiO3)、鎳酸釔(yttrium nickelate)(YNiO3)、鑭鈣錳複合氧化物(Lanthanum Calcium Manganese complex oxide)(LCMO)、鉛酸鋇(barium plumbate)(BaPbO3)、LSCO(LaxSr1-xCuO3)、LSMO(La1-xSrxMnO3)、YBCO(YBa2Cu3O7-x)、LNTO(La(NI1-xTix)O3)、LSTO((La1-x, Srx)TiO3)、STRO(Sr(Ti1-xRux)O3)和其他的鈣鈦礦型導電氧化物(perovskite type conducting oxide)或焦綠石型導電氧化物(pyrochlore type conducting oxide)、其他的材料(例如High-k材料(HfO2、Ta2O5、ZrO2、HfSixOy、ZrSixOy、LaAlO3、La2O3、(Ba1-x, Srx)TiO3、Al2O3、(Bi2-x, Znx)(Zny, Nb2-y)、Y2O3、GeO2、Gd2O3等)、豪斯勒系合金(Heusler alloy)(Co、Co-Pt、Co-Fe、Mn-Pt、Ni-Fe、CoFeB等的合金、Co-Cr-Fe-Al、Co2MnAl等)、MRAM(Magnetoresistance Random Access Memory:磁阻式隨機存取記憶體)用阻隔材料(barrier material)((La1-x, Srx)MnO3等的氧化物系半金屬(half metal)等的MRAM用電極材料、AlAs、MgO、Al2O3等)、多鐵性材料(multiferroic material)(鈣鈦礦型BiMnO3、BiFeO3、YbMnO3等、石榴石型(garnet type)R3FeO12(R=Dy、Ho、Er、Tm、Tb、Lu)、Y3Al5O12、Gd3Ga5O12、SGGG(Gd2.7Ca0.3)(Ga4.0Mg0.32Zr0.65Ca0.03)O12等)、PRAM(Parameter Random Access Memory:參數隨機存取記憶體)材料(GexTe1-x、Ge2Sb2Te5等的硫屬化物系(chalcogenide system)、Sb-X合金(X=Ge、Ga、In、Se、Te)等、光觸媒(photocatalyst)用金紅石型(rutile type)二氧化鈦(TiO2))。
[13]、在本發明的壓花構造體的製造方法中,在前述第五製程中,藉由以還原環境進行熱處理,形成由金屬構成的壓花構造體較佳。
藉由以這種方法,如後述因能以功能固體材料層當作[薄膜電晶體中的閘電極層或配線層]、[薄膜電容器中的第一電極層、第二電極層或配線層]、[致動器中的電極層]、 [光學元件中的晶格層(金屬製晶格層)]等,故可製造各種功能元件。
此情形,可製造的金屬可舉例說明例如Au、Pt、Ag、Cu、Ti、Ge、In、Sn等。
[14]、本發明的薄膜電晶體,包含閘電極層、閘絕緣層、源極層、汲極層、通道層及配線層,其特徵為:前述閘電極層、前述閘絕緣層、前述源極層、前述汲極層、前述通道層及前述配線層之中至少一層是藉由本發明的壓花構造體的製造方法形成。
藉由以這種方法,針對薄膜電晶體的至少一層,無殘膜的影響之壓花構造體可使用極少的原料及製造能量,且以比以往還短的製程製造。
[15]、本發明的薄膜電晶體,其特徵包含:包含源極區域(source region)及汲極區域(drain region)以及通道區域(channel region)之氧化物導體層;控制前述通道區域的導通狀態之閘電極;形成於前述閘電極與前述通道區域之間,由鐵電材料或順電材料構成之閘絕緣層,前述通道區域的層厚比前述源極區域的層厚及前述汲極區域的層厚薄,前述通道區域的層厚比前述源極區域的層厚及前述汲極區域的層厚薄的前述氧化物導體層是藉由本發明的壓花構造體的製造方法形成。
依照本發明的薄膜電晶體,因構成通道區域的材料使用氧化物導電性材料,故可提高載子濃度,而且因構成閘絕緣層的材料使用鐵電材料或順電材料,故能以低的驅動電壓高速地進行切換,其結果,與習知的薄膜電晶體的情形一樣,能以低的驅動電壓高速地控制大的電流。
而且,依照本發明的薄膜電晶體,因通道區域的層厚比源極區域的層厚及汲極區域的層厚薄,且僅使用本發明的壓花構造體的製造方法形成無殘膜的影響的氧化物導體層就能製造薄膜電晶體,故如習知的薄膜電晶體的情形,也可以不由不同的材料形成通道區域與源極區域及汲極區域,可使用遠少於以往的原料及製造能量,且以比以往還短的製程製造如上述優良的薄膜電晶體。
[16]、在本發明的薄膜電晶體中,前述通道區域的載子濃度及層厚被設定為如在前述薄膜電晶體為關閉狀態(OFF state)時,前述通道區域全體空乏化(deplete)的值較佳。
藉由以這種構成,因即使提高了氧化物導體層的載子濃度,也能充分降低在薄膜電晶體為關閉狀態時流過的電流量,故可一邊維持必要的開關比,一邊以低的驅動電壓控制大的電流。
在此情形下,當薄膜電晶體為增強型(enhancement type)的電晶體時,因在將0V的控制電壓(control voltage)施加於閘電極時薄膜電晶體成為關閉狀態,故被設定為如在這種時候通道區域全體空乏化的值的話也可以,當薄膜電晶體為空乏型(depletion type)的電晶體時,因在將負的控制電壓施加於閘電極時薄膜電晶體成為關閉狀態,故被設定為如在這種時候通道區域全體空乏化的值的話也可以。
[17]、本發明的薄膜電容器,包含第一電極層、介電質層、第二電極層及配線層,其特徵為:前述第一電極層、前述介電質層、前述第二電極層及前述配線層之中至少一層是藉由本發明的壓花構造體的製造方法形成。
藉由以這種方法,針對薄膜電容器的至少一層,無殘膜的影響之壓花構造體可使用極少的原料及製造能量,且以比以往還短的製程製造。
[18]、本發明的致動器,包含壓電層、電極層及配線層,其特徵為:前述壓電層、前述電極層及前述配線層之中至少一層是藉由本發明的壓花構造體的製造方法形成。
藉由以這種方法,至少針對壓電層,無殘膜的影響之壓花構造體可使用極少的原料及製造能量,且以比以往還短的製程製造。
此情形,液體材料可適合使用藉由進行熱處理而成為鐵電材料的液體材料。
[19]、本發明的壓電式噴墨頭,其特徵包含:空腔構件;安裝於前述空腔構件的一方側,形成有壓電層之振動板;安裝於前述空腔構件的他方側,形成有噴嘴孔(nozzle hole)之噴嘴板(nozzle plate);藉由前述空腔構件、前述振動板及前述噴嘴板劃定之墨水室(ink chamber),前述壓電層及/或前述空腔構件是藉由本發明的壓花構造體的製造方法形成。
依照本發明的壓電式噴墨頭,因壓電層及/或空腔構件是使用本發明的壓花構造體的製造方法而形成,故能以無殘膜的影響之壓花構造體,使用遠少於以往的原料及製造能量,且以比以往還短的製程製造壓電式噴墨頭。
[20]、本發明的光學元件,在基材上包含晶格層,其特徵為:前述晶格層是藉由本發明的壓花構造體的製造方法形成。
藉由以這種方法,針對晶格層,無殘膜的影響之壓花構造體可使用極少的原料及製造能量,且以比以往還短的製程製造。
此外,當晶格層由絕緣體構成時,液體材料可使用藉由進行熱處理而成為絕緣體材料的液體材料。而且,當晶格層由金屬構成時,可使用藉由進行熱處理而成為金屬材料的液體材料。However, since the conventional thin film transistor 900 is manufactured by the above method, there is a problem that a high vacuum is required in the process of forming the gate electrode 920, the channel layer 940, the source electrode 950, and the drain electrode 960. Process and/or photolithography processes, the use of raw materials or manufacturing energy is inefficient, and manufacturing takes a long time.
Further, such a problem is not only a problem found in the method of manufacturing the above-described thin film transistor, but also a method of manufacturing a functional device such as a film capacitor, an actuator, a piezoelectric ink jet head, an optical element, or the like. problem.
Accordingly, the present invention has been made to solve the above problems, and an object thereof is to provide a thin film transistor which is excellent in the process of manufacturing a raw material and a manufacturing energy which are much smaller than the conventional ones, and which is shorter than the prior art. A method of manufacturing an embossed structure of various functional elements.
[1] The method for producing an embossed structure according to the present invention, characterized by the process of preparing a first process for preparing a liquid material containing a metal-containing compound and forming a metal oxide or a metal by heat treatment; a second process for forming a precursor composition layer composed of the foregoing metal oxide or a precursor composition of the foregoing metal by coating the liquid material on a substrate; by forming the precursor The object layer is embossed using a embossing mold to form a third process of embossing the precursor composition layer including the residual film; by forming the precursor composition layer having the embossed structure described above Applying a fourth process of treating the residual film by an ashing treatment using atmospheric pressure plasma or low pressure plasma; heat treatment of the precursor composition layer A fifth process of forming the embossed structure composed of the metal oxide or the metal from the precursor composition layer in which the embossed structure is formed.
According to the method of manufacturing an embossed structure according to the present invention, the precursor composition layer can be formed by applying a liquid material on the substrate, and the precursor composition layer is embossed to form an embossed structure, thereby borrowing The embossed structure is formed by heat-treating the precursor composition layer at a high temperature, and is formed by embossing by using a mold having a submicron order of fine patterns. Since the micron-sized fine embossed structure is used, it is possible to use various materials and manufacturing energy which are much smaller than the conventional ones, and to manufacture various functional elements including the above-mentioned excellent thin film transistors, which are shorter than the conventional ones.
Further, according to the method for producing an embossed structure of the present invention, since the fourth process of treating the residual film by subjecting the precursor composition layer to ashing treatment is further included, the embossing without the influence of the residual film can be formed. Construct. Here, the embossed structure having no influence on the residual film means an embossed structure having a structure in which a portion where the residual film is present is split. It is included in the case where the residual film is not left at all in the portion where the residual film exists, and in the case where the island-shaped residual film remains in the portion where the residual film exists.
Moreover, according to the method for manufacturing an embossed structure according to the present invention, since the precursor composition layer is subjected to ashing treatment using atmospheric piezoelectric slurry or low-pressure plasma, an environment requiring no high vacuum is required in the fourth process. This eliminates the need for expensive high vacuum equipment and reduces the time required to implement the fourth process.
Further, techniques for forming an embossed structure without requiring a high vacuum environment include various printing techniques (letterpress, gravure printing, offset printing, screen printing method, Printing by inkjet (ink-jet), etc.). However, according to these printing techniques, since an embossed structure having a pattern of several tens of micron orders can be formed at most, an embossed structure having a fine pattern of a submicron order cannot be formed. On the other hand, according to the method for producing an embossed structure of the present invention, an embossed structure having a fine pattern of a submicron order can be formed without requiring a high vacuum environment.
In the method for producing an embossed structure of the present invention, the liquid material may be suitably used [sol-gel solution containing metal alkoxide], [MOD containing organometallic compound ( Metal Organic Decomposition), [containing metal salts (eg metal chloride, metal oxychloride (m e t a l o x y c h l o r i d e), metal nitrate, metal acetate (m e t a l a c e t a liquid material such as a metal salt solution of a t e ) or the like, [a solution in which at least two of the above sol-gel solution, the MOD solution and the metal salt solution are mixed].
In the method for producing an embossed structure according to the present invention, the residual film refers to a convex surface and a base which are most prominent in the concave-convex mold when the embossing process is applied to the precursor composition layer in the third process. A precursor composition layer between the surface of the material. Further, in the method for producing an embossed structure of the present invention, the residual film includes [a film which is discontinuous in each residual film formation region] in addition to [a film continuous in each residual film formation region] ( For example, take the membrane of the island structure).
In addition, [embossing] is sometimes referred to as [nanoimprint].
[2] In the method for producing an embossed structure according to the present invention, it is preferred that the residual film is completely removed in the fourth process.
By this method, an embossed structure free from the influence of the residual film can be formed. That is, in the fifth process, the precursor composition layer is split into a plurality of regions, and the precursor composition layer can be contracted in the in-plane direction without being reluctantly formed, so that it can be formed with high precision. The required embossed construction.
The method of completely removing the residual film can be suitably used [method of applying the first time calculated by ashing only by the relationship between the etching rate of the precursor composition layer and the thickness of the residual film by ashing treatment ( The ashing method by time management)], [the method of applying ashing time exceeding the first time (the ashing method by over etching), in which case the substrate is sometimes etched a substrate made of a material that is an etching stopper or a substrate having a layer made of a material that is an etching stopper at least on the surface is used as a substrate, and is subjected to ashing more than the above. The method of the first time (by the ashing method by using the etching stop layer together)] and the like.
[3] In the method of manufacturing an embossed structure according to the present invention, in the fourth process, the residual film is thinned until the residual film is formed by performing the fifth process subsequent to the fourth process. The thinness of the island structure is better.
By this method, an embossed structure free from the influence of the residual film can be formed. That is, in the fifth process, the precursor composition layer is split into a plurality of regions, and the precursor composition layer can be contracted in the in-plane direction without being reluctantly formed, so that the desired embossed structure can be formed with high precision. .
[4] In the method for producing an embossed structure according to the present invention, in the fourth process, it is preferred that the precursor composition layer having the embossed structure is subjected to ashing treatment using an atmospheric piezoelectric slurry. .
According to this method, since the embossed structure can be produced without using a vacuum process, it is possible to manufacture an embossed structure having no influence of the residual film by using a manufacturing process which is much smaller than the conventional production and which is shorter than the conventional one.
[5] In the method for producing an embossed structure according to the present invention, in the fourth process, the precursor composition layer having the embossed structure is subjected to ashing treatment using low-pressure plasma. good.
According to this method, since the embossed structure can be produced without using a high-vacuum process, it is possible to use an embossed structure which is much smaller than the conventional manufacturing process and which has no residual film effect. .
[6] In the method for producing an embossed structure according to the present invention, it is preferable to carry out the fourth process under a pressure of 0.1 Pa or more.
It is intended to carry out the fourth process under a pressure of 0.1 Pa or more because when the fourth process is carried out under a pressure of less than 0.1 Pa, it is time consuming and productive to form a pressure environment, or a large-scale pressure reducing device is required. There are cases where the manufacturing cost is increased. From this point of view, in the method for producing an embossed structure of the present invention, it is preferable to carry out the fourth process under a pressure of 1 Pa or more, and it is more preferable to carry out the fourth process under a pressure of 10 Pa or more.
On the other hand, in the method for producing an embossed structure of the present invention, it is preferable to carry out the fourth process under a pressure of about 1000 Pa to 100,000 Pa. However, if this pressure range is used, the pressure environment can be formed in a short time. Moreover, if it is such a pressure range, it can be continuously put into a pressure environment while transporting a work in an atmospheric pressure environment. Further, in the method for producing an embossed structure of the present invention, it is also preferable to carry out the fourth process under a pressure of 1000 Pa or less. When the fourth process is performed under a pressure of 1000 Pa or less, as will be described later, the fourth process can be stably performed in a state where a bias voltage is applied. From this point of view, in the method of manufacturing an embossed structure of the present invention, it is more preferable to carry out the fourth process under a pressure of 100 Pa or less.
[7] In the method of manufacturing an embossed structure of the present invention, it is preferable to carry out the fourth process in a state where a bias voltage is applied.
Under reduced pressure conditions, a stable glow discharge can be caused even in a state where a bias voltage is applied. Therefore, by performing the fourth process in a state where the bias voltage is applied as described above, the ashing process can be performed at a high etching rate, and the embossed structure can be manufactured with high productivity.
Moreover, since the mean free path of the gas (ashing gas) used for ashing under reduced pressure is longer than that under atmospheric pressure, and the flying direction of the ashing gas is uniform in one direction, as described above By performing the fourth process in a state where a bias voltage is applied, the ratio of etching (side etching) to the side portion of the embossed structure can be reduced, and an embossed structure having high shape accuracy can be manufactured. body.
[8] In the method of producing an embossed structure of the present invention, it is preferred to carry out the fourth process using a reactive gas.
By this method, the ashing process can be performed at a high etching rate, and the embossed structure can be produced with high productivity. In this case, the reactive gas is preferably a reactive gas which can cause a chemical reaction with a component constituting the precursor composition layer and can etch the precursor composition layer.
[9] In the method for producing an embossed structure according to the present invention, it is preferred that the fourth process is carried out by using the halogen-containing element gas as the reactive gas.
Thus, the fourth process can be carried out by using a highly reactive halogen-containing element gas for a wide variety of metals, and embossing without residual film effects can be produced from various types of precursor composition layers. Construct.
[10] In the method for producing an embossed structure according to the present invention, it is preferred that the fourth process is carried out by using the halogen-containing gas and the mixed gas containing the Ar gas as the reactive gas.
In this manner, the fourth process can be carried out by using a highly reactive halogen-containing element gas and an Ar gas having high grinding characteristics for each type of metal, and can be composed of various types of precursors. The material layer forms an embossed structure without the influence of a residual film with high productivity.
In the method of producing an embossed structure according to any one of the above [9] or [10], the halogen-containing gas can be suitably used as a fluorine-containing gas. Chlorine-containing gas, bromine-containing gas, etc. Specifically, in the case where the precursor composition layer is composed of a substance containing Si, for example, CF 4 , CF 4 /O 2 , CF 4 /H 2 , CHF 3 , C 2 F 6 , C 3 F 8 , SF 6 , SF 6 /O 2 , NF 3 , SiF 4 /O 2 , Cl 2 , BCl 3 , CCl 4 , CF 3 Br, HBr, HBr/NF 3 , HBr/O 2 , BCl 3 /CCl 4 , BCl 3 /CF 4 or the like, in the case where the precursor composition layer is composed of a substance containing Al, for example, Cl 2 , BCl 3 , CCl 4 , SiCl 4 , BCl 3 /Cl 2 /Ar, etc. may be suitably used in the precursor When the composition layer is composed of a substance containing at least one of W, Mo, Ta, and Ti, it is suitable to use, for example, CF 4 , CF 4 /O 2 , NF 3 , CCl 4 /O 2 , etc., in the precursor composition. In the case where the layer is composed of a substance containing Cr, for example, Cl 2 , Cl 2 /O 2 , CCl 4 /O 2 or the like can be suitably used, and the precursor composition layer is composed of a substance containing at least one of Au and Pt. In the case of, for example, Cl 2 , Cl 2 /Ar or the like can be suitably used.
In the method for producing an embossed structure of the present invention, it is preferred that the carrier gas is He gas or N 2 gas.
[11] In the method of manufacturing an embossed structure according to the present invention, the method further comprises heating the precursor composition layer to a range of from 80 ° C to 200 ° C between the second process and the third process. a preheating process for lowering the fluidity of the precursor composition layer in advance, in the third process, by heating the precursor composition layer to a temperature in the range of 80 ° C to 300 ° C In the state of the precursor composition layer, embossing is performed on the precursor composition layer by using a mold heated to a temperature in the range of 80 ° C to 300 ° C, and an embossed structure is preferably formed on the precursor composition layer.
By this method, the precursor composition layer is previously lowered by performing a solidification reaction of the precursor composition layer to some extent by heating to a temperature in the range of 80 ° C to 200 ° C. Fluidity, and applying a pressure to a precursor composition layer having a high plastic deformation capacity by reducing the hardness of the precursor composition layer by heating to a temperature in the range of 80 ° C to 300 ° C Since the flower is processed, the desired embossed structure can be formed with high precision, and as a result, an embossed structure having desired properties can be produced.
However, unlike the case of a normal embossing technique using embossing using a polymer material, there is a case where an embossing process using embossing of a liquid material which is a metal oxide or a metal by heat treatment is used. A report example of embossing at room temperature. However, in order to provide a predetermined plastic deformation ability, it is necessary to contain an organic component, a solvent, or the like. Therefore, the shape deterioration at the time of firing is severed.
However, as a result of research by the inventors of the present invention, if the precursor composition layer is heated to a temperature in the range of 80 ° C to 300 ° C, the plastic deformation ability of the precursor composition layer becomes high. Moreover, it is obvious that the main solvent can be removed. Therefore, in the method for producing an embossed structure of the present invention, it is intended to obtain a high plastic deformation ability by heating to a temperature in the range of 80 ° C to 300 ° C, and a precursor having less shape deterioration at the time of firing. The composition layer is subjected to embossing.
Here, the heating temperature of the precursor composition layer is in the range of [80 ° C to 300 ° C] because when the above heating temperature is less than 80 ° C, the precursor composition layer is not sufficiently softened, so that the precursor cannot be sufficiently improved. When the heating temperature exceeds 300 ° C, the curing reaction of the precursor composition layer is excessively performed and the plastic deformation ability of the precursor composition layer is again lowered.
From the above point of view, it is more preferable to apply the embossing process to the precursor composition layer while heating the precursor composition layer to a temperature in the range of 100 ° C to 200 ° C.
Further, as described above, since the precursor composition layer is subjected to embossing using a mold heated to a temperature in the range of 80 ° C to 300 ° C, the precursor composition layer is applied while the embossing process is being performed. The plastic deformation ability is not lowered, so that the desired embossed structure can be formed with higher precision.
Here, it is assumed that the heating temperature of the above-mentioned mold is in the range of [80 ° C to 300 ° C] because when the above heating temperature is less than 80 ° C, the temperature of the precursor composition layer is lowered, so that the precursor composition When the plastic deformation ability of the layer is lowered, when the above heating temperature exceeds 300 ° C, the dehydration condensation reaction due to the precursor composition layer (d e h y d r a t i o The n-c o n d e n s a t i o n reaction is excessively performed to lower the plastic deformation ability of the precursor composition layer.
From the above point of view, in the above-described third process, embossing is preferably performed using a mold which is heated to a temperature in the range of 100 ° C to 200 ° C.
In the method for producing an embossed structure according to the present invention, in the third process described above, embossing is preferably performed at a pressure in the range of 1 MPa to 20 MPa.
According to the method for producing an embossed structure according to the present invention, as described above, the embossing process is applied to the precursor composition layer which is capable of obtaining high plastic deformation ability, even if the pressure applied during the embossing process is lowered to 1 MPa. At 20 MPa, the precursor composition layer is also deformed in accordance with the surface shape of the mold, and the desired embossed structure can be formed with high precision. Further, by reducing the pressure applied during the embossing to 1 MPa to 20 MPa, the mold is hardly damaged during the embossing.
Here, in the range where the pressure is in the range of [1 MPa to 20 MPa], when the pressure is less than 1 MPa, the pressure is too low to emboss the precursor composition, and if the pressure is 20 MPa, The precursor composition can be sufficiently embossed, so that it is not necessary to apply a pressure of 20 MPa or more.
From the above point of view, it is more preferable to apply embossing at a pressure in the range of 2 MPa to 10 MPa in the third process.
[12] In the method for producing an embossed structure according to the present invention, in the fifth process, it is preferable to form an embossed structure made of a metal oxide by heat treatment in an oxygen-containing atmosphere.
By this method, an embossed structure can be manufactured as [a gate electrode layer, a gate insulating layer, a source layer, a drain layer, a channel layer or a wiring layer in a thin film transistor], [film capacitor] as described later. First electrode layer, dielectric layer, second electrode layer or wiring layer], [piezoelectric layer in the actuator, electrode layer or wiring layer], [piezoelectric Various functional elements provided in the piezoelectric layer or the cavity member in the ink jet head, and the [lattice layer (lattice layer) in the optical element].
In this case, the metal oxide that can be produced can be exemplified by various paraelectric materials (for example, BZN (Bi 1.5 Zn 1.0 Nb 1.5 O 7 ) or BST (Ba x Sr 1-x ) Ti 3 O 12 ), SiO 2 , SrTiO 3 , LaAlO 3 , HfO 2 ), various ferroelectric materials (for example, PZT(Pb(Zr x , Ti 1-x )O 3 ), BLT(Bi 4-x La x Ti 3 O 12 ), Nb Doped PZT (Nb doped PZT), La-doped PZT, barium titanate (BaTiO 3 ), lead titanate (PbTiO 3 ), BTO (Bi 4 Ti 3 O 12 ), SBT ( SrBi 2 Ta 2 O 9 ), BZN (Bi 1.5 Zn 1.0 Nb 1.5 O 7 ), bismuth ferrite (BiFeO 3 ), various semiconductor materials or various conductor materials (eg indium tin oxide (ITO), Indium oxide (In 2 O 3 ), antimony doped tin oxide (Sb-SnO 2 ), zinc oxide (ZnO), aluminum doped zinc oxide (aluminium doped zinc) Oxide (Al-ZnO), gallium doped zinc oxide (Ga-ZnO), ruthenium oxide (RuO 2 ), iridium oxide (IrO 2 ), tin oxide ( Tin oxide) (SnO 2 ), tin monoxide (SnO), antimony doped titanium dioxide (ni) Oxide doped titanium dioxide) (Nb-TiO 2 ) oxide conductor material, indium gallium zinc complex oxide (IGZO), gallium doped indium oxide (In-Ga) -O(IGO)), an amorphous conducting oxide such as indium doped zinc oxide (In-Zn-O (IZO)), or strontium titanate ( SrTiO 3 ), niobium doped strontium titanate (Nb-SrTiO 3 ), strontium barium complex oxide (SrBaO 3 ), strontium calcium complex oxide (SrCaO 3 ), strontium ruthenate (SrRuO 3 ), lanthanum nickelate (LaNiO 3 ), lanthanum titanate (LaTiO 3 ), lanthanum copper oxide ( LaCuO 3 ), neodymium nickelate (NdNiO 3 ), yttrium nickelate (YNiO 3 ), Lanthanum Calcium Manganese complex oxide (LCMO), barium lead (barium) Plumbate) (BaPbO 3 ), LSCO (La x Sr 1-x CuO 3 ), LSMO (La 1-x Sr x MnO 3 ), YBCO (YBa 2 C u 3 O 7-x ), LNTO(La(NI 1-x Ti x )O 3 ), LSTO((La 1-x , Sr x )TiO 3 ), STRO(Sr(Ti 1-x Ru x )O 3 ) and other perovskite type conducting oxides or pyrochlore type conducting oxides, other materials (such as High-k materials (HfO 2 , Ta 2 O 5 , ZrO 2 , HfSi x O y , ZrSi x O y , LaAlO 3 , La 2 O 3 , (Ba 1-x , Sr x )TiO 3 , Al 2 O 3 , (Bi 2-x , Zn x )(Zn y , Nb 2-y ), Y 2 O 3 , GeO 2 , Gd 2 O 3 , etc., Heusler alloy (Co, Co-Pt, Co-Fe, Mn-Pt, Ni-Fe) , alloys such as CoFeB, Co-Cr-Fe-Al, Co 2 MnAl, etc.), barrier materials for MRAM (Magnetoresistance Random Access Memory) ((La 1-x , An electrode material for MRAM such as an oxide-based semimetal such as Sr x ) MnO 3 , AlAs, MgO, or Al 2 O 3 , or a multiferroic material (perovskite BiMnO 3 , BiFeO 3 , YbMnO 3 , etc., garnet type R 3 FeO 12 (R=Dy, Ho, Er, Tm, Tb, Lu), Y 3 Al 5 O 12 , Gd 3 Ga 5 O 12 , SGGG (Gd 2.7 Ca 0.3 ) (Ga 4.0 Mg 0.32 Zr 0.65 Ca 0.03 )O 12 , etc.), PRAM (Parameter Random Access Memory) material (Ge x Te 1-x , Ge 2 Sb 2 Te 5th chalcogenide system (c h a l c o g e n i d e system), Sb-X alloy (X=Ge, Ga, In, Se, Te Etc. Photocatalyst uses rutile type titanium dioxide (TiO 2 ).
[13] In the method for producing an embossed structure according to the present invention, in the fifth process, it is preferable to form an embossed structure made of a metal by heat treatment in a reducing atmosphere.
By this method, as described later, the functional solid material layer can be regarded as [the gate electrode layer or wiring layer in the thin film transistor], [the first electrode layer, the second electrode layer or the wiring layer in the film capacitor] [The electrode layer in the actuator], [the lattice layer in the optical element (metal lattice layer)], etc., can manufacture various functional elements.
In this case, the metal which can be manufactured can exemplify, for example, Au, Pt, Ag, Cu, Ti, Ge, In, Sn, or the like.
[14] The thin film transistor of the present invention, comprising a gate electrode layer, a gate insulating layer, a source layer, a drain layer, a channel layer, and a wiring layer, wherein the gate electrode layer, the gate insulating layer, and the source are At least one of the electrode layer, the above-described drain layer, the channel layer, and the wiring layer is formed by the method of producing the embossed structure of the present invention.
By this method, for at least one layer of the thin film transistor, the embossed structure without the influence of the residual film can be produced by using a process which is shorter than the prior art by using a very small amount of raw materials and manufacturing energy.
[15] The thin film transistor of the present invention, comprising: an oxide conductor layer including a source region, a drain region, and a channel region; and controlling conduction of the channel region a gate electrode of the state; a gate insulating layer formed of a ferroelectric material or a paraelectric material between the gate electrode and the channel region, wherein a thickness of the channel region is greater than a thickness of the source region and the drain region The oxide conductor layer having a thickness of the channel region which is thinner than the layer thickness of the source region and the layer thickness of the drain region is formed by the method for producing an embossed structure of the present invention.
According to the thin film transistor of the present invention, since the oxide conductive material is used as the material constituting the channel region, the carrier concentration can be increased, and since the material constituting the gate insulating layer is made of a ferroelectric material or a paraelectric material, it can be low. The driving voltage is switched at a high speed, and as a result, as in the case of the conventional thin film transistor, a large current can be controlled at a high speed with a low driving voltage.
Further, according to the thin film transistor of the present invention, the layer thickness of the channel region is thinner than the layer thickness of the source region and the layer thickness of the drain region, and the effect of the residual film is formed only by the manufacturing method of the embossed structure of the present invention. The oxide conductor layer can be used to manufacture a thin film transistor. Therefore, in the case of a conventional thin film transistor, it is also possible to form a channel region, a source region, and a drain region without using different materials, and it is possible to use far less raw materials and Energy is produced, and a thin film transistor as described above is produced in a process shorter than the prior art.
[16] In the thin film transistor of the present invention, the carrier concentration and the layer thickness of the channel region are set such that when the thin film transistor is in an OFF state, the entire channel region is depleted. The value is better.
According to this configuration, even if the carrier concentration of the oxide conductor layer is increased, the amount of current flowing when the thin film transistor is turned off can be sufficiently reduced, so that the necessary switching ratio can be maintained while being low. The drive voltage controls a large current.
In this case, when the thin film transistor is an enhancement type transistor, since the thin film transistor is turned off when a control voltage of 0 V is applied to the gate electrode, it is set as in In this case, when the total value of the channel region is depleted, when the thin film transistor is a depletion type transistor, the thin film transistor is turned off when a negative control voltage is applied to the gate electrode. It is also possible to set the value of the channel area as a whole at this time.
[17] The film capacitor of the present invention, comprising: a first electrode layer, a dielectric layer, a second electrode layer, and a wiring layer, wherein the first electrode layer, the dielectric layer, and the second electrode layer At least one of the wiring layers described above is formed by the method of producing the embossed structure of the present invention.
By this method, at least one layer of the film capacitor, the embossed structure without the influence of the residual film can be produced by using a process which is shorter than the prior art by using a very small amount of raw materials and manufacturing energy.
[18] The actuator of the present invention includes a piezoelectric layer, an electrode layer, and a wiring layer, wherein at least one of the piezoelectric layer, the electrode layer, and the wiring layer is an embossed structure of the present invention. The manufacturing method of the body is formed.
By this method, at least the piezoelectric layer, the embossed structure without the influence of the residual film can be produced by a process which is shorter than the conventional one, using a very small amount of raw materials and manufacturing energy.
In this case, the liquid material may be suitably used as a liquid material which becomes a ferroelectric material by heat treatment.
[19] The piezoelectric ink jet head according to the present invention, comprising: a cavity member; a vibrating plate formed on one side of the cavity member and having a piezoelectric layer; and being mounted on the other side of the cavity member a nozzle plate having a nozzle hole; an ink chamber defined by the cavity member, the vibrating plate, and the nozzle plate, the piezoelectric layer and/or the empty The cavity member is formed by the method of manufacturing the embossed structure of the present invention.
According to the piezoelectric ink jet head of the present invention, since the piezoelectric layer and/or the cavity member are formed by the method for producing the embossed structure of the present invention, the embossed structure can be formed without the influence of the residual film. A piezoelectric ink jet head is manufactured by using a process which is much smaller than the conventional materials and manufacturing energy, and which is shorter than the prior art.
[20] The optical element of the present invention comprising a lattice layer on a substrate, wherein the lattice layer is formed by the method for producing an embossed structure of the present invention.
By this method, the embossed structure having no influence of the residual film on the lattice layer can be produced by a process which is shorter than the prior art by using a very small amount of raw materials and manufacturing energy.
Further, when the lattice layer is composed of an insulator, the liquid material may be a liquid material which becomes an insulator material by heat treatment. Further, when the lattice layer is made of a metal, a liquid material which becomes a metal material by heat treatment can be used.
圖1是用以說明與實施形態一有關的壓花構造體的製造方法而顯示之圖。
圖2是用以說明與實施形態二有關的壓花構造體的製造方法而顯示之圖。
圖3是用以說明與實施形態三有關的壓花構造體的製造方法而顯示之圖。
圖4是用以說明與實施形態四有關的壓花構造體的製造方法而顯示之圖。
圖5是用以說明與實施形態五有關的壓花構造體的製造方法而顯示之圖。
圖6是用以說明使用於實施形態六的灰化裝置40而顯示之圖。
圖7是用以說明與實施形態六有關的壓花構造體的製造方法而顯示之圖。
圖8是用以說明使用於實施形態七的灰化裝置40a而顯示之圖。
圖9是用以說明與實施形態七有關的壓花構造體的製造方法而顯示之圖。
圖10是用以說明與實施形態八有關的薄膜電晶體100而顯示之圖。
圖11是用以說明與實施形態八有關的薄膜電晶體的製造方法而顯示之圖。
圖12是用以說明與實施形態八有關的薄膜電晶體的製造方法而顯示之圖。
圖13是用以說明與實施形態八有關的薄膜電晶體的製造方法而顯示之圖。
圖14是用以說明與實施形態九有關的壓電式噴墨頭300而顯示之圖。
圖15是用以說明與實施形態九有關的壓電式噴墨頭的製造方法而顯示之圖。
圖16是用以說明與實施形態九有關的壓電式噴墨頭的製造方法而顯示之圖。
圖17是用以說明與實施形態九有關的壓電式噴墨頭的製造方法而顯示之圖。
圖18是用以說明實施例一中的灰化處理而顯示之圖。
圖19是顯示實施例一中的灰化處理的結果之圖。
圖20是顯示實施例一中的灰化處理的結果之圖。
圖21是顯示實施例一中的灰化處理的結果之圖。
圖22是顯示實施例二中的灰化處理的結果之圖。
圖23是用以說明實施例三中的評價方法而顯示之圖。
圖24是顯示實施例三中的灰化處理的結果之圖。
圖25是顯示實施例三中的灰化處理的結果之圖。
圖26是用以說明與變形例有關的壓花構造體的製造方法而顯示之圖。
圖27是用以說明習知的薄膜電晶體900而顯示之圖。
圖28是用以說明習知的薄膜電晶體的製造方法而顯示之圖。
圖29是用以說明習知的薄膜電晶體900的電特性而顯示之圖。Fig. 1 is a view for explaining a method of manufacturing an embossed structure according to the first embodiment.
Fig. 2 is a view for explaining the method of manufacturing the embossed structure according to the second embodiment.
Fig. 3 is a view for explaining the method of manufacturing the embossed structure according to the third embodiment.
Fig. 4 is a view for explaining the method of manufacturing the embossed structure according to the fourth embodiment.
Fig. 5 is a view for explaining the method of manufacturing the embossed structure according to the fifth embodiment.
Fig. 6 is a view for explaining the display of the ashing apparatus 40 used in the sixth embodiment.
Fig. 7 is a view for explaining the method of manufacturing the embossed structure according to the sixth embodiment.
Fig. 8 is a view for explaining the display of the ashing apparatus 40a used in the seventh embodiment.
Fig. 9 is a view for explaining the method of manufacturing the embossed structure according to the seventh embodiment.
Fig. 10 is a view for explaining the film transistor 100 according to the eighth embodiment.
Fig. 11 is a view for explaining the method of manufacturing a thin film transistor according to the eighth embodiment.
Fig. 12 is a view for explaining the method of manufacturing a thin film transistor according to the eighth embodiment.
Fig. 13 is a view for explaining the method of manufacturing a thin film transistor according to the eighth embodiment.
Fig. 14 is a view for explaining the piezoelectric ink jet head 300 according to the ninth embodiment.
Fig. 15 is a view for explaining the method of manufacturing the piezoelectric ink jet head according to the ninth embodiment.
Fig. 16 is a view for explaining the method of manufacturing the piezoelectric ink jet head according to the ninth embodiment.
Fig. 17 is a view for explaining the method of manufacturing the piezoelectric ink jet head according to the ninth embodiment.
Fig. 18 is a view for explaining the ashing process in the first embodiment.
Fig. 19 is a view showing the result of the ashing treatment in the first embodiment.
Fig. 20 is a view showing the result of the ashing treatment in the first embodiment.
Fig. 21 is a view showing the result of the ashing treatment in the first embodiment.
Fig. 22 is a view showing the result of the ashing treatment in the second embodiment.
Fig. 23 is a view for explaining the evaluation method in the third embodiment.
Fig. 24 is a view showing the result of the ashing treatment in the third embodiment.
Fig. 25 is a view showing the result of the ashing treatment in the third embodiment.
Fig. 26 is a view for explaining a method of manufacturing an embossed structure according to a modification.
Fig. 27 is a view for explaining a conventional thin film transistor 900.
Fig. 28 is a view for explaining a method of manufacturing a conventional thin film transistor.
Fig. 29 is a view for explaining the electrical characteristics of a conventional thin film transistor 900.
以下針對本發明的壓花構造體的製造方法、薄膜電晶體、薄膜電容器、致動器、壓電式噴墨頭及光學元件之中,本發明的壓花構造體的製造方法、薄膜電晶體及壓電式噴墨頭,根據圖示的實施的形態進行說明。實施形態一~七是關於本發明的壓花構造體的製造方法的實施形態,實施形態八是關於本發明的薄膜電晶體的實施形態,實施形態九是關於本發明的壓電式噴墨頭的實施形態。
[實施形態一]
圖1是用以說明與實施形態一有關的壓花構造體的製造方法而顯示之圖。圖1(a)~圖1(g)為各製程圖。此外,在圖1中符號P是表示電漿(plasma)。
與實施形態一有關的壓花構造體的製造方法如圖1所示包含如下的順序之製程:製備含有含金屬化合物,藉由進行熱處理而成為金屬氧化物或金屬的液體材料之第一製程;藉由在基材10上塗佈液體材料形成由金屬氧化物或金屬的前驅物組成物構成的前驅物組成物層20之第二製程(參照圖1(a)及圖1(b));藉由將前驅物組成物層20加熱到位於80℃~200℃的範圍內的溫度(例如150℃)預先降低前驅物組成物層20的流動性之預備加熱製程(參照圖1(c));藉由在將前驅物組成物層20加熱到位於80℃~300℃的範圍內的溫度(例如150℃)的狀態下,且使用加熱到位於80℃~300℃的範圍內的溫度(例如150℃)的凹凸模M1對前驅物組成物層20施以壓花加工,形成在前驅物組成物層20包含殘膜22的壓花構造之第三製程(參照圖1(d));藉由對形成有壓花構造的前驅物組成物層20施以利用大氣壓電漿的灰化處理,處理殘膜22之第四製程(參照圖1(e)及圖1(f));藉由對前驅物組成物層20進行熱處理,由形成有壓花構造的前驅物組成物層20形成由金屬氧化物或金屬構成的壓花構造體30之第五製程(參照圖1(g))。
在與實施形態一有關的壓花構造體的製造方法中,使用[含有含金屬化合物,藉由熱處理而成為金屬氧化物或金屬的液體材料(例如[含有金屬烷氧化物的溶膠-凝膠溶液]、[含有有機金屬化合物之MOD(Metal Organic Decomposition:金屬有機分解)溶液]、[含有金屬鹽(例如金屬氯化物、金屬氧氯化物、金屬硝酸鹽、金屬醋酸鹽等)的金屬鹽溶液]、[混合上述溶膠-凝膠溶液、上述MOD溶液及上述金屬鹽溶液的至少兩種的溶液])等當作液體材料。
在與實施形態一有關的壓花構造體的製造方法中,因在第三製程中使用凹凸模M1對前驅物組成物層20施以壓花加工,故如圖1(d)所示在前驅物組成物層20形成有包含殘膜22的壓花構造。因此,在第四製程中藉由對這種前驅物組成物層20施以利用大氣壓電漿的灰化處理而處理殘膜22。具體上如圖1(e)及圖1(f)所示,擬完全除去殘膜22。
在與實施形態一有關的壓花構造體的製造方法中,使用反應性氣體(例如[含鹵素元素氣體]、[含鹵素元素氣體及含Ar氣體的混合氣體]等)實施第四製程。此情形,含鹵素元素氣體可適合使用各種含氟氣體、含氯氣體、含溴氣體等。
藉由以這種方法,可形成殘膜完全被除去,[無殘膜的影響之壓花構造體,亦即具有被以存在殘膜的部位分裂的構造之壓花構造體]。其結果,在第五製程中因前驅物組成物層被分裂成各個小的區域的結果,前驅物組成物層可不勉強地收縮於面內方向,故能以高的精度形成所需的壓花構造。
完全除去殘膜的方法是使用[施以灰化僅由藉由灰化處理進行之前驅物組成物層的蝕刻速率與殘膜的厚度的關係算出的第一時間之方法(藉由時間管理進行的灰化方法)]。
依照與實施形態一有關的壓花構造體的製造方法,因可藉由在基材上塗佈液體材料形成前驅物組成物層,對該前驅物組成物層施以壓花加工形成壓花構造,進而藉由以高溫對前驅物組成物層進行熱處理,形成壓花構造體,且因可藉由使用具有次微米級的微細的圖案的模施以壓花加工,形成具有次微米級的微細的圖案的壓花構造體,故可使用遠少於以往的原料及製造能量,且以比以往還短的製程製造如上述優良的以薄膜電晶體為首的各種功能元件。
而且,依照與實施形態一有關的壓花構造體的製造方法,因更包含藉由對前驅物組成物層施以灰化處理而處理殘膜之第四製程,故可形成無殘膜的影響之壓花構造體。
而且,依照與實施形態一有關的壓花構造體的製造方法,因擬對前驅物組成物層施以利用大氣壓電漿的灰化處理,在實施第四製程時無須高真空的環境,故可不需要昂貴的高真空的設備,而且可縮短實施第四製程所需的時間。
而且,依照與實施形態一有關的壓花構造體的製造方法,因擬使用反應性氣體實施第四製程,故能以高的蝕刻速率實施灰化製程,進而能以高的生產性製造壓花構造體。
而且,依照與實施形態一有關的壓花構造體的製造方法,因擬藉由加熱到位於80℃~200℃的範圍內的溫度某種程度地進行前驅物組成物層的固化反應而預先降低前驅物組成物層的流動性,並且對透過藉由加熱到位於80℃~300℃的範圍內的溫度降低前驅物組成物層的硬度而得到高的塑性變形能力的前驅物組成物層施以壓花加工,故能以高的精度形成所需的壓花構造,其結果,可製造具有所需的性能的壓花構造體。
而且,依照與實施形態一有關的壓花構造體的製造方法,因擬使用加熱到位於80℃~300℃的範圍內的溫度的模對前驅物組成物層施以壓花加工,故正在施以壓花加工的時候,前驅物組成物層的塑性變形能力不會降低,故能以更高的精度形成所需的壓花構造。
[實施形態二]
圖2是用以說明與實施形態二有關的壓花構造體的製造方法而顯示之圖。圖2(a)是正以第四製程對前驅物組成物層20施以灰化處理的時候的前驅物組成物層20的剖面圖,圖2(b)是剛以第四製程對前驅物組成物層20施以灰化處理後的前驅物組成物層20的剖面圖。
與實施形態二有關的壓花構造體的製造方法基本上包含和與實施形態一有關的壓花構造體的製造方法同樣的製程,但第四製程的內容和與實施形態一有關的壓花構造體的製造方法的情形不同。也就是說在與實施形態二有關的壓花構造體的製造方法中,如圖2所示在第四製程中,擬施以灰化超過由藉由灰化處理進行之前驅物組成物層的蝕刻速率與殘膜22的厚度的關係算出的第一時間之時間。其結果,在與實施形態二有關的壓花構造體的製造方法中,如圖2(b)所示就會在基材10形成有凹部24。
如此,雖然與實施形態二有關的壓花構造體的製造方法其第四製程的內容和與實施形態一有關的壓花構造體的製造方法的情形不同,但因和與實施形態一有關的壓花構造體的製造方法的情形一樣,包含藉由對前驅物組成物層施以灰化處理而處理殘膜的第四製程,故可形成無殘膜的影響之壓花構造體。而且,因擬對前驅物組成物層施以利用大氣壓電漿的灰化處理,在實施第四製程時無須高真空的環境,故可不需要昂貴的高真空的設備,而且可縮短實施第四製程所需的時間。
此外,因與實施形態二有關的壓花構造體的製造方法除了第四製程以外其餘的內容和與實施形態一有關的壓花構造體的製造方法的情形一樣,故具有與實施形態一有關的壓花構造體的製造方法所具有的功效之中對應的功效。
[實施形態三]
圖3是用以說明與實施形態三有關的壓花構造體的製造方法而顯示之圖。圖3(a)是正以第四製程對前驅物組成物層20施以灰化處理的時候的前驅物組成物層20的剖面圖,圖3(b)是剛以第四製程對前驅物組成物層20施以灰化處理後的前驅物組成物層20的剖面圖。
與實施形態三有關的壓花構造體的製造方法基本上包含和與實施形態一有關的壓花構造體的製造方法同樣的製程,但第四製程的內容和與實施形態一有關的壓花構造體的製造方法的情形不同。也就是說在與實施形態三有關的壓花構造體的製造方法中,如圖3所示基材使用由成為蝕刻中止層的材料構成的基材10a,並且擬施以灰化超過由藉由灰化處理進行之前驅物組成物層的蝕刻速率與殘膜22的厚度的關係算出的第一時間之時間。
如此,雖然與實施形態三有關的壓花構造體的製造方法其第四製程的內容和與實施形態一有關的壓花構造體的製造方法的情形不同,但因和與實施形態一有關的壓花構造體的製造方法的情形一樣,包含藉由對前驅物組成物層施以灰化處理而處理殘膜的第四製程,故可形成無殘膜的影響之壓花構造體。而且,因擬對前驅物組成物層施以利用大氣壓電漿的灰化處理,在實施第四製程時無須高真空的環境,故可不需要昂貴的高真空的設備,而且可縮短實施第四製程所需的時間。
而且,依照與實施形態三有關的壓花構造體的製造方法,儘管在所謂的過度蝕刻的條件下施以灰化,但仍和與實施形態二有關的壓花構造體的製造方法的情形不同,如圖3(b)所示在基材10a不會形成有凹部。
此外,因與實施形態三有關的壓花構造體的製造方法除了第四製程以外其餘的內容和與實施形態一有關的壓花構造體的製造方法的情形一樣,故具有與實施形態一有關的壓花構造體的製造方法所具有的功效之中對應的功效。
[實施形態四]
圖4是用以說明與實施形態四有關的壓花構造體的製造方法而顯示之圖。圖4(a)是正以第四製程對前驅物組成物層20施以灰化處理的時候的前驅物組成物層20的剖面圖,圖4(b)是剛以第四製程對前驅物組成物層20施以灰化處理後的前驅物組成物層20的剖面圖。
與實施形態四有關的壓花構造體的製造方法基本上包含和與實施形態一有關的壓花構造體的製造方法同樣的製程,但第四製程的內容和與實施形態一有關的壓花構造體的製造方法的情形不同。也就是說在與實施形態四有關的壓花構造體的製造方法中,如圖4所示基材使用在第一基材12的表面具備由成為蝕刻中止層的材料構成的層14之基材10b,並且擬施以灰化超過由藉由灰化處理進行之前驅物組成物層的蝕刻速率與殘膜22的厚度的關係算出的第一時間之時間。
如此,雖然與實施形態四有關的壓花構造體的製造方法其第四製程的內容和與實施形態一有關的壓花構造體的製造方法的情形不同,但因和與實施形態一有關的壓花構造體的製造方法的情形一樣,包含藉由對前驅物組成物層施以灰化處理而處理殘膜的第四製程,故可形成無殘膜的影響之壓花構造體。而且,因擬對前驅物組成物層施以利用大氣壓電漿的灰化處理,在實施第四製程時無須高真空的環境,故可不需要昂貴的高真空的設備,而且可縮短實施第四製程所需的時間。
而且,在與實施形態四有關的壓花構造體的製造方法中,也和與實施形態三有關的壓花構造體的製造方法的情形一樣,儘管在所謂的過度蝕刻的條件下施以灰化,但仍如圖4(b)所示在基材10b不會形成有凹部。
此外,因與實施形態四有關的壓花構造體的製造方法除了第四製程以外其餘的內容和與實施形態一有關的壓花構造體的製造方法的情形一樣,故具有與實施形態一有關的壓花構造體的製造方法所具有的功效之中對應的功效。
[實施形態五]
圖5是用以說明與實施形態五有關的壓花構造體的製造方法而顯示之圖。圖5(a)是正以第四製程對前驅物組成物層20施以灰化處理的時候的前驅物組成物層20的剖面圖,圖5(b)是剛以第四製程對前驅物組成物層20施以灰化處理後的前驅物組成物層20的剖面圖,圖5(c)是藉由以第五製程對前驅物組成物層20進行熱處理形成的壓花構造體30的剖面圖。此外,在圖5中為了使後述的海島構造28容易看起見,比在圖1~圖4中還放大圖面而顯示。
與實施形態五有關的壓花構造體的製造方法基本上包含和與實施形態一有關的壓花構造體的製造方法同樣的製程,但第四製程的內容和與實施形態一有關的壓花構造體的製造方法的情形不同。也就是說在與實施形態五有關的壓花構造體的製造方法中,如圖5所示在第四製程中,擬使殘膜22變薄直到成為藉由實施接著該第四製程的第五製程而使殘膜採取海島構造28的薄度。
如此,雖然與實施形態五有關的壓花構造體的製造方法其第四製程的內容和與實施形態一有關的壓花構造體的製造方法的情形不同,但因和與實施形態一有關的壓花構造體的製造方法的情形一樣,包含藉由對前驅物組成物層施以灰化處理而處理殘膜的第四製程,故可形成無殘膜的影響之壓花構造體。而且,因擬對前驅物組成物層施以利用大氣壓電漿的灰化處理,在實施第四製程時無須高真空的環境,故可不需要昂貴的高真空的設備,而且可縮短實施第四製程所需的時間。
而且,在與實施形態五有關的壓花構造體的製造方法中,因在第五製程結束後,殘膜採取海島構造28,故即使是在第四製程結束未完全除去殘膜的情形,也能形成無殘膜的影響之壓花構造體。
此外,因與實施形態五有關的壓花構造體的製造方法除了第四製程以外其餘的內容和與實施形態一有關的壓花構造體的製造方法的情形一樣,故具有與實施形態一有關的壓花構造體的製造方法所具有的功效之中對應的功效。
[實施形態六]
圖6是用以說明使用於實施形態六的灰化裝置40而顯示之圖。圖7是用以說明與實施形態六有關的壓花構造體的製造方法而顯示之圖。圖7(a)是即將以第四製程對前驅物組成物層20施以灰化處理前的前驅物組成物層20的剖面圖,圖7(b)是剛以第四製程對前驅物組成物層20施以灰化處理後的前驅物組成物層20的剖面圖。此外,圖6中符號41是表示一方的電極,符號43是表示他方的電極。而且,在圖7中為了使側向蝕刻的樣子容易看起見,比在圖5中更放大圖面而顯示。
與實施形態六有關的壓花構造體的製造方法基本上包含和與實施形態一有關的壓花構造體的製造方法同樣的製程。再者如圖6所示,擬藉由使用灰化裝置40(大氣壓電漿灰化裝置)對前驅物組成物層施以灰化處理而實施第四製程。
如此,與實施形態六有關的壓花構造體的製造方法因和與實施形態一有關的壓花構造體的製造方法的情形一樣,包含藉由對前驅物組成物層施以灰化處理而處理殘膜的第四製程,故可形成無殘膜的影響之壓花構造體。而且,因擬對前驅物組成物層施以利用大氣壓電漿的灰化處理,在實施第四製程時無須高真空的環境,故可不需要昂貴的高真空的設備,而且可縮短實施第四製程所需的時間。
此外,在與實施形態六有關的壓花構造體的製造方法中,因擬對前驅物組成物層施以利用大氣壓電漿的灰化處理,灰化氣體的平均自由路徑變短且在第四製程中發生側向蝕刻(參照圖7),故考慮該因素而設計凹凸模的圖案較佳。此點與實施形態一~五有關的壓花構造體的製造方法的情形也一樣。
[實施形態七]
圖8是用以說明使用於實施形態七的灰化裝置40a而顯示之圖。圖9是用以說明與實施形態七有關的壓花構造體的製造方法而顯示之圖。圖9(a)是即將以第四製程對前驅物組成物層20施以灰化處理前的前驅物組成物層20的剖面圖,圖9(b)是剛以第四製程對前驅物組成物層20施以灰化處理後的前驅物組成物層20的剖面圖。此外,圖8中符號42是表示正電極,符號44是表示負電極。
與實施形態七有關的壓花構造體的製造方法基本上包含和與實施形態六有關的壓花構造體的製造方法同樣的製程,但第四製程的內容和與實施形態六有關的壓花構造體的製造方法的情形不同。也就是說在與實施形態七有關的壓花構造體的製造方法中,如圖8所示在第四製程中,擬藉由使用灰化裝置40a(低壓電漿灰化裝置)對前驅物組成物層20施以利用低壓電漿的灰化處理實施第四製程。在與實施形態七有關的壓花構造體的製造方法中,例如在1Pa~1000Pa的壓力條件(較佳為10Pa~100Pa)之下進行利用低壓電漿的灰化處理。而且,在與實施形態七有關的壓花構造體的製造方法中,如圖8所示擬在施加了偏壓的條件下實施第四製程。
如此,雖然與實施形態七有關的壓花構造體的製造方法其第四製程的內容和與實施形態六有關的壓花構造體的製造方法的情形不同,但因和與實施形態六有關的壓花構造體的製造方法的情形一樣,更包含藉由對前驅物組成物層施以灰化處理而處理殘膜的第四製程,故可形成無殘膜的影響之壓花構造體。而且,因擬在施加了偏壓的狀態下實施第四製程,灰化氣體的碰撞能量(collision energy)變高,故能以高的蝕刻速率實施灰化製程,進而能以高的生產性製造壓花構造體。
而且,依照與實施形態七有關的壓花構造體的製造方法,也能得到如以下的功效。也就是說依照與實施形態七有關的壓花構造體的製造方法,使用於灰化的氣體(灰化氣體)的平均自由路徑比在大氣壓條件下長,且灰化氣體的飛翔方向在一方向一致,故如圖9所示可降低對壓花構造的側面部分的蝕刻(側向蝕刻)的比例,進而可製造具有高的形狀精度的壓花構造體。而且,因即使是施加了偏壓的狀態,也能發生穩定的輝光放電,故能以高的蝕刻速率穩定地實施灰化製程,進而能以高的生產性穩定地製造壓花構造體。而且,因藉由前驅物組成物層與反應性氣體的反應所產生的反應產物(reaction product)揮發而容易被除去,故由此觀點也能以高的蝕刻速率穩定地實施灰化製程,進而能以高的生產性穩定地製造壓花構造體。
此外,因與實施形態七有關的壓花構造體的製造方法除了第四製程以外其餘的內容和與實施形態六有關的壓花構造體的製造方法的情形一樣,故具有與實施形態六有關的壓花構造體的製造方法所具有的功效之中對應的功效。
[實施形態八]
1、與實施形態八有關的薄膜電晶體100
圖10是用以說明與實施形態八有關的薄膜電晶體100而顯示之圖。圖10(a)是薄膜電晶體100的俯視圖,圖10(b)是圖10(a)的A1-A1剖面圖,圖10(c)是圖10(a)的A2-A2剖面圖。
與實施形態八有關的薄膜電晶體100如圖10(a)及圖10(b)所示包含:包含源極區域144及汲極區域146以及通道區域142之氧化物導體層140;控制通道區域142的導通狀態之閘電極120;形成於閘電極120與通道區域142之間,由鐵電材料構成之閘絕緣層130。通道區域142的層厚比源極區域144的層厚及汲極區域146的層厚薄。通道區域142的層厚較佳為源極區域144的層厚及汲極區域146的層厚的1/2以下。閘電極120如圖10(a)及圖10(c)所示,透過貫通孔(through hole)150連接於露出到外部的閘墊(gate pad)122。
在與實施形態八有關的薄膜電晶體100中,氧化物導體層140是使用壓花成形技術而形成。
在與實施形態八有關的薄膜電晶體100中,通道區域142的載子濃度及層厚被設定為如在將關閉(OFF)的控制電壓施加於閘電極120時,通道區域142空乏化的值。具體上通道區域142的載子濃度位於1×1015cm-3~1×1021cm-3的範圍內,通道區域142的層厚位於5nm~100nm的範圍內。
此外,在與實施形態八有關的薄膜電晶體100中,源極區域144及汲極區域146的層厚位於50nm~1000nm的範圍內。
氧化物導體層140例如由銦錫氧化物(ITO)構成,閘絕緣層130例如由PZT(Pb(Zrx, Ti1-x)O3)構成,閘電極120例如由鎳酸鑭(LNO(LaNiO3))構成,當作固體基板的絕緣性基板110例如由在Si基板的表面隔著SiO2層及Ti層形成STO(SrTiO)層的絕緣性基板構成。
2、與實施形態八有關的薄膜電晶體的製造方法
與實施形態八有關的薄膜電晶體100可藉由以下所示的薄膜電晶體的製造方法製造。以下依照製程順序進行說明。
圖11~圖13是用以說明與實施形態八有關的薄膜電晶體的製造方法而顯示之圖。圖11(a)~圖11(f)、圖12(a)~圖12(f)及圖13(a)~圖13(e)為各製程圖。此外,在各製程圖中左側所示的圖是對應圖10(b)的圖,右側所示的圖是對應圖10(c)的圖。
(1)、閘電極120的形成
首先,製備藉由進行熱處理而成為由金屬氧化物陶瓷(metaloxideceramics)(鎳酸鑭)構成的功能性固體材料的功能性液體材料(functional liquid material)(第一製程)。具體上,製備含有金屬無機鹽(metal inorganic salt)(硝酸鑭(lanthanum nitrate)(六水合物(hexahydrate))及醋酸鎳(nickel acetate)(四水合物(tetrahydrate)))的溶液(溶劑:2-甲氧基乙醇(2-methoxyethanol))。
其次,如圖11(a)及圖11(b)所示,在絕緣性基板110中的一方的表面使用旋塗法(spin coating method)塗佈功能性液體材料(例如500rpm、25秒),然後藉由將絕緣性基板110放置在熱板(hot plate)上以60℃使其乾燥1分鐘,形成鎳酸鑭的前驅物組成物層120’(層厚300nm)(第二製程)。
其次,如圖11(c)及圖11(d)所示,藉由使用對應閘電極層120及閘墊122的區域成為凹而形成的凹凸模M2(高低差300nm),以150℃對前驅物組成物層120’施以壓花加工,在前驅物組成物層120’形成壓花構造(凸部的層厚300nm、凹部的層厚50nm)(第三製程)。施以壓花加工時的壓力是以5MPa。據此,因擬對藉由加熱到位於80℃~300℃的範圍內的第二溫度而得到高的塑性變形能力的前驅物組成物層施以壓花加工,故能以高的精度形成所需的壓花構造。
其次,藉由對前驅物組成物層120’進行全面灰化處理,如圖11(e)所示,完全除去存在於對應閘電極層120的區域以外的區域的殘膜120’z(第四製程)。第四製程是使用濕式蝕刻裝置而進行。
最後,藉由使用RTA(Rapid Thermal Annealing:快速熱退火)裝置並以高溫(650℃、10分鐘)對前驅物組成物層120’進行熱處理,如圖11(f)所示,由前驅物組成物層120’形成由功能性固體材料層(鎳酸鑭)構成的閘電極120及閘墊122(第五製程)。
(2)、閘絕緣層130的形成
首先,製備藉由進行熱處理而成為由金屬氧化物陶瓷(PZT)構成的功能性固體材料的功能性液體材料。具體上,製備含有金屬烷氧化物的溶液(三菱材料股份有限公司製,PZT溶膠-凝膠溶液)當作功能性液體材料(第一製程)。
其次,藉由重複3次在絕緣性基板110中的一方的表面上使用旋塗法塗佈上述的功能性液體材料(例如2000rpm、25秒),然後將絕緣性基板110放置在熱板上以250℃使其乾燥5分鐘的操作,形成功能性固體材料(PZT)的前驅物組成物層130’(層厚300nm)(第二製程,參照圖12(a))。
其次,如圖12(b)及圖12(c)所示,藉由使用對應貫通孔150的區域成為凸而形成的凹凸模M3(高低差300nm),以150℃對前驅物組成物層130’施以壓花加工,在前驅物組成物層130’形成對應貫通孔150的壓花構造(第三製程)。施以壓花加工時的壓力是以5MPa。據此,因擬對藉由加熱到位於80℃~300℃的範圍內的第二溫度而得到高的塑性變形能力的前驅物組成物層施以壓花加工,故能以高的精度形成所需的壓花構造。
其次,藉由對前驅物組成物層130’進行全面灰化處理,如圖12(d)所示,完全除去存在於之後成為通道區域142的區域的殘膜130’z(第四製程)。第四製程是使用低壓電漿蝕刻裝置,在10Pa的壓力條件之下一邊導入反應性氣體(例如CF4氣體及Ar氣體),一邊進行。
最後,藉由使用RTA裝置並以高溫(650℃、10分鐘)對前驅物組成物層130’進行熱處理,如圖12(e)所示,由前驅物組成物層130’形成由功能性固體材料層(PZT)構成的閘絕緣層130(第五製程)。
(3)、氧化物導體層140的形成
首先,製備藉由進行熱處理而成為由金屬氧化物陶瓷(ITO)構成的功能性固體材料的功能性液體材料(第一製程)。具體上,製備含有金屬羧酸鹽(metal carboxylate)的溶液(高純度化學研究所股份有限公司製的功能性液體材料(商品名:ITO-05C)、原液(stock solution):稀釋液(diluent)=1:1.5)當作功能性液體材料。此外,在該功能性液體材料添加有於完成時通道區域142的載子濃度成為1×1015cm-3~1×1021cm-3的範圍內的濃度的雜質。
其次,如圖12(f)所示藉由在絕緣性基板110中的一方的表面上使用旋塗法塗佈上述的功能性液體材料(例如2000rpm、25秒),然後將絕緣性基板110放置在熱板上以150℃使其乾燥3分鐘,形成功能性固體材料(ITO)的前驅物組成物層140’(層厚300nm)(第二製程)。
其次,如圖13(a)~圖13(c)所示,藉由使用對應通道區域142的區域比對應源極區域144的區域及對應汲極區域146的區域還凸而形成的凹凸模M4(高低差350nm),對前驅物組成物層140’施以壓花加工,在前驅物組成物層140’形成壓花構造(凸部的層厚350nm,凹部的層厚100nm)(第三製程)。據此,前驅物組成物層140’之中成為通道區域142的部分的層厚比其他的部分薄。
此時,在上述的製程中,擬在將前驅物組成物層140’加熱到150℃的狀態下,且使用加熱到150℃的模施以壓花加工。此情形施以壓花加工時的壓力是以4MPa左右。
此外,凹凸模M4具有像對應元件分離區域(element isolation region)160及貫通孔150的區域比對應通道區域142的區域更凸的構造,在對應元件分離區域160及貫通孔150的區域就會形成有前驅物組成物層140’的殘膜140’z(參照圖13(c))。
其次,藉由對前驅物組成物層140’進行全面灰化處理,如圖13(d)所示,完全除去存在於對應元件分離區域160及貫通孔150的區域的殘膜140’z(第四製程)。第四製程是使用低壓電漿蝕刻裝置,在10Pa的壓力條件之下一邊導入反應性氣體(例如CF4氣體及Ar氣體),一邊進行。
最後,藉由對前驅物組成物層140’施以熱處理(在熱板上以400℃、10分的條件進行前驅物組成物層140’的燒成,然後使用RTA裝置以650℃、30分(前半15分氧環境、後半的15分氮環境)的條件將前驅物組成物層140’加熱),形成包含源極區域144、汲極區域146及通道區域142的氧化物導體層140(第五製程),可製造具有如圖13(e)所示的下閘極(bottom gate)構造之與實施形態八有關的薄膜電晶體100。
3、與實施形態八有關的薄膜電晶體100的功效
依照與實施形態八有關的薄膜電晶體100,因構成通道區域142的材料使用氧化物導電性材料,故可提高載子濃度,而且因構成閘絕緣層130的材料使用鐵電材料,故能以低的驅動電壓高速地進行切換,其結果,與習知的薄膜電晶體900的情形一樣,能以低的驅動電壓高速地控制大的電流。
而且,依照與實施形態八有關的薄膜電晶體100,因通道區域142的層厚比源極區域144的層厚及汲極區域146的層厚薄,且僅藉由使用上述的壓花構造體的製造方法形成無殘膜的影響之氧化物導體層140,就可製造薄膜電晶體,故也可以不像習知的薄膜電晶體900的情形般由不同的材料形成通道區域與源極區域及汲極區域,可使用遠少於以往的原料及製造能量,且以比以往還短的製程製造如上述優良的薄膜電晶體。
而且,依照與實施形態八有關的薄膜電晶體100,因氧化物導體層140、閘電極120及閘絕緣層130都不會使用高真空製程而形成,故可不使用真空製程而製造薄膜電晶體,可使用遠少於以往的製造能量,且以比以往還短的製程製造如上述優良的薄膜電晶體。
再者,依照與實施形態八有關的薄膜電晶體100,因通道區域142的載子濃度及層厚被設定為如在將關閉的控制電壓施加於閘電極120時,通道區域142空乏化的值,故即使提高了氧化物導體層的載子濃度也能充分降低關閉時流過的電流量,可一邊維持必要的開關比,一邊以低的驅動電壓控制大的電流。
[實施形態九]
圖14是用以說明與實施形態九有關的壓電式噴墨頭300而顯示之圖。圖14(a)是壓電式噴墨頭300的剖面圖,圖14(b)及圖14(c)是顯示壓電式噴墨頭300吐出墨水時的樣子之圖。
1、與實施形態九有關的壓電式噴墨頭300的構成
與實施形態九有關的壓電式噴墨頭300如圖14(a)所示包含:空腔構件340;安裝於空腔構件340的一方側,形成有壓電元件(piezoelectric element)320之振動板350;安裝於空腔構件340的他方側,形成有噴嘴孔332之噴嘴板330;藉由空腔構件340、振動板350及噴嘴板330劃定之墨水室360。在振動板350設置有連通於墨水室360用以將墨水供給至墨水室360的墨水供給口352。
依照與實施形態九有關的壓電式噴墨頭300,如圖14(b)及圖14(c)所示,在藉由將適宜的電壓施加於壓電元件320,使振動板350一時撓曲於上方並由未圖示的儲墨器(reservoir)將墨水供給至墨水室360後,藉由使振動板350撓曲於下方,經由噴嘴孔332由墨水室360使墨水滴i吐出。據此,可在被印刷物進行鮮明的印刷。
2、與實施形態九有關的壓電式噴墨頭的製造方法
具有這種構造的壓電式噴墨頭300為壓電元件320(第一電極層322、壓電層324及第二電極層326)及空腔構件340都是使用本發明的壓花構造體的製造方法形成。以下依照製程順序說明與實施形態九有關的壓電式噴墨頭300的製造方法。
圖15~圖17是用以說明與實施形態九有關的壓電式噴墨頭的製造方法而顯示之圖。圖15(a)~圖15(f)、圖16(a)~圖16(d)及圖17(a)~圖17(e)為各製程圖。
(1)、壓電元件320的形成
(1-1)、第一電極層322的形成
首先,製備藉由進行熱處理而成為由金屬氧化物陶瓷(鎳酸鑭)構成的功能性固體材料的功能性液體材料(第一製程)。具體上,製備含有金屬無機鹽(硝酸鑭(六水合物)及醋酸鎳 (四水合物))的溶液(溶劑:2-甲氧基乙醇)。
其次,如圖15(a)所示,在虛擬基板(dummy substrate)310中的一方的表面使用旋塗法塗佈功能性液體材料(例如500rpm、25秒),然後藉由將虛擬基板310放置在熱板上以60℃使其乾燥1分鐘,形成功能性固體材料(鎳酸鑭)的前驅物組成物層322’(層厚300nm)(第二製程)。
其次,如圖15(b)所示,藉由使用對應第一電極層322的區域成為凹而形成的凹凸模M8(高低差300nm),以150℃對前驅物組成物層322’施以壓花加工,在前驅物組成物層322’形成壓花構造(凸部的層厚300nm、凹部的層厚50nm)(第三製程)。施以壓花加工時的壓力是以5MPa。
其次,藉由對前驅物組成物層322’進行全面灰化處理,如圖15(c)所示,完全除去存在於對應第一電極層322的區域以外的區域的殘膜(第四製程)。第四製程是使用濕式蝕刻裝置而進行。
最後,藉由使用RTA裝置並以高溫(650℃、10分鐘)對前驅物組成物層322’進行熱處理,如圖15(d)所示,由前驅物組成物層322’形成由功能性固體材料層(鎳酸鑭)構成的第一電極層322(第五製程)。
(1-2)、壓電層324的形成
首先,製備藉由進行熱處理而成為由金屬氧化物陶瓷(PZT)構成的功能性固體材料的功能性液體材料(第一製程)。具體上,製備含有金屬烷氧化物的溶液(三菱材料股份有限公司製,PZT溶膠-凝膠溶液)當作功能性液體材料(第一製程)。
其次,如圖15(e)所示,藉由在虛擬基板310中的一方的表面上使用旋塗法塗佈上述的功能性液體材料,然後將虛擬基板310放置在熱板上以250℃使其乾燥5分鐘,形成功能性固體材料(PZT)的前驅物組成物層324’(例如層厚1μm~10μm)(第二製程)。
其次,如圖15(f)所示,藉由使用對應壓電層324的區域成為凹而形成的凹凸模M9(高低差500nm),對前驅物組成物層324’施以壓花加工,在前驅物組成物層324’形成壓花構造(例如凸部的層厚1μm~10μm、凹部的層厚50nm) (第三製程)。
此時,在上述的製程中,在將前驅物組成物層324’加熱到150℃的狀態下,且使用加熱到150℃的模施以壓花加工。施以壓花加工時的壓力是以4MPa左右。
其次,藉由對前驅物組成物層324’進行全面灰化處理,如圖15(g)所示,完全除去存在於對應壓電層324的區域以外的區域的殘膜(第四製程)。第四製程是使用低壓電漿蝕刻裝置,在10Pa的壓力條件之下一邊導入反應性氣體(例如CF4氣體及Ar氣體),一邊進行。
最後,藉由使用RTA裝置並以高溫(650℃、10分鐘)對前驅物組成物層324’進行熱處理,如圖15(h)所示,由前驅物組成物層324’形成由功能性固體材料層(PZT)構成的壓電層324(第五製程)。
(1-3)、第二電極層326的形成
首先,製備藉由進行熱處理而成為由金屬氧化物陶瓷(鎳酸鑭)構成的功能性固體材料的功能性液體材料(第一製程)。具體上,製備含有金屬無機鹽(硝酸鑭(六水合物)及醋酸鎳 (四水合物))的溶液(溶劑:2-甲氧基乙醇)。
其次,如圖16(a)所示,在虛擬基板310中的一方的表面上使用旋塗法塗佈功能性液體材料(例如500rpm、25秒),然後藉由將虛擬基板310放置在熱板上以60℃使其乾燥1分鐘,形成功能性固體材料(鎳酸鑭)的前驅物組成物層326’(層厚300nm)(第二製程)。
其次,如圖16(b)所示,藉由使用對應第二電極層326的區域成為凹而形成的凹凸模M10(高低差300nm),以150℃對前驅物組成物層326’施以壓花加工,在前驅物組成物層326’形成壓花構造(凸部的層厚300nm、凹部的層厚50nm)(第三製程)。施以壓花加工時的壓力是以5MPa。
其次,藉由對前驅物組成物層326’進行全面灰化處理,如圖16(c)所示,完全除去存在於對應第二電極層326的區域以外的區域的殘膜(第四製程)。第四製程是使用濕式蝕刻裝置而進行。
最後,藉由使用RTA裝置並以高溫(650℃、10分鐘)對前驅物組成物層326’進行熱處理,如圖16(d)所示,由前驅物組成物層326’形成由功能性固體材料層(鎳酸鑭)構成的第二電極層326(第五製程)。據此,完成由第一電極層322、壓電層324及第二電極層326構成的壓電元件320。
(2)、振動板350與壓電元件320的貼合
如圖16(e)所示,使用接著劑將具有墨水供給口352的振動板350與壓電元件320貼合。
(3)、空腔構件340的形成
首先,製備藉由進行熱處理而成為金屬氧化物陶瓷(石英玻璃)的功能性液體材料(第一製程)。具體上,製備含有金屬烷氧化物(矽酸異丙酯(isopropyl silicate)(Si(OC3H7)4)的溶液,當作功能性液體材料。
其次,如圖17(a)所示,在振動板350中的一方的表面上使用旋塗法塗佈上述的功能性液體材料,然後藉由將虛擬基板310放置在熱板上以150℃使其乾燥5分鐘,形成功能性固體材料(石英玻璃)的前驅物組成物層340’(例如層厚10μm~20μm)(第二製程)。
其次,如圖17(b)所示,藉由使用具有對應墨水室360等的形狀的凹凸模M11,對前驅物組成物層340’施以壓花加工,在前驅物組成物層340’形成壓花構造(例如凸部的層厚10μm~20μm、凹部的層厚50nm) (第三製程)。
此時,在上述的製程中,在將前驅物組成物層340’加熱到150℃的狀態下,且使用加熱到150℃的模施以壓花加工。施以壓花加工時的壓力是以4MPa左右。
其次,藉由對前驅物組成物層340’進行全面灰化處理,如圖17(c)所示,完全除去存在於形成空腔構件340的區域以外的區域的殘膜(第四製程)。第四製程是使用大氣壓電漿蝕刻裝置,在大氣壓條件之下一邊導入反應性氣體(例如CF4氣體及Ar氣體),一邊進行。
最後,藉由使用RTA裝置並以高溫(650℃、10分鐘)對前驅物組成物層340’進行熱處理,如圖17(d)所示,由前驅物組成物層340’形成由功能性固體材料層(石英玻璃)構成的空腔構件340。
(4)、空腔構件340與噴嘴板330的貼合
如圖17(e)所示,使用接著劑將空腔構件340與具有噴嘴孔332的噴嘴板330貼合。
(5)、虛擬基板310的卸下
如圖17(f)所示,由壓電元件320卸下虛擬基板310。據此,完成與實施形態九有關的壓電式噴墨頭300。
3、與實施形態九有關的壓電式噴墨頭300的功效
依照與實施形態九有關的壓電式噴墨頭300,因壓電元件320(第一電極層322、壓電層324及第二電極層326)及空腔構件340是使用壓花成形技術而形成,故可使用遠少於以往的原料及製造能量,且以比以往還短的製程製造壓電式噴墨頭。
而且,依照與實施形態九有關的壓電式噴墨頭300,因具備藉由對透過以位於80℃~300℃的範圍內的第二溫度進行熱處理而得到高的塑性變形能力的前驅物組成物層施以壓花加工而形成之具有以高的精度形成的壓花構造之第一電極層、壓電層、第二電極層及空腔構件,故成為具有所需的性能之壓電式噴墨頭。
而且,依照與實施形態九有關的壓電式噴墨頭300,因壓電元件320(第一電極層322、壓電層324及第二電極層326)及空腔構件340都是使用液體材料而形成,故可使用壓花成形加工技術製造壓電式噴墨頭,可使用遠少於以往的原料及製造能量製造如上述優良的壓電式噴墨頭。
而且,依照與實施形態九有關的壓電式噴墨頭300,因壓電元件320(第一電極層322、壓電層324及第二電極層326)及空腔構件340都不會使用高真空製程而形成,故可使用遠少於以往的製造能量,且以比以往還短的製程製造如上述優良的壓電式噴墨頭。
而且,依照與實施形態九有關的壓電式噴墨頭300,因空腔構件使用大氣壓電漿裝置而不使用真空製程而製造,可使用遠少於以往的製造能量,且以比以往還短的製程製造。
再者,依照與實施形態九有關的壓電式噴墨頭300,因壓電層及/或空腔構件使用本發明的壓花構造體的製造方法而形成,故能以無殘膜的影響之壓花構造體,使用遠少於以往的原料及製造能量,且以比以往還短的製程製造壓電式噴墨頭。
[實施例]
[實施例一]
實施例一是顯示可藉由使用反應性氣體施以灰化處理,完全除去前驅物組成物層之實施例。
圖18是用以說明實施例一中的灰化處理而顯示之圖。圖18(a)~圖18(e)是灰化處理的各製程圖。此外,圖18(c)~圖18(e)之中圖18(c)是顯示灰化條件1中的灰化處理的結果之圖,圖18(b)是顯示灰化條件2中的灰化處理的結果之圖,圖18(c)是顯示灰化條件3中的灰化處理的結果之圖。
圖19是顯示實施例一中的灰化處理的結果之圖。橫軸是表示灰化時間,縱軸是表示對前驅物組成物層520施以灰化處理後的前驅物組成物層的層厚。此外在圖19中,在前驅物組成物層520的層厚成為負的區域中是顯示被蝕刻到絕緣性基板510。
圖20是顯示實施例一中的灰化處理的結果之圖。圖20(a)是顯示施以灰化處理的部分與未施以灰化處理的部分的邊界部位中的SEM(Scanning Electron Microscope:掃描電子顯微鏡)照片之圖,圖20(b)是顯示該邊界部位中的Ti(鈦)的分布之圖。
圖21是顯示實施例一中的灰化處理的結果之圖。圖21(a)是顯示未施以灰化處理的部分R1中的EDX光譜(EDX spectrum)(能量散佈X射線光譜(Energy Dispersive X-ray spectrum))之圖,圖21(a)是顯示施以灰化處理的部分R2中的EDX光譜之圖。
在實施例一中,於在Si基板的表面形成SiO2層的絕緣性基板510上,藉由旋塗法塗佈TiO2的溶膠-凝膠溶液形成前驅物組成物層520,然後以在熱板上以200℃將形成有前驅物組成物層520的絕緣性基板乾燥了5分鐘之物當作試樣使用。絕緣性基板510的尺寸、形狀例如使用縱20mm×橫20mm×高度0.7mm的長方體。200℃乾燥後的前驅物組成物層520的層厚為75nm。
然後如圖18(a)所示,在前驅物組成物層520的表面局部地貼附耐熱性絕緣帶M20後,如圖18(b)所示,對前驅物組成物層520施以灰化處理。設一邊使反應性氣體(CF4氣體:流量0.1L/分)與載體氣體(He氣體:流量9L/分)一起流過,一邊對前驅物組成物層520施以灰化處理為灰化條件1,設一邊使Ar氣體(流量0.1L/分)與載體氣體(He氣體:流量9L/分)一起流過,一邊對前驅物組成物層520施以灰化處理為灰化條件2,設一邊使反應性氣體(CF4氣體:流量0.05L/分)及Ar氣體(流量0.05L/分)與載體氣體(He氣體:流量9L/分)一起流過,一邊對前驅物組成物層520施以灰化處理為灰化條件3。
然後,針對以灰化條件1施以灰化處理的試樣,由前驅物組成物層520的表面將耐熱性絕緣帶M20剝離後,使用KLA-Tencor股份有限公司製的階規(step gauge)[Alpha Step-500],測定了距前驅物組成物層520的表面的蝕刻量(段差(level difference))。而且,使用日本電子股份有限公司製的掃描電子顯微鏡(scanning electron microscope)/能量散佈X射線分析儀(energy dispersive X-ray analyzer)[JSM-5510],取得了施以灰化處理的部分與未施以灰化處理的部分的邊界部位中的SEM影像及元素映射影像(element mapping image)(Ti)。而且,使用日本電子股份有限公司製的掃描電子顯微鏡/能量散佈X射線分析儀[JSM-5510],取得了施以灰化處理的部分與未施以灰化處理的部分的邊界部位中的EDX光譜(能量散佈X射線光譜)。
其結果如圖18及圖19所示得知,在以灰化條件1對前驅物組成物層520施以灰化處理的情形下,以10分左右的灰化時間可完全除去前驅物組成物層520,及即使令灰化時間為10分以上,絕緣性基板510也不被蝕刻(參照圖18(c)及圖19)。而且得知,在以灰化條件2對前驅物組成物層520施以灰化處理的情形下,以30分左右的灰化時間可完全除去前驅物組成物層520。但是此情形得知,若令灰化時間為5分以上,則絕緣性基板510也被蝕刻(參照圖18(d)及圖19)。另一方面得知,在以灰化條件3對前驅物組成物層520施以灰化處理的情形下,以30分左右的灰化時間很難完全除去前驅物組成物層520(參照圖18(e)及圖19)。
而且如圖20所示,在施以灰化處理的部分與未施以灰化處理的部分之間SEM影像中的清晰的邊界線被觀測到(參照圖20(a))。而且,在施以灰化處理的部分中,與未施以灰化處理的部分比較,確認了被觀測到的Ti(鈦)的量被大幅減少(參照圖20(b))。
而且如圖21所示,在施以灰化處理的部分R2中未被觀測到:在未施以灰化處理的部分R1被觀測到的Ti的尖峰(peak)(4.6Kev及4.9Kev)(參照圖21(a)及圖21(b))。
[實施例二]
實施例二是顯示在對燒成前的前驅物組成物層施以灰化處理的情形下,能以比對燒成後的前驅物組成物層(金屬氧化物層)施以灰化處理的情形還高速蝕刻前驅物組成物層或金屬氧化物層之實施例。
圖22是顯示實施例二中的灰化處理的結果之圖。圖22(a)是顯示對燒成前的前驅物組成物層施以灰化處理的情形下的灰化處理的結果之圖,圖22(b)是顯示對燒成後的前驅物組成物層(金屬氧化物層)施以灰化處理的情形下的灰化處理的結果之圖。
在實施例二中與實施例一的情形一樣,於在Si基板的表面形成SiO2層的絕緣性基板510上,藉由旋塗法塗佈TiO2的溶膠-凝膠溶液形成前驅物組成物層520,然後以在熱板上以200℃將形成有前驅物組成物層520的絕緣性基板乾燥了5分鐘之物當作試樣(試樣1)使用。而且,以藉由RTA裝置以600℃對試樣1進行熱處理而燒成之物當作試樣(試樣2)使用。
然後,在試樣1及試樣2的表面局部地貼附耐熱性絕緣帶M20後,以與實施例一中的灰化條件3一樣的條件(一邊使反應性氣體(CF4氣體:流量0.05L/分)及Ar氣體(流量0.05L/分)與載體氣體(He氣體:流量9L/分)一起流過,一邊施以灰化處理的條件)對試樣1及試樣2施以灰化處理。
然後,針對試樣1及試樣2的兩方,由前驅物組成物層520的表面將耐熱性絕緣帶M20剝離後,使用KLA-Tencor股份有限公司製的階規[Alpha Step-500],測定了距前驅物組成物層520的表面的蝕刻量。
其結果如圖22所示得知,在對燒成前的前驅物組成物層施以灰化處理的情形(參照圖22(a))下,能以比對燒成後的前驅物組成物層(金屬氧化物層)施以灰化處理的情形(參照圖22(b))還高速蝕刻除去前驅物組成物層或金屬氧化物層。
[實施例三]
實施例三是顯示在對包含殘膜的前驅物組成物層施以規定的灰化處理的情形下,可完全除去該殘膜之實施例。
圖23是用以說明實施例三中的評價方法而顯示之圖。圖23(a)~圖23(d)是顯示其程序之圖。圖24是顯示實施例三中的灰化處理的結果(AFM(原子力顯微鏡(Atomic Force Microscopy)影像或SPM(掃描探針顯微鏡(Scanning Probe Microscope)影像)之圖。圖24(a)是顯示利用掃描探針顯微鏡(AFM或SPM)得到的施以灰化處理後的試樣表面的三維影像之圖,圖24(b)是顯示其剖面影像之圖。圖25是顯示實施例三中的灰化處理的結果(I-V特性)之圖。圖25中符號A是表示測定例1中的I-V特性,符號B是表示測定例2中的I-V特性。
在實施例三中,於在Si基板612的表面形成Pt層614的基板610上,藉由旋塗法塗佈TiO2的MOD溶液(0.4mol)(2000rpm、30秒)形成前驅物組成物層620,以在150℃的熱板上將形成有前驅物組成物層620的基板610乾燥了5分鐘之物當作試樣而使用(參照圖23(a))。基板610的尺寸、形狀例如使用縱20mm×橫20mm×高度0.7mm的長方體。
然後,藉由使用在10mm×10mm的正方形狀的中央部,縱3μm×橫3μm×高低差200nm的9個正方形凹圖案以縱橫10μm間距配置成3行3列的矩陣狀的凹凸模,對前驅物組成物層620施以壓花加工(80℃→200℃→80℃、10MPa、5分),形成了在前驅物組成物層620包含殘膜622的壓花構造(參照圖23(b))。
然後,藉由對形成有壓花構造的前驅物組成物層620施以利用大氣壓電漿的灰化處理(輸出300W、時間3分、灰化氣體:He+Ar+CF4)處理了殘膜(參照圖23(c))。
然後,使用SII NanoTechnology股份有限公司製的掃描探針顯微鏡[S-Image],取得了試樣的表面的三維影像及其剖面影像。而且,搭配組合圖23(d)所示的I-V測定系測定了I-V特性。
其結果由圖24得知,可形成寬3μm、高度170nm的美麗的圖案。而且由圖24得知,在測定例1(參照符號A)中因只流過極小的電流,故前驅物組成物層620具有高的絕緣性(參照圖25)。而且,在測定例2(參照符號B)中因流過極大的電流,故暗示了藉由施以灰化處理使得殘膜622被由存在殘膜622的區域630乾淨地除去(參照圖25)。
以上雖然是根據上述的實施形態說明了本發明,但是本發明不是被限定於該等實施形態,在不脫離其要旨的範圍中可實施,例如如以下的變形也可能。
(1)、在上述實施形態一~四、六及七中是藉由對包含[在各個殘膜形成區域內連續的殘膜]的前驅物組成物層施以灰化處理完全除去殘膜。而且,在上述實施形態五中是藉由對包含[在各個殘膜形成區域內連續的殘膜]的前驅物組成物層施以灰化處理,使殘膜變薄直到成為藉由實施第五製程而使殘膜採取海島構造的薄度。但是,本發明不是被限定於此。
圖26是用以說明與變形例有關的壓花構造體的製造方法而顯示之圖。圖26(a)是正以第四製程對前驅物組成物層20施以灰化處理的時候的前驅物組成物層20的剖面圖,圖26(b)是剛以第四製程對前驅物組成物層20施以灰化處理後的前驅物組成物層20的剖面圖,圖26(c)是藉由以第五製程對前驅物組成物層20進行熱處理而形成的壓花構造體30的剖面圖。
在與變形例有關的壓花構造體的製造方法中,如圖26(a)所示,在第三製程中形成包含[在各個殘膜形成區域內不連續的殘膜(例如採取海島構造28的膜)]的壓花構造,並且(參照圖26(a))在第四製程中藉由對前驅物組成物層20施以灰化處理而完全除去上述殘膜也可以(參照圖26(a)~圖26(c))。
(2)、在上述實施形態八中雖然是以薄膜電晶體為例說明了本發明,在上述實施形態九中雖然是以壓電式噴墨頭為例說明了本發明,但是本發明不是被限定於此。例如本發明也能在製造如下的構件時適用:具備第一電極層、介電質層、第二電極層及配線層的薄膜電容器;具備壓電層、電極層及配線層的致動器;在基材上具備晶格層(金屬氧化物層或金屬層)的光學元件(例如反射型偏光板、繞射光柵(diffraction grating)等)等。In the method for producing an embossed structure of the present invention, a thin film transistor, a film capacitor, an actuator, a piezoelectric ink jet head, and an optical element, the method for producing an embossed structure of the present invention, a thin film transistor The piezoelectric ink jet head will be described based on the embodiment of the drawings. Embodiments 1 to 7 are embodiments of a method for producing an embossed structure of the present invention, and Embodiment 8 relates to an embodiment of a thin film transistor of the present invention, and Embodiment 9 relates to a piezoelectric inkjet head of the present invention. The embodiment.
[Embodiment 1]
Fig. 1 is a view for explaining a method of manufacturing an embossed structure according to the first embodiment. Fig. 1(a) to Fig. 1(g) are diagrams of the respective processes. Further, the symbol P in Fig. 1 denotes plasma.
A method for producing an embossed structure according to the first embodiment includes a process of preparing a liquid material containing a metal compound and forming a metal oxide or a metal by heat treatment as shown in FIG. 1; a second process for forming a precursor composition layer 20 composed of a metal oxide or a metal precursor composition by coating a liquid material on the substrate 10 (refer to FIGS. 1(a) and 1(b)); The preliminary heating process for reducing the fluidity of the precursor composition layer 20 in advance by heating the precursor composition layer 20 to a temperature (for example, 150 ° C) in the range of 80 ° C to 200 ° C (refer to FIG. 1 (c)) By heating the precursor composition layer 20 to a temperature (for example, 150 ° C) in the range of 80 ° C to 300 ° C, and using heating to a temperature in the range of 80 ° C to 300 ° C (for example) The concave-convex mold M1 of 150 ° C) is subjected to embossing to the precursor composition layer 20 to form a third process of the embossed structure including the residual film 22 in the precursor composition layer 20 (refer to FIG. 1( d )); The ashing using the atmospheric piezoelectric slurry is applied to the precursor composition layer 20 formed with the embossed structure The fourth process of processing the residual film 22 (refer to FIG. 1(e) and FIG. 1(f)); by the heat treatment of the precursor composition layer 20, the precursor composition layer 20 formed with the embossed structure A fifth process of forming the embossed structure 30 made of a metal oxide or a metal (see FIG. 1(g)).
In the method for producing an embossed structure according to the first embodiment, a liquid material (for example, a metal alkoxide-containing sol-gel solution containing a metal-containing compound and being heat-treated to form a metal oxide or a metal is used. ], [MOD (Metal Organic Decomposition) solution containing an organometallic compound], [metal salt solution containing a metal salt (for example, metal chloride, metal oxychloride, metal nitrate, metal acetate, etc.) ], [mixing the above sol-gel solution, a solution of at least two of the above MOD solution and the above metal salt solution], and the like as a liquid material.
In the method of manufacturing an embossed structure according to the first embodiment, since the precursor composition layer 20 is embossed by using the concave-convex mold M1 in the third process, the precursor is as shown in Fig. 1(d). The composition layer 20 is formed with an embossed structure including the residual film 22. Therefore, the residual film 22 is treated by subjecting the precursor composition layer 20 to ashing treatment using the atmospheric piezoelectric slurry in the fourth process. Specifically, as shown in FIG. 1(e) and FIG. 1(f), the residual film 22 is completely removed.
In the method for producing an embossed structure according to the first embodiment, the fourth process is carried out using a reactive gas (for example, [halogen-containing gas], [halogen-containing gas and mixed gas containing Ar gas], etc.). In this case, a halogen-containing gas can be suitably used for various fluorine-containing gases, chlorine-containing gases, bromine-containing gases, and the like.
By this method, the residual film can be completely removed, [the embossed structure without the influence of the residual film, that is, the embossed structure having the structure split by the portion where the residual film exists). As a result, in the fifth process, as the precursor composition layer is split into individual small regions, the precursor composition layer can be contracted in the in-plane direction without being reluctantly, so that the desired embossing can be formed with high precision. structure.
The method of completely removing the residual film is a method of applying the first time calculated by the relationship between the etching rate of the precursor composition layer and the thickness of the residual film by ashing by ashing (by time management) Ashing method)].
According to the method of manufacturing an embossed structure according to the first embodiment, the precursor composition layer can be formed by applying a liquid material on the substrate to form an embossed structure by embossing the precursor composition layer. Further, the embossed structure is formed by heat-treating the precursor composition layer at a high temperature, and the embossing process can be performed by using a mold having a fine pattern of a submicron order to form a submicron-sized fine Since the embossed structure of the pattern is used, it is possible to use various materials and manufacturing energy which are much smaller than the conventional ones, and to manufacture various functional elements including the above-mentioned excellent thin film transistors, which are shorter than the conventional ones.
Further, according to the method for producing an embossed structure according to the first embodiment, since the fourth process of treating the residual film by subjecting the precursor composition layer to ashing treatment is further included, the effect of the residual film can be formed. The embossed structure.
Further, according to the method for producing an embossed structure according to the first embodiment, since the ashing treatment using the atmospheric piezoelectric slurry is applied to the precursor composition layer, there is no need for a high vacuum environment in the fourth process, so It requires expensive high vacuum equipment and can reduce the time required to implement the fourth process.
Further, according to the method for producing an embossed structure according to the first embodiment, since the fourth process is to be performed using the reactive gas, the ashing process can be performed at a high etching rate, and the embossing can be performed with high productivity. Construct.
Further, according to the method for producing an embossed structure according to the first embodiment, it is intended to reduce the curing reaction of the precursor composition layer to some extent by heating to a temperature in the range of 80 ° C to 200 ° C. The fluidity of the precursor composition layer, and the precursor composition layer obtained by lowering the hardness of the precursor composition layer by heating to a temperature in the range of 80 ° C to 300 ° C to obtain high plastic deformation ability Since embossing is performed, the desired embossed structure can be formed with high precision, and as a result, an embossed structure having desired properties can be produced.
Further, according to the method for producing an embossed structure according to the first embodiment, the precursor composition layer is subjected to embossing by using a mold heated to a temperature in the range of 80 ° C to 300 ° C. When embossing is performed, the plastic deformation ability of the precursor composition layer is not lowered, so that the desired embossed structure can be formed with higher precision.
[Embodiment 2]
Fig. 2 is a view for explaining the method of manufacturing the embossed structure according to the second embodiment. 2(a) is a cross-sectional view of the precursor composition layer 20 when the precursor composition layer 20 is subjected to ashing treatment in the fourth process, and FIG. 2(b) is a composition of the precursor just after the fourth process. The material layer 20 is subjected to a cross-sectional view of the precursor composition layer 20 after the ashing treatment.
The manufacturing method of the embossed structure according to the second embodiment basically includes the same process as the method of manufacturing the embossed structure according to the first embodiment, but the contents of the fourth process and the embossing structure relating to the first embodiment The manufacturing method of the body is different. That is, in the manufacturing method of the embossed structure relating to the second embodiment, as shown in FIG. 2, in the fourth process, the ashing is performed more than the precursor composition layer by the ashing treatment. The relationship between the etching rate and the thickness of the residual film 22 is calculated as the first time. As a result, in the method of manufacturing the embossed structure according to the second embodiment, the concave portion 24 is formed on the base material 10 as shown in Fig. 2(b).
As described above, in the method of manufacturing the embossed structure according to the second embodiment, the content of the fourth process is different from that of the embossed structure according to the first embodiment, but the pressure is related to the first embodiment. In the same manner as in the production method of the flower structure, the fourth process of treating the residual film by subjecting the precursor composition layer to ashing treatment can form an embossed structure without the influence of the residual film. Moreover, since the ashing treatment using the atmospheric piezoelectric slurry is applied to the precursor composition layer, the high-vacuum environment is not required in the implementation of the fourth process, so that expensive high-vacuum equipment can be eliminated, and the fourth process can be shortened. The time required.
Further, the method of manufacturing the embossed structure according to the second embodiment has the same contents as those of the method of manufacturing the embossed structure according to the first embodiment except for the fourth process, and therefore has the first embodiment. The corresponding effect among the effects of the manufacturing method of the embossed structure.
[Embodiment 3]
Fig. 3 is a view for explaining the method of manufacturing the embossed structure according to the third embodiment. Fig. 3(a) is a cross-sectional view of the precursor composition layer 20 when the precursor composition layer 20 is subjected to ashing treatment in the fourth process, and Fig. 3(b) is a composition of the precursor just after the fourth process. The material layer 20 is subjected to a cross-sectional view of the precursor composition layer 20 after the ashing treatment.
The method for producing an embossed structure according to the third embodiment basically includes the same process as the method for producing the embossed structure according to the first embodiment, but the contents of the fourth process and the embossed structure relating to the first embodiment The manufacturing method of the body is different. That is, in the method of manufacturing the embossed structure according to the third embodiment, as shown in Fig. 3, the substrate 10a is made of a material which is an etch stop layer, and the ashing is exceeded by The ashing process is performed for the first time period in which the relationship between the etching rate of the precursor composition layer and the thickness of the residual film 22 is calculated.
As described above, in the method of manufacturing the embossed structure according to the third embodiment, the content of the fourth process is different from that of the embossed structure according to the first embodiment, but the pressure is related to the first embodiment. In the same manner as in the production method of the flower structure, the fourth process of treating the residual film by subjecting the precursor composition layer to ashing treatment can form an embossed structure without the influence of the residual film. Moreover, since the ashing treatment using the atmospheric piezoelectric slurry is applied to the precursor composition layer, the high-vacuum environment is not required in the implementation of the fourth process, so that expensive high-vacuum equipment can be eliminated, and the fourth process can be shortened. The time required.
Further, according to the method for producing an embossed structure according to the third embodiment, although the ashing is performed under the condition of so-called over-etching, the method of manufacturing the embossed structure according to the second embodiment is different. As shown in FIG. 3(b), a concave portion is not formed in the substrate 10a.
Further, the method of manufacturing the embossed structure according to the third embodiment has the same contents as the method of manufacturing the embossed structure according to the first embodiment except for the fourth process, and therefore has the first embodiment. The corresponding effect among the effects of the manufacturing method of the embossed structure.
[Embodiment 4]
Fig. 4 is a view for explaining the method of manufacturing the embossed structure according to the fourth embodiment. 4(a) is a cross-sectional view of the precursor composition layer 20 when the precursor composition layer 20 is subjected to ashing treatment in the fourth process, and FIG. 4(b) is a composition of the precursor just after the fourth process. The material layer 20 is subjected to a cross-sectional view of the precursor composition layer 20 after the ashing treatment.
The manufacturing method of the embossed structure according to the fourth embodiment basically includes the same process as the method of manufacturing the embossed structure according to the first embodiment, but the contents of the fourth process and the embossing structure relating to the first embodiment are basically the same. The manufacturing method of the body is different. In other words, in the method of manufacturing the embossed structure according to the fourth embodiment, as the substrate shown in Fig. 4, a substrate having the layer 14 made of a material which is an etching stopper layer on the surface of the first substrate 12 is used. 10b, and the ashing time is calculated to be longer than the first time calculated by the relationship between the etching rate of the precursor composition layer by the ashing treatment and the thickness of the residual film 22.
As described above, in the method of manufacturing the embossed structure according to the fourth embodiment, the content of the fourth process is different from that of the embossed structure according to the first embodiment, but the pressure is related to the first embodiment. In the same manner as in the production method of the flower structure, the fourth process of treating the residual film by subjecting the precursor composition layer to ashing treatment can form an embossed structure without the influence of the residual film. Moreover, since the ashing treatment using the atmospheric piezoelectric slurry is applied to the precursor composition layer, the high-vacuum environment is not required in the implementation of the fourth process, so that expensive high-vacuum equipment can be eliminated, and the fourth process can be shortened. The time required.
Further, in the method of manufacturing the embossed structure according to the fourth embodiment, as in the case of the method of manufacturing the embossed structure according to the third embodiment, the ashing is performed under the condition of so-called over-etching. However, as shown in FIG. 4(b), a concave portion is not formed in the base material 10b.
Further, since the method of manufacturing the embossed structure according to the fourth embodiment is the same as the method of manufacturing the embossed structure according to the first embodiment except for the fourth process, it is related to the first embodiment. The corresponding effect among the effects of the manufacturing method of the embossed structure.
[Embodiment 5]
Fig. 5 is a view for explaining the method of manufacturing the embossed structure according to the fifth embodiment. Fig. 5(a) is a cross-sectional view of the precursor composition layer 20 when the precursor composition layer 20 is subjected to ashing treatment in the fourth process, and Fig. 5(b) is a composition of the precursor just after the fourth process. The material layer 20 is subjected to a cross-sectional view of the precursor composition layer 20 after the ashing treatment, and FIG. 5(c) is a cross section of the embossed structure 30 formed by heat-treating the precursor composition layer 20 in the fifth process. Figure. In addition, in FIG. 5, in order to make the sea-island structure 28 mentioned later easy to see, it is enlarged by the figure in FIG.
The manufacturing method of the embossed structure according to the fifth embodiment basically includes the same process as the method of manufacturing the embossed structure according to the first embodiment, but the content of the fourth process and the embossing structure related to the first embodiment The manufacturing method of the body is different. That is, in the method of manufacturing the embossed structure according to the fifth embodiment, as shown in FIG. 5, in the fourth process, the residual film 22 is intended to be thinned until it becomes the fifth by performing the fourth process. The process allows the residual film to take the thinness of the island structure 28.
As described above, in the method of manufacturing the embossed structure according to the fifth embodiment, the content of the fourth process is different from that of the embossed structure according to the first embodiment, but the pressure is related to the first embodiment. In the same manner as in the production method of the flower structure, the fourth process of treating the residual film by subjecting the precursor composition layer to ashing treatment can form an embossed structure without the influence of the residual film. Moreover, since the ashing treatment using the atmospheric piezoelectric slurry is applied to the precursor composition layer, the high-vacuum environment is not required in the implementation of the fourth process, so that expensive high-vacuum equipment can be eliminated, and the fourth process can be shortened. The time required.
Further, in the method of manufacturing an embossed structure according to the fifth embodiment, since the residual film adopts the sea-island structure 28 after the end of the fifth process, even if the residual film is not completely removed at the end of the fourth process, An embossed structure capable of forming an effect without a residual film.
Further, the method of manufacturing the embossed structure according to the fifth embodiment has the same contents as those of the method of manufacturing the embossed structure according to the first embodiment except for the fourth process, and therefore has the first embodiment. The corresponding effect among the effects of the manufacturing method of the embossed structure.
[Embodiment 6]
Fig. 6 is a view for explaining the display of the ashing apparatus 40 used in the sixth embodiment. Fig. 7 is a view for explaining the method of manufacturing the embossed structure according to the sixth embodiment. Fig. 7(a) is a cross-sectional view of the precursor composition layer 20 immediately before the ashing treatment of the precursor composition layer 20 by the fourth process, and Fig. 7(b) is the composition of the precursor just after the fourth process. The material layer 20 is subjected to a cross-sectional view of the precursor composition layer 20 after the ashing treatment. Further, reference numeral 41 in Fig. 6 denotes one electrode, and reference numeral 43 denotes an electrode on the other side. Further, in Fig. 7, in order to make the side etching look easy, it is displayed more enlarged than in Fig. 5.
The method for producing an embossed structure according to the sixth embodiment basically includes the same process as the method for producing an embossed structure according to the first embodiment. Further, as shown in FIG. 6, it is intended to carry out the fourth process by applying ashing treatment to the precursor composition layer by using the ashing apparatus 40 (atmospheric piezoelectric ashing apparatus).
As described above, the method of manufacturing the embossed structure according to the sixth embodiment includes the ashing treatment of the precursor composition layer as in the case of the method of manufacturing the embossed structure according to the first embodiment. The fourth process of the residual film can form an embossed structure without the influence of the residual film. Moreover, since the ashing treatment using the atmospheric piezoelectric slurry is applied to the precursor composition layer, the high-vacuum environment is not required in the implementation of the fourth process, so that expensive high-vacuum equipment can be eliminated, and the fourth process can be shortened. The time required.
Further, in the method of manufacturing an embossed structure according to the sixth embodiment, the average free path of the ashing gas is shortened and the fourth is applied to the precursor composition layer by the ashing treatment using the atmospheric piezoelectric slurry. Lateral etching occurs in the process (see Fig. 7), so it is preferable to design the pattern of the concave-convex mold in consideration of this factor. This point is also the same as the method of manufacturing the embossed structure according to the first to fifth embodiments.
[Embodiment 7]
Fig. 8 is a view for explaining the display of the ashing apparatus 40a used in the seventh embodiment. Fig. 9 is a view for explaining the method of manufacturing the embossed structure according to the seventh embodiment. Figure 9(a) is a cross-sectional view of the precursor composition layer 20 immediately before the ashing treatment of the precursor composition layer 20 by the fourth process, and Figure 9(b) is the composition of the precursor just after the fourth process. The material layer 20 is subjected to a cross-sectional view of the precursor composition layer 20 after the ashing treatment. Further, reference numeral 42 in Fig. 8 denotes a positive electrode, and reference numeral 44 denotes a negative electrode.
The method for producing an embossed structure according to the seventh embodiment basically includes the same process as the method for producing the embossed structure according to the sixth embodiment, but the content of the fourth process and the embossed structure relating to the sixth embodiment are basically the same. The manufacturing method of the body is different. That is, in the manufacturing method of the embossed structure relating to the seventh embodiment, as shown in FIG. 8, in the fourth process, the precursor is intended to be used by using the ashing device 40a (low-pressure plasma ashing device). The composition layer 20 is subjected to a fourth process by applying ashing treatment using low-pressure plasma. In the method for producing an embossed structure according to the seventh embodiment, for example, ashing treatment using low-pressure plasma is performed under a pressure condition of 1 Pa to 1000 Pa (preferably 10 Pa to 100 Pa). Further, in the method of manufacturing an embossed structure according to the seventh embodiment, the fourth process is carried out under the condition that a bias voltage is applied as shown in FIG.
In the method of manufacturing the embossed structure according to the seventh embodiment, the content of the fourth process is different from that of the embossed structure according to the sixth embodiment, but the pressure is related to the sixth embodiment. In the same manner as in the production method of the flower structure, the fourth process of treating the residual film by subjecting the precursor composition layer to ashing treatment further forms an embossed structure having no residual film influence. Further, since the fourth process is performed in a state where a bias voltage is applied, the collision energy of the ashing gas becomes high, so that the ashing process can be performed at a high etching rate, and the ashing process can be manufactured with high productivity. Embossed structure.
Further, according to the method for producing an embossed structure according to the seventh embodiment, the following effects can be obtained. That is, according to the manufacturing method of the embossed structure relating to the seventh embodiment, the average free path of the gas (ashing gas) used for ashing is longer than that under atmospheric pressure, and the flying direction of the ashing gas is in one direction. Consistently, as shown in FIG. 9, the ratio of etching (lateral etching) to the side portion of the embossed structure can be reduced, and an embossed structure having high shape accuracy can be manufactured. Further, since a stable glow discharge can be generated even in a state where a bias voltage is applied, the ashing process can be stably performed at a high etching rate, and the embossed structure can be stably produced with high productivity. Further, since the reaction product generated by the reaction between the precursor composition layer and the reactive gas is volatilized and easily removed, the ashing process can be stably performed at a high etching rate from this viewpoint, and further The embossed structure can be stably produced with high productivity.
In addition, the method of manufacturing the embossed structure according to the seventh embodiment is the same as the case of the method of manufacturing the embossed structure according to the sixth embodiment except for the fourth process. The corresponding effect among the effects of the manufacturing method of the embossed structure.
[Embodiment 8]
1. Thin film transistor 100 related to embodiment VIII
Fig. 10 is a view for explaining the film transistor 100 according to the eighth embodiment. Fig. 10(a) is a plan view of the thin film transistor 100, Fig. 10(b) is a cross-sectional view taken along line A1-A1 of Fig. 10(a), and Fig. 10(c) is a cross-sectional view taken along line A2-A2 of Fig. 10(a).
The thin film transistor 100 according to the eighth embodiment includes, as shown in FIGS. 10(a) and 10(b), an oxide conductor layer 140 including a source region 144 and a drain region 146 and a channel region 142; and a control channel region. a gate electrode 120 of an on state of 142; a gate insulating layer 130 formed of a ferroelectric material formed between the gate electrode 120 and the channel region 142. The layer thickness of the channel region 142 is thinner than the layer thickness of the source region 144 and the layer thickness of the drain region 146. The layer thickness of the channel region 142 is preferably 1/2 or less of the layer thickness of the source region 144 and the layer thickness of the drain region 146. As shown in FIGS. 10(a) and 10(c), the gate electrode 120 is connected to a gate pad 122 exposed to the outside through a through hole 150.
In the thin film transistor 100 according to the eighth embodiment, the oxide conductor layer 140 is formed using an embossing technique.
In the thin film transistor 100 according to the eighth embodiment, the carrier concentration and the layer thickness of the channel region 142 are set to a value at which the channel region 142 is depleted when a control voltage of OFF is applied to the gate electrode 120. . Specifically, the carrier concentration of the channel region 142 is located at 1×10. 15 Cm -3 ~1×10 twenty one Cm -3 Within the range of the channel region 142, the layer thickness is in the range of 5 nm to 100 nm.
Further, in the thin film transistor 100 according to the eighth embodiment, the layer thickness of the source region 144 and the drain region 146 is in the range of 50 nm to 1000 nm.
The oxide conductor layer 140 is composed of, for example, indium tin oxide (ITO), and the gate insulating layer 130 is, for example, PZT (Pb (Zr) x , Ti 1-x )O 3 The gate electrode 120 is composed of, for example, lanthanum nickelate (LNO(LaNiO) 3 )) The insulating substrate 110 which is a solid substrate is interposed, for example, by SiO on the surface of the Si substrate. 2 The layer and the Ti layer form an insulating substrate of an STO (SrTiO) layer.
2. A method of manufacturing a thin film transistor related to the eighth embodiment
The thin film transistor 100 according to the eighth embodiment can be produced by the method for producing a thin film transistor described below. The following is described in the order of the process.
11 to 13 are views for explaining the method of manufacturing the thin film transistor according to the eighth embodiment. 11(a) to 11(f), 12(a) to 12(f), and Figs. 13(a) to 13(e) are diagrams of the respective processes. Further, the map shown on the left side in each of the process maps is a map corresponding to FIG. 10(b), and the graph shown on the right side is a map corresponding to FIG. 10(c).
(1) Formation of gate electrode 120
First, the preparation is made of a metal oxide ceramic by heat treatment (m e t a l o x i d e c e r a m i c a functional liquid material of a functional solid material composed of s) (barium strontium) (first process). Specifically, a solution containing a metal inorganic salt (lanthanum nitrate (hexahydrate) and nickel acetate (tetrahydrate)) was prepared (solvent: 2) 2-methoxyethanol).
Next, as shown in FIGS. 11( a ) and 11 ( b ), a functional liquid material (for example, 500 rpm, 25 seconds) is applied to one surface of the insulating substrate 110 by a spin coating method. Then, the insulating substrate 110 was placed on a hot plate and dried at 60 ° C for 1 minute to form a precursor composition layer 120' of strontium nickelate (layer thickness: 300 nm) (second process).
Next, as shown in FIGS. 11(c) and 11(d), the concave-convex mold M2 (having a height difference of 300 nm) formed by using the region corresponding to the gate electrode layer 120 and the gate pad 122 is used, and the precursor is 150 ° C. The composition layer 120' is subjected to embossing, and an embossed structure is formed in the precursor composition layer 120' (the layer thickness of the convex portion is 300 nm, and the layer thickness of the concave portion is 50 nm) (third process). The pressure applied to the embossing process was 5 MPa. According to this, since the embossing process is performed on the precursor composition layer which is obtained by heating to the second temperature in the range of 80 ° C to 300 ° C to obtain high plastic deformation ability, the formation can be performed with high precision. The embossed structure required.
Next, by performing the overall ashing treatment on the precursor composition layer 120', as shown in FIG. 11(e), the residual film 120'z existing in the region other than the region corresponding to the gate electrode layer 120 is completely removed (fourth Process). The fourth process is performed using a wet etching apparatus.
Finally, the precursor composition layer 120' is heat-treated at a high temperature (650 ° C, 10 minutes) by using an RTA (Rapid Thermal Annealing) apparatus, as shown in FIG. 11(f), composed of a precursor. The object layer 120' forms a gate electrode 120 and a gate pad 122 composed of a functional solid material layer (barium nickelate) (fifth process).
(2) Formation of the gate insulating layer 130
First, a functional liquid material which becomes a functional solid material composed of a metal oxide ceramic (PZT) by heat treatment is prepared. Specifically, a solution containing a metal alkoxide (PZT sol-gel solution manufactured by Mitsubishi Materials Corporation) was prepared as a functional liquid material (first process).
Next, the above functional liquid material (for example, 2000 rpm, 25 seconds) is applied on one surface of the insulating substrate 110 by spin coating three times, and then the insulating substrate 110 is placed on a hot plate. The operation was carried out by drying at 250 ° C for 5 minutes to form a precursor composition layer 130' (layer thickness 300 nm) of a functional solid material (PZT) (second process, see Fig. 12 (a)).
Next, as shown in FIGS. 12(b) and 12(c), the precursor composition layer 130 is formed at 150 ° C by using the concave-convex mold M3 (having a height difference of 300 nm) formed by the region corresponding to the through-hole 150. The embossing process is performed, and the embossing structure corresponding to the through hole 150 is formed in the precursor composition layer 130' (third process). The pressure applied to the embossing process was 5 MPa. According to this, since the embossing process is performed on the precursor composition layer which is obtained by heating to the second temperature in the range of 80 ° C to 300 ° C to obtain high plastic deformation ability, the formation can be performed with high precision. The embossed structure required.
Next, by performing the overall ashing treatment on the precursor composition layer 130', as shown in Fig. 12 (d), the residual film 130'z (fourth process) existing in the region which becomes the channel region 142 later is completely removed. The fourth process uses a low-pressure plasma etching apparatus to introduce a reactive gas (for example, CF) under a pressure of 10 Pa. 4 Gas and Ar gas) are carried out at the same time.
Finally, by using the RTA apparatus and heat-treating the precursor composition layer 130' at a high temperature (650 ° C, 10 minutes), as shown in FIG. 12(e), the precursor composition layer 130' is formed of a functional solid. A gate insulating layer 130 (the fifth process) composed of a material layer (PZT).
(3) Formation of oxide conductor layer 140
First, a functional liquid material (first process) which becomes a functional solid material composed of a metal oxide ceramic (ITO) by heat treatment is prepared. Specifically, a solution containing a metal carboxylate (a functional liquid material (trade name: ITO-05C) manufactured by High Purity Chemical Research Co., Ltd., a stock solution: a diluent) is prepared. =1: 1.5) as a functional liquid material. Further, when the functional liquid material is added, the carrier concentration of the channel region 142 is 1 × 10 when completed. 15 Cm -3 ~1×10 twenty one Cm -3 The concentration of impurities within the range.
Next, as shown in FIG. 12(f), the above-described functional liquid material (for example, 2000 rpm, 25 seconds) is applied by spin coating on one surface of the insulating substrate 110, and then the insulating substrate 110 is placed. It was dried on a hot plate at 150 ° C for 3 minutes to form a precursor composition layer 140' (layer thickness 300 nm) of a functional solid material (ITO) (second process).
Next, as shown in FIGS. 13(a) to 13(c), the concave-convex mold M4 formed by using the region corresponding to the channel region 142 and the region corresponding to the source region 144 and the region corresponding to the gate region 146 is convex. (a height difference of 350 nm), the precursor composition layer 140' is subjected to embossing, and an embossed structure is formed in the precursor composition layer 140' (the layer thickness of the convex portion is 350 nm, and the layer thickness of the concave portion is 100 nm) (third process) ). Accordingly, the layer thickness of the portion of the precursor composition layer 140' that becomes the channel region 142 is thinner than the other portions.
At this time, in the above-described process, it is intended to emboss processing by heating the precursor composition layer 140' to 150 ° C and using a mold heated to 150 ° C. In this case, the pressure at the time of embossing is about 4 MPa.
Further, the concave-convex mold M4 has a structure in which a region corresponding to the element isolation region 160 and the through-hole 150 is more convex than a region corresponding to the channel region 142, and is formed in a region corresponding to the element isolation region 160 and the through-hole 150. There is a residual film 140'z of the precursor composition layer 140' (see Fig. 13(c)).
Next, by performing the overall ashing treatment on the precursor composition layer 140', as shown in FIG. 13(d), the residual film 140'z existing in the region corresponding to the element isolation region 160 and the through hole 150 is completely removed (No. Four processes). The fourth process uses a low-pressure plasma etching apparatus to introduce a reactive gas (for example, CF) under a pressure of 10 Pa. 4 Gas and Ar gas) are carried out at the same time.
Finally, heat treatment was performed on the precursor composition layer 140' (the precursor composition layer 140' was fired on a hot plate at 400 ° C for 10 minutes, and then 650 ° C, 30 minutes using an RTA apparatus. The condition of the first half of the 15 minute oxygen atmosphere and the second half of the 15 minute nitrogen atmosphere heats the precursor composition layer 140' to form the oxide conductor layer 140 including the source region 144, the drain region 146, and the channel region 142 (the first) In the five-process, a thin film transistor 100 according to the eighth embodiment having a bottom gate structure as shown in Fig. 13(e) can be manufactured.
3. The efficacy of the thin film transistor 100 related to the eighth embodiment
According to the thin film transistor 100 according to the eighth embodiment, since the oxide conductive material is used as the material constituting the channel region 142, the carrier concentration can be increased, and since the ferroelectric material is used as the material constituting the gate insulating layer 130, it is possible to The low driving voltage is switched at a high speed, and as a result, as in the case of the conventional thin film transistor 900, a large current can be controlled at a high speed with a low driving voltage.
Further, according to the thin film transistor 100 according to the eighth embodiment, the layer thickness of the channel region 142 is thinner than the layer thickness of the source region 144 and the layer thickness of the drain region 146, and only by using the embossed structure described above. The manufacturing method forms the oxide conductor layer 140 without the influence of the residual film, and the thin film transistor can be manufactured. Therefore, the channel region and the source region can be formed from different materials unlike the conventional thin film transistor 900. In the polar region, a thin film transistor excellent in the above-described manner can be produced by using a material which is much smaller than the conventional materials and manufacturing energy, and which is shorter than the prior art.
Further, according to the thin film transistor 100 according to the eighth embodiment, since the oxide conductor layer 140, the gate electrode 120, and the gate insulating layer 130 are formed without using a high vacuum process, the thin film transistor can be manufactured without using a vacuum process. A film transistor having excellent properties as described above can be produced by using a process much smaller than the conventional production energy and having a process shorter than the prior art.
Further, according to the thin film transistor 100 according to the eighth embodiment, the carrier concentration and the layer thickness of the channel region 142 are set to a value at which the channel region 142 is depleted when a closed control voltage is applied to the gate electrode 120. Therefore, even if the carrier concentration of the oxide conductor layer is increased, the amount of current flowing during shutdown can be sufficiently reduced, and a large current can be controlled with a low driving voltage while maintaining a necessary switching ratio.
[Embodiment 9]
Fig. 14 is a view for explaining the piezoelectric ink jet head 300 according to the ninth embodiment. Fig. 14 (a) is a cross-sectional view of the piezoelectric ink jet head 300, and Figs. 14 (b) and 14 (c) are views showing a state in which the piezoelectric ink jet head 300 discharges ink.
1. The constitution of a piezoelectric inkjet head 300 according to the ninth embodiment
The piezoelectric ink jet head 300 according to the ninth embodiment includes a cavity member 340 as shown in Fig. 14 (a), and a vibration of a piezoelectric element 320 formed on one side of the cavity member 340. The plate 350 is mounted on the other side of the cavity member 340, the nozzle plate 330 having the nozzle hole 332, and the ink chamber 360 defined by the cavity member 340, the vibration plate 350, and the nozzle plate 330. The vibrating plate 350 is provided with an ink supply port 352 that communicates with the ink chamber 360 for supplying ink to the ink chamber 360.
According to the piezoelectric ink jet head 300 according to the ninth embodiment, as shown in Figs. 14(b) and 14(c), the vibrating plate 350 is scratched by applying an appropriate voltage to the piezoelectric element 320. After the ink is supplied to the ink chamber 360 by an ink reservoir (not shown), the diaphragm 350 is deflected downward, and the ink droplets are ejected from the ink chamber 360 through the nozzle holes 332. According to this, it is possible to perform vivid printing on the printed matter.
2. A method of manufacturing a piezoelectric inkjet head according to Embodiment 9
The piezoelectric ink jet head 300 having such a configuration is that the piezoelectric element 320 (the first electrode layer 322, the piezoelectric layer 324, and the second electrode layer 326) and the cavity member 340 are both embossed structures using the present invention. The manufacturing method is formed. Hereinafter, a method of manufacturing the piezoelectric ink jet head 300 according to the ninth embodiment will be described in accordance with a process sequence.
15 to 17 are views for explaining the method of manufacturing the piezoelectric ink jet head according to the ninth embodiment. 15(a) to 15(f), Figs. 16(a) to 16(d), and Figs. 17(a) to 17(e) are diagrams of the respective processes.
(1) Formation of Piezoelectric Element 320
(1-1) Formation of the first electrode layer 322
First, a functional liquid material (first process) which becomes a functional solid material composed of a metal oxide ceramic (barium nickel hydride) by heat treatment is prepared. Specifically, a solution containing a metal inorganic salt (cerium nitrate (hexahydrate) and nickel acetate (tetrahydrate)) (solvent: 2-methoxyethanol) was prepared.
Next, as shown in FIG. 15(a), a functional liquid material (for example, 500 rpm, 25 seconds) is applied to one surface of a dummy substrate 310 by spin coating, and then the dummy substrate 310 is placed. It was dried on a hot plate at 60 ° C for 1 minute to form a precursor composition layer 322' (layer thickness 300 nm) of a functional solid material (barium strontium) (second process).
Next, as shown in Fig. 15 (b), the precursor composition layer 322' is pressed at 150 ° C by using the concave-convex mold M8 (having a height difference of 300 nm) which is formed by recessing the region corresponding to the first electrode layer 322. In the flower processing, an embossed structure was formed in the precursor composition layer 322' (the layer thickness of the convex portion was 300 nm, and the layer thickness of the concave portion was 50 nm) (third process). The pressure applied to the embossing process was 5 MPa.
Next, by performing the overall ashing treatment on the precursor composition layer 322', as shown in FIG. 15(c), the residual film existing in the region other than the region corresponding to the first electrode layer 322 is completely removed (fourth process) . The fourth process is performed using a wet etching apparatus.
Finally, by using the RTA apparatus and heat-treating the precursor composition layer 322' at a high temperature (650 ° C, 10 minutes), as shown in FIG. 15(d), the precursor composition layer 322' is formed of a functional solid. A first electrode layer 322 composed of a material layer (barium nickelate) (fifth process).
(1-2) Formation of piezoelectric layer 324
First, a functional liquid material (first process) which becomes a functional solid material composed of a metal oxide ceramic (PZT) by heat treatment is prepared. Specifically, a solution containing a metal alkoxide (PZT sol-gel solution manufactured by Mitsubishi Materials Corporation) was prepared as a functional liquid material (first process).
Next, as shown in FIG. 15(e), the above-described functional liquid material is applied by spin coating on one surface of the dummy substrate 310, and then the dummy substrate 310 is placed on a hot plate at 250 ° C. It is dried for 5 minutes to form a precursor composition layer 324' of a functional solid material (PZT) (for example, a layer thickness of 1 μm to 10 μm) (second process).
Next, as shown in Fig. 15 (f), the precursor composition layer 324' is embossed by using the concave-convex mold M9 (having a height difference of 500 nm) formed by the concave portion corresponding to the region of the piezoelectric layer 324. The precursor composition layer 324' forms an embossed structure (for example, a layer thickness of the convex portion is 1 μm to 10 μm, and a layer thickness of the concave portion is 50 nm) (third process).
At this time, in the above-described process, the precursor composition layer 324' was heated to 150 ° C, and embossing was performed using a mold heated to 150 ° C. The pressure at the time of embossing is about 4 MPa.
Next, by performing overall ashing treatment on the precursor composition layer 324', as shown in Fig. 15(g), the residual film existing in the region other than the region corresponding to the piezoelectric layer 324 is completely removed (fourth process). The fourth process uses a low-pressure plasma etching apparatus to introduce a reactive gas (for example, CF) under a pressure of 10 Pa. 4 Gas and Ar gas) are carried out at the same time.
Finally, by using the RTA apparatus and heat-treating the precursor composition layer 324' at a high temperature (650 ° C, 10 minutes), as shown in FIG. 15 (h), the precursor composition layer 324' is formed of a functional solid. Piezoelectric layer 324 composed of a material layer (PZT) (fifth process).
(1-3), formation of the second electrode layer 326
First, a functional liquid material (first process) which becomes a functional solid material composed of a metal oxide ceramic (barium nickel hydride) by heat treatment is prepared. Specifically, a solution containing a metal inorganic salt (cerium nitrate (hexahydrate) and nickel acetate (tetrahydrate)) (solvent: 2-methoxyethanol) was prepared.
Next, as shown in FIG. 16(a), a functional liquid material (for example, 500 rpm, 25 seconds) is applied on one surface of the dummy substrate 310 by spin coating, and then the dummy substrate 310 is placed on the hot plate. The film was dried at 60 ° C for 1 minute to form a precursor composition layer 326' (layer thickness 300 nm) of a functional solid material (barium nickelate) (second process).
Next, as shown in Fig. 16 (b), the precursor composition layer 326' is pressed at 150 ° C by using the concave-convex mold M10 (having a height difference of 300 nm) which is formed by recessing the region corresponding to the second electrode layer 326. In the flower processing, an embossed structure was formed in the precursor composition layer 326' (the layer thickness of the convex portion was 300 nm, and the layer thickness of the concave portion was 50 nm) (third process). The pressure applied to the embossing process was 5 MPa.
Next, by performing overall ashing treatment on the precursor composition layer 326', as shown in FIG. 16(c), the residual film existing in the region other than the region corresponding to the second electrode layer 326 is completely removed (fourth process) . The fourth process is performed using a wet etching apparatus.
Finally, by using an RTA apparatus and heat-treating the precursor composition layer 326' at a high temperature (650 ° C, 10 minutes), as shown in FIG. 16(d), the precursor composition layer 326' is formed of a functional solid. A second electrode layer 326 of a material layer (barium nickelate) (fifth process). Accordingly, the piezoelectric element 320 composed of the first electrode layer 322, the piezoelectric layer 324, and the second electrode layer 326 is completed.
(2) The bonding of the vibration plate 350 and the piezoelectric element 320
As shown in FIG. 16(e), the vibrating plate 350 having the ink supply port 352 is bonded to the piezoelectric element 320 by using an adhesive.
(3) Formation of the cavity member 340
First, a functional liquid material (first process) which becomes a metal oxide ceramic (quartz glass) by heat treatment is prepared. Specifically, the preparation contains a metal alkoxide (isopropyl silicate (Si (OC) 3 H 7 ) 4 The solution is treated as a functional liquid material.
Next, as shown in Fig. 17 (a), the above-described functional liquid material is applied by spin coating on one surface of the vibrating plate 350, and then placed at 150 ° C by placing the dummy substrate 310 on a hot plate. It is dried for 5 minutes to form a precursor composition layer 340' of a functional solid material (quartz glass) (for example, a layer thickness of 10 μm to 20 μm) (second process).
Next, as shown in Fig. 17 (b), the precursor composition layer 340' is subjected to embossing by using the concave-convex mold M11 having a shape corresponding to the ink chamber 360 or the like, and is formed in the precursor composition layer 340'. The embossed structure (for example, the layer thickness of the convex portion is 10 μm to 20 μm, and the layer thickness of the concave portion is 50 nm) (third process).
At this time, in the above-described process, the precursor composition layer 340' was heated to 150 ° C, and embossing was performed using a mold heated to 150 ° C. The pressure at the time of embossing is about 4 MPa.
Next, by performing the overall ashing treatment on the precursor composition layer 340', as shown in Fig. 17 (c), the residual film existing in the region other than the region where the cavity member 340 is formed is completely removed (fourth process). The fourth process uses an atmospheric piezoelectric slurry etching apparatus to introduce a reactive gas (for example, CF) under atmospheric pressure. 4 Gas and Ar gas) are carried out at the same time.
Finally, by using the RTA apparatus and heat-treating the precursor composition layer 340' at a high temperature (650 ° C, 10 minutes), as shown in FIG. 17(d), the precursor composition layer 340' is formed of a functional solid. A cavity member 340 of a material layer (quartz glass).
(4) The fitting of the cavity member 340 and the nozzle plate 330
As shown in Fig. 17 (e), the cavity member 340 is attached to the nozzle plate 330 having the nozzle holes 332 using an adhesive.
(5), the removal of the virtual substrate 310
As shown in FIG. 17(f), the dummy substrate 310 is removed by the piezoelectric element 320. According to this, the piezoelectric ink jet head 300 according to the ninth embodiment is completed.
3. The efficacy of the piezoelectric inkjet head 300 related to the ninth embodiment
According to the piezoelectric ink jet head 300 according to the ninth embodiment, the piezoelectric element 320 (the first electrode layer 322, the piezoelectric layer 324, and the second electrode layer 326) and the cavity member 340 are formed using an embossing technique. Since it is formed, it is possible to manufacture a piezoelectric ink jet head using a process which is much smaller than the conventional materials and manufacturing energy, and which is shorter than the conventional one.
Further, the piezoelectric ink jet head 300 according to the ninth embodiment is provided with a precursor composition which is highly heat-resistant by heat treatment at a second temperature in the range of 80 ° C to 300 ° C. The first electrode layer, the piezoelectric layer, the second electrode layer and the cavity member having an embossed structure formed with high precision are formed by embossing, so that it is a piezoelectric type having desired properties. Inkjet head.
Further, according to the piezoelectric ink jet head 300 according to the ninth embodiment, the piezoelectric element 320 (the first electrode layer 322, the piezoelectric layer 324, and the second electrode layer 326) and the cavity member 340 are both made of a liquid material. Since it is formed, a piezoelectric ink jet head can be manufactured by using an embossing forming technique, and a piezoelectric ink jet head excellent in the above-described manner can be manufactured using much less raw materials and manufacturing energy.
Further, according to the piezoelectric ink jet head 300 according to the ninth embodiment, the piezoelectric element 320 (the first electrode layer 322, the piezoelectric layer 324, and the second electrode layer 326) and the cavity member 340 are not used high. Since it is formed by a vacuum process, it is possible to manufacture a piezoelectric ink jet head which is excellent as described above by using a manufacturing process which is much smaller than the conventional one and which is shorter than the prior art.
Further, according to the piezoelectric ink jet head 300 according to the ninth embodiment, the cavity member is manufactured by using an atmospheric piezoelectric device without using a vacuum process, and it is possible to use much less manufacturing energy than conventional ones, and it is shorter than ever. Process manufacturing.
Further, according to the piezoelectric ink jet head 300 according to the ninth embodiment, since the piezoelectric layer and/or the cavity member are formed by using the method for producing the embossed structure of the present invention, it is possible to have no residual film influence. The embossed structure is manufactured using a material that is much smaller than conventional materials and manufacturing energy, and is manufactured in a shorter process than in the past.
[Examples]
[Example 1]
The first embodiment shows an embodiment in which the precursor composition layer can be completely removed by applying a reactive gas to the ashing treatment.
Fig. 18 is a view for explaining the ashing process in the first embodiment. 18(a) to 18(e) are process diagrams of the ashing process. 18(c) to 18(e) are diagrams showing the results of the ashing treatment in the ashing condition 1, and FIG. 18(b) is the ash in the ashing condition 2. FIG. 18(c) is a view showing the result of the ashing treatment in the ashing condition 3. FIG.
Fig. 19 is a view showing the result of the ashing treatment in the first embodiment. The horizontal axis represents the ashing time, and the vertical axis represents the layer thickness of the precursor composition layer after the ashing treatment is applied to the precursor composition layer 520. Further, in FIG. 19, in the region where the layer thickness of the precursor composition layer 520 is negative, the display is etched to the insulating substrate 510.
Fig. 20 is a view showing the result of the ashing treatment in the first embodiment. Fig. 20 (a) is a view showing a SEM (Scanning Electron Microscope) photograph in a boundary portion between a portion subjected to ashing treatment and a portion not subjected to ashing treatment, and Fig. 20 (b) is a view showing A map of the distribution of Ti (titanium) in the boundary portion.
Fig. 21 is a view showing the result of the ashing treatment in the first embodiment. Fig. 21 (a) is a view showing an EDX spectrum (Energy Dispersive X-ray spectrum) in a portion R1 not subjected to ashing treatment, and Fig. 21 (a) is a display showing A plot of the EDX spectrum in the portion R2 treated with ashing.
In the first embodiment, SiO is formed on the surface of the Si substrate. 2 On the insulating substrate 510 of the layer, TiO is coated by spin coating 2 The sol-gel solution forms the precursor composition layer 520, and then the insulating substrate on which the precursor composition layer 520 was formed was dried at 200 ° C for 5 minutes on a hot plate as a sample. For the size and shape of the insulating substrate 510, for example, a rectangular parallelepiped having a length of 20 mm, a width of 20 mm, and a height of 0.7 mm is used. The layer thickness of the precursor composition layer 520 after drying at 200 ° C was 75 nm.
Then, as shown in FIG. 18(a), after the heat-resistant insulating tape M20 is partially attached to the surface of the precursor composition layer 520, the precursor composition layer 520 is ashed as shown in FIG. 18(b). deal with. Set one side to make reactive gas (CF 4 Gas: a flow rate of 0.1 L/min) flows together with a carrier gas (He gas: flow rate: 9 L/min), and the precursor composition layer 520 is subjected to ashing treatment to ashing condition 1, and Ar gas is disposed at the same time. 0.1 L/min) flows along with the carrier gas (He gas: flow rate: 9 L/min), and the precursor composition layer 520 is subjected to ashing treatment to the ashing condition 2, and the reactive gas (CF) is set. 4 Gas: flow rate: 0.05 L/min) and Ar gas (flow rate: 0.05 L/min) flowed together with a carrier gas (He gas: flow rate: 9 L/min), and the precursor composition layer 520 was subjected to ashing treatment to be ashed. Condition 3.
Then, the sample which was subjected to the ashing treatment by the ashing condition 1 was peeled off from the surface of the precursor composition layer 520 by the heat-resistant insulating tape M20, and a step gauge manufactured by KLA-Tencor Co., Ltd. was used. [Alpha Step-500], the amount of etching (level difference) from the surface of the precursor composition layer 520 was measured. Furthermore, a scanning electron microscope/energy dispersive X-ray analyzer [JSM-5510] manufactured by JEOL Ltd. was used, and the part to be subjected to ashing treatment was obtained. The SEM image and the element mapping image (Ti) in the boundary portion of the portion subjected to the ashing treatment. Furthermore, using a scanning electron microscope/energy dispersive X-ray analyzer [JSM-5510] manufactured by JEOL Ltd., the EDX in the boundary portion between the portion subjected to the ashing treatment and the portion not subjected to the ashing treatment was obtained. Spectra (energy dispersive X-ray spectroscopy).
As a result, as shown in FIG. 18 and FIG. 19, in the case where the precursor composition layer 520 is subjected to ashing treatment by the ashing condition 1, the precursor composition can be completely removed by the ashing time of about 10 minutes. In the layer 520, and even if the ashing time is 10 minutes or more, the insulating substrate 510 is not etched (see FIGS. 18(c) and 19). Further, it is understood that in the case where the precursor composition layer 520 is subjected to ashing treatment by the ashing condition 2, the precursor composition layer 520 can be completely removed by the ashing time of about 30 minutes. However, in this case, when the ashing time is 5 minutes or more, the insulating substrate 510 is also etched (see FIGS. 18(d) and 19). On the other hand, in the case where the precursor composition layer 520 is subjected to ashing treatment by the ashing condition 3, it is difficult to completely remove the precursor composition layer 520 with an ashing time of about 30 minutes (refer to FIG. 18). (e) and Figure 19).
Further, as shown in Fig. 20, a clear boundary line in the SEM image between the portion subjected to the ashing treatment and the portion not subjected to the ashing treatment was observed (refer to Fig. 20 (a)). Further, in the portion to which the ashing treatment was applied, it was confirmed that the amount of Ti (titanium) observed was greatly reduced as compared with the portion to which the ashing treatment was not applied (see FIG. 20(b)).
Further, as shown in Fig. 21, it was not observed in the portion R2 subjected to the ashing treatment: the peak of Ti (4.6 KeV and 4.9 KeV) observed in the portion R1 to which the ashing treatment was not applied ( 21(a) and 21(b)).
[Embodiment 2]
In the second embodiment, in the case where the precursor composition layer before firing is subjected to ashing treatment, the precursor composition layer (metal oxide layer) after the firing can be subjected to ashing treatment. It is also the case that the precursor composition layer or the metal oxide layer is etched at high speed.
Fig. 22 is a view showing the result of the ashing treatment in the second embodiment. Fig. 22 (a) is a view showing the result of ashing treatment in the case where the precursor composition layer before firing is subjected to ashing treatment, and Fig. 22 (b) is a diagram showing the precursor composition after firing. A diagram showing the results of the ashing treatment in the case where the layer (metal oxide layer) is subjected to ashing treatment.
In the second embodiment, as in the case of the first embodiment, SiO is formed on the surface of the Si substrate. 2 On the insulating substrate 510 of the layer, TiO is coated by spin coating 2 The sol-gel solution forms the precursor composition layer 520, and then the insulating substrate on which the precursor composition layer 520 is formed is dried at 200 ° C for 5 minutes on the hot plate as a sample (sample 1) )use. Further, the sample fired by heat-treating the sample 1 at 600 ° C by an RTA apparatus was used as a sample (sample 2).
Then, after the heat-resistant insulating tape M20 was partially attached to the surfaces of the sample 1 and the sample 2, the same conditions as those of the ashing condition 3 in the first embodiment (the reactive gas (CF) were made. 4 Gas: flow rate: 0.05 L/min) and Ar gas (flow rate: 0.05 L/min) flowed together with carrier gas (He gas: flow rate: 9 L/min), and the conditions of ashing treatment were applied to the sample 1 and the sample. 2 Apply ashing treatment.
Then, for both the sample 1 and the sample 2, the heat-resistant insulating tape M20 was peeled off from the surface of the precursor composition layer 520, and a step gauge [Alpha Step-500] manufactured by KLA-Tencor Co., Ltd. was used. The amount of etching from the surface of the precursor composition layer 520 was measured.
As a result, as shown in Fig. 22, in the case where the precursor composition layer before firing is subjected to ashing treatment (see Fig. 22 (a)), the precursor composition after firing can be compared. When the layer (metal oxide layer) is subjected to ashing treatment (refer to FIG. 22(b)), the precursor composition layer or the metal oxide layer is also removed by high-speed etching.
[Embodiment 3]
The third embodiment is an embodiment in which the residual film can be completely removed in the case where a predetermined ashing treatment is applied to the precursor composition layer containing the residual film.
Fig. 23 is a view for explaining the evaluation method in the third embodiment. 23(a) to 23(d) are diagrams showing the procedure. Fig. 24 is a view showing the result of the ashing treatment in the third embodiment (AFM (Atomic Force Microscopy) image or SPM (Scanning Probe Microscope image). Fig. 24(a) shows use. A three-dimensional image of the surface of the sample after the ashing treatment obtained by a scanning probe microscope (AFM or SPM), FIG. 24(b) is a view showing a cross-sectional image thereof, and FIG. 25 is a view showing the ash in the third embodiment. A graph showing the result of the treatment (IV characteristics). In Fig. 25, symbol A is an IV characteristic in Measurement Example 1, and symbol B is an IV characteristic in Measurement Example 2.
In the third embodiment, TiO is coated by spin coating on the substrate 610 on which the Pt layer 614 is formed on the surface of the Si substrate 612. 2 The MOD solution (0.4 mol) (2000 rpm, 30 seconds) formed the precursor composition layer 620 to dry the substrate 610 on which the precursor composition layer 620 was formed on a hot plate at 150 ° C for 5 minutes. It is used as it is (refer to Fig. 23 (a)). The size and shape of the substrate 610 are, for example, a rectangular parallelepiped of 20 mm in length × 20 mm in width × 0.7 mm in height.
Then, by using a square concave portion having a square shape of 10 mm × 10 mm, nine square concave patterns having a length of 3 μm × a width of 3 μm × a height difference of 200 nm are arranged in a matrix of three rows and three columns at a pitch of 10 μm in the vertical and horizontal directions, and the precursor is formed. The composition layer 620 is subjected to embossing (80 ° C → 200 ° C → 80 ° C, 10 MPa, 5 minutes) to form an embossed structure including the residual film 622 in the precursor composition layer 620 (refer to FIG. 23( b ) ).
Then, the precursor composition layer 620 formed with the embossed structure is subjected to ashing treatment using atmospheric piezoelectric slurry (output 300 W, time 3 minutes, ashing gas: He+Ar+CF 4 The residual film was treated (see Fig. 23(c)).
Then, using a scanning probe microscope [S-Image] manufactured by SII NanoTechnology Co., Ltd., a three-dimensional image of the surface of the sample and a cross-sectional image thereof were obtained. Further, the IV characteristics were measured in combination with the IV measurement system shown in Fig. 23(d).
As a result, as seen from Fig. 24, a beautiful pattern having a width of 3 μm and a height of 170 nm can be formed. Further, as is clear from Fig. 24, in the measurement example 1 (reference symbol A), since only a very small current flows, the precursor composition layer 620 has high insulation (see Fig. 25). Further, in Measurement Example 2 (reference symbol B), since a very large current flows, it is suggested that the residual film 622 is cleanly removed by the region 630 in which the residual film 622 is present by applying the ashing treatment (refer to FIG. 25). .
The present invention has been described above based on the above-described embodiments, but the present invention is not limited to the embodiments, and may be practiced without departing from the scope of the invention. For example, the following modifications are possible.
(1) In the above-described first to fourth, sixth and seventh embodiments, the residual film is completely removed by subjecting the precursor composition layer including the [residual film continuous in each residual film formation region] to an ashing treatment. Further, in the fifth embodiment, the precursor composition layer including the [residual film continuous in each residual film formation region] is subjected to ashing treatment to thin the residual film until the fifth step is performed. The process makes the residual film take the thinness of the island structure. However, the invention is not limited thereto.
Fig. 26 is a view for explaining a method of manufacturing an embossed structure according to a modification. Figure 26(a) is a cross-sectional view of the precursor composition layer 20 when the precursor composition layer 20 is subjected to ashing treatment in the fourth process, and Figure 26(b) is a composition of the precursor just after the fourth process. The material layer 20 is subjected to a cross-sectional view of the precursor composition layer 20 after the ashing treatment, and FIG. 26(c) is an embossed structure 30 formed by heat-treating the precursor composition layer 20 in the fifth process. Sectional view.
In the method of manufacturing an embossed structure relating to the modification, as shown in FIG. 26(a), a residual film including [discontinued in each residual film formation region (for example, taking an island structure 28) is formed in the third process. The embossed structure of the film)] and (see FIG. 26(a)) may be completely removed by applying the ashing treatment to the precursor composition layer 20 in the fourth process (refer to FIG. 26 (refer to FIG. 26 ( a) ~ Figure 26 (c)).
(2) In the eighth embodiment, the present invention has been described by taking a thin film transistor as an example. In the above-described ninth embodiment, the present invention has been described by taking a piezoelectric ink jet head as an example, but the present invention is not Limited to this. For example, the present invention can also be applied to a film capacitor including a first electrode layer, a dielectric layer, a second electrode layer, and a wiring layer, and an actuator including a piezoelectric layer, an electrode layer, and a wiring layer; An optical element (for example, a reflective polarizing plate, a diffraction grating, or the like) having a lattice layer (a metal oxide layer or a metal layer) on a substrate.
10、10a、10b...基材10, 10a, 10b. . . Substrate
12...第一基材12. . . First substrate
14...由成為蝕刻中止層的材料構成的層14. . . a layer composed of a material that becomes an etch stop layer
20、20a...前驅物組成物層20, 20a. . . Precursor composition layer
22、22a、120’z、130’z、140’z、522...殘膜22, 22a, 120'z, 130'z, 140'z, 522. . . Residual film
24...凹部twenty four. . . Concave
26、28...海島構造26, 28. . . Island structure
30...壓花構造體30. . . Embossed structure
40、40a...灰化裝置40, 40a. . . Ashing device
41、43...電極41, 43. . . electrode
42...正電極42. . . Positive electrode
44...負電極44. . . Negative electrode
100、900...薄膜電晶體100, 900. . . Thin film transistor
110、510、910...絕緣性基板110, 510, 910. . . Insulating substrate
120、920...閘電極120, 920. . . Gate electrode
120’...前驅物組成物層(閘電極)120’. . . Precursor composition layer (gate electrode)
122...閘墊122. . . Brake pad
130、930...閘絕緣層130, 930. . . Brake insulation
130’...前驅物組成物層(閘絕緣層)130’. . . Precursor composition layer (gate insulating layer)
140...氧化物導體層140. . . Oxide conductor layer
140’...前驅物組成物層(氧化物導電性層)140’. . . Precursor composition layer (oxide conductive layer)
142...通道區域142. . . Channel area
144...源極區域144. . . Source area
146...汲極區域146. . . Bungee area
150...貫通孔150. . . Through hole
160...元件分離區域160. . . Component separation area
300...壓電式噴墨頭300. . . Piezoelectric inkjet head
310...虛擬基板310. . . Virtual substrate
320...壓電元件320. . . Piezoelectric element
322...第一電極層322. . . First electrode layer
322’、324’...前驅物組成物層322', 324’. . . Precursor composition layer
324...壓電層324. . . Piezoelectric layer
326...第二電極層326. . . Second electrode layer
330...噴嘴板330. . . Nozzle plate
332...噴嘴孔332. . . Nozzle hole
340...空腔構件340. . . Cavity member
350...振動板350. . . Vibrating plate
352...墨水供給口352. . . Ink supply port
360...墨水室360. . . Ink room
520、620...前驅物組成物層520, 620. . . Precursor composition layer
610...基板610. . . Substrate
612...Si基板612. . . Si substrate
614...Pt層614. . . Pt layer
622...殘膜622. . . Residual film
630...不存在殘膜622的區域630. . . Area where residual film 622 is absent
940...通道層940. . . Channel layer
950...源電極950. . . Source electrode
960...汲電極960. . . Helium electrode
i...墨水滴i. . . Ink drop
M1、M2、M3、M4、M8、M9、M10、M11...凹凸模M1, M2, M3, M4, M8, M9, M10, M11. . . Concave mode
M20...耐熱性絕緣帶M20. . . Heat resistant insulation tape
P...電漿P. . . Plasma
10...基材10. . . Substrate
20...前驅物組成物層20. . . Precursor composition layer
22...殘膜twenty two. . . Residual film
30...壓花構造體30. . . Embossed structure
40...灰化裝置40. . . Ashing device
M1...凹凸模M1. . . Concave mode
P...電漿P. . . Plasma
Claims (20)
製備含有含金屬化合物,藉由進行熱處理而成為金屬氧化物或金屬的液體材料之第一製程;
藉由在基材上塗佈該液體材料形成由該金屬氧化物或該金屬的前驅物組成物構成的前驅物組成物層之第二製程;
藉由對該前驅物組成物層使用凹凸模施以壓花加工,形成在該前驅物組成物層包含殘膜的壓花構造之第三製程;
藉由對形成有該壓花構造的該前驅物組成物層施以利用大氣壓電漿或低壓電漿的灰化處理而處理該殘膜之第四製程;以及
藉由對該前驅物組成物層進行熱處理,由形成有該壓花構造的該前驅物組成物層形成由該金屬氧化物或該金屬構成的壓花構造體之第五製程。A method of manufacturing an embossed structure, the method comprising the following sequence of processes:
a first process for preparing a liquid material containing a metal-containing compound and forming a metal oxide or a metal by heat treatment;
Forming a second process of a precursor composition layer composed of the metal oxide or a precursor composition of the metal by coating the liquid material on a substrate;
Forming an embossed structure including a residual film in the precursor composition layer by embossing using the embossing mold on the precursor composition layer;
Forming the fourth process of treating the residual film by applying a ashing treatment using atmospheric piezoelectric or low-pressure plasma to the precursor composition layer having the embossed structure; and by using the precursor composition The layer is subjected to a heat treatment for forming a fifth process of the embossed structure composed of the metal oxide or the metal from the precursor composition layer in which the embossed structure is formed.
在該第三製程中,藉由在將該前驅物組成物層加熱到位於80℃~300℃的範圍內的溫度的狀態下,且使用加熱到位於80℃~300℃的範圍內的溫度的模對該前驅物組成物層施以壓花加工,在該前驅物組成物層形成壓花構造。The method of manufacturing an embossed structure according to any one of the preceding claims, wherein the second process and the third process further comprise heating the precursor composition layer to a preheating process in which the temperature of the precursor composition layer is lowered in advance in a temperature range of 80 ° C to 200 ° C,
In the third process, by heating the precursor composition layer to a temperature in a range of 80 ° C to 300 ° C, and using a temperature heated to a temperature in the range of 80 ° C to 300 ° C The mold applies embossing to the precursor composition layer, and an embossed structure is formed on the precursor composition layer.
該閘電極層、該閘絕緣層、該源極層、該汲極層、該通道層及該配線層之中至少一層是藉由申請專利範圍第1項至第13項中任一項之壓花構造體的製造方法形成。A thin film transistor comprising a gate electrode layer, a gate insulating layer, a source layer, a drain layer, a channel layer and a wiring layer, and is characterized by:
At least one of the gate electrode layer, the gate insulating layer, the source layer, the drain layer, the channel layer, and the wiring layer is pressed by any one of the first to the thirteenth claims A method of manufacturing a flower structure is formed.
包含源極區域及汲極區域以及通道區域之氧化物導體層;
控制該通道區域的導通狀態之閘電極;以及
形成於該閘電極與該通道區域之間,由鐵電材料或順電材料構成之閘絕緣層,
該通道區域的層厚比該源極區域的層厚及該汲極區域的層厚薄,
該通道區域的層厚比該源極區域的層厚及該汲極區域的層厚薄的該氧化物導體層是藉由申請專利範圍第1項至第13項中任一項的壓花構造體的製造方法形成。A thin film transistor characterized by:
An oxide conductor layer including a source region and a drain region and a channel region;
a gate electrode for controlling an on state of the channel region; and a gate insulating layer formed of a ferroelectric material or a paraelectric material formed between the gate electrode and the channel region,
The layer thickness of the channel region is thinner than the layer thickness of the source region and the layer thickness of the drain region.
The oxide conductor layer having a layer thickness of the channel region which is thinner than the layer thickness of the source region and the layer thickness of the drain region is an embossed structure according to any one of claims 1 to 13. The manufacturing method is formed.
該第一電極層、該介電質層、該第二電極層及該配線層之中至少一層是藉由申請專利範圍第1項至第13項中任一項的壓花構造體的製造方法形成。A film capacitor comprising a first electrode layer, a dielectric layer, a second electrode layer and a wiring layer, wherein:
At least one of the first electrode layer, the dielectric layer, the second electrode layer, and the wiring layer is a method of manufacturing an embossed structure according to any one of claims 1 to 13. form.
該壓電層、該電極層及該配線層之中至少一層是藉由申請專利範圍第1項至第13項中任一項的壓花構造體的製造方法形成。An actuator comprising a piezoelectric layer, an electrode layer and a wiring layer, characterized by:
At least one of the piezoelectric layer, the electrode layer, and the wiring layer is formed by the method for producing an embossed structure according to any one of claims 1 to 13.
空腔構件;
安裝於該空腔構件的一方側,形成有壓電層之振動板;
安裝於該空腔構件的他方側,形成有噴嘴孔之噴嘴板;以及
藉由該空腔構件、該振動板及該噴嘴板劃定之墨水室,
該壓電層及/或該空腔構件是藉由申請專利範圍第1項至第13項中任一項的壓花構造體的製造方法形成。A piezoelectric inkjet head characterized by:
Cavity member
a vibration plate formed on one side of the cavity member and having a piezoelectric layer;
a nozzle plate formed on the other side of the cavity member, the nozzle hole is formed; and an ink chamber defined by the cavity member, the vibration plate, and the nozzle plate,
The piezoelectric layer and/or the cavity member is formed by the method for producing an embossed structure according to any one of the first to thirteenth aspects of the invention.
該晶格層是藉由申請專利範圍第1項至第13項中任一項的壓花構造體的製造方法形成。An optical component comprising a lattice layer on a substrate, characterized by:
The lattice layer is formed by the method for producing an embossed structure according to any one of claims 1 to 13.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011245360A JP2013102072A (en) | 2011-11-09 | 2011-11-09 | Method for manufacturing die-pressed structural body, thin-film transistor, thin-film capacitor, actuator, piezoelectric type inkjet head, and optical device |
Publications (1)
Publication Number | Publication Date |
---|---|
TW201324788A true TW201324788A (en) | 2013-06-16 |
Family
ID=48289831
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW101140727A TW201324788A (en) | 2011-11-09 | 2012-11-02 | Manufacturing method of embossed structure, thin film transistor, film capacitor, actuator, piezoelectric inkjet head and optical component |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP2013102072A (en) |
TW (1) | TW201324788A (en) |
WO (1) | WO2013069448A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113261124A (en) * | 2018-12-19 | 2021-08-13 | Rf360欧洲有限责任公司 | Piezoelectric material and piezoelectric device |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6260326B2 (en) * | 2014-02-14 | 2018-01-17 | 凸版印刷株式会社 | Thin film transistor device and manufacturing method thereof |
JP2016021298A (en) * | 2014-07-14 | 2016-02-04 | 東芝機械株式会社 | Conductive substrate, and apparatus and method for producing conductive substrate |
JP6337363B1 (en) * | 2016-10-05 | 2018-06-06 | 国立大学法人北陸先端科学技術大学院大学 | Composite member and manufacturing method thereof |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7143609B2 (en) * | 2002-10-29 | 2006-12-05 | Corning Incorporated | Low-temperature fabrication of glass optical components |
JP5204380B2 (en) * | 2006-04-10 | 2013-06-05 | 富士フイルム株式会社 | Piezoelectric element, method for manufacturing the same, and liquid ejection device |
JP2008049544A (en) * | 2006-08-23 | 2008-03-06 | Nippon Sheet Glass Co Ltd | Nano-imprinting method and nano-imprinting apparatus |
CN102341866A (en) * | 2009-03-06 | 2012-02-01 | 东洋铝株式会社 | Electrically conductive paste composition and electrically conductive film formed by using same |
JP2010247461A (en) * | 2009-04-17 | 2010-11-04 | Murata Mfg Co Ltd | Imprinting method |
JP5633346B2 (en) * | 2009-12-25 | 2014-12-03 | 株式会社リコー | Field effect transistor, semiconductor memory, display element, image display apparatus and system |
-
2011
- 2011-11-09 JP JP2011245360A patent/JP2013102072A/en active Pending
-
2012
- 2012-10-23 WO PCT/JP2012/077323 patent/WO2013069448A1/en active Application Filing
- 2012-11-02 TW TW101140727A patent/TW201324788A/en unknown
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113261124A (en) * | 2018-12-19 | 2021-08-13 | Rf360欧洲有限责任公司 | Piezoelectric material and piezoelectric device |
Also Published As
Publication number | Publication date |
---|---|
JP2013102072A (en) | 2013-05-23 |
WO2013069448A1 (en) | 2013-05-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI514585B (en) | A manufacturing method of a functional element, a thin film transistor, and a piezoelectric ink jet head | |
TWI514476B (en) | A manufacturing method of a functional element, and a manufacturing apparatus for a functional element | |
JP5140972B2 (en) | Manufacturing method of semiconductor device | |
JP5198506B2 (en) | Method for manufacturing functional device, thin film transistor, and piezoelectric ink jet head | |
TWI520346B (en) | Laminated structures, iron gate thin film transistors and ferroelectric thin film capacitors | |
TW201324788A (en) | Manufacturing method of embossed structure, thin film transistor, film capacitor, actuator, piezoelectric inkjet head and optical component | |
JP2000169297A (en) | Production of thin ferroelectric oxide film, thin ferroelectric oxide film and thin ferroelectric oxide film element | |
KR100308190B1 (en) | Method of removing pyrochlore caused during a ferroelectric crystalline dielectric film process | |
JP5154605B2 (en) | Ferroelectric material layer manufacturing method, thin film transistor, and piezoelectric ink jet head | |
JP5615894B2 (en) | Thin film transistor manufacturing method, actuator manufacturing method, optical device manufacturing method, thin film transistor, and piezoelectric inkjet head | |
TW201327841A (en) | Thin film transistor and method for manufacturing thin film transistor | |
JP5154603B2 (en) | Field effect transistor and manufacturing method thereof | |
JP5575864B2 (en) | Ferroelectric material layer manufacturing method, thin film transistor, and piezoelectric ink jet head | |
JP5656966B2 (en) | Field effect transistor and manufacturing method thereof | |
US20060093841A1 (en) | Method of forming ferroelectric thin film | |
JP2004056108A (en) | Semiconductor device and manufacturing method thereof | |
Seong et al. | Thickness effect of Pb2Ru2O7− x conductive interfacial layers on ferroelectric properties of Pt/Pb (Zr0. 35Ti0. 65) O3/Pt capacitors |