TW201319595A - Method for measuring power length of semiconductor test device - Google Patents

Abstract

The present invention provides a power length measuring method for measuring a power length of one of the plurality of probes as a first end signal path in a semiconductor testing device having a plurality of probes in contact with a wafer to be tested; The power length measuring method includes the steps of: contacting the conductive region of the calibration wafer having the conductive region with the entire plurality of probes; and making the conductive region of the calibration wafer and the complex probe In the state of total contact, a measurement signal is input from the second end of the signal path to be measured, and one of the probes in the conductive region and the plurality of probes is measured on the second end side. The step of reflecting the signal waveform of the contact portion; and the step of calculating the power length of the signal path based on the signal waveform measured by the second end side.

Description

Method for measuring power length of semiconductor test device

The present invention is a power length measuring technique for performing timing adjustment between pins in a test device for a semiconductor for a wafer stage.

The following patents, patent applications, patent publications, scientific publications, etc.

Fig. 7 is a view showing a basic configuration of a connection between a semiconductor test device and a device under test (DUT) in the prior art. As shown in FIG. 7, the semiconductor test apparatus 100 includes a measurement control unit 110 and a pin electronic card (PE card) 120. The pin electronic card 120 is connected to cables 600a and 600b provided in a base unit (not shown). The other ends of the cables 600a and 600b are connected to the probe card 700. The probe card 700 is provided with a plurality of probes that are in contact with the DUT 800. The complex probe includes a probe that is in contact with the signal pin (Sig) of the DUT 800, and a probe that is in contact with the ground pin (GND) of the DUT 800.

The pin electronic card 120 includes: a plurality of arrays of drivers 121a and 121b, and comparators 122a and 122b. The driver 121a generates a signal waveform in accordance with an instruction from the measurement control unit 110, and outputs it to the cable 600a and the comparator 122a via the resistor Ra. The driver 121b generates a signal waveform in accordance with an instruction from the measurement control unit 110, and outputs it to the cable 600b and the comparator 122b via the resistor Rb. The comparator 122a compares the input signal with the reference voltage instructed by the measurement control unit 110, and outputs the comparison result to the measurement control unit 110. The comparator 122b compares the input signal with the reference voltage instructed by the measurement control unit 110, and outputs the comparison result to the measurement control unit 110. The measurement control unit 110 determines the quality of the DUT 800 based on the comparison results from the comparators 122a and 122b.

As such, the semiconductor test apparatus 100 uses the output signals to the DUT 800 and the input signals from the DUT 800 to share the cables 600a and 600b. These input-incoming common types are disadvantageous in improving the timing accuracy, but since the number of pins per unit area is increased, it is often used in the pre-engineering test for the wafer stage.

In the semiconductor test apparatus 100, in order to reduce the time lag (offset) of the timing at which the test signals are applied to the respective pins of the DUT 800, the power length (delay time of the signal) is measured in advance for each of the pins, and the obtained The power length is used to perform timing adjustment of the test signal output.

Fig. 8A is a block diagram for explaining the power length measurement of the prior art. In Fig. 8A, in order to explain a portion in which only one pin is displayed. The power length was measured by the TDR method (Time Domain Reflectometry method). As shown in FIG. 8A, in the past, when the power length is measured, the probe tip of the probe card 700 is opened. Then, the self-driver 121 outputs a test signal, and measures the time T1 until it reaches the comparator 122 directly through the path R1. Next, the test signal is again output from the driver 121, and the time T2 until the comparator 122 is passed through the path R2. The path R2 is a path that is reflected by the open end of the probe card 700 via the cable 600 and returned via the cable 600.

The difference between the time T2 and the time T1 corresponds to twice the length of the electric power to be measured. Therefore, the measurement control unit 110 can obtain the electric power length of the measurement target by measuring the time T2 and the time T1.

Fig. 9A is a view for explaining an input signal of a comparator when the power length is measured in the prior art. The measurement signal of the power length, for example, uses a rectangular wave that rises from Low to High. At this time, as shown in FIG. 9A, the time T1 can be set to the time t1 when the comparator 122 detects the input signal of the first threshold or more corresponding to the High signal from the time t0 at which the driver 121 rises to High. The time until then. this In addition, the first threshold may be a value lower than the measured signal voltage, for example, 25% of the measured signal voltage.

When the front end of the probe card 700 is in an open state, the reflected reflected waves overlap and the voltage rises. Therefore, the time T2 can be set to a time from the time t0 at which the driver 121 rises from Low to High to the time t2 at which the comparator 122 detects the input signal equal to or higher than the second threshold value higher than the first threshold value. Further, the second threshold value may be a value lower than the measured signal voltage, for example, about 75% of the measured signal voltage.

By subtracting the time T1 from the time T2, the time from the time t1 to the time t2, that is, the time twice the length of the electric power can be obtained. Naturally, the time from the time t1 to the time t2 can be directly measured to calculate the time twice the power length.

Fig. 8B is a block diagram for explaining another example of the power length measurement of the prior art. In the above-described conventional example, the front end of the probe card 700 is in an open state, but in recent years, as shown in FIG. 8B, the probe tip end of the probe card 700 is grounded.

In this case, if the reflected wave from the ground terminal returns, the input voltage of the comparator 122 becomes 0V. Fig. 9B is a view for explaining an input signal of a comparator when the power length is measured in the configuration. As shown in FIG. 9B, the time T2 can be set to the time from the time t0 at which the driver 121 rises from Low to High to the time t2 at which the comparator 122 detects the input signal below the second threshold. The second threshold in this case can be a value equal to the first threshold.

[Practical Technical Literature]

[Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2005-331264

In general, it is possible to improve the timing accuracy by measuring the power length by making the probe tip end grounded. In recent years, high-speed semiconductor semiconductor devices, miniaturization, and shortened working hours have required high timing accuracy in the semiconductor test equipment for the wafer segment, and the probe tip is grounded to measure power. The necessity of length is increased.

Since the probe tip is disconnected in the standby state, it is necessary to use a tool in order to make the probe tip grounded during the power length measurement. As a tool for grounding the probe tip end, for example, a calibration wafer described in Patent Document 1 is considered. Here, the wafer is calibrated to have a pad that is configured in the same configuration as the pins of the DUT, and the short-circuit wiring is used to short-circuit the pad to the ground.

However, if the power length measurement is performed using a calibration wafer having pads of the same configuration as the pins of the DUT, it is necessary to design a calibration wafer for each type of DUT, resulting in an increase in load for power length measurement. Incurring an increase in costs.

According to the present invention, in a semiconductor test device for a wafer, the probe tip can be simply grounded to measure the power length.

A method for measuring a power length according to the present invention for measuring a power of a signal path in which one of the plurality of probes is the first end in a semiconductor test device having a plurality of probes in contact with a wafer to be tested The method for measuring the power length includes the steps of: contacting the entirety of the plurality of probes with the conductive region of the calibration wafer having the conductive region; and contacting the entirety of the plurality of probes with the conductivity of the calibration wafer In the state of the region, a measurement signal is input from the second end of the signal path to be measured, and the measurement signal is measured at the second end side. a step of reflecting a signal waveform of a contact between the region and one of the plurality of probes; and calculating a power length of the signal path based on the signal waveform measured by the second end side.

A method for measuring a power length according to the present invention for measuring a plurality of probes having contact with a wafer to be tested, and including a probe for connecting a probe to a plurality of signal paths, Taking one of the plurality of probes as the power length of one signal path of the first end; the method for measuring the power length includes the steps of: contacting the whole of the plurality of probes with the conductive wafer of the calibration wafer having the conductive region a step of inputting a measurement signal from the second end of the signal path to be measured, in a state where the entire plurality of probes are in contact with the conductive region of the calibration wafer, and on the second end side Determining a signal waveform of the measurement signal reflected by the contact portion of the conductive region and one of the plurality of probes; and calculating the power of the signal path according to the signal waveform measured by the second end side The length of the step.

Another method for measuring the power length of the present invention is for measuring a semiconductor test device having a plurality of probes in contact with a wafer to be tested, wherein one of the plurality of probes is a signal path of the first end The power length measuring method includes the following steps of: bringing the entire plurality of probes into contact with the conductive region of the calibration wafer having the conductive region.

The plurality of probes may include a probe for grounding.

The calibration wafer can be in the shape that the probe station device on which the wafer to be tested is placed can be placed.

The calibration wafer may be composed of a germanium wafer having a conductor film formed on its surface, and may be composed of a metal plate or a resin having a conductor film formed on its surface.

According to the present invention, in the semiconductor test device for a wafer, the probe tip can be simply grounded to measure the power length.

[Best Mode for Carrying Out the Invention]

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following description of the embodiments of the present invention is specifically described by the appended claims and the equivalents thereof, and in accordance with the disclosure of the present invention, those of ordinary skill in the art should understand To be limited.

Fig. 1 is a view for explaining electric power length measurement according to a first embodiment of the present invention. The configuration of the semiconductor test device 100, the cables 600a and 600b, and the probe card 700 can be the same as those of the prior art. The semiconductor test device 100 includes a measurement control unit 110 and a pin electronic card (PE card) 120. The pin electronic card 120 is connected to cables 600a and 600b provided in a base unit (not shown). The other ends of the cables 600a and 600b are connected to the probe card 700. The probe card 700 includes a plurality of probes that are in contact with a device to be measured (DUT). The complex probe includes a probe that is in contact with the signal pin (Sig) of the DUT, and a probe that is in contact with the ground pin (GND) of the DUT.

The pin electronic card 120 includes: a plurality of arrays of drivers 121a and 121b, and comparators 122a and 122b. The driver 121a generates a signal waveform in accordance with an instruction from the measurement control unit 110, and outputs it to the cable 600a and the comparator 122a via the resistor Ra. The driver 121b generates a signal waveform in accordance with an instruction from the measurement control unit 110, and outputs it to the cable 600b and the comparator 122b via the resistor Rb. The comparator 122a compares the input signal with the reference voltage instructed by the measurement control unit 110, and outputs the comparison result to the measurement control unit 110. The comparator 122b compares the input signal with the reference voltage instructed by the measurement control unit 110, and outputs the comparison result to the measurement control unit 110. The measurement control unit 110 determines the quality of the DUT based on the comparison results from the comparators 122a and 122b.

In the first embodiment of the present invention, the calibration wafer 200 having the entire surface or the surface of the conductive layer is used, and all the probe tips are brought into contact with the surface of the calibration wafer 200. Thereby, all the probe tips can be grounded regardless of the arrangement of the probes and the arrangement state. That is, the length of the electric power can be measured while the probe tip of the probe card 700 is grounded.

Fig. 2A is a view showing a calibration wafer 200 according to the first embodiment of the present invention. FIG. 2B is a view showing the wafer 820 of the test object. As shown in FIG. 2A and FIG. 2B, the calibration wafer 200 has a shape similar to that of the wafer 820 to be tested, and may be formed, for example, by a wafer having a conductor film formed on the entire surface. The material of the conductor film is not limited, and various materials such as Al, Ag, Au, and Cu can be used. Further, the substrate is not limited to a crucible, and a resin or the like may be used. Further, the calibration wafer 200 may be formed using a metal disk or a dielectric substrate whose entire surface is a conductor.

In the semiconductor test, in order to mount a wafer, a probe station device (not shown) is used, and the calibration wafer 200 is preferably placed in a probe station device on which the wafer 820 to be tested is placed. Thereby, the power length measurement can be performed under the same conditions as the wafer test. In addition, if the same diameter is used, it can be used for the measurement of the power length of the test for different types of wafers.

In the calibration wafer 200 according to the first embodiment of the present invention, since it is not necessary to form a pad, a transistor, a wiring pattern, or the like on the wafer, it can be manufactured at a very low cost.

FIG. 3 is a flow chart showing the procedure for measuring the electric power length using the calibration wafer 200 according to the first embodiment of the present invention.

(Step S101)

First, all of the probe tips of the probe card 700 are brought into contact with the conductive faces of the calibration wafer 200. The probe can include a ground probe. Thereby, the entire probe tip is grounded.

(Step S102)

In this state, the measurement control unit 110 outputs a rectangular wave as a measurement signal from the drivers 121a and 121b.

(Step S103)

Then, the measurement control unit 110 determines whether or not the input signals of the comparators 122a and 122b are equal to or larger than the first threshold (refer to FIG. 9B).

(Step S104)

The measurement control unit 110 records the timing at which the input signal intersects the first threshold as soon as the input signal of the comparator 122 is detected to be equal to or greater than the first threshold. The timing can be made, for example, the time after the signal is output.

(Step S105)

Next, the measurement control unit 110 determines whether or not the input signal of the comparator 122 is equal to or lower than the second threshold (refer to FIG. 9B).

(Step S106)

The measurement control unit 110 records the timing at which the input signal intersects the second threshold as soon as the input signal of the comparator 122 is detected to be equal to or less than the second threshold. The timing can be made, for example, the time after the signal is output.

(Step S107)

Then, the measurement control unit 110 calculates the power length from the difference between the timing at which the input signal intersects the first threshold and the timing at which the input signal intersects the second threshold.

Fig. 4 is a view for explaining the staggering operation of the electric power length measurement in the first embodiment of the present invention. As shown in FIG. 4, the power length measurement according to the first embodiment of the present invention can be effectively applied to a case where a plurality of paths are connected to the probe card 710 to perform an interleaving operation. In the example shown in FIG. 4, the path from the driver 121a is connected to the probe card 710 from the path from the driver 121b, and is connected to the clock terminal of the DUT 710.

In this configuration, when the phase of the driver 121a and the driver 121b is shifted and the interleaving operation is performed, the combined waveform of the signal output from the driver 121a and the signal output from the driver 121b is input to the DUT 710, which is more common. The DUT710 is tested at a higher frequency.

In recent years, in order to reduce the size of a portable device or the like, the semiconductor device tends to have a SoP (system single chip) in order to reduce the mounting area. Due to this tendency, the components of a single piece are shipped in the state of unpackaged bare wafers. In this case, in the past, after the package, the final inspection performed by the semiconductor test device for the post-engineering must be performed in the wafer state. Since the final inspection is performed at the highest speed of the components, the semiconductor test equipment for the wafer stage is also required to be speeded up. In order to meet this requirement, staggering actions are carried out.

FIG. 5 is a view for explaining a problem in the case where the power length is measured when the probe end is off in the configuration in which the power length measurement is performed in the staggered operation according to the first embodiment of the present invention. In the case of the configuration shown in FIG. 4, if the power length is measured while the probe end is open as shown in FIG. 5, the power length of the path R3 of the two paths is measured, and the power length of each path cannot be measured. .

FIG. 6 is a view showing a state in which the power length is measured using the calibration wafer 200 in the configuration in which the power length measurement is performed in the interleaving operation according to the first embodiment of the present invention. As shown in Fig. 6, the probe end is brought into contact with the calibration wafer 200 according to the first embodiment of the present invention to be grounded, and a rectangular wave is output from the driver 121a that connects the other path, and is output from the driver 121b of the other path. 0V, by which the power length of the former path can be determined.

At this time, the wiring delay of the connection point of the two paths and the probe is made shorter than the rise time of the driver 121a. The impedance from the probe end to the ground point is very small compared to the impedance of the path, so the falling waveform measured by the comparator 122a can be approximated as a reflection at the fixed end of the probe end. So even on the probe card 710 The path of the medium phase connection can still measure the power length equivalent to a single path.

The words "front, rear, upper, lower, right, left, vertical, horizontal, lower, horizontal, vertical, and column" are used in this specification to describe such directions in the apparatus of the present invention. Accordingly, such terms used in the description of the invention are to be construed as being

Terms such as "constitution" are used to implement the functions of the present invention, or to be used for the structure, elements, and parts of the display device.

Further, the vocabulary expressed in the "Means Plus Function" in the scope of the patent request shall include any configuration usable for carrying out the functions of the present invention.

The present invention has been described and illustrated in the preferred embodiments of the present invention, and the invention is intended to be illustrative, not limiting, and may be added, removed, substituted, and substituted without departing from the spirit or scope of the invention. Other changes. That is, the present invention is not limited by the foregoing embodiments, and is defined by the scope of the following claims.

100‧‧‧Semiconductor test set

110‧‧‧Measurement Control Department

120‧‧‧pin electronic card

121 (121a, 121b, 121c) ‧‧‧ drive

122 (122a, 122b, 122c) ‧ ‧ comparator

200‧‧‧ Calibration wafer

600 (600a, 600b, 600c) ‧‧‧ cable

700, 710‧ ‧ probe card

800, 810‧‧DUT

820‧‧‧ wafer

Ra, Rb, Rc‧‧‧ resistance

Fig. 1 is a view for explaining the measurement of the electric power length in the first embodiment of the present invention.

Fig. 2A is a view showing a calibration wafer according to the first embodiment of the present invention.

Figure 2B shows a diagram of the wafer of the test object.

Fig. 3 is a flow chart showing the procedure for measuring the electric power length using the calibration wafer according to the first embodiment of the present invention.

Fig. 4 is a view for explaining the staggered operation of the electric power length measurement in the first embodiment of the present invention.

FIG. 5 is a view for explaining a problem in the case where the power length is measured when the probe end is off in the configuration in which the power length measurement is performed in the staggered operation according to the first embodiment of the present invention.

Fig. 6 is a view showing the execution of electric power length measurement in the first embodiment of the present invention; In the configuration of the staggered operation, a graph of the case where the power length is measured using the calibration wafer is used.

Fig. 7 is a view showing a basic configuration of a connection between a semiconductor test device and a device under test (DUT) in the prior art.

Figure 8A is a block diagram showing the power length measurement of the prior art.

Figure 8B is a block diagram illustrating the power length measurement of the prior art.

Fig. 9A is a view showing the input signal of the comparator when the power length is measured in the prior art.

Fig. 9B is a view showing the input signal of the comparator when the power length is measured in the prior art.

Claims (18)

An electric length measuring method for measuring a power length of a signal path in which one of the plurality of probes is the first end in a semiconductor testing device having a plurality of probes in contact with a wafer to be tested; The method for measuring the power length includes the steps of: contacting the entirety of the plurality of probes with the conductive region of the calibration wafer having the conductive region; and contacting the entirety of the plurality of probes with the conductive region of the calibration wafer And inputting a measurement signal from the second end of the signal path to be measured, and measuring, on the second end side, a signal reflected by the contact portion of the measurement signal in one of the conductive region and the plurality of probes a step of waveforms; and a step of calculating a power length of the signal path based on the signal waveform measured on the second end side. The power length measuring method according to claim 1, wherein the plurality of probes include a grounding probe. The power length measuring method according to claim 1 or 2, wherein the calibration wafer is in a shape that can be placed on a probe station device on which the wafer to be tested is placed. The method for measuring an electric power length according to claim 1 or 2, wherein the calibration wafer is formed by a tantalum wafer having a conductor film formed on its surface. The power length measuring method according to claim 1 or 2, wherein the calibration wafer is formed of a metal plate. The power length measuring method according to claim 1 or 2, wherein the calibration wafer is made of a resin having a conductor film formed on its surface. A method for measuring a power length for determining a plurality of probes having a contact with a wafer of a test object, and including a probe for connecting a probe to a plurality of signal paths, in the plurality of semiconductor test devices One of the probes is a power length of one signal path of the first end; the power length measuring method includes the steps of: contacting the whole of the plurality of probes with the conductive wafer of the calibration wafer having the conductive region a step of inputting a measurement signal from the second end of the signal path to be measured, in a state where the entire plurality of probes are in contact with the conductive region of the calibration wafer, and on the second end side Determining a signal waveform of the measurement signal reflected by the contact portion of the conductive region and one of the plurality of probes; and calculating the power of the signal path according to the signal waveform measured by the second end side The length of the step. The power length measuring method according to claim 7, wherein the plurality of probes comprise a grounding probe. The power length measuring method according to claim 7 or 8, wherein the calibration wafer is in a shape that can be placed by a probe station device on which the wafer to be tested is placed. The power length measuring method according to claim 7 or 8, wherein the calibration wafer is formed by a germanium wafer having a conductor film formed on its surface. The power length measuring method according to claim 7 or 8, wherein the calibration wafer is formed of a metal plate. The method for measuring a power length according to claim 7 or 8, wherein the calibration wafer is made of a resin having a conductor film formed on its surface. An electric length measuring method for measuring a power length of a signal path of a first end of a plurality of probes of a semiconductor test device having a plurality of probes in contact with a wafer to be tested; The length measuring method includes the step of bringing the entire plurality of probes into contact with the conductive region of the calibration wafer having the conductive region. The power length measuring method according to claim 13, wherein the plurality of probes include a grounding probe. The power length measuring method according to claim 13 or 14, wherein the calibration wafer is in a shape that can be placed by a probe station device on which the wafer to be tested is placed. The power length measuring method according to claim 13 or 14, wherein the calibration wafer is formed by a germanium wafer having a conductor film formed on its surface. The power length measuring method according to claim 13 or 14, wherein the calibration wafer is formed of a metal plate. The method of measuring the power length according to claim 13 or 14, wherein the calibration wafer is made of a resin having a conductor film formed on its surface.