TW201316504A - Electrically insulating joint for connecting a light-emitting element - Google Patents

Abstract

Embodiments of the invention include a wafer and a mount. The wafer includes a plurality of light emitting devices, each light emitting device comprising a light emitting region disposed between an n-type region and a p-type region. A first conductive pad is electrically connected to the n-type region. A second conductive pad is electrically connected to the p-type region. An electrically insulating bonding layer is disposed between the wafer and the mount. Openings aligned with the first and second conductive pads are formed in the electrically insulating bonding layer.

Description

Electrically insulating joint for connecting a light-emitting element

The present invention relates to an electrically insulating joint for attaching a semiconductor light emitting element to a bonding sheet. The semiconductor light emitting element can be attached to a die via a wafer level process.

Semiconductor light-emitting elements (including light-emitting diodes (LEDs), resonant cavity light-emitting diodes (RCLEDs), vertical-cavity laser diodes (such as a surface-emitting laser (VCSEL)), and edge-emitting lasers) are currently The most efficient light source available. In the manufacture of high-brightness light-emitting elements capable of operating throughout the visible spectrum, current material systems of interest include Group III to V semiconductors, especially binary, ternary and quaternary alloys of gallium, aluminum, indium and nitrogen (also Known as the Group III nitride material). Typically, a semiconductor layer having a stack of different compositions and dopant concentrations is epitaxially grown by organometallic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or other epitaxial techniques. A group III nitride light-emitting element is produced by using sapphire, germanium carbide, group III nitride or other suitable substrate. The stack generally includes one or more light-emitting layers formed on the substrate, such as one or more n-type layers doped with Si, formed on one of the n-type layers, and formed in the function The region is doped, for example, with one or more p-type layers of Mg. Electrical contacts are formed on the n-type and p-type regions.

LEDs are typically mounted on a carrier and packaged to protect the LED from environmental damage and mechanical damage. Conventionally, LED chips are mounted on a carrier one at a time. That is, each LED is individually mounted to, for example, a printed circuit board Or a reflector on the cup. In addition, the pinch joints are connected to the respective LED wafers in a conventional manner. These operations are expensive and time consuming and require a lot of manpower and/or special equipment.

US 2008/0142817 describes a "wafer level" method for packaging LEDs. "Wafer level" means bonding an LED wafer to a carrier substrate on a wafer level. One of the elements formed by the method of US 2008/0142817 is shown in FIG. A substrate wafer on which a plurality of diodes 160 are formed is bonded to a carrier substrate 200 on which a plurality of bonding pads 240 are formed. One of the metal stacks 260 on each of the diodes is bonded to one of the bond pads 240 on the carrier substrate 200. The growth substrate can be removed after bonding the wafer to the carrier substrate 200. A plurality of via holes 22A and 22B may be formed in the carrier substrate, and then metal or other conductive material electrically connected to the bonding pads 28A, 28B on the back side of the substrate 200 (ie, opposite to the diode 160). The via holes 22A and 22B are plated or filled. A passivation layer 320 may be formed on the upper surface of the substrate 200 adjacent to the diode 160 and patterned to expose at least a portion of one of the electrodes on one surface of the diode 160 and the via hole 22B (then, Metal interconnects 330 cover at least a portion of via holes 22B, as described below. The via holes 22A and 22B are electrically isolated from each other (again, the bond pads 28A and 28B are isolated from each other). A metal interconnect 330 can be formed using conventional techniques, such as evaporation, to connect the conductive via 22B to the exposed electrode of the diode 160. The finished components can then be separated to provide individual package components.

It is an object of the present invention to provide an inexpensive wafer level process for attaching a wafer of a semiconductor light emitting element to a die, such as a germanium wafer.

Embodiments of the invention include a wafer and an adhesive sheet. The wafer includes a plurality of light emitting elements, and each of the light emitting elements includes a light emitting region disposed between an n-type region and a p-type region. A first conductive pad is electrically connected to the n-type region. A second conductive pad is electrically connected to the p-type region. An electrically insulating bonding layer is disposed between the wafer and the adhesive sheet. An opening aligned with the first and second conductive pads is formed in the electrically insulating bonding layer.

A method in accordance with an embodiment of the present invention includes forming an electrically insulating bonding layer on one of a wafer and a die. The wafer includes a plurality of light emitting elements, and each of the light emitting elements includes a light emitting region disposed between an n-type region and a p-type region. A first conductive pad is electrically connected to the n-type region. A second conductive pad is electrically connected to the p-type region. The method further includes attaching the wafer to the adhesive sheet via the electrically insulating bonding layer. After attaching the wafer to the adhesive sheet, at least one opening of the electrically insulating bonding layer is formed to expose at least one of the first conductive pad and the second conductive pad. A conductive material is formed in the opening.

In the method described above with reference to Figure 11, the diode wafer is attached to the carrier substrate by metal bonding that also establishes an electrical connection between the diode and the carrier substrate.

In an embodiment of the invention, one of the semiconductor light emitting elements is attached to a die by an electrically insulating material such as a dielectric bond. The adhesive sheet can be, for example, a partially processed tantalum wafer. An opening is formed in the bonding material to expose an electrical pad on the light emitting elements, and then a conductive material is disposed in the openings. Unlike a metal bond, it can be formed near room temperature The dielectric bonding reduces the internal stress of the bond caused by the difference in thermal expansion coefficient between the wafer and the adhesive sheet of the semiconductor light emitting element.

FIG. 1 illustrates a portion of a wafer of a semiconductor light emitting device. Three light-emitting elements 11A, 11B, and 11C are illustrated in FIG. A complete wafer of semiconductor light emitting elements will typically contain many more light emitting elements. Although a group III nitride LED emitting blue or UV light in the following examples is located under the semiconductor light emitting element, a semiconductor light emitting element other than the LED may be used, such as by other material systems (such as other group III to V materials, group III phosphorous). A laser diode and a semiconductor light-emitting device made of a compound, a group III arsenide, a group II to VI material, a ZnO or a ruthenium-based material.

A semiconductor structure 12 is grown on a growth substrate 10 to form the structure depicted in FIG. The growth substrate 10 can be any suitable substrate such as, for example, sapphire, SiC, Si, GaN, or a composite substrate. The semiconductor structure 12 includes a light-emitting or active region sandwiched between an n-type region and a p-type region. An n-type region may be grown first and may comprise a plurality of layers having different compositions and dopant concentrations, such as, for example, comprising: a preparation layer, such as a buffer layer or a nucleation layer; and/or designed to promote growth of the substrate The removed layer, which may be n-type or unintentionally doped; and an n-type or even a p-type element layer, which is designed to efficiently emit for the particular optical, material or electrical properties desired for the illuminating region Light. A luminescent or active region is grown on the n-type region. Examples of suitable illuminating regions include: a single thicker or thinner luminescent layer; or a multi-quantum well illuminating region comprising a plurality of thinner or thicker luminescent layers separated by a barrier layer. Next, a p-type region can be grown on the light-emitting region. Like the n-type region, the p-type region can comprise multiple layers having different compositions, thicknesses, and dopant concentrations, etc., including unintentional Doped layer, or n-type layer. The total thickness of all of the semiconductor material in the component is less than 10 microns in some embodiments and less than 6 microns in some embodiments.

A metal p-contact is formed on the p-type region. The p-contact may be reflective if a substantial portion of the light is directed outward from the semiconductor structure (such as in a flip-chip element) through a surface opposite the p-contact. Forming a flip-chip element to form a mesa by patterning a semiconductor structure (operating by standard photolithography) and etching the semiconductor structure to remove a portion of the entire thickness of the p-type region and a portion of the entire thickness of the emissive region The mesa reveals one of the n-type regions on which a metal n junction is formed. The mesas and p-contacts and n-contacts can be formed in any suitable manner. The formation of the mesas and p-contacts and n-contacts is well known to those skilled in the art and is no longer shown in FIG. In region 13 between elements 11, semiconductor structure 12 is etched down to an insulating layer, which may be a semiconductor insulating layer that is part of semiconductor structure 12 or substrate 10.

The p and n contacts can be redistributed by stacking one of the insulating layers and the metal (as known in the art) to form large electrical pads 14A and 14B. One of the electrical pads 14A and 14B is electrically connected to the p-type region of the semiconductor structure 12 and the other of the electrical pads 14A and 14B is electrically connected to the n-type region of the semiconductor structure 12. The electrically conductive pad can be any suitable electrically conductive material including, for example, copper, gold, and alloys. In some embodiments, a p-contact and an n-contact are formed, the stack of the contacts is re-distributed, and the electrical pads 14A and 14B are supported to support the semiconductor structure 12 during subsequent removal of the growth substrate 10 to, for example, prevent or reduce semiconductors. Cracking in structure 12. As shown in FIG. 1, a gap 16 electrically isolates the electrical pads 14A and 14B from each other. An insulating material (such as a dielectric, air) can be used. Or any other suitable gas) fill gap 16.

2 is a cross-sectional view of one of the portions of the adhesive sheet 18 that can be attached to the structure of FIG. 1. Figure 3 is a plan view of one of the portions of the adhesive sheet 18. In some embodiments, the adhesive sheet 18 is a wafer. A via hole 22 may be formed through the entire thickness of the crucible 20. The via holes 22 are sized and configured to correspond to the electrical pads 14A and 14B of the structure of FIG. The vias 22 can have substantially vertical sidewalls (as shown) or angled sidewalls. The tantalum sheet 18 can be rendered non-electrical by coating the crucible 20 with a coating 24 which can be formed, for example, by any suitable treatment which includes plasma enhanced chemical vapor deposition or thermal oxidation. Oxide oxide.

In FIG. 4, the wafer of component 11 is attached to the adhesive sheet 18 by a bonding layer 26. Bonding layer 26 can be an electrically insulating material such as a dielectric, benzocyclobutene (BCB), polyfluorene, or any material suitable for attaching the wafer of component 11 to the adhesive sheet 18. The adhesive sheet 18 can contact the wafer of the component 11 or can be separated from the wafer of the component 11 by the bonding layer 26, as depicted in FIG. In some embodiments, the bonding material is disposed on the wafer of the component 11, the adhesive sheet 18, or both the wafer and the adhesive sheet 18. Then, the wafer of the component 11 is aligned with the adhesive sheet 18 to be pressed together. And the bonding layer 26 is cured. Alignment, pressing together, and curing can be performed according to sequential or simultaneous processing steps. Some or all of these steps may be performed at a high temperature. For example, the opening 22 in the adhesive sheet 18 is substantially aligned with the electrical pads 14A and 14B on the component 11 by visual alignment. As shown in FIG. 4, the bonding layer 26 can completely cover the electrical pads 14A and 14B. Accordingly, the bonding layer 26 forms only a mechanical connection between the wafer of the component 11 and the adhesive sheet 18 that is not created by attaching the wafer of the component to the adhesive. Electrical connection. The bonding layer 26 can also be formed such that it fills any gaps or recesses on the surface of the wafer of the component 11 to, for example, prevent contaminants from reaching the component 11 or supporting the component 11 during removal of the layer of the growth substrate 10.

In FIG. 5, the adhesive sheet 18 can be thinned as appropriate, for example, by etching away a portion of the thickness of the germanium wafer 20. For example, one of a 6 inch diameter germanium wafers typically has a thickness of 650 microns. The layer 20 of the adhesive sheet 18 can be thinned to, for example, 200 microns or less in some embodiments, thinned to 150 microns or less in some embodiments, and thinned to 100 microns in some embodiments. Or thinner. The adhesive sheet 18 can be thinned to reduce the thickness of the metal-filled opening 22, as described below with reference to FIG. In some embodiments, the adhesive sheet 18 is thinned such that the thickness of the adhesive sheet 18 is insufficient to mechanically support the element 11. In these embodiments, element 11 is supported by growth substrate 10 during the processing stages illustrated in FIGS. 5 and 6.

Also in FIG. 5, an opening 28 is formed in the electrically insulating bonding layer 26 to expose the electrical pads 14A and 14B. The opening 28 can be formed by conventional masking, patterning, and etching by any suitable technique, including, for example, plasma etching. In some embodiments, the adhesive wafer 20 and its preformed opening 22 are sufficient to act as a hard mask to act as a patterned protective layer defining the opening 28. The opening 22 is formed using an anisotropic etch chemistry, such as reactive ion etching or inductively coupled plasma etching, such that further processing of the fill metal is possible.

For the sake of clarity, only a single component 11 is illustrated in Figures 6, 7, 8, 9, and 10. It should be understood that the structures depicted in these figures can be formed on one of the elements 11 wafers. Accordingly, it can be repeated multiple times in the entire wafer of the component 11. The structure depicted in these figures is repeated.

In Figure 6, a conductive seed layer 30 is formed on the bottom surface of the structure (in the orientation depicted in Figure 6). A seed layer 30 is also formed on the sidewalls of the opening 22 and the exposed surface of the layer 20. The seed layer 30 can be, for example, a single metal, an alloy, or a metal stack. Examples of suitable materials include Cu, Au, Ti, and TiW. In one example, the seed layer 30 comprises a TiW barrier/adhesive layer and a Cu layer. Examples of suitable thicknesses include 50 nm to 100 nm TiW and 0.5 micron to 1 micron Cu. The seed layer 30 can be formed by any suitable process which includes, for example, sputtering, evaporation or a deposition process such as CVD. The seed layer 30 is in direct electrical contact with the electrical pads 14A and 14B. The seed layer 30 forms the base layer of the via fill process illustrated in FIG.

Also in FIG. 6, a top layer 32 is formed over portions of the seed layer 30, and the seed layer 30 is located on the bottom surface of the layer 20 (in the orientation shown). The top layer 32 can be, for example, an electrically insulating material such as a dielectric, an organic layer, polyimide, BCB or epoxy. The top layer 32 can be formed by any suitable treatment, which includes, for example, roll coating. The top layer prevents the conductive material formed in the via holes of FIG. 7 from being formed on the germanium layer 20.

In FIG. 7, a conductive material 34 is formed in the opening 22 of the adhesive sheet 18. Conductive material 34 can be a metal such as Cu formed by any suitable process that includes electroplating. During plating, the metal only adheres to the conductive surface, such as the exposed surface of the seed layer 30. Since the top layer 32 is electrically insulative, no metal adheres to the top layer 32; accordingly, no metal is electroplated onto the tantalum layer 20. The conductive material 34 can completely fill the opening 22 (as shown in FIG. 7), or the conductive material 34 can be isomorphically coated in contact with the electrical pads 14A and 14B. The seed layer 30 on the sidewalls of the opening 22 is such that the opening 22 is only partially filled. In the configuration depicted in FIG. 7, conductive metal 34 is disposed directly beneath the opening formed in bonding material 26 to expose electrical pads 14A and 14B. In some embodiments, the conductive material 34 in an alternate configuration can be formed by forming an equi-top layer 32 on the bottom surface of the structure; then, patterning the top layer 32 in the region where the conductive material 34 is desired The seed layer 30 is exposed.

In FIG. 8, portions of seed layer 30 and top layer 32 on the bottom surface of germanium layer 20 are removed by any suitable process, such as etching. A layer of insulating material 36, such as a solder resist, photoimageable solder resist (PI) or BCB, is applied to the bottom surface of the structure and then patterned to form openings that are aligned with the conductive material 34. The layer of insulating material 36 electrically isolates the semiconductor germanium layer 20, defining the location of the pads 38 and creating stress relief between the pads 38 and the germanium layer 20. Examples of thicknesses suitable for this insulating material 36 are up to 50 microns to 100 microns for BCB 5 microns and for more conventional thin plate laminated solder resist materials. Next, the pad 38 is formed in the opening of the insulating material 36. Pad 38 can be, for example, a conductive material such as an inert, solderable or solder layer suitable for attachment to other substrates, such as printed circuit boards.

In FIG. 9, the growth substrate 10 is removed (as shown in FIG. 9) or thinned as appropriate. In other embodiments, the growth substrate 10 can remain part of the final component. The growth substrate 10 is removed or thinned by any process suitable for the particular growth substrate material, such as laser lift-off, etching, or a mechanical technique (such as grinding) for a sapphire substrate. After the growth substrate is removed, the top surface of the semiconductor structure 12 and the bonding layer 26 in the region 13 between the components are exposed. The top surface of the semiconductor structure 12 may be roughened or patterned as appropriate to, for example, improve the light extraction take. One or more optional additional layers 40 (such as a wavelength conversion layer, a filter layer, a dichroic layer, a lens, or other optical device) may be formed on the growth substrate (if present) or the semiconductor structure 12 (if the growth substrate has been removed) Except). An optional additional layer can be in contact with the structure (as depicted in Figure 9) or spaced from the top surface of the structure.

Next, individual components of the completed structure can be tested as appropriate. The structure can then be cut into individual elements 11 or groups of elements 11 by any suitable technique.

FIG. 10 illustrates an alternate embodiment of the present invention in which an integrated electrical function is formed in the germanium wafer 20 of the adhesive sheet 18. For example, the germanium wafer can be processed to form integrated circuit 42 and via 22 . The integrated circuit 42 can be, for example, an electrostatic protection diode such as a Zener diode. Other circuitry may be included in some embodiments, such as, for example, a switch for selecting a portion of a single component or an array of components to be driven, or a driver. The formation of such a component in a germanium wafer is well known to those skilled in the art. As shown in FIG. 10, an integrated circuit can be formed in the region of the germanium wafer 20 disposed between the electrical pads 14A and 14B. Since the wafer 20 has been thinned in FIG. 5, the circuit 42 can be formed in the top portion of the germanium layer 20.

Direct contact of the electrical contacts 44 on the adhesive sheet 18 to the circuitry 42 can be formed prior to bonding. Electrical contacts 44 may be formed on vias 22 in germanium wafer 20. Next, a seed layer 30 is deposited in the via holes 22 as described in FIG. The seed layer 30 is in electrical contact with the electrical contacts 44. Additional via holes 22 that are in electrical contact with circuit 42 can be formed. In the example depicted in FIG. 10, circuit 42 is connected in series between electrical pads 14A and 14B. The first side of circuit 42 is coupled to electrical pad 14A via conductive materials 34B and 34A. The second side of circuit 42 It is connected to the electrical pad 14B through the conductive materials 34C and 34D.

Although the invention has been described in detail, it is understood by those skilled in the art that the invention may be modified without departing from the spirit of the invention described herein. Therefore, the scope of the invention is not intended to be limited to the particular embodiments shown and described.

10‧‧‧ Growth substrate

11‧‧‧ components

11A‧‧‧Lighting elements

11B‧‧‧Lighting elements

11C‧‧‧Lighting elements

12‧‧‧Semiconductor structure

13‧‧‧ District

14A‧‧‧Electrical mat

14B‧‧‧Electrical mat

16‧‧‧ gap

18‧‧‧Adhesive

20‧‧‧矽 Wafer/Layer/Adhesive Wafer

22‧‧‧Medium hole/opening

22A‧‧‧Interlayer hole

22B‧‧‧Interlayer hole

24‧‧‧Coating

26‧‧‧Connection layer/bonding material

28‧‧‧ openings

28A‧‧‧Material pads

28B‧‧‧Join Mat

30‧‧‧ seed layer

32‧‧‧ top

34‧‧‧Conductive materials/conductive metals

34A‧‧‧Electrical materials

34B‧‧‧Electrical materials

34C‧‧‧Electrical materials

34D‧‧‧Electrical materials

36‧‧‧Insulation materials

38‧‧‧ pads

40‧‧‧Additional layer

42‧‧‧ integrated circuit

44‧‧‧Electrical contacts

160‧‧‧ diode

200‧‧‧ Carrier substrate

240‧‧‧ joint pad

260‧‧‧Metal stacking

320‧‧‧ Passivation layer

330‧‧‧Metal interconnects

FIG. 1 illustrates a portion of a wafer including one of three semiconductor light emitting elements.

Figure 2 depicts a portion of the adhesive sheet.

3 is a top plan view of a portion of the adhesive sheet illustrated in FIG. 2.

4 illustrates the structure of FIG. 1 attached to the structure depicted in FIG. 2.

Figure 5 illustrates the structure of Figure 4 after forming an opening in the bonding material and thinning the adhesive.

Figure 6 illustrates one of the components shown in Figure 5 after forming a seed layer and a top layer.

Figure 7 illustrates the structure of Figure 6 after a metal layer is disposed in the opening.

Figure 8 illustrates the structure of Figure 7 after removal of the top layer and seed layer and formation of the pad.

Figure 9 illustrates the structure of Figure 8 after removing the growth substrate and forming an optional additional layer on the semiconductor light emitting element.

FIG. 10 illustrates a semiconductor light emitting element attached to one of the adhesive sheets including the integrated circuit.

Figure 11 illustrates a prior art semiconductor light emitting element attached to one of the adhesive sheets.

10‧‧‧ Growth substrate

11‧‧‧ components

12‧‧‧Semiconductor structure

14A‧‧‧Electrical mat

14B‧‧‧Electrical mat

18‧‧‧Adhesive

20‧‧‧矽 Wafer/Layer/Adhesive Wafer

22‧‧‧Medium hole/opening

24‧‧‧Coating

26‧‧‧Connection layer/bonding material

Claims (15)

A structure comprising: a wafer comprising: a plurality of light emitting elements, each light emitting element comprising a light emitting region disposed between an n-type region and a p-type region; and electrically connecting to each of the light emitting elements a first conductive pad of the n-type region and a second conductive pad electrically connected to one of the p-type regions of each of the light-emitting elements; an adhesive sheet; and an electrically insulating bonding layer disposed on the wafer and the adhesive Between the sheets, an opening aligned with the first and second conductive pads is formed in the electrically insulating bonding layer. The structure of claim 1, wherein the electrically insulating bonding layer separates the wafer from the adhesive sheet. The structure of claim 1, further comprising a metal disposed in the openings. The structure of claim 1, wherein the adhesive sheet comprises a single wafer. The structure of claim 1, wherein the first conductive pad and the second conductive pad are formed on the same side of the wafer. The structure of claim 1, wherein the plurality of light emitting elements are group III nitride light emitting diodes and the wafer comprises a growth substrate for one of the group III nitride light emitting diodes. The structure of claim 1, further comprising a circuit component disposed in the adhesive sheet, wherein the circuit component is electrically connected to the plurality of light emitting At least one of the components. A method comprising: forming an electrically insulating bonding layer on one of a wafer and a bonding sheet, the wafer comprising: a plurality of light emitting elements, each of the light emitting elements comprising an n-type region and a p-type a light-emitting region between the regions; and a first conductive pad electrically connected to one of the n-type regions of each of the light-emitting elements; and a second conductive pad electrically connected to one of the p-type regions of each of the light-emitting elements; Attaching the wafer to the adhesive sheet; after attaching the wafer to the adhesive sheet, forming at least one opening in the electrically insulating bonding layer to expose the first conductive pad and the At least one of the second conductive pads; and forming a conductive material in the opening. The method of claim 8, wherein the adhesive layer comprises: a stack of wafers; and a plurality of via holes extending through the entire thickness of the germanium wafer, wherein the vias are The second conductive pads are aligned. The method of claim 8, wherein the electrically insulating bonding layer is one of a dielectric and a BCB. The method of claim 8, wherein the electrically insulating bonding layer separates the wafer from the adhesive sheet after attachment. The method of claim 8, further comprising forming a conductive seed layer in the at least one opening. The method of claim 12, further comprising forming an electrically insulating top layer to partially isolate one of the electrically conductive seed layers. The method of claim 12, wherein forming a conductive material comprises plating a metal onto the conductive seed layer. The method of claim 8, further comprising cutting the wafer and the adhesive sheet.