TW201315296A - Circuit board and manufacturing method thereof - Google Patents

Abstract

A method for manufacturing a circuit board is provided. The method includes adhering a first metal foil layer and a second metal foil layer by an adhesion layer; laminating first dielectric layers and third metal foil layers on the first metal foil layer and the second conductive layer, respectively; forming first vias in the first dielectric layers, wherein the first vias connect to the first metal foil layer and the second metal foil layer, respectively; performing a semi-additive process to form first circuit layers on the first dielectric layers, respectively, wherein the first circuit layers connect to the first vias; laminating second dielectric layers and a fourth metal foil layers on the first dielectric layers; forming a second vias in the second dielectric layers and the fourth metal foil layers, wherein the second vias connect to the first circuit layers; separating the first metal foil layer and the second metal foil layer; and patterning the first metal foil layer, the second metal foil layer and the fourth metal foil layers.

Description

Circuit board and manufacturing method thereof

The present invention relates to a circuit board and a method of fabricating the same, and more particularly to a circuit board including a fine circuit and having high reliability and a method of fabricating the same.

In recent years, with the rapid development of electronic technology, the high-tech electronics industry has come out one after another, making more humanized and better-functioning electronic products constantly innovating and designing towards light, thin, short and small trends. A circuit board having conductive lines is usually disposed in these electronic products.

In order to increase the wiring density in the wiring board, a substrative process may be used to fabricate the wiring layer in the wiring board to have a line width of 40 μm or more. However, for line widths below 40 μm, the use of a subtractive process to fabricate the wiring layer will result in a reduction in product yield. Therefore, a circuit layer having a line width of 40 μm or less is currently produced by a semi-additive process (SAP) or a modified semi-additive process (MSAP).

However, the copper foil used has a low roughness (center line average roughness (Ra) and ten point average roughness (Rz) in the process of fabricating the wiring layer in a semi-additive process or an improved semi-additive process. ), the adhesion between the circuit layer and the dielectric layer is reduced, resulting in the outermost circuit layer being easily peeled off from the dielectric layer, thereby reducing the reliability of the circuit board.

The present invention provides a method of fabricating a circuit board for fabricating a circuit board including fine wiring and having high reliability.

The present invention further provides a wiring board that includes fine wiring and has high reliability.

The invention provides a method for manufacturing a circuit board, which firstly bonds a first metal foil layer and a second metal foil layer by a glue layer. Then, the first dielectric layer and the third metal foil layer are respectively pressed onto the first metal foil layer and the second metal foil layer. Then, a first via hole is respectively formed in the first dielectric layers, wherein the first via holes respectively connect the first metal foil layer and the second metal foil layer. Then, a semi-addition process is performed to form a first circuit layer on the first dielectric layers, wherein the first circuit layer is connected to the first via holes. Then, the second dielectric layer and the fourth metal foil layer are respectively pressed onto the first dielectric layers. Then, a second via hole is formed in each of the second dielectric layer and the fourth metal foil layer, wherein the second via hole is connected to the first circuit layer. Next, the first metal foil layer and the second metal foil layer are separated. Thereafter, the first metal foil layer, the second metal foil layer and the fourth metal foil layer are patterned and the second metal foil layer and the sixth metal foil layer are patterned to form two separate wiring boards.

According to the manufacturing method of the circuit board according to the embodiment of the present invention, the adhesive layer is located, for example, at the periphery of the first metal foil layer and the second metal foil layer to form a closed space with the first metal foil layer and the second metal foil layer. .

According to the manufacturing method of the circuit board according to the embodiment of the invention, the shape of the glue layer is, for example, a continuous frame pattern.

According to the manufacturing method of the circuit board according to the embodiment of the invention, the shape of the glue layer is, for example, a discontinuous frame shape.

According to the method of fabricating a circuit board according to the embodiment of the invention, the thickness of the third metal foil layer is, for example, smaller than the thickness of the first metal foil layer, the second metal foil layer and the fourth metal foil layer.

According to the manufacturing method of the circuit board according to the embodiment of the invention, the thickness of the third metal foil layer is, for example, between 2 μm and 5 μm.

According to the manufacturing method of the circuit board of the embodiment of the present invention, after the forming the first circuit layer and before pressing the second dielectric layer and the fourth metal foil layer, forming at least the first dielectric layer A stacked line structure.

According to the method for fabricating a circuit board according to the embodiment of the invention, the method for forming the stacked circuit structure is, for example, first pressing the third dielectric layer and the fifth metal foil layer onto the first dielectric layer. Then, a third via hole is formed in each of the third dielectric layers, wherein the third via hole is connected to the first circuit layer. Thereafter, a semi-additive process is performed to form a second circuit layer on the third dielectric layers, wherein the second circuit layer is connected to the third via.

According to the method of fabricating a circuit board according to the embodiment of the invention, the thickness of the fifth metal foil layer is, for example, smaller than the thickness of the first metal foil layer, the second metal foil layer and the fourth metal foil layer.

According to the manufacturing method of the circuit board according to the embodiment of the invention, the thickness of the fifth metal foil layer is, for example, between 2 μm and 5 μm.

The present invention further provides a wiring board including at least one first stacked wiring structure, a second stacked wiring structure, and a third wiring layer. The first line structure includes a first dielectric layer, a first via, and a first wiring layer. The first dielectric layer has a first surface and a second surface opposite to each other. The first via hole is disposed in the first dielectric layer. The first circuit layer is disposed on the first surface and connected to the first via hole. The first circuit layer includes a first rolled metal foil layer and a first plated conductive layer on the first rolled metal foil layer. The second line structure is disposed on the first surface. The second line structure includes a second dielectric layer, a second via, and a second wiring layer. The second dielectric layer is disposed on the first surface and covers the first circuit layer. The second circuit layer is disposed on the second dielectric layer. The second circuit layer includes a second rolled metal foil layer and a second plated conductive layer on the second rolled metal foil layer. The second via hole is disposed in the second dielectric layer and the second circuit layer, and is connected to the first circuit layer. The third circuit layer is disposed on the second surface and connected to the first via hole. The third circuit layer includes a third rolled metal foil layer. The thickness of the first rolled metal foil layer is less than the thickness of the second rolled metal foil layer and the third rolled metal foil layer, and the thickness of the first plated conductive layer is greater than the thickness of the second plated conductive layer.

According to the circuit board of the embodiment of the invention, the roughness of the surface of the second rolled metal foil layer facing the second dielectric layer and the surface of the third rolled metal foil layer facing the first dielectric layer For example, greater than 3 μm.

According to the circuit board of the embodiment of the present invention, the roughness of the surface of the second rolled metal foil layer facing the second dielectric layer and the center line of the surface of the third rolled metal foil layer facing the first dielectric layer The average roughness and the ten point average roughness are, for example, greater than 3 μm.

According to the circuit board of the embodiment of the invention, the roughness of the surface of the first rolled metal foil layer facing the first dielectric layer is, for example, less than or equal to 3 μm.

According to the circuit board of the embodiment of the invention, the center line average roughness and the ten point average roughness of the surface of the first rolled metal foil layer facing the first dielectric layer are, for example, less than or equal to 3 μm.

According to the circuit board of the embodiment of the invention, the thickness of the first rolled metal foil layer is, for example, between 2 μm and 5 μm.

According to the circuit board of the embodiment of the invention, the first via hole and the third circuit layer have an interface.

According to the circuit board of the embodiment of the invention, the second via hole and the second electroplated conductive layer in the second circuit layer have no interface.

According to the circuit board of the embodiment of the present invention, the at least one first stacked line structure includes a plurality of first stacked line structures stacked on each other, and the second stacked line structure is disposed on the first stacked line structure of the uppermost layer. On one surface, the third circuit layer is disposed on the second surface of the lowermost first stacked wiring structure.

Based on the above, the present invention utilizes a semi-additive process to form an inner layer circuit layer, thereby enabling the circuit layer to meet the requirements of high wiring density. In addition, the present invention utilizes a subtractive process to form a circuit layer of the outermost layer. Since the circuit layer includes a metal foil layer having a high roughness, the outermost circuit layer can be effectively prevented from being peeled off from the dielectric layer, thereby improving the circuit board. Reliability.

The above described features and advantages of the present invention will be more apparent from the following description.

1A-1G are cross-sectional views showing a manufacturing process of a circuit board according to an embodiment of the invention. First, referring to FIG. 1A, the metal foil layer 100 and the metal foil layer 200 are bonded by the adhesive layer 300. The metal foil layers 100, 200 are, for example, copper foil layers. The surface of the metal foil layers 100, 200 facing the subsequent press-fit (i.e., the surfaces 100a, 200a) has, for example, a roughness greater than 3 μm. Further, the center line average roughness (Ra) and the ten point average roughness (Rz) of the surfaces 100a, 200a are, for example, greater than 3 μm. For the definition and measurement method of the above roughness, reference may be made to the contents of Japanese Industrial Standard JIS B 0601. The metal foil layers 100, 200 are generally referred to as rolled metal foil layers.

Further, the adhesive layer 300 is located at the periphery of the metal foil layer 100 and the metal foil layer 200 to form a closed space R with the metal foil layer 100 and the metal foil layer 200. For example, the glue layer 300 can be a continuous frame pattern (please refer to FIG. 1A(a)). This continuous frame pattern encloses a flat closed space R with the metal foil layer 100 and the metal foil layer 200. In this way, in the subsequent wet process (such as development, etching, cleaning, etc.), foreign objects (such as developer, etching solution, cleaning agent, etc.) are not easily passed through the adhesive layer 300 and enter the closed space R, which can be avoided. Damage is caused to the metal foil layer 100 and the metal foil layer 200. In the present embodiment, the material of the adhesive layer 300 is, for example, a solder resist ink, a chemical resistant tape or a pure rubber material, and the width thereof is, for example, 12 mm. It should be noted that, in another embodiment (please refer to FIG. 1A(b)), the glue layer 300 may also be a discontinuous frame pattern. That is, a plurality of air guiding holes H (at least 6 or more) are present in the discontinuous frame pattern, wherein each of the air guiding holes H has a length of, for example, 10 mm to 15 mm, and a width of, for example, 1 mm. Up to 3 mm.

Then, referring to FIG. 1B, the dielectric layer 102 and the metal foil layer 104 are pressed onto the metal foil layer 100 and the metal foil layer 200. The metal foil layer 104 is, for example, a copper foil layer whose surface facing the dielectric layer 102 has, for example, a roughness of less than or equal to 3 μm. Further, the center line average roughness (Ra) and the ten point average roughness (Rz) of the surface of the metal foil layer 104 facing the dielectric layer 102 are, for example, less than or equal to 3 μm. Likewise, the metal foil layer 104 is generally referred to as a rolled metal foil layer. Further, in the present embodiment, the thickness of the metal foil layer 104 is smaller than that of the metal foil layers 100, 200. The thickness of the metal foil layer 104 is, for example, between 2 μm and 5 μm. Therefore, the metal foil layer 104 is also generally referred to as an ultra-thin copper skin. Thereafter, via holes 106 are formed in the dielectric layer 102. The method of forming the via hole 106 is, for example, a laser drilling process in which a blind hole exposing a portion of the metal foil layer 100 and the metal foil layer 200 is formed in the metal foil layer 104 and the dielectric layer 102. The conductive material is then filled into these blind vias by electroplating or other means.

Next, referring to FIG. 1C, a patterned mask layer 108 is formed on the metal foil layer 104. The patterned mask layer 108 exposes areas of the predetermined wiring. It should be noted that the area on and below the glue layer 300 does not belong to the area of the predetermined wiring. Conductive layer 110 is then formed in the area exposed by patterned mask layer 108. In the present embodiment, the conductive layer 110 is formed, for example, by electroplating. Metal foil layer 110 is generally referred to as an electroplated conductive layer.

Then, referring to FIG. 1D, the patterned mask layer 108 is removed. The metal foil layer 104 under the patterned mask layer 108 is then removed. In the present embodiment, the metal foil layer 104 is removed, for example, by etching. In this step, after removing the metal foil layer 104 under the patterned mask layer 108, the conductive layer 110 and the metal foil layer 104 therebelow constitute the wiring layer 112. The wiring layer 112 is connected to the via hole 106. Moreover, after removing the metal foil layer 204 below the patterned mask layer 208, the metal foil layer 210 and the metal foil layer 204 therebelow constitute the wiring layer 212. The wiring layer 212 is connected to the via 206.

The steps of Figures 1C through 1D above are generally referred to as modified semi-additive processes (MSAP). Of course, in other embodiments, a semi-additive process (SAP) or a primer-coated foil for semi-additive process (PSAP) may also be used. A wiring layer 112 is formed. In particular, the wiring layer 112 formed of MSAP, SAP or PSAP may have a line width of 40 μm or less, and thus can meet the demand for high wiring density.

Next, referring to FIG. 1E , the dielectric layer 114 and the metal foil layer 116 are pressed onto the dielectric layer 102 and cover the circuit layer 112 . The metal foil layer 116 is, for example, a copper foil layer whose surface facing the dielectric layer 114 has, for example, a roughness of more than 3 μm. Further, the center line average roughness (Ra) and the ten point average roughness (Rz) of the metal foil layer 116 are, for example, greater than 3 μm. Likewise, the metal foil layer 116 is generally referred to as a rolled metal foil layer. Further, the thickness of the metal foil layer 116 is greater than the thickness of the metal foil layer 104. Then, via holes 118 are formed in the dielectric layer 114 and the metal foil layer 116. The via hole 118 is formed by, for example, performing a laser drilling process to form a blind via in the metal foil layer 116 and the dielectric layer 114 to expose a portion of the conductive layer 110. Then, these blind holes are filled with a conductive material by electroplating. In addition, the conductive layer 120 is simultaneously formed on the metal foil layer 116 during the plating process. Likewise, conductive layer 120 is generally referred to as an electroplated conductive layer.

In addition, after performing the above steps, the conductive layer 120 and the metal foil layer 116 on the dielectric layer 114 may be thinned to make the thickness of the film on the dielectric layer 114 meet the requirements.

In particular, the thickness of the conductive layer 120 is less than the thickness of the conductive layer 110 in order to have substantially the same thickness of each of the circuit layers, and since the thickness of the metal foil layer 116 is greater than the thickness of the metal foil layer 104.

Then, referring to FIG. 1F, the metal foil layer 100 and the metal foil layer 200 are separated to form two stacked structures 10, 20 having the same or similar structures. There are many ways to separate the metal foil layer 100 from the metal foil layer 200. For example, in the embodiment, the adhesive layer 300 and the metal foil layer partially overlapping the adhesive layer 300 may be cut along the plurality of cutting lines Y by, for example, a computer numerical control (CNC) milling technique. 100, metal foil layer 200, dielectric layer 102, wiring layer 112, dielectric layer 114, metal foil layer 116 and conductive layer 120 to separate metal foil layer 100 from metal foil layer 200.

Thereafter, referring to FIG. 1G, the stacking structures 10, 20 are patterned, the portion of the metal foil layer 100 is removed to form the wiring layer 122, and the portion of the conductive layer 120 and the metal foil layer 116 are removed to form the wiring layer 124. The wiring boards 12, 22 are obtained, wherein the wiring layer 122 is connected to the via holes 106, and the wiring layer 124 is connected to the via holes 118.

The steps of Figure 1G above are generally referred to as a subtractive process. Since the circuit layers 122 and 124 formed by the subtractive process include a metal foil layer having a high roughness, the wiring layers can be effectively prevented from being peeled off from the dielectric layer to improve the reliability of the circuit board. In one embodiment, the adhesion strength of the circuit layers 122, 124 can be above 1 kgf/cm ² by tensile testing.

The present invention will be described below by taking the circuit board 12 as an example.

Referring to FIG. 1G, the circuit board 12 includes a first stacked wiring structure (consisting of the dielectric layer 102, the vias 106, and the wiring layer 112) and a second stacked wiring structure (by the dielectric layer 114, the vias 118, and the wiring layer 124). And the circuit layer 122.

In the first stacked wiring structure, the dielectric layer 102 has a first surface 102a and a second surface 102b that are opposite to each other. The via hole 106 is disposed in the dielectric layer 102. The circuit layer 112 is disposed on the first surface 102a and connected to the via hole 106. The wiring layer 112 includes a first rolled metal foil layer (metal foil layer 104) and a first plated conductive layer (conductive layer 110) on the first rolled metal foil layer.

The second stacking line structure is disposed on the first surface 102a. In the second stacked wiring structure, the dielectric layer 114 is disposed on the first surface 102a and covers the wiring layer 112. The wiring layer 124 is disposed on the dielectric layer 114. The wiring layer 124 includes a second rolled metal foil layer (metal foil layer 116) and a second plated conductive layer (conductive layer 120) on the second rolled metal foil layer. The via hole 118 is disposed in the dielectric layer 114 and the wiring layer 124 and is connected to the wiring layer 112.

The circuit layer 122 is disposed on the second surface 102b and connected to the via hole 106. In the wiring board 12, the wiring layer 122 is a third rolled metal foil layer.

In this embodiment, the thickness of the first rolled metal foil layer (metal foil layer 104) is smaller than the thickness of the second rolled metal foil layer (metal foil layer 116) and the third rolled metal foil layer (circuit layer 122), and The thickness of an electroplated conductive layer (conductive layer 110) is greater than the thickness of the second electroplated conductive layer (conductive layer 120).

In addition, in the present embodiment, the via 106 and the wiring layer 122 have an interface 106a, and the via 118 and the plating conductive layer 120 in the wiring layer 124 have no interface.

In the circuit board 12, since the metal foil layer 116 and the wiring layer 122 have higher roughness (roughness greater than 3 μm), the wiring layer 122 can be effectively prevented from being peeled off from the dielectric layer 102 and the wiring layer 124 is prevented from being self-mediated. The electrical layer 114 is stripped, thereby increasing the reliability of the board.

In the present embodiment, the wiring boards 12, 22 are wiring boards having three wiring layers, but the present invention is not limited thereto. In other embodiments, a circuit board having more layers of wiring layers can also be formed in a similar manner.

2A-2D are cross-sectional views showing a manufacturing process of a circuit board according to another embodiment of the present invention. First, referring to FIG. 2A, after the steps described in FIG. 1D, the same steps as those of FIG. 1B to FIG. 1D are performed, and a dielectric layer 126, a metal foil layer 128, a conductive layer 130, and a conductive layer are formed on the dielectric layer 102. The wiring structure formed by the holes 132. Of course, depending on actual needs, the same steps as those of FIGS. 1B through 1D can be repeated to form more layers of inner layer wiring layers.

Next, referring to FIG. 2B, the same steps as in FIG. 1E are performed to form a dielectric layer 114, a metal foil layer 116, a conductive layer 120, and via holes 118 on the dielectric layer 126.

Then, referring to FIG. 2C, the same steps as those of FIGS. 1F to 1G are performed to obtain the wiring boards 14, 24. In the present embodiment, the circuit boards 14, 24 are circuit boards having four circuit layers, and have a stack structure similar to the circuit boards 12, 22, which will not be described herein.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 20. . . Stack structure

12, 14, 22, 24. . . circuit board

100, 104, 116, 128, 200, 204, 210, 216, 220, 228, 230. . . Metal foil layer

100a, 200a. . . surface

102, 114, 126, 202, 214, 226. . . Dielectric layer

102a. . . First surface

102b. . . Second surface

106, 118, 132, 206, 218, 232. . . Via

106a. . . interface

108, 208. . . Patterned mask layer

110, 120, 130. . . Conductive layer

112, 122, 124, 212, 222, 224. . . Circuit layer

300. . . Glue layer

H. . . Air vent

R. . . Closed space

Y. . . Cutting line

1A-1G are cross-sectional views showing a manufacturing process of a circuit board according to an embodiment of the invention.

2A-2C are cross-sectional views showing a manufacturing process of a circuit board according to another embodiment of the present invention.

12, 22. . . circuit board

104, 116. . . Metal foil layer

102, 114. . . Dielectric layer

102a. . . First surface

102b. . . Second surface

106, 118. . . Via

106a. . . interface

110, 120. . . Conductive layer

112, 122, 124. . . Circuit layer

Claims (19)

A method for manufacturing a circuit board, comprising: bonding a first metal foil layer and a second metal foil layer by a glue layer; respectively pressing a first dielectric layer and a third metal foil layer to the first a first conductive via is formed in each of the first dielectric layers, and the first conductive vias are respectively connected to the first metal foil layer and the second metal foil layer And performing a semi-addition process to form a first circuit layer on the first dielectric layers, wherein the first circuit layers are connected to the first via holes; and a second dielectric layer is The second metal foil layer is respectively pressed onto the first dielectric layers; a second via hole is formed in each of the second dielectric layer and the fourth metal foil layer, wherein the second via holes are formed. Connecting the first circuit layers; separating the first metal foil layer and the second metal foil layer; and patterning the first metal foil layer, the second metal foil layer and the fourth metal foil layers to Form two separate circuit boards. The manufacturing method of the circuit board of claim 1, wherein the adhesive layer is located at a periphery of the first metal foil layer and the second metal foil layer, and the first metal foil layer and the second metal The foil layer forms an enclosed space. The method for fabricating a circuit board according to claim 2, wherein the adhesive layer has a continuous frame shape. The method for fabricating a circuit board according to claim 2, wherein the adhesive layer has a discontinuous frame shape. The method of manufacturing the circuit board according to the first aspect of the invention, wherein the thickness of the third metal foil layer is smaller than the thickness of the first metal foil layer, the second metal foil layer and the fourth metal foil layer . The method for fabricating a circuit board according to claim 5, wherein the third metal foil layer has a thickness of between 2 μm and 5 μm. The method for fabricating a circuit board according to claim 1, wherein after forming the first circuit layers and before pressing the second dielectric layers and the fourth metal foil layers, At least one stacked wiring structure is formed on the first dielectric layers. The method for fabricating a circuit board according to claim 7, wherein the method for forming the stacked circuit structure comprises: pressing a third dielectric layer and a fifth metal foil layer respectively to the first dielectric layers; a third via hole is formed in each of the third dielectric layers, wherein the third via holes are connected to the first circuit layers; and a semi-additive process is performed for the third dielectric layers A second circuit layer is formed on the electrical layer, and the second circuit layers are connected to the third conductive vias. The manufacturing method of the circuit board of claim 8, wherein the thickness of the fifth metal foil layer is smaller than the thickness of the first metal foil layer, the second metal foil layer and the fourth metal foil layer. . The method for fabricating a circuit board according to claim 9, wherein the fifth metal foil layer has a thickness of between 2 μm and 5 μm. A circuit board comprising: at least one first stacked circuit structure, the first stacked circuit structure comprising: a first dielectric layer having a first surface and a second surface opposite to each other; a first via hole, configured In the first dielectric layer; and a first circuit layer disposed on the first surface and connected to the first via hole, the first circuit layer includes a first rolled metal foil layer and is located at the first a first plating conductive layer on the rolled metal foil layer; a second stacked wiring structure disposed on the first surface, the second wiring structure comprising: a second dielectric layer disposed on the first surface And covering the first circuit layer; a second circuit layer disposed on the second dielectric layer, the second circuit layer comprising a second rolled metal foil layer and a layer on the second rolled metal foil layer a second electroplated conductive layer; and a second via hole disposed in the second dielectric layer and the second circuit layer and connected to the first circuit layer; and a third circuit layer disposed in the second Surface, and connected to the first via hole, the third The road layer includes a third rolled metal foil layer, wherein the first rolled metal foil layer has a thickness smaller than a thickness of the second rolled metal foil layer and the third rolled metal foil layer, and the first conductive conductive layer has a thickness greater than The thickness of the second electroplated conductive layer. The circuit board of claim 11, wherein a roughness of a surface of the second rolled metal foil layer facing the second dielectric layer and a surface of the third rolled metal foil layer facing the first dielectric layer The surface roughness is greater than 3 μm. The circuit board of claim 12, wherein a roughness of a surface of the second rolled metal foil layer facing the second dielectric layer and a surface of the third rolled metal foil layer facing the first dielectric layer The centerline average roughness of the surface and the ten point average roughness are greater than 3 μm. The circuit board of claim 11, wherein a roughness of a surface of the first rolled metal foil layer facing the first dielectric layer is less than or equal to 3 μm. The circuit board according to claim 14, wherein a center line average roughness and a ten point average roughness of the surface of the first rolled metal foil layer facing the first dielectric layer are less than or equal to 3 μm. The circuit board of claim 11, wherein the first rolled metal foil layer has a thickness of between 2 μm and 5 μm. The circuit board of claim 11, wherein the first via hole and the third circuit layer have an interface. The circuit board of claim 11, wherein the second via hole does not have an interface with the second plated conductive layer in the second circuit layer. The circuit board of claim 11, wherein the at least one first stack line structure comprises a plurality of the first stack line structures stacked on each other, and the second stack line structure is disposed on the first layer of the uppermost layer Stacking the first surface of the line structure, and the third circuit layer is disposed on the second surface of the lowermost layer of the first stacked line structure.