TW201301749A - Amplifier - Google Patents

Abstract

The invention relates to a configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit comprises a degeneration inductance whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit comprises a feedback resistance whereby the low noise amplifier circuit operates as a resistive feedback low noise amplifier.

Description

Amplifier

This invention relates to low noise amplifiers. In particular, but not exclusively, the present invention relates to configurable low noise amplifier circuits.

The radio frequency receiver can be configured to operate in many different radio frequency bands. For example, a base station receiver (or cellular telephone device) can be configured to operate in any of the following frequency bands: Global System for Mobile Communications (GSM) 850, 900, 1800, and/or 1900, wideband multiple code access ( WCDMA), High Speed Packet Access (HSPA), and/or Long Term Evolution (LTE) bands 1, 2, 3, and the like. This allows the base station to include such receivers that are used in different areas, where the above radio frequency bands of the varying subset can be supported (eg, to cause roaming).

The receiver basically incorporates one or more radio frequency integrated circuits (RFICs), which include a low noise amplifier (LNA) that acts as a first amplification stage in the receiver. For example, one or more LNAs can be used substantially to amplify the RF signals collected by an antenna, and the amplified signals produced by the LNA can then be used by other components in the receiver.

The receiver basically includes one or more radio frequency (RF) filters disposed between the antenna and the LNA, which form a first amplification stage of the receiver. FIG. 1 shows an exemplary receiver that includes a radio frequency module 100 and an antenna 130. The radio frequency module 100 includes a radio frequency front end module 132, which in turn includes one or more (multiple to all n) radio frequency filters 110-112, which are filtered by The RF signal collected by the antenna 130. The RF module 100 also includes an RFIC 134 that in turn includes one or more (up to all n) LNAs 120-122 that amplify the filtered signals generated by the RF filters 110-112.

It is known from the Friis formula of the noise index that the LNA forming the first amplification stage of the receiver controls the noise index of the receiver. The LNA forming the first stage also has a key role in determining the input impedance of the receiver. The input impedance of this LNA must be carefully matched to the specific impedance, otherwise the performance of the RF filter (eg, 110-112) in front of the LNA will be degraded. In addition, the RF filter prior to the LNA will essentially have a fixed frequency range that would require the input of the LNA to also match that frequency range.

As a result, depending on the LNA structure, it is necessary to use a matching element outside the RFIC including the LNA to appropriately set the input impedance to match the frequency range. However, these external matching components are expensive, and in some cases, it is preferable to use an LNA having internal matching performance to appropriately set its input impedance to match the frequency range.

Another measure of receiver performance is its sensitivity (reference sensitivity level), which measures the minimum detectable signal level at the receiver input. The signal characteristics of the received signal can basically be determined by the bit error rate or yield. The sensitivity level S is determined by: S = -174dBm / Hz + 10log (BW) + SNR _min + NF (1) where -174dBm / Hz is the available noise power density from the input source at a temperature of 290K BW is the channel bandwidth, SNR _min is the necessary signal-to-noise ratio, and NF is the receiver's noise index. For example, SNR _{min is} based on the target bit error rate and the module method used.

The RF filter prior to forming the LNA in the first amplification stage in the receiver has significant insertion loss in some radio frequency bands within which the receiver can be configured to operate. This insertion loss can cause the receiver to be less sensitive, and it has a higher noise index for these RF bands. Because the receiver sensitivity in these RF bands is poor, the range between the transceiver and receiver of the operational receiver is reduced, thus making the cellular network design more challenging and more expensive. Furthermore, the size of the antenna connected to the receiver may be limited due to space limitations in devices such as base stations, which thus limits the performance of the antenna; this can be degraded at lower frequencies, such as below 1 GHz, The size of this antenna tends to become larger due to longer wavelengths. The receiver performance can therefore be degraded, resulting in reduced link performance.

In order to mitigate the above effects, the LNA noise index should be as good as possible. However, the use of external matching components before the LNA and good noise performance with low current consumption is a challenging task. In addition, as with expensive and well-sized external components, the cost of RFCs containing LNAs will also be considered. In order to maintain a small semiconductor die area of the RFIC, the number of inductors on the wafer should be kept to a minimum because high quality inductors require significant grain area and their size does not accompany the feature width of the integrated circuit. Reduced and reduced in size.

It can be seen from the above that when designing the LNA, there are many different design factors to consider, and at the same time accepting some or some of these factors proves to be difficult. Therefore, there is a need to improve LNA design by providing improved ways of accepting various design factors.

According to a first aspect of the present invention, a configurable low noise amplifier circuit is provided, the low noise amplifier circuit being configurable between any of a first topology and a second topology, at the first In the topology, the low noise amplifier circuit includes a degraded inductor, whereby the low noise amplifier circuit functions as an inductively degraded low noise amplifier, and in the second topology, the low noise amplifier circuit includes a feedback resistor Thereby, the low noise amplifier circuit acts as a resistance feedback low noise amplifier. Thus, the present invention allows to provide an inductively degraded low noise amplifier function or a resistive feedback low noise amplifier function via a single low noise amplifier circuit. Only a single-case component that is shared by both topologies is necessary, and such reusable components help to reduce cost and die area.

In an embodiment of the invention, the circuit includes a switching arrangement and is disposed between the first topology and the second topology via the switching arrangement. Thus, depending on the desired characteristics of the circuit, the circuit can be configured in an inductively degraded topology or a resistive feedback topology.

In one embodiment of the invention, the low noise amplifier includes a first input transistor and the degraded inductor includes a degeneration inductor coupled between the first output of the first input transistor and ground. Accordingly, the present invention provides a low noise amplifier topology with associated good noise index and sensitivity performance. Impedance matching is provided via degenerate inductance and one or more external matching elements.

In another embodiment of the invention, the low noise amplifier includes a first input transistor, and the feedback resistor includes a feedback resistor that is coupled to The input of the first input transistor is between the first output of the circuit. In this topology, impedance matching of external matching components is not required, and impedance matching can be provided via an internal feedback resistor.

In some embodiments of the invention, the switching arrangement includes a first topology switching member (or function) coupled between the first output of the first input transistor and ground, and is coupled to the first input transistor A second topology switching member (or function) between the input and the feedback resistor. The circuit can be configured in the first topology by configuring the first and second topological switching members to be in an open state, and the circuit can be configured by configuring the first and second topological switching members to be in a closed state. In the second topology.

In the arrangement of the present invention, the first and/or second topological switching members comprise switching transistors, each switching transistor system being configured to be in an on state by inputting an on state control signal to an input of the individual switching transistor And each switching transistor system is configured to be in a closed state by inputting a shutdown state control signal to an input of the individual switching transistor. Thus, the topology of the circuit can be conveniently configured by applying appropriate control signals (e.g., digital control signals) to a plurality of switching transistors within the circuit.

In an embodiment of the invention, the circuit includes a first series of transistors connected to a second output of the first input transistor and a first output of the circuit. Therefore, the undesired amplification of the input capacitance of the first input transistor to the output of the amplifier is reduced.

In an embodiment of the invention, the circuit includes a decoupling capacitor coupled between the input of the first input transistor and the second topology switching member. Therefore, it can be provided to the first input transistor and the second topology Decoupling of alternating current.

In some arrangements of the invention, the circuit includes a decoupling capacitor coupled between the feedback resistor and an output of the circuit. It is thus possible to provide another decoupling of the alternating current to the second topological switching member.

In other arrangements of the invention, the circuit includes a feedback amplifier coupled between the feedback resistor and the output of the circuit. This provides an additional buffer to improve the performance of the circuit.

In one embodiment of the invention, the first topology includes a capacitor coupled between the first output of the first input transistor and ground. Therefore, the mutual conductance level (including 200, 250, and/or 202) PSRR and/or CMRR metrics can be adjusted.

Embodiments of the invention include circuitry including a configurable load, such as an LC (inductor/capacitor) resonator load, that is coupled to a first output of the circuit. The invention thus allows for the configuration of the transconductance state of the circuit.

In the arrangement of the present invention, when the low noise amplifier circuit is configured in the second topology, the degraded inductor is adapted to provide a power supply noise rejection impedance. Therefore, the degraded inductance of the inductively degraded low noise amplifier topology can be usefully applied to the resistive feedback topology to offset the noise effects of the circuit power supply.

In an embodiment of the invention, the circuit includes a second input transistor, whereby the low noise amplifier circuit includes a differential low noise amplifier circuit. The degraded inductor includes a center tap differential degeneration inductor that is coupled to a first output of the first input transistor, a first output of the second input transistor, and to ground. The feedback resistor includes another feedback resistor coupled to the input of the second input transistor and the second output of the circuit between. Accordingly, the present invention provides a configurable differential amplifier with associated good common mode rejection performance.

In an embodiment of the invention, the first topology switching component is connected between the first output end of the first input transistor and the first output end of the second input transistor, and the circuit includes being connected to the first A third topology switching member (or function) between the input of the two input transistor and the other feedback resistor. The circuit can be configured in the first topology by configuring the first, second, and third topological switching members to be in an open state, and configured to be in a closed state by configuring the first, second, and third topological switching members The circuit can be configured in the second topology. Therefore, a further topology switching component can be used to configure the differential low noise amplifier circuit to an appropriate topology.

In the arrangement of the present invention, when the low noise amplifier circuit is configured in the second topology, the degraded inductor is adapted to provide a common mode signal rejection impedance associated with the input signal to the differential low noise amplifier circuit Shared signal component. Therefore, the degraded inductance of the inductively degraded low noise amplifier topology can be usefully used in the resistance feedback topology to provide the desired common mode signal rejection to a differential amplifier.

In accordance with a second aspect of the present invention, there is provided a radio frequency semiconductor integrated circuit comprising one or more configurable low noise amplifier circuits designed in accordance with a first aspect of the present invention.

In accordance with a third aspect of the present invention there is provided a radio frequency module comprising one or more radio frequency filters coupled to one or more configurable low noise amplifier circuits designed in accordance with a first aspect of the present invention Circuit.

According to a fourth aspect of the present invention, there is provided a device comprising A configurable low noise amplifier circuit designed in accordance with a first aspect of the invention.

According to a fifth aspect of the present invention, there is provided a method of configuring a low noise amplifier circuit, comprising: one of: applying a first set of one or more control signals to the circuit to configure the circuit in the first extension Park, wherein the low noise amplifier circuit includes a degraded inductor, whereby the low noise amplifier circuit acts as an inductively degraded low noise amplifier; or

Applying a second set of one or more control signals to the circuit to configure the circuit in a second topology, wherein the low noise amplifier circuit includes a feedback resistor, whereby the low noise amplifier circuit acts as a resistive feedback Low noise amplifier.

In accordance with a sixth aspect of the present invention, there is provided a configurable low noise amplifier circuit that can be configured between: an internal input impedance matching topology, wherein the low noise amplifier circuit includes One or more internal input impedance matching components adapted to match an input impedance of the low noise amplifier to a known input, the one or more internal input impedance matching components being placed in the low noise amplifier circuit; A topology is different from the internal input impedance matching topology.

The topology different from the internal input impedance matching topology differs from the internal input impedance matching topology in that the topology does not include one or more internal input impedance matching components of the internal input impedance matching topology.

Therefore, when the configurable low noise amplifier circuit is configured for the internal input impedance matching topology, no external matching components are necessary for matching the input impedance of the low noise amplifier to the known input. When configurable low When the noise amplifier circuit is configured in a topology different from the internal input impedance matching topology, one or more external impedance matching components are necessary for matching the input impedance of the low noise amplifier to the known input. .

Further features and advantages of the present invention will become apparent from the following description of the preferred embodiments of the invention.

Several LNA architectures are known, each of which has specific advantages and disadvantages associated with their noise characteristics, total cost, and input matching capabilities.

The first known LNA topology is an inductively degraded LNA topology, which is analyzed in detail in 〝A 1.5-V, 1.5-GHz CMOS low noise amplifier, as proposed by DK Shaeffer and THLee, in solid state. Circuit IEEE J., Vol. 32, No. 5, May 1997, pp. 745-759.

An exemplary inductively degraded LNA circuit will be illustrated in FIG. The LNA of Figure 2 is a differential amplifier where transistors 200 and 210 form the positive or negative + 〞 side of the differential amplifier, and transistors 202 and 212 form the negative or 〝-〞 side of the differential amplifier. The + and - sides of the differential amplifier are each arranged in a tandem configuration, where they are each arranged in a common source configuration of transistors 200 and 202, which respectively form + and - side input transistors, and the transistor 210 and 212 then form a + and - side tandem transistor. In this case, each of the transistors 200, 202, 210, 212 is an enhancement mode n-channel metal oxide semiconductor field effect transistor (MOSFET), (also referred to as NMOS).

The differential amplifier will be applied to its input Input_p 220 with The difference between the two input signals of Input_m 222 is amplified, and the signal applied to the input terminal Input_m 222 is one having the same magnitude as the signal applied to the input terminal Input_p 220 but inverted 180 degrees from the signal. Signals (ie, the signals have opposite phases). The differential amplifier rejects the signal components that are common to both input signals and amplifies the difference between the two signals. The difference amplifier amplifies the difference between the two signals while rejecting the signal component shared by the two input signals, which can be measured by the Common Mode Rejection Ratio (CMRR) metric.

The gate terminal of the input transistor 200 on the + side of the amplifier is connected to a decoupling capacitor 240, which in turn is connected to the outer matching element 230. The input Input_p220 will be connected to the outer matching element 230. The outer matching component 230 will then be placed in a separate circuit or onto a device containing the circuitry of the LNA of Figure 2, i.e., the matching component 230 is external to the wafer (represented by the dashed line in Figure 2) . In this case, the matching component 230 is an inductor.

Also on the - side of the amplifier, the gate terminal of the input transistor 202 is connected to a decoupling capacitor 242, which in turn is connected to the outer matching element 232. The input Input_m 222 is then connected to the outer matching element 232. Again, the matching component 232 will be placed outside the wafer, and in this case an inductor.

The gate terminals of the input transistors 200 and 202 each thus form the input of their respective input transistors. The source and drain terminals of the input transistors 200 and 202 thus form the output of the input transistor.

The source terminals of each of the two input transistors 200, 202 are connected to different respective ends of the inductor 250. Inductor 250 is coupled to each other The center taps the differential inductor device. Inductor 250 provides inductive degradation of the source terminals of the two input transistors 200, 202. The center tap of the inductor 250 is connected to ground.

The drain terminal of the input transistor 200 on the + side of the differential amplifier is connected to the source terminal of the tandem transistor 210. Likewise, the drain terminal of the input transistor 202 on the side of the differential amplifier will be connected to the source terminal of the tandem transistor 212.

Both the gate terminals of the tandem transistors 210 and 212 are connected to the circuit voltage supply Vdd (DC voltage). It is to be noted that the gate terminal DC voltage can be set at a level different from Vdd, so that the gate voltage of the input transistor 200 can be set at a desired level to increase at the top of the tandem transistor 210. The effective voltage swing.

The gate terminals of the tandem transistors 210 and 212 are individually connected to the output terminals Output_p 260 and Output_m 262, where Output_p is the output of the + side of the differential amplifier, and Output_m is the output of the side of the differential amplifier. . The turns of the tandem transistors 210 and 212 are each also connected to a voltage supply Vdd via a configurable load; in this case, the configurable load includes an inductor 280 and a variable capacitor 270 that are connected in parallel. Inductor 280 is a center tap differential inductor device with its center tap connected to voltage supply Vdd. The outputs OUT_p 260 and Output_m 262 of the LNA of Figure 2 are therefore connected to the configurable load.

The noise characteristics of the LNA topology illustrated in Figure 2 are essentially controlled by the noise characteristics of the input transistors 200 and 202. The noise characteristics can be improved by optimizing the input matching network (e.g., including input transistors 200 and 202 and outer matching components 230 and 232). In this topology, the input matching network before the input transistor provides passive voltage gain, which is the voltage swing that can be observed at the gate-to-source junction of the corresponding input transistor (eg, 200). The ratio of the voltage swing on the LNA input is measured. In this context, it is considered to be a high value of the ratio of the Q value of the input matching network, which is effective in reducing the buckling current noise of the input transistor 200, but it increases the sensing gate current of the input transistor. Noise. The most appropriate Q-value can be determined using the following equation:

In equation (2), R _Lin , R _g and R _{s are} each a series resistance of the outer matching element 230, a gate resistance of the input transistor 200, and a source impedance of the transistor 200. The symbols δ, γ, and α are the transistor noise parameters, while Q _in is the Q-value of the input matching network, and f _o and f _T are the operation and unity gain frequencies, respectively. Finally, c is the correlation coefficient between the 汲 extremes of the input transistor 200 and the gate extreme noise.

The inductively degraded LNA of Figure 2 has a relatively good noise index, thereby reducing the noise effects of its subsequent stages in the receiver and providing both current and voltage gain. In general, the noise index of this LNA topology will improve with higher unity gain frequencies. However, as the transistor channel is shortened, the noise parameters γ and α tend to increase. Fortunately, some components can be shaped as the ratio of the noise index γ to α, which can be considered to be fixed; this is a reasonable assumption because the two sources have the same physical source. Therefore, the increase in the noise parameters γ and α due to the short channel effect is not as severe as the inductively degraded LNA input stage. However, inductively degraded LNA topologies require several off-chip mating components 230 and 232, which are and therefore tend to be relatively expensive.

The second known LNA topology is the resistive feedback (or 'shunt resistor') LNA, which has been analyzed in detail by C.-F.Liao and S.-I.Liu. Broadband Noise in the 3.1-10.6-GHz UWB Receiver Eliminates CMOS LNA/Solid State Circuit IEEE J., Volume 42, Number, February 2007, pp. 329-339.

An exemplary resistive feedback LNA circuit will be illustrated in FIG. As for the inductively degraded LNA of Figure 2, the LNA of Figure 3 is a differential amplifier where transistors 200 and 210 form the positive or negative + side of the differential amplifier, and transistors 202 and 212 form a negative or negative of the differential amplifier. -"side.

Figure 3 shows the topology of the resistive feedback LNA similar to Figure 2 inductively degrading the LNA; however, there are several differences:

First, no inductor 250 will appear in the resistive feedback LNA of Figure 3, which would provide inductance degradation of the source terminals of input transistors 200 and 202 in the inductively degraded LNA of Figure 2. Alternatively, the source terminals of the input transistors 200 and 202 of the resistive feedback LNA of Figure 3 are directly connected to ground.

Second, the output terminal Output_p 260 (i.e., the output of the + side of the differential amplifier) is connected via the feedback resistor 300 to the input terminal Input_p 220, that is, the input of the + side of the differential amplifier. Similarly, the output terminal Output_m 262, that is, the output of the side of the differential amplifier, is connected to the input terminal Input_m 222 via the feedback resistor 302, that is, differential amplification. The input of the side of the device. Feedback resistors 300 and 302 can thus each provide resistive feedback to the + and - sides of the differential amplifier.

Third, the important difference between these LNA topologies is the groupable attitude of input matching frequencies. In the resistance feedback topology, the optimal input matching frequency follows the output swing of the output. When the gain on the resistive feedback LNA output is set to the desired frequency by adjusting the resonator load applied to the output, the input match can be observed on the same frequency. This can be understood by calculating the input impedance value of the resistive feedback topology, which is roughly defined by Z _in = (R _fb + Z _L ) / (1 + G _m ^* Z _L ), where R _fb is For feedback resistor values, Z _L is the load impedance and G _m is the mutual conductance of the input device. This would match the input of the inductively degraded LNA topology that would normally be more fixed at a particular frequency.

Finally, none of the outer matching elements 230 and 232 will be provided in the resistive feedback LNA of FIG. The input transistors 200 and 202 can thus be individually connected directly to the Input_p 220 and Input_m 222 terminals via decoupling capacitors 240 and 242, respectively.

The resistive feedback LNA of Figure 3 can be matched to the impedance of the input terminals Input_p 220 and Input_m 222 that are internally connected to the LNA, and no external matching components are needed to match the impedance to which the input terminals Input_p 220 and Input_m 222 are connected ( Here, the impedance to be matched is, for example, the output impedance of the RF filter before the LNA).

No external matching components 230 and 232 are present in the resistive feedback LNA of Figure 3, which would provide passive voltage gain before capacitors 240 and 242, as illustrated by the inductively degraded LNA of Figure 2 above, thus inputting electricity The noise effects of crystals 200 and 202 are not alleviated. In addition, due to the feedback loop between the output terminals 260 and 262 of the LNA and the inputs 220 and 222, there is an additional source of noise in the resistive feedback LNA of FIG. As the resistance of feedback resistors 300 and 302 decreases, the input reference noise from the configurable load and feedback loop increases.

In general, the noise performance of the resistive feedback LNA of Figure 3 is worse than that of the inductively degraded LNA of Figure 2. However, since the resistive feedback LNA of FIG. 3 does not require external matching components 230 and 232 and does not require inductor 250 for inductive degradation, the total cost of the resistive feedback LNA of FIG. 3 is comparable to that of FIG. 2 for inductively degraded LNA. The total cost will be lower.

The present invention relates to an LNA circuit that is disposed between either a first topology and a second topology. In the first topology, the low noise amplifier circuit includes a degraded inductor such that the low noise amplifier The circuit can act as an inductively degraded low noise amplifier, and in the second topology, the low noise amplifier circuit includes a feedback resistor such that the low noise amplifier circuit can act as a resistive feedback low noise amplifier. In the first topology, the outer matching component can be used in conjunction with the LNA for input impedance matching purposes. In the second topology, input impedance matching can be implemented using components within the LNA topology; in the second topology, no external matching components are necessary. Input impedance matching, for example, includes an output impedance that relates to a radio frequency filter that is matched to one or more inputs that are connected to the LNA.

An exemplary configurable LNA circuit designed in accordance with the present invention is shown in FIG. Like the LNAs of Figures 2 and 3, the exemplary LNA of Figure 4 is a differential amplifier where transistors 200 and 210 form a differential amplifier. The positive or '+' side, and transistors 202 and 212 form the negative or '-' side of the differential amplifier.

The topology of the configurable LNA of Figure 4 must include some features similar to those of the inductively degraded low noise amplifier of Figure 2 and the resistive feedback LNA of Figure 3; however, there are several important differences, including the following: First, The configurable LNA of Figure 4 includes a switch arrangement for configuring an LNA between either the first topology and the second topology. The switching arrangement includes a number of topology switching components.

Second, similar to the resistive feedback LNA of FIG. 3, the configurable LNA of FIG. 4 includes a feedback resistor 300 on the + side of the differential amplifier. However, instead of directly connecting the feedback resistor 300 on the differential amplifier + side to the input terminal Input_p 220, it is better to connect the feedback resistor 300 to the topology switching member, in this case switching the transistor 400, which in turn is Connect to the input Input_p 220. One of the 汲 extreme and source terminals of the switching transistor 400 will be connected to the feedback resistor 300 while the other terminal will be connected to the input Input_p 220. The gate terminal of the switching transistor 400 is connected to a configuration control signal terminal 421. The topology switching member 400 will thus be connected between the gate of the input transistor 200 (via the decoupling capacitor 240) and the feedback resistor 300.

Third, similar to the resistive feedback LNA of FIG. 3, the configurable LNA of FIG. 4 includes a feedback resistor 302 on the - side of the differential amplifier. However, instead of directly connecting the feedback resistor 302 on the differential amplifier-side to the input terminal Input_m 222, it is better to connect the feedback resistor 302 to the topology switching member, in this case switching the transistor 402, which in turn is Connect to input Terminal Input_m 222. One of the 汲 extreme and source terminals of the switching transistor 402 will be connected to the feedback resistor 302 while the other terminal will be connected to the input Input_m 222. The gate terminal of switching transistor 402 is coupled to a configuration control signal terminal 423. The topology switching component 402 will thus be connected between the gate of the input transistor 202 (via the decoupling capacitor 242) and the feedback resistor 302.

Fourth, similar to the inductively degraded LNA of FIG. 2, inductor 250 is present in the configurable LNA of FIG.

Fifth, the topology switching member, in this case the switching transistor 410, is connected between the source terminals of the input transistors 200 and 202. One of the 汲 extreme and source terminals of the switching transistor 410 will be connected to the source terminal of the input transistor 200 while the other end will be connected to the source terminal of the input transistor 202. The gate terminal of switching transistor 410 is coupled to configuration control signal terminal 425.

Sixth, decoupling capacitors 430 and 432 each provide decoupling of voltage supply to ground potential for switching transistors 400 and 402.

By applying appropriate configuration control signals to configuration control terminals 421, 423, and 425, switching transistors 400, 402, and 410 can be switched to an on state (by which the configurable LNA of FIG. 4 can be configured for the first topology) And between the closed state (wherein the configurable LNA of Figure 4 can be configured in the second topology). The first and second topologies configured by using the topology switching member will now be explained in more detail.

In the first topology, the switching transistors 400, 402, and 410 can be configured to be in an on state. When in the on state, switching the transistor will provide a high voltage Blocking between its drain and source terminals, it effectively interrupts (or opens) the drain and source terminals. The switching transistor can be placed in an on state by applying an appropriate control signal to the respective configuration control signal terminals such that the voltage between the gate terminal and the source terminal of the switching transistor (ie, voltage Vgs) It can be less than (or approximately less than) the threshold voltage of the switching transistor (i.e., voltage Vt), that is, a switching transistor can therefore be illustrated as being in a cut-off mode. The configuration control signal for configuring the switching transistor to be in an on state may include, for example, a digital 〞0 signal (eg, a signal including a first voltage level).

By configuring switching transistors 400 and 402 to be in an on state, feedback resistors 300 and 302 can each effectively be disconnected from an input signal applied to input terminals Input_p 220 and Input_m 222. As a result, no feedback loops exist between the output terminals Output_p 260 and Output_m and the input terminals Input_p 220 and Input_m 222, respectively.

By configuring the switching transistor 410 to be in an on state, the source terminals of the input transistors 200 and 202 can be effectively connected only via the inductor 250, and their center taps are connected to ground. Inductor 250 can thus provide inductive degradation of the source terminals of input transistors 200 and 202, as in the inductively degraded LNA of FIG.

When the switching transistors 400, 402, and 410 are switched to the on state, that is, when the configurable LNA is configured in the first topology, the configurable LNA thus acts as an inductively degraded LNA.

Therefore, when configured in the first topology, the configurable LNA does not provide internal input impedance matching, for example to be connected to the input Input_p 220 and Matching of the output impedance of the previous RF filter of Input_m 222. As a result, the external impedance matching elements (e.g., the outer matching elements 230 and 232 described in the inductively degraded LNA of FIG. 2) are respectively coupled between the decoupling capacitor 240 and the input terminal Input_p 220 and the decoupling capacitor 242 and input. Between the inputs Input_m 222, the input impedance of the configurable LNA in Figure 4 should, for example, be matched to the previous RF filter.

The first topology of the configurable LNA in Figure 4 thus provides the benefit of the inductively degraded LNA of Figure 2, i.e., a relatively low noise index, but requires the use of external matching components to provide input impedance matching.

In the second topology, the switching transistors 400, 402, and 410 are configured to be in a closed state. When in the off state, the switching transistor provides a low resistance between its drain and source terminals, which effectively connects (or 'shorts') the drain to the source terminal. A switching transistor can be placed in a closed state by applying a configuration control signal to its control signal terminal such that the voltage (ie, voltage _Vgs ) between the gate terminal and the source terminal of the switching transistor is is greater than the threshold voltage (i.e., voltage V _t) of the transistor switch, i.e. switching transistor may therefore be described as shape triode mode. The configuration control signal used to configure a switching transistor to be in a closed state includes, for example, a number '1' (eg, a signal containing a second voltage level).

By configuring switching transistors 400 and 402 to be in a closed state, feedback transistors 300 and 302 are effectively coupled to input terminals Input_p 220 and Input_m 222, respectively. As a result, the feedback loops will each exist between the output terminals Output_p 260 and Output_m and between the input terminals Input_p 220 and Input_m 222 (and thus via decoupling capacitors 240, respectively). The input terminals of the input transistors 200 and 202 of 242).

When the switching transistors 400, 402, and 410 are configured to be in a closed state, that is, when the configurable LNA is configured in the second topology, the configurable LNA thus acts as a resistive feedback LNA.

Thus, when configured in the second topology, the configurable LNA provides internal input impedance matching, such as to the output impedance of the previous RF filter connected to input Input_p 220 and Input_m 222. As a result, the outer matching elements (e.g., outer matching elements 230 and 232 as described in the inductively degraded LNA of Figure 2) are not required when the configurable LNA is configured in the second configuration state.

When the configurable LNA of Figure 4 is configured in the second topology, the switching transistor 410 will be configured to be in an off state; this will provide additional benefits, which will be explained at this time.

By configuring the switching transistor 410 to be in a closed state, the source terminals of the input transistors 200 and 202 are effectively connected (i.e., shorted). By switching the connections formed by the transistors 410 between the source terminals of the input transistors 200 and 202, they are parallel to the inductor 250, which connects the source terminals of the input transistors 200 and 202.

As in the inductively degraded LNA of Figure 2, the inductor 250 is a differential inductor device with mutual coupling. The mutual coupling of the differential inductor devices causes the inductor to operate differently for the common mode signal applied to the differential amplifier as compared to the differential mode signal applied to the differential amplifier.

The common mode signal applied to the differential amplifier is a signal component that is applied to the input terminals Input_p 220 and Input_m 222. The input signal has the same magnitude and the same phase. In contrast, the differential mode signal is a signal component having the same magnitude and opposite phase in the respective input signals applied to the input terminals Input_p 220 and Input_m 222.

With respect to the differential mode signal applied to the input terminals Input_p 220 and Input_m 222, when the configurable LNA is configured in the second topology, by switching between the input terminals of the input transistors 200 and 202 The connection formed by the crystal 410 forms a virtual ground to the differential signal.

However, in relation to the common mode signal applied to the input terminals Input_p 220 and Input_m 222, when the configurable LNA is configured in the second topology, the inductor 230 will remain active to input the transistors 200 and 202. An inductance equal to or less is provided between the source terminal and the ground (which is connected to the center of the inductor 250): (1-k)/2 ^* L _n (3) where k is the mutual coupling of the inductor 250 The coefficient, and L _n , is the nominal inductance based on the electrical length of the inductor 250.

Therefore, when the configurable LNA is configured in the second topology, the inductor 250 (according to equation (3) above) provides an impedance related to the common mode signal, which is used to weaken the ground voltage. Supply of interference and other noise. When configured in the second topology, power supply noise rejection performance, such as controlled by a higher power supply rejection ratio (PSRR) metric of the configurable LNA, is therefore improved. When the configurable LNA is configured in the second topology, the degraded inductance provided by the inductor 250 is thus adapted to provide a power supply rejection impedance.

These improvements in the PSRR metrics are basically only in Figure 2 The induced degradation is seen in the LNA topology. However, by substituting the 'borrowed' inductor 250 from the inductively degraded LNA, the LNA can be configured to cause such improvements in the resistance feedback LNA topology. The 'borrowed' inductor 250 also ensures that the expensive (according to wafer area) wafer elements from the first topology of the configurable LNA can be used in both the configurable LNA architecture.

In addition, when the configurable LNA is architected in the second topology, the inductance associated with the common mode signal provided by the inductor 250 (according to equation (3) above) forms a degraded inductor for inputting the input. The source terminals of crystals 200 and 202. As explained above with respect to the inductively degraded LNA of FIG. 2, this degraded inductor is suitable for improving the rejection performance of the shared mode of the configurable LNA when architected in the second topology, for example by a higher CMRR The metrics are displayed. When the configurable LNA is configured in the second topology, the degraded inductance provided by the inductor 250 is thus adapted to provide a common mode signal rejection impedance that is related to and applied to the inputs Input_p 220 and Input_m 222. Enter the signal component common to the signal.

These improvements in the CMRR metrics are basically only seen in the inductively degraded LNA topology, as shown in Figure 2. However, by omitting the inductor 250 from the inductively degraded LNA of Figure 2, the configurable LNA facilitates such improvements in the resistive feedback LNA topology. The 'borrowed' inductor 250 also ensures that the on-wafer components from the configurable LNA's first topology are expensive (depending on the die area) that will be used in both the configurable LNA architecture.

The configurable LNA of Figure 4 thus provides an LNA that can be configured according to a desired use case or design specification.

If you need a more sensitive LNA with a better noise index, LNA It can be configured in the second topology at the expense of requiring external matching components (e.g., 230 and 232) to provide impedance matching to the input of the configurable LNA.

Alternatively, the LNA can be configured in a second topology to provide a more cost effective approach.

Moreover, when the configurable LNA is configured in the second topology, the use of the inductor 250 can provide PSRR and CMRR that are improved over the LNA on the resistive feedback LNA of FIG. This can result in the reuse of components on the expensive wafer (i.e., inductor 250) that would consume a significant amount of wafer area of the configurable LNA.

The configurable LNA can be configured by its manufacturer or by a third party installing a configurable LNA, such as a device or module; this can include a method of configuring an LNA that includes one or more controls of the first group A signal is applied to the LNA to configure it in the first topology, or a second set of one or more control signals is applied to the LNA to configure it in the second topology. A set of control signals can be applied, for example, to one or more switching transistors.

The configurable LNA of Figure 4 can be implemented in a radio frequency semiconductor integrated circuit (RFIC). The RFIC is included in the RF module and includes an RF filter placed in the RF front-end module prior to the LNA. The RFIC includes input and output pins that can be used to connect external matching components between the configurable LNA and the RF filter. The RFIC may alternatively include one or more RF filters that are connected to one or more configurable LNAs.

The configurable LNA of Figure 4 can be incorporated into many different devices. The device comprises user equipment, such as a base station, a personal digital assistant or a cellular telephone device, etc.; the configurable LNA can be included, for example, in a user setting Prepared in the receiver. Moreover, such a device includes a data machine device to be attached to the user device, such as a universal serial bus data machine. Still further, the device includes a communication module, such as a mechanical-to-mechanical (M2M) module, which can be inserted into another device, such as a laptop or other device having communication capabilities (eg, a vending machine) ). Still further, the apparatus includes a chip set that includes a radio frequency and a fundamental frequency portion.

The above embodiments are to be understood as illustrative examples of the invention. Further embodiments of the invention are conceivable, and here are some examples.

In a first alternative arrangement, the tandem transistors 210 and 212 are not included in the configurable LNA circuit of FIG. In this configuration, on the + side of the differential amplifier, the ? terminal of the input transistor 200 is connected to the output of the configurable LNA Output_p 260 and the configurable load (eg, inductor 280 and variable capacitor 270), Its system will be connected to the voltage supply Vdd. Similarly, on the - side of the differential amplifier, the ? terminal of the input transistor 202 is connected to the output of the configurable LNA Output_m 262, and a configurable load that is connected to the voltage supply Vdd. Omitting the tandem transistors 210 and 212 can degrade the input-output insulation of the present invention and make the Miller effect of the configurable LNA worse; however, this arrangement can still benefit from the other advantages of the configurable LNA of Figure 4 described above. Benefit.

In a second alternative arrangement, only one of the differential amplifiers will be included in the configurable LNA circuit of Figure 4, such as the + side or the - side. In this arrangement, only one input (eg, Input_p 220) and only one output (eg, Output_p) are included in the configurable LNA circuit. In addition, the degeneration inductor 250 is connected to an input transistor of a configurable LNA (eg, For example, between 200) the source terminal and ground. Finally, the source and drain terminals of the switching transistor 410 are connected such that when the switching transistor 410 is turned off, the source terminal of the input transistor 200 is effectively connected to ground. This configuration therefore does not include a differential amplifier and does not benefit from the shared mode rejection capability of the differential amplifier; however, this arrangement will still benefit from the other advantages of the LNA of Figure 4 described above.

An exemplary configurable LNA circuit incorporating a first alternative arrangement and a second arrangement will be shown in FIG. 5, in a first alternative arrangement, the tandem transistor can be omitted, and in the second arrangement, only One side of the differential amplifier of the configurable LNA circuit of Figure 4 will be included. This arrangement will still benefit from the many advantages of the LNA in Figure 4 described above.

In still further alternative embodiments, the switching transistor 410 is not included in the configurable LNA circuit, and the inductor 250 will still be in the circuit in both the first and second topologies of the configurable LNA. Different types of topology switching members can be used with any of the embodiments described above. For example, a p-type and/or a depletion MOSFET can be used with respect to an n-type reinforced module MOSFET. In another embodiment, a bipolar junction transistor can be used.

In a further alternative embodiment, a topology switching member other than a switching transistor can be used, such as a mechanical switch, which can be physically switched to configure the configurable LNA in a desired topology. Alternatively, an electromagnetically operated repeater can be used as a topology switching member.

In another further alternative embodiment, the inductor 250 is not a differential inductor with a center tap connected to ground, but instead is replaced by two inductors. In this case, the first inductor connections of these inductors At the source terminal of the input transistor 200 (on the + side of the differential amplifier) and ground, and the second inductor of these inductors is connected to the source terminal of the input transistor 202 (on the side of the differential amplifier) and to ground between.

Decoupling capacitors 240 and 242 can be omitted from any of the embodiments described above.

A configurable load (eg, a resonator load formed by inductor 280 and variable capacitor 270) can be removed from the circuit or alternatively replaced with another impedance, such as a non-resonator load, a broadband load, an active load, and the like.

In still further alternative embodiments, the configuration control signals applied to configuration control terminals 421, 423, 425 may be provided by an RFIC comprising the configurable LNA of FIG. For example, one or more topology switching components can be used to connect the configuration control terminals 421, 423, 425 to the appropriate voltage supply of the RFIC (eg, Vdd for one configuration, and for another configuration Ground) to configure the LNA in the first topology or the second topology. In another example, one or more non-volatile memory devices can be configured to provide configuration control signals, such as an output of a static random access memory (SRAM) device, a flash memory device, or an electrically erasable device. A configuration control signal is provided in addition to a programmable read only memory (EEPROM) device. The non-volatile memory device can be externally programmed to store appropriate data (eg, '0' bits or '1' bits) to allow the memory device to provide an LNA that can be configured in the first topology. Or the configuration control signal in the second topology. In this case, the method of configuring the LNA includes applying a set of control signals to the LNA by appropriately programming the above non-volatile memory device.

In still another alternative embodiment, in addition to resistive feedback, The feedback loop between the input and output of the configurable LNA circuit can be applied with an amplification stage to provide additional buffering to improve overall circuit performance. An example of such a configurable LNA circuit is illustrated in FIG. 6 includes elements similar to those described in FIG. 4 except that the input of feedback amplifier 600 is coupled to the output of the configurable LNA on the + side of the circuit, and the output of the feedback amplifier is external to drive feedback resistor 300. The system is in turn connected to the gate of the input transistor 200; the feedback amplifier 602 is similarly connected to the feedback loop on the side of the circuit.

Another alternative embodiment includes adding a configurable capacitor to the source terminal of the input transistor of the configurable LNA in addition to the configurable degeneration inductance, such as capacitor 700 as shown in FIG. This allows the resonator frequency at the source terminal to be set at the desired frequency and likewise allows adjustment of the PSRR and/or CMRR metrics.

In an embodiment, the configurable low noise amplifier circuit includes a common output at which the output signal of the configurable low noise amplifier circuit can be configured when configured in the first topology or the second topology provide. The reuse of a single output for the two LNA topologies provides a lower cost solution for configurable RFICs.

In a further embodiment, since the input matching network of the configurable LNA is capable of generating passive gain in the inductive degradation topology, the current consumption in the inductive degradation topology is smaller than in the resistive feedback topology. This means that different bias points for input transistor size or alternating transistor size can be used in different topologies to trade off current consumption and performance.

It should be understood that any of the features described in relation to any of the embodiments Other features may be used alone or in combination, and may be used in conjunction with any one or more of any other embodiments or any other combination of any of the other embodiments. Further, equivalents and modifications which are not described above may be applied without departing from the scope of the invention, which is defined in the appended claims.

100‧‧‧RF Module

110-112‧‧‧RF filter

120-122‧‧‧Low noise amplifier

130‧‧‧Antenna

132‧‧‧RF front-end module

134‧‧‧RF integrated circuit

200, 202‧‧‧ input transistor

210, 212‧‧‧ tandem crystal

230, 232‧‧‧ external matching components

240, 242‧‧‧ Decoupling capacitors

220‧‧‧Input (Input_p)

222‧‧‧ input (Input_m)

250‧‧‧Inductors

260‧‧‧output (Output_p)

262‧‧‧Output (Output_m)

270‧‧‧Variable capacitor

280‧‧‧Inductors

300, 302‧‧‧ feedback resistors

400, 402, 410‧‧‧Switching transistor

421, 423, 425‧‧‧ configuration control signal end

430, 432‧‧‧ decoupling capacitors

600, 602‧‧‧ feedback amplifier

700‧‧‧ capacitor

Figure 1 shows a radio frequency integrated circuit designed in accordance with the prior art.

2 shows an inductively degraded low noise amplifier circuit designed in accordance with the prior art.

Figure 3 shows a resistive feedback low noise amplifier circuit designed in accordance with the prior art.

4 shows a configurable low noise amplifier designed in accordance with an embodiment.

Figure 5 shows a configurable low noise amplifier designed in accordance with an embodiment.

Figure 6 shows a configurable low noise amplifier designed in accordance with an embodiment.

Figure 7 shows a configurable low noise amplifier designed in accordance with an embodiment.

200, 202‧‧‧ input transistor

210, 212‧‧‧ tandem crystal

220‧‧‧Input (Input_p)

222‧‧‧ input (Input_m)

240, 242‧‧‧ Decoupling capacitors

250‧‧‧Inductors

260‧‧‧output (Output_p)

262‧‧‧Output (Output_m)

270‧‧‧Variable capacitor

280‧‧‧Inductors

300, 302‧‧‧ feedback resistors

400, 402, 410‧‧‧Switching transistor

421, 423, 425‧‧‧ configuration control signal end

430, 432‧‧‧ decoupling capacitors

Claims (24)

A configurable low noise amplifier circuit, the low noise amplifier circuit being configurable between: a first topology, wherein the low noise amplifier circuit includes a degraded inductor, whereby the low noise The amplifier circuit acts as an inductively degraded low noise amplifier; and a second topology, wherein the low noise amplifier circuit includes a feedback resistor whereby the low noise amplifier circuit acts as a resistive feedback low noise amplifier. A configurable low noise amplifier circuit as claimed in claim 1, the circuit comprising a switching arrangement, the circuit being configurable between the first topology and the second topology via the switching arrangement . The configurable low noise amplifier circuit of claim 1, wherein the low noise amplifier comprises a first input transistor, and the degraded inductor comprises a first output connected to the first input transistor A degraded inductor between ground and ground. The configurable low noise amplifier circuit of claim 1, wherein the low noise amplifier comprises a first input transistor, and the feedback resistor comprises an input connected to the first input transistor and the circuit A feedback resistor between a first output. The configurable low noise amplifier circuit of claim 3 or 4, wherein the switching arrangement comprises: a first topology switching component coupled to a first output of the first input transistor and Between grounding; and a second topology switching component is coupled between the input end of the first input transistor and the feedback resistor, wherein the circuit can be configured to be turned on by the first and second topological switching members The state may be configured in the first topology, and wherein the circuit is configurable in the second topology by configuring the first and second topology switching members to be in a closed state. The configurable low noise amplifier circuit of claim 5, wherein the first and/or the second topology switching component comprises a switching transistor, wherein the switching signal is input to each of the switching states by setting an on state configuration control signal An input end of the crystal, each of the switching transistors being configurable in the open state; and wherein each of the switching transistors is configurable by inputting a closed state configuration control signal to an input of each switching transistor In the off state. A configurable low noise amplifier circuit as in claim 3, the circuit comprising a first series of transistors connected to a second output of the first input transistor and a first output of the circuit. A configurable low noise amplifier circuit as in claim 5, the circuit comprising a decoupling capacitor coupled between the input of the first input transistor and the second topology switching member. A configurable low noise amplifier circuit as in claim 4, the circuit comprising a decoupling capacitor coupled between the feedback resistor and an output of the circuit. Configurable low noise amplifier power according to item 4 of the patent application scope The circuit includes a feedback amplifier coupled between the feedback resistor and an output of the circuit. A configurable low noise amplifier circuit as in claim 3, wherein the first topology comprises a capacitor coupled between a first output of the first input transistor and ground. A configurable low noise amplifier circuit as in claim 1 of the patent application, the circuit comprising a configurable load coupled to a first output of the circuit. The configurable low noise amplifier circuit of claim 1, wherein the degraded inductor is adapted to provide a power supply noise rejection impedance when the low noise amplifier circuit is configurable in the second topology . For example, the configurable low noise amplifier circuit of claim 1 includes a second input transistor, whereby the low noise amplifier circuit includes a differential low noise amplifier circuit. A configurable low noise amplifier circuit as in claim 14 wherein the degraded inductor comprises a center tap differential degeneration inductor coupled to a first output of the first input transistor, the second A first output of the input transistor is coupled to ground. A configurable low noise amplifier circuit as claimed in claim 14 wherein the feedback resistor includes a further feedback resistor coupled between the input of the second input transistor and a second output of the circuit . The configurable low noise amplifier circuit of claim 5, wherein the first topology switching component is connected to the first output terminal of the first input transistor and the second input power The first loss of the crystal Between the outputs, the circuit includes: a third topology switching component coupled between the input end of the second input transistor and the other feedback resistor, wherein the first And the second and third topological switching members are in an open state, the circuit can be configured in the first topology, and wherein the first, second, and third topological switching members are configured to be in a closed state The circuit can be configured in the second topology. The configurable low noise amplifier circuit of claim 14 wherein the degraded inductor is adapted to provide a common mode signal rejection impedance when the low noise amplifier circuit is configured in the second topology. It is related to the signals shared by the first and second input signals. A radio frequency semiconductor integrated circuit comprising one or more configurable low noise amplifier circuits as in claim 1 of the patent application. An RF module comprising one or more RF filter circuits coupled to one or more configurable low noise amplifier circuits as in claim 1 of the patent application. A device comprising a configurable low noise amplifier circuit as in item 1 of the patent application. A method of configuring a low noise amplifier circuit, comprising: one of: applying a first set of one or more control signals to the circuit to configure the circuit in a first topology, wherein the low noise amplifier The circuit includes a degraded inductor whereby the low noise amplifier circuit acts as an inductively degraded low noise amplifier; or Applying a second set of one or more control signals to the circuit to configure the circuit in a second topology, wherein the low noise amplifier circuit includes a feedback resistor, whereby the low noise amplifier circuit acts as a resistor Sexual feedback low noise amplifier. A configurable low noise amplifier circuit configurable between: an internal input impedance matching topology, wherein the low noise amplifier circuit includes an input impedance suitable for matching a low noise amplifier Inputting an impedance matching component to one or more input inputs of a known input, the one or more internal input impedance matching components being disposed within the low noise amplifier circuit; and a topology different from the internal input impedance matching Topology. The configurable low noise amplifier circuit of claim 23, wherein the topology different from the internal input impedance matching is different from the internal input impedance matching topology, wherein the internal input impedance matching topology is different from The topology consists in the one or more internal input impedance matching elements that do not include the internal input impedance matching topology.