TW201301511A - Metal gate and fabrication method thereof - Google Patents

Abstract

A metal gate including a substrate, a gate dielectric layer, a work function metal layer, an aluminum nitride layer and a stop layer is provided. The gate dielectric layer is located on the substrate. The work function metal layer is located on the gate dielectric layer. The aluminum nitride layer is located on the work function metal layer. The stop layer is located on the aluminum nitride layer.

Description

Metal gate and manufacturing method thereof

The present invention relates to a metal gate and a method of fabricating the same, and more particularly to a metal gate structure in which a barrier layer on a work function metal layer is formed in-situ, and a metal gate structure and a method of fabricating the same.

In the conventional semiconductor industry, polycrystalline lanthanide is widely used in semiconductor components such as metal-oxide-semiconductor (MOS) transistors as a standard gate material. However, as the size of the MOS transistor continues to shrink, the conventional polysilicon gate causes a decrease in component efficiency due to boron penetration effects, and an unavoidable depletion effect, etc., resulting in an equivalent gate. The thickness of the dielectric layer increases, and the value of the gate capacitance decreases, which leads to the dilemma of the deterioration of the component driving capability. Therefore, the semiconductor industry is trying to replace the traditional polysilicon gate with a new gate material, such as a metal electrode with a work function metal layer, as a matching high dielectric constant (High-K) gate. The control electrode of the pole dielectric layer.

In the current process, after the metal layer of the success function, the vacuum is directly broken or even a process such as oxygen is introduced, and then a titanium nitride layer is formed on the work function metal layer to block the metal thereon, such as aluminum. Spread down. However, this process will oxidize the work function metal layer to form an oxide layer, which will promote the degradation of the work function metal layer, thus seriously affecting the electrical quality of the work function metal layer applied to devices such as MOS transistors. For example, an NMOS transistor fabricated in such a process environment generally has a work function value of about 4.81 eV, so how to reduce the work function value is an important issue today.

The invention provides a metal gate and a manufacturing method thereof, which are used for reducing the thickness of an oxide layer formed on a work function metal layer by oxidation, thereby changing a work function value of a work function metal layer, thereby improving a work function metal layer. Electrical quality of devices such as MOS transistors.

The invention provides a metal gate comprising a substrate, a gate dielectric layer, a work function metal layer, an aluminum nitride layer and a barrier layer. The gate dielectric layer is on the substrate. The work function metal layer is on the gate dielectric layer. The aluminum nitride layer is on the work function metal layer. The barrier layer is on the aluminum nitride layer.

The invention provides a method of manufacturing a metal gate. First, a gate dielectric layer is formed on a substrate. Next, a work function metal layer is formed on the gate dielectric layer. Successively, a barrier layer is formed in-situ on the work function metal layer.

The invention provides a method of manufacturing a metal gate. First, a gate structure is formed on a substrate, wherein the gate structure comprises a gate dielectric layer and a sacrificial gate on the gate dielectric layer. Next, an etching process is performed to remove the sacrificial gate. Thereafter, a work function metal layer is formed to replace the sacrificial gate. Finally, a barrier layer is formed in-situ on the work function metal layer.

Based on the above, the present invention provides a metal gate and a method of fabricating the same, which is formed by in-situ forming a barrier layer on a work function metal layer, so that a work function metal between the work function metal layer and the barrier layer The thickness of the native oxide layer of the layer can be reduced as much as possible. Specifically, the thickness of the oxide layer of the work function metal layer of the present invention is less than 30% of the thickness of the work function metal layer, and even in a preferred embodiment, the thickness can be nearly zero. Thus, the metal gate structure formed by the metal gate process of the present invention has a lower work function value than the conventional metal gate structure, thereby improving the electrical quality of the metal gate.

1A-1B is a schematic cross-sectional view showing a metal gate process in accordance with a first embodiment of the present invention. Please refer to FIG. 1A-1B. First, as shown in FIG. 1A, a substrate 110 is provided, and a gate dielectric layer 120 is formed on the substrate 110. The substrate 110 is, for example, a germanium substrate, a germanium-containing substrate or germanium. The semiconductor substrate of a silicon-on-insulator (SOI) substrate or the like, and the gate dielectric layer 120 may be a stacked layer of a single layer or a composite layer. Furthermore, a buffer interface layer (not shown) may be formed as a buffer for the connection substrate 110 and the gate dielectric layer 120 before the formation of the gate dielectric layer 120, and the material thereof is, for example, hafnium oxide. In the present embodiment, the gate dielectric layer 120 is a high dielectric constant gate dielectric layer, but the invention is not limited thereto, and the high dielectric constant gate dielectric layer may be Hafnium oxide. , Zirconium oxide, etc. Specifically, the high dielectric constant gate dielectric layer may be selected from the group consisting of hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), and hafnium silicon (hafnium silicon). Oxynitride, HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ ) ₃ ), zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ) , strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate , a group consisting of Ba _x Sr _1-x TiO ₃ , BST).

Next, a work function metal layer 130 is formed on the gate dielectric layer 120. The present embodiment is used as the metal gate 100 of the NMOS transistor. Therefore, the work function metal layer 130 of the present embodiment is a titanium aluminide metal layer, but the invention is not limited thereto, wherein the titanium aluminide metal layer It can be formed by Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD). Specifically, by forming a titanium aluminide metal layer by physical vapor deposition, aluminum and titanium may be sputtered on the gate dielectric layer 120 in a desired ratio, and then fully mixed by high temperature tempering. Aluminum-titanium alloy, or directly blended with a good proportion of aluminum and titanium alloy on the gate dielectric layer 120. Of course, after forming the gate dielectric layer 120, the present embodiment may also selectively form a barrier layer (not shown) and then shape the success function metal layer 130 so that the barrier layer (not shown) is located. Between the gate dielectric layer 120 and the work function metal layer 130 to further prevent components in the work function metal layer 130, such as aluminum, from diffusing to the gate dielectric layer 120, thereby reducing the electrical quality of the metal gate 100. In an embodiment, the barrier layer (not shown) may include a titanium nitride layer, a tantalum nitride layer, or the like, but the invention is not limited thereto.

Next, as shown in FIG. 1B, a barrier layer 140 is formed in-situ on the work function metal layer 130. In the present embodiment, the barrier layer 140 is a titanium nitride layer. However, the present invention is not limited thereto, and any material that can block unnecessary components such as the upper metal from being diffused downward may be used depending on the needs of the process at that time. In other words, the present invention is modified to not break the vacuum and to perform any process such as oxygenation, such as an oxygen annealing process, as compared to conventional processes. In this way, the work function metal layer 130 can be made to reduce contact with oxygen as much as possible, so that between the work function metal layer 130 and the barrier layer 140, the thickness of the oxide layer formed by the work function metal layer 130 due to oxidation will be reduced as much as possible. In the embodiment, the work function metal layer 130 is a titanium aluminide metal layer, so the oxide layer is a titanium aluminum oxide layer, and the titanium aluminum oxide layer is formed to have a thickness at least 30% less than the thickness of the aluminized titanium metal layer. The best is almost zero, that is, the surface of the work function metal layer 130 does not form an oxide layer at all.

It is worth emphasizing that the applicant has noticed that if an oxygen-containing environment is introduced after vacuuming the aluminum aluminide metal layer, or an oxygen-containing process such as heat treatment is performed, an oxide layer is formed on the surface of the titanium aluminide metal layer, and even The oxygen-containing environment introduced by the vacuum is aluminized titanium metal layer, and the thickness of the primary titanium aluminum oxide layer is about 35% or more of the thickness of the titanium aluminide metal layer. The oxide layer captures the metal of the work function metal layer 130, such as aluminum, and inhibits its downward migration and diffusion, while making the metal gate 100 have a higher work function value. The present invention forms the barrier layer 140 in-situ, thereby reducing the thickness of the oxide layer formed by reacting the work function metal layer 130 with oxygen, thereby effectively reducing the work function of the metal gate 100 and improving the metal gate. The pole 100 is applied to the electrical quality of devices such as MOS transistors (especially NMOS transistors).

For example, in an NMOS implementation, as shown in FIG. 4, it is detected by a transmission electron microscope or the like, and (right) is formed by in-situ (in-situ). After the method of blocking layer 140, that is, under vacuum or oxygen-free environment, the thickness of the oxide layer may be substantially close to zero, and the work function of metal gate 100 at this time may be about 3.9 to 4.5. . Compared with the conventional process method, (left), when the vacuum is introduced and introduced into an oxygen-containing environment, the thickness of the native oxide layer is as high as 24 angstroms, which is about 64 angstroms of the work function metal layer. 37%, and the measured work function is 4.81 eV. Therefore, it can be seen from the actual measurement experiments that the present invention can reduce the work function value of the metal gate 100 by reducing the thickness of the oxide layer, thereby improving the electrical quality of the N-type metal gate 100. Further, as shown in FIG. 4, in the embodiment in which the barrier layer 140 is a titanium nitride layer and the work function metal layer 130 is a titanium aluminide metal layer, a titanium nitride layer is directly formed in-situ. At the same time, nitrogen gas is introduced to nitride the surface of the titanium aluminide metal layer to form an aluminum nitride layer 150.

2A-2E is a cross-sectional view showing a metal gate process according to a second embodiment of the present invention, wherein the metal gate and the method of fabricating the same are applied to a gate of a front high-k dielectric layer In the gate last for high-k first process. Of course, the metal gate of the present invention and the method of manufacturing the same can be applied to other semiconductor processes, and the invention is not limited thereto. Please refer to FIG. 2A-2E. First, as shown in FIG. 2A, an interface layer 222 may be selectively formed on the substrate 210 as a buffer layer, and then a gate dielectric layer 224 is formed thereon. The material mentioned is the same as the metal gate of the first embodiment (Fig. 1A-1B). For example, the interface layer 222 in the embodiment may be a ceria layer, and the gate dielectric layer 224 may be a high dielectric. Constant dielectric layer, so no more details are given. Then, a first barrier layer 226 is selectively formed on the gate dielectric layer 224, and the first barrier layer 226 may include at least one of a titanium nitride layer and a tantalum nitride layer. Then, a sacrificial gate 228 is formed on the first barrier layer 226. In this way, a gate structure 220 having at least one gate dielectric layer 224 and a sacrificial gate 228 can be formed. The interface 222, the gate dielectric layer 224, the first barrier layer 226, and the sacrificial gate 228 are patterned to form the gate structure 220 in the figure. Of course, in an embodiment, the process may be first to selectively form a cap layer (not shown) on the sacrificial gate layer (not shown), and then use a yellow light etch process (PEP) pattern. The cap layer sequentially forms a patterned cap layer 230, and then the patterned cap layer 230 is used as an etch mask to etch the sacrificial gate 228, the first barrier layer 226, and the gate dielectric layer. 224 and interface layer 222. Continuing, a spacer 240 is formed on a side of the gate structure 220, wherein the spacer 240 can be a single layer or a plurality of layers. In one embodiment, the gate structure 220 and the spacer 240 can be used as a mask, and the processes such as the ion implantation process, the junction activation tempering, and the like can be automatically aligned to form a source on the side of the spacer 240. Bungee area 250. In addition, in this embodiment, the strain enthalpy process can be selectively matched, and other processes such as metal germanide, contact hole etch stop layer (CESL) are formed on the source/drain region 250. Thereafter, a dielectric layer 260 is formed to cover the substrate 210, the cap layer 230, and the spacers 240 (as in FIG. 2A).

Then, as shown in FIG. 2B, a portion of the dielectric layer 260 and the cap layer 230 are removed and the sacrificial gate 228 is exposed, for example, by a planarization method such as a chemical mechanical polishing process. Thereafter, the sacrificial gate 228 is removed, for example, by a dry or wet etch process to form the recess R and expose the first barrier layer 226. In this embodiment, the sacrificial gate 228 may be composed of a polysilicon material, but may be other materials; and the first barrier layer 226 is a titanium nitride layer for use as an etch stop layer in the process to prevent etching. The process damages the gate dielectric layer 224 underneath, and can also prevent the material component formed subsequently thereon from diffusing down to the gate dielectric layer 224, but the invention is not limited thereto, and the foregoing functions are Materials are available.

Next, as shown in FIG. 2C, a second barrier layer 270 is selectively formed on the first barrier layer 226 in the recess R, which may be a tantalum nitride layer in this embodiment, but in other Other materials may be used in the embodiment. Then, a work function metal layer 280 is formed on the second barrier layer 270 in the recess R. The work function metal layer 280 in this embodiment is a titanium aluminide metal layer and is generally used as an NMOS. The work function metal layer of the gate electrode of the transistor, but in other embodiments, the work function metal layer 280 may also be a metal layer of other materials, and is used as a structure for forming a PMOS transistor, and the invention is not limited thereto.

Continuing, as shown in FIG. 2D, a barrier layer 290 is formed in-situ on the work function metal layer 280 in the recess R without breaking the vacuum or oxygen-free environment. Finally, as shown in FIG. 2E, on the barrier layer 290, a main metal electrode 295 is formed by using a planarization process. Thus, the gate last for high-k first process is performed before the present embodiment is completed to form the transistor 200 of the second embodiment. Of course, this embodiment is an NMOS transistor, and in other embodiments, it may be a PMOS transistor or a semiconductor device integrated in a CMOS transistor. Furthermore, the main metal electrode 295 in this embodiment is an aluminum metal electrode, and the barrier layer 290 is a titanium nitride layer for blocking the downward diffusion of aluminum in the main metal electrode 295 thereon, contaminating the lower gate. The structure, particularly the gate dielectric layer 224, degrades the electrical quality of the transistor 200. In addition, in this embodiment, the dielectric layer 260 and the contact hole etch stop layer (CESL) are selectively removed, and then the contact hole etch stop layer (CESL) and the dielectric layer are newly formed to effectively improve the power of the MOS transistor. Sexual performance.

Since the barrier layer 290 is directly formed on the work function metal layer 280 in-situ, it is easy to say that it is not formed after the successful function metal layer 280, and is formed by a conventional vacuum or oxygen process. The barrier layer 290 is on the work function metal layer 280. Therefore, the thickness of the oxide layer formed by the oxidation reaction of the work function metal layer 280 of the present invention may be less than 30% of the thickness of the work function metal layer 280. In a preferred embodiment, the thickness of the oxide layer of the present invention can be substantially close to zero.

Further, as shown in FIG. 2D, in the embodiment in which the barrier layer 290 is a titanium nitride layer and the work function metal layer 280 is a titanium aluminide metal layer, a titanium nitride layer is directly formed in-situ. At the same time, nitrogen gas is introduced to nitride the surface of the titanium aluminide metal layer to form an aluminum nitride layer 285.

As such, the work function of the transistor 200 can be lowered, and the electrical quality of the transistor 200 can be increased. In a preferred embodiment, the work function of the transistor 200 of the present embodiment can reach 3.9 to 4.5 eV.

3A-3B is a cross-sectional view showing a metal gate process according to a third embodiment of the present invention, wherein the metal gate of the first embodiment and the method of fabricating the same are applied to a post-high dielectric constant dielectric. In the gate last for high-k last process. The third embodiment still uses the same reference numerals in the second embodiment to denote the same elements for the sake of simplicity and clarity of the present embodiment.

The previous stage process of this embodiment is the same as that of the second embodiment as shown in FIG. 2A except that the second embodiment directly deposits a gate dielectric layer 224 having a high dielectric constant, but the present embodiment In the example, after the interface layer 222 is formed, a sacrificial gate dielectric layer 224 is formed by any material, which has the characteristics of low cost, easy etching, and easy deposition. Then, the first barrier layer 226 is selectively formed, the sacrificial gate 228 is formed in sequence, the spacer 240 is formed, and the source/drain region 250 is formed, and the substrate 210, the cap layer 230, and the spacer 240 are formed on the substrate 210, the cap layer 230, and the spacer 240. Electrical layer 260. Thereafter, as shown in FIG. 3A, the capping layer 230 is removed by planarization and the sacrificial gate 228 is exposed, and then an etching process is performed to sequentially etch away the sacrificial gate 228, the first barrier layer 226, and the gate dielectric layer. A recess R' is formed 224, leaving an interface layer 222 on the substrate 210 as an etch stop layer.

Then, as shown in FIG. 3B, a gate dielectric layer 324, a first barrier layer 326, a second barrier layer 370, and a work function metal layer 380 are sequentially refilled. Thereafter, a barrier layer 390 is formed on the surface of the work function metal layer 380 in an in-situ manner without breaking the vacuum or an oxygen-free environment, and finally a main metal electrode 395 is formed and planarized. . The gate dielectric layer 324 is, for example, a high dielectric constant gate dielectric layer, the first barrier layer 326 is, for example, a titanium nitride layer, and the second barrier layer 370 is, for example, a tantalum nitride layer or a work function metal layer 380. For the aluminized titanium metal layer of the NMOS transistor, the barrier layer 390 is, for example, a titanium nitride layer, and the main metal electrode 395 is, for example, an aluminum electrode, but the invention is not limited thereto. The barrier layer is exemplified as a multilayer structure of the first barrier layer 326 and the second barrier layer 370, but the barrier layer may also have a single layer structure.

Compared with the second embodiment, the gate dielectric layer 324, the first barrier layer 326, the second barrier layer 370, the work function metal layer 380, and the barrier layer 390 of the present embodiment have a U-shaped cross section. structure. Similarly, this embodiment can also be selectively matched with the strain 矽 process, and further metal oxide, contact hole etch stop layer (CESL) and other processes are formed on the source/drain regions. In this way, the gate last for high-k last process is performed after the third embodiment of the present invention is completed to form the transistor 300 of the third embodiment. Since the present embodiment also forms the barrier layer 390 directly on the work function metal layer 380 in the in-situ manner, the present embodiment can also effectively prevent the oxidation of the surface of the work function metal layer 380, thereby forming the formed The thickness of the oxide layer is less than 30% of the thickness of the work function metal layer 380, and in a preferred embodiment, the thickness of the oxide layer can be substantially close to zero, while the work function of the transistor 300 of the present invention can reach 3.9 to 4.5. eV.

Further, as shown in FIG. 3B, in the embodiment in which the barrier layer 390 is a titanium nitride layer and the work function metal layer 380 is a titanium aluminide metal layer, a titanium nitride layer is directly formed in-situ. At the same time, nitrogen gas is introduced to nitride the surface of the titanium aluminide metal layer to form an aluminum nitride layer 385.

In summary, since the present invention is formed by in-situ formation of a barrier layer on a work function metal layer, that is, under a vacuum-free or oxygen-free environment, the work function metal layer is oxidized. The thickness of the oxide layer formed between the barrier layer and the work function metal layer can be reduced. Specifically, the thickness of the oxide layer of the present invention is less than 30% of the thickness of the work function metal layer, and even in a preferred embodiment, the thickness of the oxide layer can be nearly zero. Compared with the conventional work function metal layer, the thickness of the oxide layer formed by oxidation is higher than 35% of the thickness of the work function metal layer. The metal gate structure formed by the metal gate process of the present invention has a work function. Achieving 3.9 to 4.5 eV, which is lower than the conventional work function value, can improve the electrical quality of the metal gate.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Metal gate

110, 210. . . Base

120, 224, 324. . . Gate dielectric layer

130. . . Work function metal layer

140. . . Barrier layer

150, 285, 385. . . Aluminum nitride layer

220. . . Gate structure

222. . . Interface layer

226, 326. . . First barrier layer

228. . . Sacrificial gate

230. . . Cover

240. . . Clearance wall

250. . . Source/bungee area

260. . . Dielectric layer

270, 370. . . Second barrier layer

280, 380. . . Work function metal layer

290, 390. . . Barrier layer

295, 395. . . Main metal electrode

R, R’. . . Groove

1A-1B is a schematic cross-sectional view showing a metal gate process in accordance with a first embodiment of the present invention.

2A-2E is a schematic cross-sectional view showing a metal gate process in accordance with a second embodiment of the present invention.

3A-3B is a schematic cross-sectional view showing a metal gate process in accordance with a third embodiment of the present invention.

4 is a cross-sectional view of a metal gate structure under a transmission electron microscope in accordance with a preferred embodiment of the present invention.

100. . . Metal gate

110. . . Base

120. . . Gate dielectric layer

130. . . Work function metal layer

140. . . Barrier layer

150. . . Aluminum nitride layer

Claims (18)

A metal gate includes: a substrate; a gate dielectric layer on the substrate; a work function metal layer on the gate dielectric layer; and an aluminum nitride layer on the work function metal layer And a barrier layer on the aluminum nitride layer. The metal gate of claim 1, wherein the metal gate comprises a metal gate of an NMOS. The metal gate of claim 1, wherein the gate dielectric layer comprises a high-k dielectric layer. The metal gate of claim 1, wherein the metal gate further comprises a barrier layer between the gate dielectric layer and the work function metal layer. The metal gate of claim 1, wherein the barrier layer comprises a titanium nitride layer. The metal gate of claim 1, wherein the metal gate has a work function of about 3.9 to 4.5 eV. A method of fabricating a metal gate includes: forming a gate dielectric layer on a substrate; forming a work function metal layer on the gate dielectric layer; forming a barrier layer in-situ The work function is on the metal layer. The method of fabricating a metal gate according to claim 7, wherein the metal gate comprises a metal gate of an NMOS transistor. The method of manufacturing a metal gate according to claim 7, wherein the barrier layer comprises a titanium nitride layer. The method for fabricating a metal gate according to claim 7 further comprises forming a barrier layer after forming the gate dielectric layer on the substrate. The method of manufacturing a metal gate according to claim 7, wherein the metal gate has a work function of about 3.9 to 4.5 eV. A method for fabricating a metal gate includes: forming a gate structure on a substrate, wherein the gate structure comprises a gate dielectric layer and a sacrificial gate on the gate dielectric layer; performing an etching process To remove the sacrificial gate; forming a work function metal layer to replace the sacrificial gate; in-situ forming a barrier layer on the work function metal layer. The method of fabricating a metal gate according to claim 12, wherein the metal gate comprises a metal gate of an NMOS transistor. The method of fabricating a metal gate according to claim 12, wherein the gate dielectric layer comprises a high-k dielectric layer. The method for manufacturing a metal gate according to claim 12, wherein the work function metal layer further comprises a titanium aluminide metal layer. The method of manufacturing a metal gate according to claim 12, wherein the metal gate has a work function of 3.9 to 4.5 eV. The method of fabricating the MOS transistor according to claim 12, wherein after removing the sacrificial gate, the method further comprises removing the gate dielectric layer and forming a high-k dielectric layer. The method for fabricating an MOS transistor according to claim 12, further comprising forming a spacer on a side of the gate structure after forming the gate structure on the substrate.