201248683 六、發明說明： 【發明所屬之技術領域】 亡2發明是有關於""種積體電路的製程方法，且特別是 有關於-種半導體元件的製程方法。 【先前技術】 離子植人製程是—種經常使祕半導體元件製程中 成各種摻雜區的方法。典型齡子植人製程是透過 二:口@案的單_層的光阻層來做為植人罩幕。然而， 二者=件不斷地小觀，對於高低起伏落差較大的表面來 ==欲形成的開σ圖案的高寬比㈣⑽論)過高，製程 不=空間_cesswind〇w)非常小，時有曝光製程的景深 圖案阻層破裂或殘留，所形成的開口 位罟b*斤而的輪廓，而導致所形成的摻雜區輪扉或 位置不正確，甚至有無法形成開Π圖案的情形。 【發明内容】 有所提供一種半導體元件的製程方法，可以形成且 以形離子植入罩幕’以將離子植入於正確的區域 起伏體元:的製7法’包括在高低 質不同’且與_之材f不二=== 201248683 使光阻層圖案化，形成第—開口，裸靈中 然後，刻移除第一 ：::更 下方的平坦層，以形成第n 口 n 與其 後’移 之材=同發明—實施例所述，上述靖 之材實施例所述，上述平坦層與上述光阻屬 依照本發明一實施例所述，上述平 之材;=:有機材料、域材料或聚 感光=本發明一實施例所述，上述平坦層之材質包括不 不感=㈣—糊㈣，上轉幕層之材質包括 層的述，上述硬罩幕層對上述平坦 之枯明—實施例所述，上述平坦層與上述光阻層 ζ質包括昌碳型光阻；上述硬罩幕層之材質包括富石夕型 依照本發明-實施綱述，上述平坦層、上述硬罩幕 4 201248683 層以及上述光阻層之厚度分別為500nm至550nm、Mnm 至 35nm 與 150nm 至 200 nm。 依照本發明一實施例所述，上述半導體元件的製程方 法更包括在進行上述離子植入製程之後，在移除上述硬罩 幕層之前，於上述第二開口之中填入保護層，且在移除上 述硬罩幕層之後，移除上述保護層。 依照本發明一實施例所述，上述保護層之材質包括有 機材料、無機材料或聚合物材料。 依照本發明一實施例所述，上述保護層之材質包括感 光材料。 依照本發明一實施例所述，上述保護層之材質包括富 碳型光阻。 依照本發明一實施例所述，上述保護層之材質包括不 感光材料。 依照本發明一實施例所述，上述保護層與上述平坦層 之材質相同。 ""曰 依照本發明一實施例所述，上述保護層與上述平坦層 之材質不相同。 —θ 依照本發明一實施例所述，上述半導體元件的製程方 法更包括在移除上述平坦層的同時，移除上述保護層。 依照本發明一實施例所述，上述保護層的形成方法包 括形成保護材料層，填入於上述第二開口中並且覆蓋於= 上述硬罩幕層上，之後，移除上述硬罩幕層上的保護材料 層’使上述硬罩幕層裸露出來。 201248683 本發明—實施例所述，上述基底上具有多 二覆蓋上述些堆叠結構且填人於上‘ -間間，上述第二開口使上述些空間其令之 遍i㈣層的厚度為 具有= 來形成摻㈣。 ㈣子植人正確的區域 下文特 兴實=本上述特徵和優點能更明顯易懂 舉貫施例，並配合所_式作詳細說明如下。 【實施方式】 -彼至4是依據本發明—實施例崎*之—種半導體 兀件的製程方法的剖面示意圖。 S照圖卜提供—個具有高低起伏表面娜。在— 2:在表面100的高低落差例如是1〇0™至 200mn。在另-實施例中，冑低起伏表自_ 例如是lOOrnn至500nm。此外，在一實 成/差 ^犬，⑽包括基底1G以及堆疊結構12。基底== 】如疋半導體，例如是矽，或是化合物半導體 姓 ^的高度例如是150至3〇〇nm。堆叠結構心、: 。括閘，，電層14、間極導體層16以及頂蓋層π : 以此為限。閘介電層14之材質例如是氧化閘極導體層 6 201248683 導辦展是播雜多晶石夕、金屬石夕化物或其組合。閘極 is夕1所&列如疋做為非揮發性記憶元件的控制閘。頂蓋層 實施例中广是氮化梦或是氧切。在另- 起伕…土底0以及堆疊結構12之外，構成高低 12 1包括介電層2〇。介電層2〇位於堆疊結構 。"電層2〇例如是氮化矽、氧化矽或是氧化 •V陰1氧化石夕堆叠層。介電層20例如是做為非揮發性 ^ ^件中控制閘與浮置閘之間的閘間介電層。此外，在 之外，m’除了基底1〇、堆疊結構12以及介電層2〇 構成N低起伏表面100還包括介電層22。介電層22 :二二堆牙结構12之間的空間的基底 .^ ㈢22之材負例如是氧化石夕，或是i 的 2材料。介電層的厚度例如是3〇nm至 ^ 發明是以基底H)上具有堆疊結構12、介 2二為實闕來舉舰明高购伏表面二 圖3所示)’本發二二二二入區36(如 的製程係在高低起伏表面〗⑻上依序 ^罩2 雜㈣之_空間。平料24可; 料或是不感光材料哼坦層Μ的材料可以 感先材 機材料物材料。_ 24之#料; 阻。平坦層24的厚度例如是則⑽ 201248683 度是指堆疊結構12之間之介電層22以上的厚度 24可以旋塗的方式形成’或其他任何已知的方式來形成層 硬罩幕層26之材質與平坦層μ不同，且與光阻异28 不同。硬罩幕層26對平坦層24的侧選擇比為6 乂， 例如是6至10。硬罩幕層26之材質例如是富石夕型光 氮化矽’但並不以此為限。硬罩幕層26的厚度例如是乃〆 至35nm。硬罩幕層26可以旋塗的方式形成，或其他= 已知的方式來形成。 =且層28之材質可與平坦層24之材f相同或相里。 二之材富碳型光阻’但並不以此為限。、光 28在後續將形成開口 3。圖案(請參 =8 = 口二圖/將再轉移至硬罩幕層％，因此， 罩幕i 26 G。光阻口 3_找轉移至硬 -55〇nm . 35 50〇nm 之後，物 使光阻層28圖案化，^阻^ 28進行曝光顯影製程， 方，而且光阻層28 相的表面的平坦層μ上 景深，因此，非常易"C相§ 4，在進行曝光時有足夠的 口 30具有所需的輪^控制’且可以使得所形成之第-開 然後，請參照圖 划移除第一開口 3〇所裸露的硬 8 201248683 罩幕層26與其下方的平坦層24 ’以形 露出堆疊結構12之間的空間上的介 一開口 32，裸 的高寬比例如是1〇至20 1刻的方\層221二開口 32 姓刻法’例如是乾式蝕刻法，所以#木用非等向性 膽。在-實施例中，光阻層28卿垣=刻氣體例如是 在硬罩幕層26侧之後，在進行侧材質相同， 光阻層28會被消耗殆盡，而裸露出一^的過程中， 罩幕層26對平坦層24的餘刻選擇罩幕層2卜由於硬 刻平坦層24的過程中硬罩墓屏 ’、、、至10，因此在蝕 罩幕層26錢平坦層24是夢曰㈣做為硬罩幕。由於硬 ，、有所❿的輪靡，不會如㈤使 深寬比的情料，會受限於曝峨=難化^ 繼之’請繼續參照圖3， 做為植入罩幕，進行離C f平坦層24 庙邱-苴产丄 植八展私34 ’以於第二開口 32 二 =〇中形成摻雜區36。摻雜區糾 26^^c 程34 子t輪廓非f良好，因此，離子植入製 摻雜區36。 入正確的區域而形成具有所需輪廓的 然後’請參照圖4 ,縣降 24,使堆疊社構 示更罩幕層26，再移除平坦層 的介電層2〇裸露出戈電層22以及堆疊結構12側壁上 路出來。移除硬罩幕層如的方法例如是以 201248683 乾触刻方法，利用版做為_氣體。在— 實施例中，硬罩幕層26的材質為料光阻層，平坦層24 的材質為富礙光阻層，由於硬單幕層26的厚度#常薄，易 ^移除’不會有轉光阻層過厚騎生的殘留問題。平坦 層24的材質為畜碳光阻層，相較於富石夕光阻層，非常易於 ，除’其可以^用任何已知的方法，例如是以氧氣電衆(〇2 plasma)，或以有機溶劑移除，但並不以此為限。 上述實施例’係在基底1G巾形成隸區％之後，隨 =除硬罩幕層26、然而，在另—實施例中，請參照圖3a 暮基底1〇中形成摻雜區36之後，移除硬罩 後 之刚，形成保護材料層38，覆蓋硬罩幕層26並 之中然後，再移除硬罩幕層26上方所裸 路的保護材料層38，留下篦-鬥η π 使上述硬罩幕層26裸露出H32i護層38a ’並 保護層38a之材質硬罩幕層26° 料。π 匕括有機材料、無機材料或聚合物材 保護二二二材質可以是感光材料或是不感光材料。 的過i中，V電層質::是富碳型光阻。在移除硬罩幕層2 6 因此，伴被保護層38a所覆蓋，不會裸露出來， 故可防以避免介電層22暴露於靖境中， 護==損傷的問題。此外’在-實施例中，保 24時，保二％、，平坦層24相同，在移除上述平坦層 综上所述，乂同時被移除，以簡化製程步驟。 所組成的三層利用平坦層、硬罩幕層以及光阻層 、、Q構來形成離子植入製程所需的罩幕。光阻 201248683 層的圖案是透郷光顯影 坦層則是以韻刻的方式來L化。硬罩幕層以及平 平坦的表面的平坦層上方，而2先阻層是位於具有 進行曝光時有足夠的景植相厚餘當薄，在 第一開口的輪靡。再者，由1^ ’非常易於控制所形成之 蝕刻選擇比，因此在韻列；硬罩幕層對平坦層具有高的 為_琳。坦==草幕層可做 供平坦的表面 h—層給要足夠的厚度來提 平坦層是以偏心式圖案:為=罩罩幕層以及 第二開口的輪廓，使得離二易於控制所形成的 的區域而形成呈 製耘可以將離子植入正確 —①底具有所需輪廓之接雜區。 =區;後，移除硬罩幕層之前，先在第二 程中i到損:避:：伏表面在後續移除硬罩幕層的過 層相同的材I 層的材質可以選用與平坦 省製程的步驟。迹平坦層的同時被移除，以節 本發:然實施例揭露如上，然其並非用以限定 本發明之精技術領域中具有通常知識者，在不脫離 發明之佯護r鬥^圍内，當可作些許之更動與潤飾，故本 之保4乾圍虽視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1至4是依據本發明—實施例麟 兀件的製程方法的剖面示意圖。 料導體 201248683 【主要元件符號說明】 10 :基底 28 12 :堆疊結構 30 14 :閘介電層 32 16 :閘極導體層 34 18 :頂蓋層 36 20 :介電層 38 22 :介電層 38a 24 :平坦層 100 26 :硬罩幕層 光阻層 第一開口 第二開口 離子植入製程 摻雜區 保護材料層 :保護層 :高低起伏表面 12201248683 VI. Description of the invention: [Technical field to which the invention pertains] The invention of the invention is a method of manufacturing a "" type of integrated circuit, and particularly relates to a method of manufacturing a semiconductor element. [Prior Art] The ion implantation process is a method of frequently forming various doping regions in a semiconductor device process. The typical age-in-plant process is to use the single-layer photoresist layer of the second: mouth@ case as a mask. However, both of them are constantly small, and for the surface with large fluctuations, the aspect ratio of the open σ pattern to be formed is too high (4) (10) is too high, the process is not = space _cesswind〇w) is very small, When the depth of field pattern of the exposure process is broken or left, the formed opening is located at a contour of b*, and the formed rim or position of the doped region is incorrect, and even the opening pattern cannot be formed. . SUMMARY OF THE INVENTION There is provided a method of fabricating a semiconductor device that can be formed and implanted into a mask with a shaped ion to implant ions in the correct region of the undulating body element: And _ the material f not two === 201248683 patterning the photoresist layer, forming the first opening, naked and then removing the flat layer below the first::: to form the nth port n and thereafter The material of the above-mentioned flat layer and the above-mentioned photoresist are according to an embodiment of the present invention, the above-mentioned flat material; =: organic material, domain material, as described in the embodiment of the invention. Or a photosensitive sensation: according to an embodiment of the present invention, the material of the flat layer includes no (four)-paste (four), the material of the upper revolving layer includes a layer, and the hard mask layer is applied to the flatness of the flat-implementation For example, the flat layer and the photoresist layer include a permanent carbon type photoresist; the material of the hard mask layer includes a Fu Shi Xi type according to the present invention - the flat layer and the hard mask 4 201248683 layer and the thickness of the above photoresist layer respectively 500nm to 550nm, Mnm to 35nm and 150nm to 200 nm. According to an embodiment of the present invention, the method for fabricating the semiconductor device further includes: after performing the ion implantation process, filling a protective layer in the second opening before removing the hard mask layer, and After removing the above hard mask layer, the above protective layer is removed. According to an embodiment of the invention, the material of the protective layer comprises an organic material, an inorganic material or a polymer material. According to an embodiment of the invention, the material of the protective layer comprises a photosensitive material. According to an embodiment of the invention, the material of the protective layer comprises a carbon-rich photoresist. According to an embodiment of the invention, the material of the protective layer comprises a non-photosensitive material. According to an embodiment of the invention, the protective layer is made of the same material as the flat layer. "" In accordance with an embodiment of the present invention, the protective layer is different from the material of the flat layer. - θ According to an embodiment of the invention, the method of fabricating the semiconductor device further includes removing the protective layer while removing the planar layer. According to an embodiment of the present invention, the method for forming the protective layer includes forming a protective material layer, filling the second opening and covering the hard mask layer, and then removing the hard mask layer. The layer of protective material 'exposed the hard mask layer above. 201248683 In the embodiment of the present invention, the substrate has a plurality of layers covering the stacked structures and is filled in the upper portion, and the second opening causes the spaces to have the thickness of the i (four) layer as having = Forming the doping (four). (4) The correct area of the sub-planter The following features: The above features and advantages can be more clearly understood and applied in detail, and the details are as follows. [Embodiment] - 4 to 4 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to the present invention. S is provided as a picture of a high and low undulating surface. At - 2: the height difference at the surface 100 is, for example, 1 〇 0 TM to 200 mn. In another embodiment, the deflated undulations are, for example, from 100 rnn to 500 nm. Further, in a real/poor dog, (10) includes a substrate 1G and a stacked structure 12. Substrate == 】 For example, a semiconductor such as germanium or a compound semiconductor has a height of, for example, 150 to 3 nm. Stack structure heart, : . The gate, the electric layer 14, the interlayer conductor layer 16, and the cap layer π are limited thereto. The material of the gate dielectric layer 14 is, for example, an oxide gate conductor layer. The 201248683 guide is a broadcast polycrystalline stone, a metal cerium or a combination thereof. The gate is the 1st & column as the control gate of the non-volatile memory element. Top cover layer In the embodiment, it is a dream of nitriding or oxygen cutting. In addition to the soil base 0 and the stack structure 12, the height 12 1 includes a dielectric layer 2 〇. The dielectric layer 2 is located in a stacked structure. "Electrical layer 2〇 is, for example, tantalum nitride, hafnium oxide or oxidized • V anion 1 oxide layer stack. The dielectric layer 20 is, for example, a dielectric layer between the gate and the floating gate in the non-volatile material. In addition, m' includes a dielectric layer 22 in addition to the substrate 1 堆叠, the stacked structure 12, and the dielectric layer 2 构成 constituting the N low relief surface 100. Dielectric layer 22: the base of the space between the two or two stacks of teeth 12. The material of the (3) 22 is, for example, an oxide oxide or a material of i. The thickness of the dielectric layer is, for example, 3 〇 nm to ^. The invention is based on the substrate H) having a stacked structure 12, and the second is a solid 阙 举 举 明 购 购 购 购 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二Area 36 (if the process is on the high and low undulating surface) (8), the space of the second (four) is sequentially covered. The flat material 24 can be used; the material or the material of the non-photosensitive material can be used as the material of the precursor material. The thickness of the flat layer 24 is, for example, (10) 201248683 degrees means that the thickness 24 above the dielectric layer 22 between the stacked structures 12 can be formed by spin coating ' or any other known manner The material of the hard mask layer 26 is different from the flat layer μ and is different from the photoresist. The side ratio of the hard mask layer 26 to the flat layer 24 is 6 乂, for example, 6 to 10. Hard mask The material of the layer 26 is, for example, a fluorite-type photo-nitriding crucible, but is not limited thereto. The thickness of the hard mask layer 26 is, for example, 35 to 35 nm. The hard mask layer 26 can be formed by spin coating, or Other = a known way to form. = and the material of layer 28 can be the same as or in the phase f of flat layer 24. The material of the material is carbon-rich photoresist 'but Not limited to this. Light 28 will form opening 3 in the following. The pattern (please refer to =8 = port 2 map / will be transferred to hard mask layer %, therefore, mask i 26 G. photoresist port 3_ After looking for transfer to hard-55〇nm. 35 50〇nm, the photoresist layer 28 is patterned, and the exposure and development process is performed, and the flat layer μ of the surface of the photoresist layer 28 is deep. Therefore, it is very easy to "C phase § 4, when the exposure is performed, there are enough ports 30 to have the required wheel control" and the formed first-opening can be made, then the first opening 3 is removed with reference to the drawing. The exposed hard 8 201248683 mask layer 26 and the flat layer 24 ′ below it form a dielectric opening 32 in the space between the stacked structures 12 , and the bare aspect ratio is, for example, a square layer of 1 〇 to 20 1 221 second opening 32 last name 'for example, dry etching method, so # wood isotropic biliary. In the embodiment, the photoresist layer 28 刻 = engraved gas, for example, after the hard mask layer 26 side, In the same side material, the photoresist layer 28 will be exhausted, and during the process of exposing a film, the mask layer 26 is left to the flat layer 24. The mask layer 2 is selected as a hard mask tomb screen ',, to 10 in the process of hard engraving the flat layer 24, so the money flat layer 24 in the mask layer 26 is a nightmare (four) as a hard mask. The rim of the cockroach will not be as good as (five) to make the aspect ratio of the material, it will be limited by the exposure = difficult to be ^ followed by 'Please continue to refer to Figure 3, as an implant mask, proceed from C f The flat layer 24 Miao Qiu - 苴 丄 丄 八 八 八 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 Ions are implanted into doped regions 36. Enter the correct area to form the desired contour and then 'please refer to Figure 4, the county drop 24, so that the stacking community will display the mask layer 26, and then remove the flat layer of the dielectric layer 2, bare the exposed layer 22 And the side wall of the stack structure 12 is out. The method of removing the hard mask layer is, for example, a 201248683 dry etch method using the plate as a gas. In the embodiment, the hard mask layer 26 is made of a material photoresist layer, and the flat layer 24 is made of a material that is obstructive to the photoresist layer. Since the thickness of the hard single layer 26 is often thin, it is easy to remove 'will not There is a residual problem of the light-transfer layer being too thick. The material of the flat layer 24 is a livestock carbon photoresist layer, which is very easy to be compared with the Fu Shi Xi photoresist layer, except that it can be used by any known method, such as oxygen plasma (〇2 plasma), or Removed with organic solvents, but not limited to this. The above embodiment is after the base 1G towel formation lands%, with = hard mask layer 26, however, in another embodiment, please refer to Figure 3a 暮 substrate 1 形成 after forming doped regions 36, Immediately after the hard mask, a protective material layer 38 is formed, covering the hard mask layer 26 and then, and then the protective material layer 38 bare above the hard mask layer 26 is removed, leaving the 篦-hopper η π The hard mask layer 26 exposes the H32i sheath 38a' and the protective layer 38a is made of a hard mask layer of 26°. π Include organic materials, inorganic materials or polymer materials The protective material can be photosensitive or non-photosensitive. In the past, the V-electrolayer:: is a carbon-rich photoresist. Therefore, the hard mask layer 2 6 is removed, so that the mask is covered by the protective layer 38a and is not exposed, so that the dielectric layer 22 can be prevented from being exposed to the environment, and the problem of damage == damage. Further, in the embodiment, the second layer is kept at the same time, and the flat layer 24 is the same. As described above, the flat layer is removed, and the crucible is simultaneously removed to simplify the process steps. The three layers are formed by a flat layer, a hard mask layer, and a photoresist layer, Q structure to form a mask required for the ion implantation process. Photoresistance 201248683 The pattern of the layer is through the development of the light. The layer of the layer is L-shaped in a rhyme manner. The hard mask layer and the flat surface are flat above the flat layer, while the 2 first resist layer is located at the rim of the first opening when there is sufficient thickness of the landscape to be exposed. Moreover, it is very easy to control the etching selection ratio formed by 1^', and therefore in the rhyme; the hard mask layer has a high _ 琳 for the flat layer. Tan == the grass layer can be used for the flat surface h-layer to give enough thickness to raise the flat layer in an eccentric pattern: = the mask layer and the contour of the second opening, so that the two are easy to control The area is formed to form a defect that can implant ions into the correct one with the desired contour. = area; after removing the hard mask layer, first in the second pass i to the loss: avoid:: the surface of the voltaic surface in the subsequent removal of the hard mask layer of the same material I layer material can be selected and flat Provincial process steps. The track flat layer is removed at the same time as the present invention. However, the embodiment is disclosed above, but it is not intended to limit the general knowledge in the technical field of the present invention, without departing from the invention. When there are some changes and refinements that can be made, the warranty of the company is subject to the definition of the patent application scope attached to it. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1 to 4 are schematic cross-sectional views showing a method of manufacturing a lining member according to the present invention. Material conductor 201248683 [Main component symbol description] 10: Substrate 28 12: Stack structure 30 14 : Gate dielectric layer 32 16 : Gate conductor layer 34 18 : Cap layer 36 20 : Dielectric layer 38 22 : Dielectric layer 38a 24: flat layer 100 26: hard mask layer photoresist layer first opening second opening ion implantation process doped region protective material layer: protective layer: high and low undulating surface 12