201246772 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種切換式電源管理控制之方法及 .路’可用以控制功率（p〇wer ) MOS電晶體。本發明 亦可用於發光二極體（LED )之切換.式電源管理裝置， 以達到節能的效果。 【先前技術】 ，統AC/D<：隔離式切換式電源管理控制器為了維 持穩定電流，通常會使用功率M〇s電晶體來控制。然 而’在無效區（dead zone )頻繁地切換功率MOS電晶 體不僅浪費能源，也限制控制器使用範圍。 第1圖顯示一種典型降壓（Buck)式LED驅動裝 置之切換式電源管理控制電路。交流電源9〇1提供輸入 電壓Vin，點亮發光二極體921所需之啟動電壓為 vle_d。輸入電壓V1N與啟動電壓vLED的關係如第2圖 所示’其中陰影區域為無效區（Vin<Vled)。（A)為led 串接數較少時的電壓’無效區較窄；（B)為LED串接數 較多時的電壓’無效區較寬。發光二極體921與飛輪二 極體922、電感923形成一降壓（Buck)電路。輸入電 壓Vin經過橋式整流器902及電阻904後，電壓降為 vdd。電容905與二極體906及電感907並聯。電容905 的電壓達到最低電壓（under voltage lock out，UVLO ) 所需時間約0.8秒，此時可提供第一次啟動的能量。若 第一次啟動成功，則會有電流經過電感923。為了儲存 電源提供的電壓VIN，可藉由切換電感923感應至互感 907「自偏繞組（self bias winding )」產生電流。一般積 體電路（1C )工作電流約2〜3mA。在正常無TRIAC條 件下，1C所需電壓由互感所產生。電容903為電磁干 擾（electric magnetic interruption，EMI)遽波用。二 201246772 極體整流後，線性降壓穩壓器（1〇w dr〇p 〇m Hnear regulator ) ( LD0 ) 9〇8 由 Vdd 降至 vcc ( 5 v )給 ic 内 部用’電容909為5V濾波用。 NM〇S電晶體（Q1 )包括源極、集極及閘極，其 集極連接至發光二極體921。控制電晶體Q1之電路包 括 fWM (pulse Width modulati〇n，脈衝寬度調變）產 生态（或時脈產生器）951、比較器952、RS正反器953 f偵測電阻957。第3圖顯示PWM週期訊號，於電壓 咼時開啟電晶體Q1。為使流經發光二極體921的電流 保持穩定，當V〖N持續增加使VsEN亦增加至Vsen>〇 時，比較器952經由正反器953將電晶體qi關閉，則 Vsen及ISEN下降。然而，當V丨n<Vled時，在此無效區 並無電流流經電晶體Q1，而PWM產生器951仍持續 週期性地使電晶體Q1作開/關切換動作。 、巧 當愈多LED串聯時，無效區時間比率便愈長。此 時，上述電晶體Q1的切換將浪費更多能源。由於電感 923無法藉由互感電流供應電容9〇5足夠的電壓甚^ 低於正常工作電壓。最後必須由電阻904慢慢供應最初 電位，重新啟動ic。如此錯誤循環，將容易使L^D產 生閃爍（flicker )。 了第^ 1圖所示之電源外，在電源端亦常使用交流 矽控管或三極交流（tri-electrode AC，TRIAC )調光 (dimming)控制。第4圖顯示TRIAC導通是由電容 961的電壓決定，觸發導通所需時間會造成相位往後移 動現象。第5圖顯示經過整流二極體962後，火線角度 (firing angle)為9〇度之電壓波型。傳統式電源管^ 之電源來自自偏繞組。因此’當無輸入電源時，功率 NM0S電晶體會持續切換，使v電源迅速消耗。 IC耗盡能量後，過低電壓保護（UVL0) 動= 動’關閉並停止切換NM0S電晶體。當回到重新啟動 201246772 模式，需等VDD滿足UVLO之啟動電壓後方可正常工 作。然而，充電時間卻遠超過TRIAC正常控制週期 (>8ms ) 〇由於停止時間過長及頻繁地啟動、關閉，亦 造成閃爍現象。 為解決上述問題，本發明提出一電路設計，以減少 NMOS電晶體不必要的切換動作。 【發明内容】 本發明之目的在於提供一種切換式電源管理控制 方法及電路，可控制功率MOS電晶體，具有節能及延 長電路使用壽命的功效。 功率MOS電晶體之源極電壓為Vs εν’本發明之切 換式電源管理控制方法至少包括下列步驟：設定一參考 電壓VrEF2 ’於VsEN〈VrEF2 ,且持續一段時間T時，開 啟該功率MOS電晶體，直至Vsen〉Vref2 ’則關閉該功 率MOS電晶體。其中，VREF2<0.3V，較佳為約10〜50mV; 時間 T之滿足係藉由計算 PWM ( pulse width modulation，脈衝寬度調變）或時脈週期訊號之次數而 判定。VSEN與VREF2之比較通常係由一比較器完成。 PWM或時脈週期訊號之次數可為1〜100次，通常為 3〜10次。 本發明控制功率MOS電晶體之電路主要包括偵測 電阻、閘極驅動器、第一比較器、第二比較器、PWM 產生器、RS正反器及零電流計數器。 偵測電阻的一端連接至功率MOS電晶體之源極， 另一端接地，偵測電阻與功率MOS電晶體間之電壓為 VsEN及電流為〗SEN。 閘極驅動器的輸出端連接至功率MOS電晶體之閘 極，驅動功率MOS電晶體為開或關。 第一比較器的負端連接於功率MOS電晶體之源極 與偵測電阻之間，正端設定參考電壓VREF1，輸出端連 201246772 接至RS正反器的重設端。 第一比較态的負端接電阻，正端設定參考電壓 VREF2，且VREF2<VREF1，輸出端連接至零電流計數器。 P WM產生器係輸出p WM週期訊號至RS正反器的 啟動端及零電流計數器。 正反器的啟動端接收PWM週期訊號，重設端 接收第一比較器之訊號，輸出端連接至閘極驅動器。 零電流計數器接收第二比較器及PWM週期訊號， 輸出端連接至閘極驅動器。若Vsen<Vref2的次數連續 超過η次，則輸出訊號至閘極驅動器開啟功率M〇s電 晶體。η可為1〜1〇〇之整數，通常為3〜1〇之整數。 本發明亦可應用於切換式發光二極體（LED)之電 源管理裝置中，LED串可視為負載，可為降壓（Buck) 架構或順向式（Forward)架構。在電源端則可使用傳 統電源控制或交流矽控管或三極交流（tri electr〇de AC，TRIAC)調光控制。 +在vIN>vLED (亦即工作模式）時，功率M〇s電晶 體藉由PWM週期訊號及第一比較器控制開或關。 在Vin<Vled時，VSEN接近零。因此，若連續數個 PWM週期^之VSEN<VREF2 ’便可判定為此狀況。此時， 第一比較器經由閘極驅動器開啟功率M〇s電晶體， 閉PWM產生器及1C中不必要電路的電流，進入休眠 模式。功率MOS電晶體保持開啟，直到Vin>Vled，並 使vSEN>vREF2 ’則關閉功率M0S電晶體，重新啟動pwM 產生器，恢復到工作模式。 【實施方式】 本發明之較佳實施例如第6圖所示，為發光二極 (LED )之切換式電源管理控制電路。交流電源ι〇ι 供起始電壓V【N，EMI濾波電容1〇3可將控制電路進^ 切換控制時所產生之切換雜訊濾除，啟動負載發光二 6 、 —个 201246772 體121所需的電壓為vLED。發光二極體121與飛輪二 極體122、電感123形成一降壓（Buck)電路。起始電 壓Vm經過橋式整流器102的電壓輸出波型為連續μ 型正電壓及電阻104及並聯電容1〇5，流入電位Vdd。 電谷105的電壓達到最低電壓（under voltage lockout， UVLO )所需時間約0.8秒，此時可提供第一次啟動的 能量。若第一次啟動成功，則會有電流經過電感123。 為了儲存電源提供的電壓V1N ’可藉由切換電感123感 應至互感1 〇 7「自偏繞組」的電流。一般驅動積體電路 (1C )工作電流約2〜3mA。在正常條件下，ic所需電 壓由互感所產生’整流二極體1〇6提供單方向電流後， 將互感的電位儲存在電容105並提供1C電源，並經線 性降壓穩壓器（low drop out linear regulator )( LDO ) 108 ’由高壓VDD降至VCC ( 5V)給IC内部用，電容 109為5V濾波用。 NMO S電晶體Q1包括源極、集極及閘極，其集極 連接至電感123,電感123另一端接至發光二極體pi。 控制NMOS電晶體之電路包括PWM產生器151、第一 比較器152、第一比較器154、RS正反器153、零電流 計數器15 5、閘極驅動器15 6及偵測電阻15 7。 偵測電阻157的一端連接至NMOS電晶體的源 極’另一端接地。偵測電阻157與NMOS電晶體之間 的電壓為VSEN，電流為ISEN。閘極驅動器ι56的輸出端 連接至NMOS電晶體的閘極，驅動NMOS電晶體為開 或關。第一比較器152的負端接電阻rsen，正端設& 參考電壓VREF1為0.4 V。第二比較器154的負端接電 阻RSEN，正端設定參考電壓Vref2為3〇 mV。 PWM產生器1 51係用以產生pWM週期訊號，並 傳送至RS正反器153的啟動端（S )及零電流計數器 155。如第3圖所示之PWM週期訊號，於電壓高時開 201246772 啟NMOS電晶體。 當輸入電壓VIN>VLED時，為正常工作模式，PWM 訊號若為電位高，則觸發正反器153的S端，經由閘極 驅動器156開啟NMOS電晶體。但若VSEN>0.4V，第一 比較器152輸出訊號經由RS正反器153的R端及閘極 驅動器156，強制關閉NMOS電晶體；直到下一個PWM 週期開始，再重新開啟NMOS電晶體。 然而，當輸入電壓逐漸降低至Vin<VLED，亦即無 效區（dead zone )時，電流ISEN接近零，電壓VSEN降 低至VSEN<30mV。此狀況可藉由零電流計數器155連 續3次接收到第二比較器154輸出訊號為1來判定。此 時，零電流計數器155輸出訊號至閘極驅動器156，將 NMOS電晶體開啟。同時，驅動裝置中不必要的電流被 關閉，進入休眠模式。PWM產生器151亦可關閉，以 強迫NMOS電晶體保持開啟，等待電流流過，以減少 電晶體的切換動作。 當輸入電壓V〖n逐漸增加至V!n〉Vled，且NMOS 電晶體保持開啟狀悲*電流自然地將流過Rsεν電阻。 若ISEN>0，且VSEN>30mV，則LED驅動裝置恢復工作， 且PWM產生器151被重新啟動，以控制NMOS電晶體 及維持穩定LED輸出恆電流。 在LED端，除了上述的Buck架構，本發明亦適用 於順向式（Forward )架構，可廣泛運用於傳統式照明。 Forward隔離式LED控制電路係利用光搞合器（photo coupler)將LED放在二次側，與AC的一次側隔離。 LED訊號藉由光耦合器將訊號傳至AC控制端。 此外，在電源端亦可使用TRIAC調光控制。使用 本發明之電路設計，由於有效減少NMOS電晶體不必 要的切換動作，將可解決習知TRIAC電路中，因頻繁 地啟動、關閉所造成的閃爍問題。 201246772 實施方法雖係以LED之驅動裝置為較佳 Y本發明之方法及控制電路並不以此為限。貫 【圖式簡單說明】 施 例， =1圖顯示_傳統AC/DC隔離式電源管理控制器。 f 2圖顯示起始輸入電壓Vin與串接led °負載電 vled的關係。 第3圖顯示典型的PWM週期訊號。 第4圖顯示典型的TRIAC電路。 第5圖顯示典型的TRIAC電路中，整流後火線角度為 90度之電壓波型。 第6圖顯示本發明較佳實施例之NMOS電晶體控制電 201246772 【主要元件符號說明】 NMOS電晶體 Q1 交流電源 101 橋式整流器 102 EMI濾波電容 103 電阻 104 電容 105 整流二極體 106 互感 107 線性降壓穩壓器 108 電容 109 發光二極體 121 飛輪二極體 122 電感 123 PWM產生器 151 第一比較器 152 RS正反器 153 第二比較器 154 零電流計數 155 閘極驅動器 156 偵測電阻 157 父流電源 901 橋式整流器 902 EMI濾波電容 903 電阻 904 電容 905 整流二極體 906 電感 907 線性降壓穩壓器 908 電容 909 發光二極體 921 飛輪二極體 922 電感 923 PWM產生器 951 比較器 952 RS正反器 953 偵測電阻 957 電容 961 整流二極體 962201246772 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of switching power management control and a circuit that can be used to control a power MOS transistor. The invention can also be used for switching the light source diode (LED) type power management device to achieve energy saving effect. [Prior Art], the AC/D<: isolated switching power management controller is usually controlled by a power M〇s transistor in order to maintain a stable current. However, frequently switching power MOS transistors in a dead zone not only wastes energy but also limits the range of controller use. Figure 1 shows a switched power management control circuit for a typical buck LED driver. The AC power supply 9〇1 provides an input voltage Vin, and the starting voltage required to illuminate the LED 921 is vle_d. The relationship between the input voltage V1N and the startup voltage vLED is as shown in Fig. 2, where the shaded area is the inactive area (Vin < Vled). (A) is a voltage when the number of LEDs is small, and the 'invalid area is narrow; (B) is a voltage where the number of LEDs is large. The light-emitting diode 921 forms a buck circuit with the flywheel diode 922 and the inductor 923. After the input voltage Vin passes through the bridge rectifier 902 and the resistor 904, the voltage drops to vdd. The capacitor 905 is connected in parallel with the diode 906 and the inductor 907. The time required for the capacitor 905 to reach the minimum voltage lock out (UVLO) is about 0.8 seconds, at which point the energy for the first start can be provided. If the first startup is successful, current will flow through the inductor 923. In order to store the voltage VIN supplied by the power supply, the current can be generated by switching the inductance 923 to the mutual inductance 907 "self bias winding". Generally, the integrated circuit (1C) operates at a current of about 2 to 3 mA. Under normal TRIAC-free conditions, the required voltage for 1C is produced by mutual inductance. Capacitor 903 is used for electromagnetic magnetic interruption (EMI) chopping. Second 201246772 After the body rectification, the linear buck regulator (1〇w dr〇p 〇m Hnear regulator ) ( LD0 ) 9〇8 is reduced from Vdd to vcc ( 5 v ) to the ic internal with 'capacitor 909 for 5V filtering use. The NM〇S transistor (Q1) includes a source, a collector, and a gate, and its collector is connected to the LED 921. The circuit for controlling the transistor Q1 includes a fWM (pulse Width modulati), an ecological generator (or clock generator) 951, a comparator 952, and an RS flip-flop 953 f detecting resistor 957. Figure 3 shows the PWM period signal, which turns on transistor Q1 at voltage 咼. In order to keep the current flowing through the light-emitting diode 921 stable, when V [N] continues to increase such that VsEN also increases to Vsen>, the comparator 952 turns off the transistor qi via the flip-flop 953, and Vsen and ISEN fall. However, when V丨n < Vled, no current flows through the transistor Q1 in this inactive region, and the PWM generator 951 continues to periodically turn on and off the transistor Q1. When more LEDs are connected in series, the time ratio of the invalid area will be longer. At this time, the switching of the above transistor Q1 will waste more energy. Since the inductor 923 cannot supply a sufficient voltage by the mutual current supply capacitor 9〇5, it is lower than the normal operating voltage. Finally, the initial potential must be slowly supplied by resistor 904 to restart ic. Such an error loop will easily cause L^D to produce flicker. In addition to the power supply shown in Figure 1, AC 矽 control or tri-electrode AC (TRIAC) dimming control is often used at the power supply. Figure 4 shows that the TRIAC conduction is determined by the voltage of capacitor 961. The time required to trigger conduction causes the phase to move backward. Fig. 5 shows a voltage waveform having a firing angle of 9 经过 after passing through the rectifying diode 962. The power supply of the conventional power supply tube ^ comes from the self-bias winding. Therefore, when there is no input power, the power NM0S transistor will continue to switch, so that the v power supply is quickly consumed. After the IC runs out of energy, the over-voltage protection (UVL0) activates = 'off' and stops switching the NM0S transistor. When you return to restarting the 201246772 mode, you need to wait for VDD to meet the UVLO startup voltage before it can work normally. However, the charging time is much longer than the TRIAC normal control period (>8ms). Due to the long stop time and frequent startup and shutdown, it also causes flicker. In order to solve the above problems, the present invention proposes a circuit design to reduce unnecessary switching action of the NMOS transistor. SUMMARY OF THE INVENTION An object of the present invention is to provide a switching power management control method and circuit capable of controlling a power MOS transistor, which has the advantages of energy saving and long circuit life. The source voltage of the power MOS transistor is Vs εν'. The switching power management control method of the present invention comprises at least the following steps: setting a reference voltage VrEF2' at VsEN<VrEF2 and continuing for a period of time T, turning on the power MOS transistor The power MOS transistor is turned off until Vsen>Vref2'. Wherein, VREF2 < 0.3V, preferably about 10 to 50 mV; and the time T is satisfied by calculating the number of times of PWM (pulse width modulation) or clock period signal. The comparison of VSEN and VREF2 is usually done by a comparator. The number of PWM or clock cycle signals can be from 1 to 100 times, usually from 3 to 10 times. The circuit for controlling the power MOS transistor of the present invention mainly comprises a detecting resistor, a gate driver, a first comparator, a second comparator, a PWM generator, an RS flip-flop and a zero current counter. One end of the detecting resistor is connected to the source of the power MOS transistor, and the other end is grounded. The voltage between the detecting resistor and the power MOS transistor is VsEN and the current is SEN. The output of the gate driver is connected to the gate of the power MOS transistor, and the driving power MOS transistor is turned on or off. The negative terminal of the first comparator is connected between the source of the power MOS transistor and the detecting resistor, the positive terminal is set to the reference voltage VREF1, and the output terminal is connected to the reset terminal of the RS flip-flop at 201246772. The negative terminal of the first comparison state, the positive terminal sets the reference voltage VREF2, and VREF2 < VREF1, the output terminal is connected to the zero current counter. The P WM generator outputs a p WM period signal to the start of the RS flip-flop and a zero current counter. The start end of the flip-flop receives the PWM period signal, the reset terminal receives the signal of the first comparator, and the output end is connected to the gate driver. The zero current counter receives the second comparator and the PWM period signal, and the output is connected to the gate driver. If the number of Vsen<Vref2 is continuously more than n times, the output signal to the gate driver turn-on power M〇s transistor. η may be an integer of 1 to 1 ,, and is usually an integer of 3 to 1 〇. The present invention can also be applied to a power management device for a switched light-emitting diode (LED). The LED string can be regarded as a load, and can be a Buck structure or a Forward architecture. On the power side, you can use traditional power control or AC 矽 control or tri- electrified AC (TRIAC) dimming control. + In vIN>vLED (ie, operating mode), the power M〇s transistor is turned on or off by the PWM period signal and the first comparator. At Vin<Vled, VSEN is close to zero. Therefore, this condition can be determined if VSEN < VREF2 ' of several consecutive PWM periods ^. At this time, the first comparator turns on the power M〇s transistor via the gate driver, and closes the current of the unnecessary circuit in the PWM generator and 1C, and enters the sleep mode. The power MOS transistor remains on until Vin > Vled, and vSEN > vREF2 ' turns off the power MOS transistor, restarts the pwM generator, and returns to the active mode. [Embodiment] A preferred embodiment of the present invention, as shown in Fig. 6, is a switched-type power management control circuit for a light-emitting diode (LED). AC power supply ι〇ι for the starting voltage V [N, EMI filter capacitor 1 〇 3 can switch the control circuit into the switching noise generated by the switching noise, start the load illuminating two 6, a 201246772 body 121 required The voltage is vLED. The light-emitting diode 121 forms a buck circuit with the flywheel diode 122 and the inductor 123. The initial voltage Vm passes through the bridge rectifier 102 and the voltage output mode is a continuous μ type positive voltage and the resistor 104 and the shunt capacitor 1〇5, and flows into the potential Vdd. The time required for the voltage of the valleys 105 to reach the lowest voltage lockout (UVLO) is about 0.8 seconds, at which point the energy for the first start can be provided. If the first startup is successful, there will be current through the inductor 123. The voltage V1N' supplied by the power supply can be sensed by switching the inductance 123 to the current of the mutual inductance 1 〇 7 "self-bias winding". Generally, the driving integrated circuit (1C) operates at a current of about 2 to 3 mA. Under normal conditions, the voltage required by ic is generated by the mutual inductance. After the rectifying diode 1〇6 provides a unidirectional current, the potential of the mutual inductance is stored in the capacitor 105 and provides a 1C power supply, and is passed through a linear buck regulator (low). Drop out linear regulator ) ( LDO ) 108 ' is reduced from high voltage VDD to VCC ( 5V) for internal IC use and capacitor 109 for 5V filtering. The NMO S transistor Q1 includes a source, a collector and a gate, the collector of which is connected to the inductor 123, and the other end of the inductor 123 is connected to the light-emitting diode pi. The circuit for controlling the NMOS transistor includes a PWM generator 151, a first comparator 152, a first comparator 154, an RS flip-flop 153, a zero current counter 153, a gate driver 156, and a sense resistor 157. One end of the detecting resistor 157 is connected to the source of the NMOS transistor, and the other end is grounded. The voltage between the sense resistor 157 and the NMOS transistor is VSEN, and the current is ISEN. The output of the gate driver ι 56 is connected to the gate of the NMOS transistor to drive the NMOS transistor on or off. The negative terminal of the first comparator 152 is rsen, and the positive terminal & reference voltage VREF1 is 0.4 V. The negative terminal of the second comparator 154 is connected to the resistor RSEN, and the positive terminal setting reference voltage Vref2 is 3 〇 mV. The PWM generator 1 51 is for generating a pWM period signal and transmitting it to the start (S) and zero current counter 155 of the RS flip flop 153. As shown in Figure 3, the PWM period signal turns on the 201246772 NMOS transistor when the voltage is high. When the voltage VIN > VLED is input, it is in the normal operation mode. If the PWM signal is high, the S terminal of the flip-flop 153 is triggered, and the NMOS transistor is turned on via the gate driver 156. However, if VSEN > 0.4V, the first comparator 152 outputs a signal via the R terminal of the RS flip-flop 153 and the gate driver 156 to forcibly turn off the NMOS transistor; until the next PWM period begins, the NMOS transistor is turned back on. However, when the input voltage gradually decreases to Vin < VLED, i.e., the dead zone, the current ISEN approaches zero and the voltage VSEN drops to VSEN < 30 mV. This condition can be determined by the zero current counter 155 receiving the second comparator 154 for three consecutive times and outputting the signal to one. At this time, the zero current counter 155 outputs a signal to the gate driver 156 to turn on the NMOS transistor. At the same time, unnecessary current in the drive unit is turned off and enters sleep mode. The PWM generator 151 can also be turned off to force the NMOS transistor to remain on, waiting for current to flow to reduce the switching action of the transistor. When the input voltage V is gradually increased to V!n>Vled, and the NMOS transistor remains open, the current will naturally flow through the Rsεν resistance. If ISEN > 0, and VSEN > 30 mV, the LED driver resumes operation, and the PWM generator 151 is restarted to control the NMOS transistor and maintain a constant LED output constant current. At the LED end, in addition to the above-described Buck architecture, the present invention is also applicable to a Forward architecture, which can be widely applied to conventional illumination. The Forward isolated LED control circuit uses a photo coupler to place the LED on the secondary side, isolated from the primary side of the AC. The LED signal transmits the signal to the AC control terminal through the optical coupler. In addition, TRIAC dimming control can be used on the power supply side. By using the circuit design of the present invention, the flicker problem caused by frequent activation and shutdown in the conventional TRIAC circuit can be solved by effectively reducing the unnecessary switching action of the NMOS transistor. 201246772 Although the implementation method is preferably a driving device for LEDs, the method and control circuit of the present invention are not limited thereto. [Simplified illustration of the diagram] Example, =1 shows _ traditional AC / DC isolated power management controller. The f 2 diagram shows the relationship between the initial input voltage Vin and the serial led load voltage vled. Figure 3 shows a typical PWM period signal. Figure 4 shows a typical TRIAC circuit. Figure 5 shows the voltage waveform of a typical TRIAC circuit with a rectified fire line angle of 90 degrees. Figure 6 shows an NMOS transistor control system 201246772 according to a preferred embodiment of the present invention. [Main component symbol description] NMOS transistor Q1 AC power supply 101 bridge rectifier 102 EMI filter capacitor 103 resistor 104 capacitor 105 rectifier diode 106 mutual inductance 107 linear Buck Regulator 108 Capacitor 109 LED Diode 121 Flywheel Diode 122 Inductor 123 PWM Generator 151 First Comparator 152 RS Forwarder 153 Second Comparator 154 Zero Current Count 155 Gate Driver 156 Sense Resistor 157 Parent Current Supply 901 Bridge Rectifier 902 EMI Filter Capacitor 903 Resistor 904 Capacitor 905 Rectifier Diode 906 Inductor 907 Linear Buck Regulator 908 Capacitor 909 Light Emitting Diode 921 Flywheel Diode 922 Inductor 923 PWM Generator 951 Compare 952 RS forward and reverse 953 detection resistor 957 capacitor 961 rectifier diode 962