201246170 六、發明說明： 【發明所屬之技術領域】 本發明係為一種液晶顯示器驅動電路，尤指一種減少 下拉式（PuU-down)薄膜電晶體面積，以便於電路佈局之 電路架構。 【先前技術】 近年來，為降低面板的成本，主動式液晶顯示器之開 極驅動電路期_電晶體技術設計已逐漸成為主流的趨 勢：2而，非晶矽薄膜電晶體元件會因為長時間的使用或 者是高正向驗施加而產生臨界電麵漂移，造成薄膜電201246170 VI. Description of the Invention: [Technical Field] The present invention relates to a liquid crystal display driving circuit, and more particularly to a circuit structure for reducing the area of a pull-down (PuU-down) thin film transistor to facilitate circuit layout. [Prior Art] In recent years, in order to reduce the cost of the panel, the open-circuit driving circuit period of the active liquid crystal display has gradually become the mainstream trend: 2, the amorphous germanium thin film transistor component will be long-time Using a high-positive test to create a critical electrical surface drift, resulting in thin film electricity
Transistor，以下簡稱m)的電流驅動 力大幅降低’使得驅動電路的輸出波形失真，進 驅動電路的穩定度，並且造成畫面的顯示品f下降^ a 另外，由於閘極㈣電路賴供之錢源是周期 父w電壓訊號，因此，在電壓信號轉換時，若炎 浮接（floating)的狀態，則容易產鈕^卩”為 (capacitor coupling effect)，使得驅動線 生波動而賴像品質下降，甚至造成軸作㈣況發^發 鑑於傳統的方法之薄膜電晶體佈局面 生。 巧式的液晶顯示器而言，無多餘的空積&大，對於輕 的輸出節點雜訊較多，亦造成影像品佈局’另傳統 路因頻繁驅動某幾個薄膜電晶體而提早老者習知電 路整體的壽命減短，上述的問題皆為 ’ ^成驢動電 決的。 X θ技術内容可解 201246170 f發明内容j 曰顯上所述習知技術的缺失’本發明為一種液 ===路，主要目的為減少下拉式(—) 之之間極的連接點上Γ: 一電容與二電晶體 六電曰 ο即點，可猎由調變第五電晶體與第 八電日日尺寸以延長放電時間 以助該第二電晶體之第m寻第-電曰曰體延遲關閉， 脈信之二㈣在於減少輸出節點雜訊，當第二時 可週期性門啟：：為南電位時’第三電晶體與第五電晶體 動:象開啟即點-茂流路徑’以防止因浮接所產生的波 的漂= 於減緩第三電晶體及第五電晶體 =錢以延長驅動電路之整體壽命。 包括達上述目的，本發為為—種液晶顯示器驅動電路， 括 :串接之複數個移位暫存器，且每-個移位暫存器更包 第一電 Β曰 體 閘極 輕接 ’其中該第一 電晶體之該第 第—極，一第二極及一 極與該閘極相 一第二電晶體， 閘極，耸中該第二電 — 1一第一極，一第二極及 晶體之該第體ί該閘極轉接該第-電 -笛-^極細第二電晶體之該第-極輪接 第二時脈信 ’且第二電晶體之第二極連接一 4 201246170 輪出節點，該第二電晶體之之閘極與第二極之間 連接有一第一電容，i該第一電容與二電晶體之 之閘極的連接點為一節點； 第二電晶體’包括一第一極，一第二極及一 閘極，其中該第三電晶體之第一極耦接該第二電 晶體之該第二極，該第三電晶體第二極耦至一接 地點； 第四電晶體’包括一第一極，一第二極及一 閘極，其中該第四電晶體之該第二極耦接該第三 電晶體之該閘極，該第四電晶體之該第一極耦接 第二時脈信號，且第四電晶體之該第二極耦接 有—第二電容； 第五電晶體，包括一第一極，一第二極及一 ，極，其中該第五電晶體之該閘極耦接該第四電 二體之該第二極’該第五電晶體之該第一極耗接 :亥第-電晶體之該閘極’該第五電晶體之該第二 極轉接該接地點； 門搞第'、電晶體，包括一第一極，一第二極及一 :接:電晶體之該第-極與該閘極相 之該開極，/、晶體之該第二極輕該第五電晶體 节日日遐，包括 閘極，爷坌上φ 使，一弟 號，該；體之該間極轉接-第-咖 該問極，4=之該第一極轉該第五電晶體 第七電晶體之該第二極_接 5 201246170 點；以及 一第八電晶體，包括一第一極，一第二極及一 閘極，該第八電晶體之5玄閘極輕接該第二時脈信 號，該第八電晶體之5亥第一極轉該第一電晶體之 該第一極，该第八電晶體之該第二極耦接該接地 點。 為使貴審查委員對於本發明之結構目的和功效有更 進一步之了解與認同’级配合圖示範例詳細說明如後。 【實施方式】 以下將參照隨附之圖式來描述本發明為達成目的所使 用的技術手段與功效，而以下圖式所列舉之實施例僅為輔 助說明，關㈣查委貝瞭解’但本案之技術手段並不限 於所列舉圖式。 圖一係顯示一液晶顯示器 π邵架構，包括有 、電晶體液晶顯示面板11、—資料驅動電路12、一驅動 路13以及-時序控制器14，其中時序控制器Η用以接 一控制信號且驅動電路13包料接之複數個移位 :5 ^於薄？電晶體液晶顯示面板"、資料驅動電路 述時序控· 14為-傳統的電子裝置，故不在此做一 圖二係顯示根據本發明之移 第一電晶體Τ1，包括一篦k ^ 八匕栝.一 兮够奋 Α 第一極’一第二極及一閘極， 該第一電晶體丁1之哕坌—k h Η 兵甲 ^ το , 第極與該閘極相耦接；一第-雷曰 體Τ2’包括-第—極 w安弟一電曰曰 第一極及一閘極，其令該第二電 6 201246170 :體T2之該間極輕接該第一電晶體τι之該第二極盘 =電晶體T2之該第一極耦接一第二時脈信號，且第二電曰 T2之第二極連接一輸出節點，該第二電晶體打 極與第二極之間連接有一第一電容C1，且該第—電容之= J 一電晶體（n、T2)之之間極的連接點為-節點Q㈤；— 電晶體Τ3,包括—第—極…第二極及1極，其中 ^二電晶體Τ3之第—_接該第二電晶體Τ2之該 Τ4，包ϋ::τ3第二極耦至一接地點;-第四電晶體 μ 第 一第二極及一閑極，其中該第四電晶 之〜苐二極耦接該第三電晶體Τ3之該閘極，該第四. 第一_接一第三時脈信細，且第= 體TWm 帛-極及-閘極，其中該第五電晶 電曰體二=:四電晶體T4之該第二極，該第五 第inTf _㈣第一電晶體T1之該閑極，該 2電曰曰體T5之該第二極耦接該接地點Vss; 一 晶 曰體6T6H一第一極’ 一第二極及一閘極，其中該第六電 =極極與該閘極相_，該第六電晶體T6之 閉極麵接-第-時脈信號CK1，該第七電晶】;;體 極f該第五電晶…該閘極，該第七 -極轉接雜地點Vss; — H晶體Τδ -第二極及一閘極，該第八電晶體Τ8 ’ 時脈信號CK2,該第八電晶體Τ8 Λ ’極耦接5亥第- 电曰曰㈣之該第一極耦該第一電晶 201246170 該第-極’該“電晶體以之該第二_接該接 =第接=移r器所送 接點之該節點Qfn}，可藉日=T1、T2)之閘極的連 體Τ6尺寸以延長放雷電晶體Τ5與第六電晶 以笛^ 寺4 ’使彳寸第二電晶體Τ2延遲關閉， =第晶體72之第二極連接之 : ㈡:一:二信號CK2由低電位轉至高電位時，該第三 位轉至高雷μ ΓΓ 第二時脈信號CK2由低電 D 5亥第二電晶體T3與該第五雷曰辦Τς叮Transistor, hereinafter referred to as m), greatly reduces the current driving force, which makes the output waveform of the driving circuit distorted, enters the stability of the driving circuit, and causes the display of the picture to fall. ^ In addition, due to the source of the gate (four) circuit It is a periodic parent w voltage signal. Therefore, when the voltage signal is converted, if the state of floating is floating, it is easy to produce a coupling coupling effect, so that the driving line fluctuates and the image quality is degraded. Even the shaft (4) condition is issued. In view of the conventional method, the thin film transistor layout is born. In the case of a compact liquid crystal display, there is no extra space product & large, and there are more noises for light output nodes. Image layout [other traditional roads frequently drive a certain number of thin-film transistors, and the older ones know that the overall life of the circuit is shortened. The above problems are all '^成驴电电。 X θ technical content can be solved 201246170 f SUMMARY OF THE INVENTION j The absence of the prior art is a liquid === way, the main purpose of which is to reduce the connection point between the pull-down (-) poles: a capacitor and two The crystal six electric 曰 ο point, can be tuned by modulating the fifth transistor and the eighth electric day size to extend the discharge time to help the mth dynamometer of the second transistor to be turned off, the pulse letter The second (four) is to reduce the output node noise, and the second time can be periodically gated:: for the south potential, the 'third transistor and the fifth transistor move: like the open point-mao flow path' to prevent floating due to The drift of the generated wave = slowing down the third transistor and the fifth transistor = money to extend the overall life of the driving circuit. Including the above purpose, the present invention is a liquid crystal display driving circuit, including: a plurality of serial connections a shift register, and each shift register further includes a first electrical gate gate lightly connected to the first pole, a second pole and a pole of the first transistor The gate phase is a second transistor, and the gate is connected to the second electric body - a first pole, a second pole, and the first body of the crystal. The gate is switched to the first electric-flute-^ The first pole of the very fine second transistor is connected to the second clock signal 'and the second pole of the second transistor is connected to a 4 201246170 round out section a first capacitor is connected between the gate and the second electrode of the second transistor, wherein the connection point between the first capacitor and the gate of the two transistors is a node; the second transistor includes a a first pole, a second pole and a gate, wherein a first pole of the third transistor is coupled to the second pole of the second transistor, and a second pole of the third transistor is coupled to a ground point; The fourth transistor includes a first pole, a second pole and a gate, wherein the second pole of the fourth transistor is coupled to the gate of the third transistor, and the fourth transistor The first pole is coupled to the second clock signal, and the second pole of the fourth transistor is coupled to the second capacitor; the fifth transistor includes a first pole, a second pole and a pole, wherein The gate of the fifth transistor is coupled to the second pole of the fourth electrical body. The first pole of the fifth transistor is: the gate of the second transistor - the fifth The second pole of the crystal is switched to the grounding point; the gate is made of 'the transistor, and includes a first pole, a second pole and a first: the first pole of the transistor and the gate phase The opening pole, /, the second pole of the crystal is light, the fifth transistor holiday day, including the gate, the 坌 坌, 弟 弟, the younger one, the body of the pole transfer - the first - The first pole is turned to the second pole of the fifth transistor of the fifth transistor, and the second pole is connected to the 5 201246170 point; and an eighth transistor includes a first pole and a second pole. a gate, the fifth gate of the eighth transistor is lightly connected to the second clock signal, and the first pole of the eighth transistor is turned to the first pole of the first transistor, and the eighth electrode The second pole of the crystal is coupled to the ground point. In order to enable your review board to have a better understanding and approval of the structural purpose and efficacy of the present invention, the detailed examples of the level matching diagram are as follows. [Embodiment] Hereinafter, the technical means and effects of the present invention for achieving the object will be described with reference to the accompanying drawings, and the embodiments listed in the following drawings are only for the purpose of explanation, and (4) The technical means are not limited to the illustrated figures. 1 shows a liquid crystal display π-shoring structure, including a transistor liquid crystal display panel 11, a data driving circuit 12, a driving circuit 13 and a timing controller 14, wherein the timing controller is used to receive a control signal and The drive circuit 13 is connected to the plurality of shifts: 5 ^ is thin? The transistor liquid crystal display panel "data drive circuit description timing control 14 is a conventional electronic device, so it is not shown here. FIG. 2 shows the first transistor Τ1 according to the present invention, including a 篦k^ gossip.栝 兮 兮 兮 Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α - Thunder body 2' includes - the first pole - the second pole and the first pole, which makes the second electric 6 201246170: the body T2 is extremely lightly connected to the first transistor τι The second pole=the first pole of the transistor T2 is coupled to a second clock signal, and the second pole of the second electrode T2 is connected to an output node, and the second transistor is poled and the second pole Connected to a first capacitor C1, and the junction of the first capacitor = J - the transistor (n, T2) is - node Q (f); - the transistor Τ 3, including - the first pole ... the second pole And a pole, wherein the second transistor Τ3 is connected to the Τ4 of the second transistor ,2, the package:: τ3 is coupled to a grounding point; the fourth transistor μ is the first second pole An idle pole, wherein the second transistor is coupled to the gate of the third transistor ,3, the fourth. The first _ a third clock signal, and the body TWm 帛a pole and a gate, wherein the fifth transistor is the second pole of the fourth transistor T4, the fifth intf_(four) the idle pole of the first transistor T1, the 2 pole The second pole of the body T5 is coupled to the grounding point Vss; the first body of the transistor 6T6H is a second pole and a gate, wherein the sixth pole=pole is opposite to the gate, the sixth The closed-end face of the transistor T6 is connected to the -th clock signal CK1, the seventh transistor; the body electrode f the fifth transistor... the gate, the seventh-pole switching point Vss; The crystal Τ δ - the second pole and a gate, the eighth transistor Τ 8 'clock signal CK2, the eighth transistor Τ 8 Λ 'polar coupling 5 hai - 曰曰 (4) of the first pole coupled to the first a transistor 201246170 the first pole 'the transistor' with the second _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The Siamese Τ 6 size to extend the Thunderbolt Τ 5 and the sixth electro-crystal to the flute ^ Temple 4 ' The second transistor Τ2 is delayed to be turned off, and the second pole of the second transistor 72 is connected: (2): 1: When the second signal CK2 is turned from a low potential to a high potential, the third position is turned to a high lightning μ ΓΓ second clock The signal CK2 is operated by the low voltage D 5 Hai second transistor T3 and the fifth radar
週期性開啟，以使該節點心 阳 I 調變第二電容T2的尺寸㈣料绝出即點〇UT(4流，該 雷曰f W第三電晶體T3及該第五 暫存電路設置於一破璃基板 古亥此電曰體Π _nV"曰曰體係為非晶石夕薄膜電晶體；且 口茨二！日日體 <尔為顏〇S電晶體。 請參閱圖三所示，請同時對照條狀 顯㈣態’其中第一時脈CK1為高電位，第=:數 第二時脈CK3為低電位，前一級輸出 、 晶體π灌入本級Q點並充電至—高出電：立=^ T2開啟將，穩定在一低電位VL:=此時第二電晶體 貼啟沾业能势i兩 L U時第四電晶體T4為 開啟的狀態。第七電晶體T7為開啟狀態將 和第五電晶體Τ5閘極端關流至―低電位，使—其關日曰閉，同 8 201246170 時第= 與第八電晶體Τδ亦處於關閉狀態。 顧-所不’請同時對照條狀點網即為各個來數 顯不之狀態，其中第二日#脑rF9 *丄_ lu，级 ^ CK3 ^ ^ t；, ^ ^ a^^Kl . H T2 一 ；脈CK2開始經由第二電晶Periodically turned on, so that the node yang I modulates the size of the second capacitor T2 (four) material is out of the point 〇UT (4 streams, the thunder f W third transistor T3 and the fifth temporary storage circuit are set A broken glass substrate, Guhai, this electric body Π _nV" 曰曰 system is amorphous 夕 夕 thin film transistor; and mouth two! 日日体< 尔为颜〇 S transistor. Please refer to Figure 3, Please also compare the strip display (four) state, where the first clock CK1 is high, and the second: CK3 is low, the previous output, crystal π is poured into the current Q point and charged to - high Electric: vertical = ^ T2 is turned on, stabilized at a low potential VL: = At this time, the second transistor T4 is turned on when the second transistor is attached to the potential energy i. The seventh transistor T7 is turned on. The state will be closed to the "low potential" of the fifth transistor Τ5 gate, so that it will be closed, and the same as the 8th 201246170, the = and the eighth transistor Τ δ are also closed. The strip-like dot network is the state of the digital display, where the second day # brain rF9 *丄_ lu, level ^ CK3 ^ ^ t;, ^ ^ a^^Kl . H T2 one; pulse CK2 Crystal start via a second electrical
I J Γ ： VH Q 第-電谷Cl t容耦合效應提升一電 =電:驅動能力。第八電晶體T8開啟將前； 點雖舍、Γ 第五電晶體T5的閘極端 2:2第二電容C2和第二時脈CK2轉合(Coupilng) m，但因第四電晶體ΐ4在此階段仍為 態，因此可確保第二雷a驴τ<3 $妨 幻狀 不舍士 和第五電晶體15完全關閉， :會誤開啟，同時第一電晶體T1、第四電晶體Μ、 曰曰體Τ6及第七電晶體Τ7亦處於關閉狀態。 請=圖五所示，請同時對照條狀點網即為各 =之狀態，其中第三時脈c κ 3為高電位一 ，時脈CK2為低電位，下—級輸出高電位VH經由第Γ電 =T6傳至第二電晶體T3和第五電晶體τ5的間極端點。 由於隨設計的關係，使得第五電晶體Τ5的驅動力較低 Q，流的延遲’因此第二電晶體Τ2可以幫助輸出 四電晶體74也因㈣__持開啟狀 I’輸入一南電位VH至第三電晶體T3和第五電晶體乃 閘極端點’同時第-電晶體Π、第七電晶體Τ7及第八雷 晶體Τ8亦處於關閉狀態。 請參閱圖六所示，請同時對照條狀點網即為各個 顯示之狀態，其中當第五電晶體Τ5完全將Q _流至低電 201246170 =VL同二曰電晶體T2和第四電晶體T4即會馬上關 亦處： = 、第七電晶體Π及第八電晶體Τ8 „狀態，完成閘極驅動電路主要的操作步驟。此 寺第二電晶體Τ3和第五電晶體Τ5仍為開啟的狀離。 顯示=圖為梅數 作號(0UT( ΟΠΤ 郎點Q[n]和輸出 Γ i曰:Π+1)、〇UT(n-1))能穩定維持在-低電位VL， 第-電曰曰體T3和第五電晶體T5會經由 出造成誤動作。同時二於；6三)二的二 =藉此可以降低其_漂移，延長電路整體使用壽命 代 =一電晶體T1、第二電晶體T2、第四電晶體τ!、第 :態:體Τ 7、第七電晶體Τ 7及第八電晶體Τ 8亦處於關閉 請，，圖八所示’請同時對照條狀點網即為各個參數 ’其中為延長節點QU]㈣流時間，第五電 曰日體T5的Size設計較小。 後之= : = 晶體經下降時間 ^ Λ 17 國其中圖九Α第五電晶體之臨界電壓 ^ :’0 V’且下降時間為TFALL = 4.9心’但隨 ^第五電晶體之臨界漂移電壓上昇，圖九B顯示第五電曰 體之臨界電壓雖上昇為"丨但是下降時間為曰 FALL = 4.6 //s’足證本發明改善第五電晶體之臨界漂移 10 201246170 電壓。 藉由上述圖一至圖九B所揭露，即可瞭解本發明為一 種液晶顯示器驅動電路，主要技術特徵為減少下拉式 —(Pull-down)薄膜電晶體面積，以便於電路佈局，第一 ^ 容與二電晶體之之閘極的連接點之該節點， 第六電晶尺寸以延長放電時間，使^ =關’以助該第二電晶體之第二極連接之該輸出節 可減少輸出節點雜訊，當第二時脈信號由低電 節點；時’第二電晶體與第五電晶體可週期性開啟 晶體及第五電晶體的漂移電壓以延長驅4 =Si出=示器的市場中，具有極高的= M專利申相尋求專利權之保護。 以之限實:堇=發明之範例實施態樣，當不能 範圍所作之均等變關m依本發明申請專利 之範圍内，謹許1多飾，皆應仍屬於本發明專利涵蓋 月貝審查委員明鑑，並祈惠准，是所至禱。 201246170 【圖式簡單說明】 圖一圖係為本發明液晶顯示器之控制電路架構功能方塊示意 圖二係為本發明驅動電路之較為詳細電路架構與波形 示意圖； ° ' 圖一八係為圖二電路之動作實施例圖； 圖九A、B係為第五電晶體經下降時間後之波形影響示意 圖。 〜 【主要元件符號說明】 I 液晶顯示器 II 薄膜電晶體液晶顯示面板 12 資料驅動電路 13 驅動電路 14 時序控制器 15 移位暫存器 T1〜T8 電晶體I J Γ : VH Q The first-electric valley Cl t capacitive coupling effect is improved by one electricity = electricity: driving capacity. The eighth transistor T8 is turned on; the point is 舍, 闸 the gate terminal 2 of the fifth transistor T5 is 2: the second capacitor C2 and the second clock CK2 are turned (Coupilng) m, but because the fourth transistor ΐ 4 is This stage is still in the state, so it can be ensured that the second thunder a 驴 &< 3 $ 不 不 和 和 and the fifth transistor 15 are completely closed, : will be turned on by mistake, while the first transistor T1, the fourth transistor Μ The body Τ 6 and the seventh transistor Τ 7 are also in a closed state. Please refer to Figure 5. Please refer to the strip dot network for the status of each =, where the third clock c κ 3 is high, the clock CK2 is low, and the lower output is high. The electric current = T6 is transmitted to the intermediate point between the second transistor T3 and the fifth transistor τ5. Due to the design relationship, the driving force of the fifth transistor Τ5 is lower than Q, and the delay of the flow 'so the second transistor Τ2 can help the output of the four transistors 74 also because of the (four) __ holding open state I' input a south potential VH The third transistor T3 and the fifth transistor are the gate terminal 'the same time - the first transistor Π, the seventh transistor Τ7 and the eighth lemma Τ8 are also in a closed state. Please refer to Figure 6, please refer to the strip dot network for the status of each display, when the fifth transistor Τ5 completely flows Q _ to the low electricity 201246170 = VL with the second transistor T2 and the fourth transistor T4 will immediately turn off: =, seventh transistor Π and eighth transistor Τ8 „ state, complete the main operation steps of the gate drive circuit. The second transistor Τ3 and the fifth transistor Τ5 of this temple are still open. The display = the picture is the number of the number (0UT (ΟΠΤ 点 point Q[n] and output Γ i曰: Π +1), 〇 UT (n-1)) can be stably maintained at - low potential VL, The first-electrode body T3 and the fifth transistor T5 may cause a malfunction through the out-and-out. At the same time, the second and the second; the second and the second== thereby reducing the _drift and prolonging the overall life of the circuit=one transistor T1 The second transistor T2, the fourth transistor τ!, the first state: the body Τ 7, the seventh transistor Τ 7 and the eighth transistor Τ 8 are also closed, as shown in Fig. 8 The point network is the parameter of each parameter 'which is the extended node QU' (4), and the size of the fifth e-throat T5 is smaller. The following = : = crystal falling time ^ Λ 17 countries where the threshold voltage of the fifth transistor is 9: '0 V' and the falling time is TFALL = 4.9 heart' but with the critical drift voltage of the fifth transistor rising, Figure 9B shows the fifth power The threshold voltage of the body rises to "丨, but the fall time is 曰FALL = 4.6 //s'. The invention improves the critical drift of the fifth transistor 10 201246170. As disclosed by the above figures 1 to 9B, It can be understood that the present invention is a liquid crystal display driving circuit, and the main technical feature is to reduce the pull-down film transistor area, so as to facilitate the circuit layout, the connection point between the first gate and the gate of the two transistors. The node, the sixth transistor size is extended to extend the discharge time, so that the output section of the second transistor connected to the second transistor can reduce the output node noise, and when the second clock signal is low Node; the second transistor and the fifth transistor can periodically turn on the drift voltage of the crystal and the fifth transistor to extend the drive 4 = Si out = the market of the display, has a very high = M patent application Protection of patent rights. Limitation: 堇= In the example embodiment of the invention, when the equalization of the range cannot be made, m is within the scope of the patent application of the present invention, and it is recommended that the multi-decoration of the invention should still belong to the patent review of the monthly review committee, and pray for it. 201246170 [Simple diagram of the diagram] Figure 1 is a schematic diagram of the control circuit architecture of the liquid crystal display of the present invention. The second is a detailed circuit structure and waveform diagram of the driving circuit of the present invention; ° 'Figure 18 FIG. 9A and B are schematic diagrams showing the influence of the waveform of the fifth transistor after the falling time. ~ [Main component symbol description] I Liquid crystal display II Thin film transistor liquid crystal display panel 12 Data drive circuit 13 Drive circuit 14 Timing controller 15 Shift register T1~T8 transistor
Cl ' C2 電容 OUT(n) ' 0UT(n+l) ' OUT(n-l)輸出信號 CK1、CK2、CK3 時脈信號 Q[n] 節點 gdl、gd3、gs3、gd5、gs5、gs6 雜散電容 Vss 接地點 12Cl ' C2 Capacitor OUT(n) ' 0UT(n+l) ' OUT(nl) Output signal CK1, CK2, CK3 Clock signal Q[n] Node gdl, gd3, gs3, gd5, gs5, gs6 Stray capacitance Vss Grounding point 12