201243942 六、發明說明： 【發明所屬之技術領域】 本發明係關於被配置在處理室內之用來對半導體基板 等的基板，施行蝕刻處理等的規定的電漿處理之聚焦環及 電漿處理裝置。 【先前技術】 以往，蝕刻處理裝置等的電漿處理裝置，例如常用於 半導體裝置的微細電路的製程等之中。 如此的電漿處理裝置，係將半導體晶圓等的被處理基 板配置在被構成可以將其內部氣密地密封之處理室內，並 在此處理室內產生電漿，使此電漿作用在被處理基板上， 而可以施行蝕刻等的電漿處理。 又，在如此的電漿處理裝置內，配置可以包圍被處理 基板亦即半導體晶圓的周圍之被稱爲聚焦環的環狀構件。 此聚焦環的設置目的爲：封閉電漿、及緩和半導體晶圓面 內之由於偏壓的沿面效果所造成的不連續性，使得在半導 體晶圓的周邊部也可以與中央部同樣地進行均勻且良好的 處理。 上述的聚焦環，已知有：配置成可以圍住半導體晶圓 ，並使電介質接近電漿之情況下，使電漿在上方軸方向位 移，利用電漿遠離下部電極，使得電漿中的反應種不會集 中於下部電極周邊，來降低半導體晶圓周邊部的處理速度 (例如參照專利文獻1 )。 -5- 201243942 又，如上所述，由於聚焦環的目的之一在於緩和偏壓 的不連續性，所以使聚焦環的表面（頂面）與要進行處理 的半導體晶圓的處理面大致成爲相同的平面，也就是說， 係使聚焦環的表面（頂面）和半導體晶圓的處理面，其高 度大約相同。又，以往已知有使聚焦環的表面（頂面）比 半導體晶圓的處理面高、或是藉由選擇其材質來緩和偏壓 的不連續性之試驗（例如參照專利文獻2)。 【專利文獻1】日本特表200 1 -5 1 6948號公報（第 13-41 頁、第 1-7 圖） 【專利文獻2】日本特表2003 -5 03 84 1號公報（第 12-22 頁、第 2-6 圖） 【發明內容】 (發明所欲解決之課題） 如上所述，就以往的電漿處理裝置而言，聚焦環被使 用，而藉由使用此種聚焦環，以謀求處理均勻性的提高。 第1 5圖係表示習知的聚焦環的一例，如該圖所示， 在兼作爲下部電極的載置台100上，爲了可以包圍作爲被 處理基板的半導體晶圓W的周圍，例如配置著由矽等的 導電性材料而被形成環狀的聚焦環101。 而且，在第15圖所示的例子之中，聚焦環101的頂 面的高度，係設定成與半導體晶圓W的處理面（表面） 的高度大約相同；結果，聚焦環101上方的電場，變成大 致與半導體晶圓W的表面上方的電場相同，由於偏壓的 -6- 201243942 沿面效果所造成的不連續性被緩和，如圖中的虛線所示， 在半導體晶圓W的上方和聚焦環1〇1的上方，大約相同 高度的電獎鞘（plasma sheath)被形成。藉由如此的電漿 鞘，如圖中的箭頭所示，即使在半導體晶圓W的邊緣部 ，離子也對半導體晶圓W的表面垂直地入射。 然而，使用上述構成的聚焦環101的情況，在半導體 晶圓W的周邊部（邊緣部）的背面側，會發生由CF系聚 合物等所組成的附著物附著之所謂的沉積。 當詳查如此的沉積的原因時，使用上述構成的聚焦環 101的情況，由於半導體晶圓W和聚焦環101大約相同電 位，所以如第1 6圖的擴大圖，在半導體晶圓W的周邊部 (邊緣部）和聚焦環101的內周部之間，以圖中的虛線來 表示其電力線之電場被形成。因此，如圖中的實線的箭頭 所示，電漿變成可以從半導體晶圓W的周邊部（邊緣部 )和聚焦環1 〇 1的內周部之間的中間部分，容易地侵入半 導體晶圓W的背面側的狀態；由於侵入此半導體晶圓W 的背面側之電漿，在半導體晶圓W的周邊部（邊緣部） 的背面側，沉積會發生一事也被推測出來。 本發明係爲了處理此種習知的問題點而開發出來，其 目的在於提供一種聚焦環及電漿處理裝置，即使在半導體 晶圓的周邊部，也能夠進行與半導體晶圓的中央部同樣地 進行良好且均勻的處理，不但能夠提高處理的面內均勻性 ，並且相較於習知技術，可以減少對半導體晶圓的周邊部 背面側之沉積的發生。 201243942 (解決課題所用的手段） 亦即，申請專利範圍第1項的發明，係一種聚焦環， 針對被配置在用來收容被處理基板並施以規定的電漿處理 之處理艙內之載置著前述被處理基板的下部電極上，且可 以包圍前述被處理基板的周圍之形態的環狀聚焦環，其特 徵爲： 具備：由電介質所形成的下側構件；及被配置在此下 側構件的上部，由導電性材料所形成的上側構件； 前述上側構件，其頂面係被形成其外周側比內周側高 的傾斜部，且該傾斜部的外周側端部，係被構成至少位於 比前述被處理基板的被處理面更高的位置，並被配置成與 前述被處理基板的周邊部隔開規定的間隔； 相對於前述被處理基板的被處理面之前述傾斜部的外 周側的高度h，係被構成在〇<h$6mm的範圍內。 又，申請專利範圍第2項的發明，係針對申請專利範 圍第1項所述的聚焦環，其中在前述下部電極和前述下側 構件之間，設置導電性構件。 又，申請專利範圍第3項的發明，係針對申請專利範 圍第2項所述的聚焦環，其中前述導電性構件，係由矽或 矽橡膠所構成》 又’申請專利範圍第4項的發明，係針對申請專利範 圍第1、2或3項所述的聚焦環，其中前述傾斜部的外周 側’係作成比前述被處理基板的被處理面更高的平坦部》 -8- 201243942 又，申請專利範圍第5項的發明，係針對申請專利範 圍第1、2或3項所述的聚焦環，其中前述導電性材料， 係矽、碳或S i C。 又，申請專利範圍第6項的發明’係針對申請專利範 圍第1、2或3項所述的聚焦環’其中相對於前述被處理 基板的被處理面之前述傾斜部的外周側的高度h，係被構 成在2 S h $ 4mm的範圍內。 又，申請專利範圍第7項的發明，係針對申請專利範 圍第1、2或3項所述的聚焦環，其中前述上側構件的縱 剖面中的傾斜部的水平方向的長度1，係被構成在〇.5mm 的範圍內。 又，申請專利範圍第8項的發明，係針對申請專利範 圍第1、2或3項所述的聚焦環，其中前述上側構件和前 述被處理基板的周邊部之間的規定間隔c 1，係被構成在 0.3mm$ CIS 1.5mm 的範圍內。 又，申請專利範圍第9項的發明，係針對申請專利範 圍第1、2或3項所述的聚焦環，其中前述下側構件，係 使電漿和前述下部電極高頻結合’並且對於被施加在下部 電極上的高頻，使阻抗增加。 又，申請專利範圍第10項的發明，係一種電漿處理 裝置，其特徵係具備： 處理艙，此處理艙係用來收容被處理基板’並施行規 定的電漿處理； 下部電極，此下部電極係被設置在前述處理艙內’並 -9- 201243942 載置著前述被處理基板： 下側構件，此下側構件係由電介質所形成，爲環狀的 構件，並被配置在前述下部電極上，且可以包圍前述被處 理基板的周圍；以及 上側構件，此上側構件係被配置在前述下側構件的上 部，而由導電性材料所形成的環狀構件，在其頂面形成其 外周側比內周側高的傾斜部，且該傾斜部的外周側端部， 係被構成至少位於比前述被處理基板的被處理面更高的位 置，並被配置成與前述被處理基板的周邊部隔開規定的間 隔； 相對於前述被處理基板的被處理面之前述傾斜部的外 周側的高度h，係被構成在〇<h$6mm的範圍內。 又，申請專利範圍第11項的發明，係針對申請專利 範圍第1〇項所述的電漿處理裝置，其中在前述下部電極 和前述下側構件之間，設置導電性構件》 又，申請專利範圍第1 2項的發明，係針對申請專利 範圍第11項所述的電漿處理裝置，其中前述導電性構件 ，係由矽或矽橡膠所構成。 又，申請專利範圍第1 3項的發明，係針對申請專利 範圍第10、11或12項所述的電漿處理裝置，其中前述上 側構件的前述傾斜部的外周側，係作成比前述被處理基板 的被處理面更高的平坦部。 又，申請專利範圍第1 4項的發明，係針對申請專利 範圍第10、11或12項所述的電漿處理裝置，其中前述導 -10- 201243942 電性材料，係矽、碳或S i C。 又，申請專利範圍第1 5項的發明，係針對申請專利 範圍第10' 11或12項所述的電漿處理裝置，其中相對於 前述被處理基板的被處理面之前述傾斜部的外周側的高度 h，係被構成在4 mm的範圍內。 又’申請專利範圍第1 6項的發明，係針對申請專利 範圍第10、11或12項所述的電漿處理裝置，其中前述上 側構件的縱剖面中的傾斜部的水平方向的長度1，係被構 成在0.5mmSl$9mm的範圍內。 又，申請專利範圍第1 7項的發明，係針對申請專利 範圍第10、11或12項所述的電漿處理裝置，其中前述上 側構件和前述被處理基板的周邊部之間的規定間隔C 1， 係被構成在0.3 mm S CIS 1.5 mm的範圍內。 又，申請專利範圍第1 8項的發明，係針對申請專利 範圍第10、11或12項所述的電漿處理裝置，其中前述下 側構件，係使電漿和前述下部電極高頻結合，並且對於被 施加在下部電極上的高頻，使阻抗增加。 【實施方式】 (實施發明的最佳形態） 以下，參照圖面來詳細地說明本發明的實施形態。 第1圖係模式地表示關於本發明的實施形態之電漿處 理裝置（蝕刻裝置）全體的槪略構成；在此圖中’符號1 係表示圓筒狀的處理艙（真空艙）；此處理艙，其材質例 -11 - 201243942 如係由鋁等所形成，被構成可以氣密地閉塞其內部，而構 成處理室。 在前述真空艙1的內部，設置載置台2，此載置台2 係由例如鋁等的導電性材料構成塊狀，並兼作爲下部電極 〇 此載置台2,經由陶瓷等的絕緣板3而被支持在真空 艙1內；在載置台2的半導體晶圓W載置面，設置用來 吸著保持半導體晶圓W之未圖示的靜電夾盤。 又，在載置台2的內部，設置：熱媒體流路4，此流 路係用來使作爲溫度控制的熱媒體之絕緣性流體循環；以 及氣體流路5，此流路係用來將氦氣等的溫度控制用氣體 供給至半導體晶圓W的背面^ 而且’藉由在熱媒體流路4內，使被控制在規定溫度 的絕緣性流體循環，將載置台2控制在規定溫度；並且， 經由氣體流路5將溫度控制用的氣體供給至此載置台2和 半導體晶圓W的背面之間，以促進其間的熱交換，而能 夠精度佳且有效率地將半導體晶圓W控制在規定溫度。 又，高頻電源（RF電源）7經由匹配器6連接至載 置台2，而可以自高頻電源7供給規定頻率的高頻電力。 進而’在載置台2的上側周邊部，設置聚焦環8。此 聚焦環8’係由：以電介質（例如石英、氧化鋁等的陶瓷 、VES PEL (登錄商標）等的樹脂）所形成的環狀的下側 構件9 ;及被配置在此下側構件9的上部，而由導電性材 料（例如矽、碳、SiC等）所形成的環狀的上側構件！ 〇 -12- 201243942 所構成；並且被載置成可以包圍被處理基板亦即半導體晶 圓w的周圍。 上述上側構件1 0，如第2圖所示，其頂面的外周側 ’被作成比半導體晶圓W的被處理面更高的平坦部10a; 而此平坦部1 0 a的內周部，係被作成其外周側比內周側高 而傾斜的傾斜部1 Ob。又，上側構件1 0被配置在上側構 件10和半導體晶圓W的周邊部之間，使得間隔C 1被形 成。再者，在第2圖中，P係表示電漿；而就聚焦環8的 部分而言，載置台（下部電極）2，對於自高頻電源7被 施加的高頻電力，介由下側構件9被高頻結合，且藉由下 側構件9 (電介質）介於其間，對於此高頻，阻抗增加。 在此，說明關於聚焦環8被作成上述構成的理由。如 前所述，如第15圖、第16圖所示，聚焦環101，由於半 導體晶圓W和聚焦環1 0 1大約相同電位，所以起因於該 電場的狀態，電漿變成容易繞進半導體晶圓W的端部背 面側。 因此，如第17圖所示，使用將導電性環112載置在 電介質環111的上部之構成的聚焦環110，而在半導體晶 圓W和導電性環1 1 2之間設置電位差，如圖中的虛線的 箭頭所示，形成其電力線自半導體晶圓W的端部朝向導 電性環112之電場。於是，藉由此電場’已知可以抑制電 漿繞進半導體晶圓w的端部背面側之情況。 然而，使用上述構成的聚焦環110的情況，如第17 圖的虛線所示，由於在半導體晶圓w的上方所產生的電 -13- 201243942 漿鞘（plasma sheath)、及被形成在聚焦環110上的電漿 鞘的厚度相異，所以在半導體晶圓W的周邊部，電場傾 斜，因而自上方朝向半導體晶圓W的面碰撞的離子進入 角度，發生傾斜，蝕刻傾斜地進行而發生蝕刻處理的均勻 性降低的問題。 因此，在本實施形態中，係藉由採用上述構成的聚焦 環8，一邊抑制電漿繞進半導體晶圓W的端部背面側，一 邊抑制在半導體晶圓W的周邊部的電場傾斜，來抑制蝕 刻處理的均勻性降低的情況。 又，在上述聚焦環8的外側，設置被構成環狀並形成 有多數個排氣口之排氣環11;經由此排氣環11，藉由與 排氣口 12連接之排氣系統13的真空泵等，構成可以進行 真空臆1內的處理空間的真空排氣。 另一方面’在載置台2上方的真空艙1的天花板部分 ，噴灑頭14係被設置成與載置台2平行地面對面；這些 載置台2和噴氣頭14，係發揮作爲一對電極（上部電極 和下部電極）的功能。又，高頻電源1 6經由匹配器1 5連 接至此噴氣頭14。 上述噴氣頭14，在其底面設置多數個氣體吐出口 17 ’且在其上部具有氣體導入部18。而且，在其內部形成 氣體擴散用空隙19»氣體供給配管20連接至氣體導入部 1 8，而氣體供給系統2 1則連接至此氣體供給配管20的另 一端。此氣體供給系統2 1，係由用來控制氣體流量之質 量流量控制器（MFC ) 22、用來供給例如蝕刻用的處理氣 14- 201243942 體等之處理氣體供給源23等所構成。 接著，說明關於藉由上述般地構成的蝕刻裝置所進行 的蝕刻處理的順序。 首先，使被設置在真空艙1內之未圖示的閘閥開放， 經由被配置成鄰接此閘閥之加載互鎖真空室（未圖示）， 藉由搬送機構（未圖示）將半導體晶圓W搬入真空艙1 內，並載置於載置台2上。並且，使搬送機構退避至真空 艙1外之後，關閉閘閥。 之後，一邊藉由排氣系統13的真空泵，通過排氣口 12，將真空艙1內部排氣至規定的真空度，一邊自處理氣 體供給源23將規定的處理氣體供給至真空艙1內。 而且，在此狀態下，自高頻電源7供給頻率較低的規 定的高頻電力、自高頻電源16供給頻率較高的高頻電力 ，以產生電漀，來進行藉由電漿之半導體晶圓W的蝕刻 〇 而且，若實行規定的蝕刻處理，便停止自高頻電源7 、1 6來的高頻電力的供給，使蝕刻處理停止，並利用與 上述順序相反的順序，將半導體晶圓W搬出真空艙1外 〇 當藉由上述電漿來進行蝕刻處理之時，本實施形態中 的聚焦環8，如上所述，由電介質所形成的下側構件9係 被載置在載置台2上，而由於上側構件1〇被配置在此下 側構件9上，所以與半導體晶圓W相比，上側構件1 〇的 部分的阻抗（對於被施加在載置台2上的高頻電力的阻抗 -15- 201243942 )變高，結果電位降低，而在半導體晶圓W和上側構件 10之間產生電位差°藉由此電位差所形成的電場的作用 ，抑制電漿繞進半導體晶圓w的周邊部背面側，而能夠 抑制在半導體晶圓w的周邊部背面側發生CF系聚合物等 的沉積之情形。 測量第3圖所示之半導體晶圓W的周邊部背面側的 水平部分的端部（〇.〇mm)、自此處算起1.0mm內側的部 分、0.5mm內側的部分、及端面的30°和45°的部分之沉積 量’並將結果表不於第4圖。在表1中，比較例係表示使 用第15、16圖所示的構成的聚焦環101之情況的結果； 實施例1、2係表示使用第1、2圖中所示的上述構成的聚 焦環8之倩況；且實施例1、2係分別表示無灰化（ ashing)、有灰化的情況。又，第4圖的圖表，縱軸係表 示沉積量、橫軸表示半導體晶圓W上的位置，實線A表 示比較例、虛線B表示實施例1、鏈線C表示實施例2。 如第4圖所示，使用聚焦環8的情況，與適用聚焦環101 的情況相比，能夠大幅地降低沉積量。 -16- 201243942 0.5咖 0.0〇» 30* 45* 比較例 27.0 73.05 121.5 184.3 實施例1 0 61.0 61.5 25.5 實施例2 0 14.5 26.0 0 (表l) 又，在本實施形態中，藉由使由上述電介質形成的下 側構件9介於其間，而在半導體晶圓w和上側構件1 〇之 間·產生電位差；在上側構件1 0的頂面，形成其外周側比 內周側較高而傾斜的傾斜部1 0b，並在傾斜部1 Ob的外周 側’形成比半導體晶圓W的被處理面高的平坦部丨0a。如 此’藉由在聚焦環8的頂面，存在比半導體晶圓W的被 處理面高的部分，能夠使被形成在聚焦環8的上方之電漿 的邊界部分’上升至與半導體晶圓W的上方之電漿的邊 界部分’大約相同的高度，而能夠抑制在半導體晶圓W 的周邊部中的電場的傾斜。 又，上述聚焦環8，被形成位於比半導體晶圓W的被 處理面更高的位置之上側構件10的平坦部10a，其作用 係提高電漿鞘的高度，而該電漿鞘高度的變化係藉由傾斜 部1 Ob的存在而被緩和；藉此，能夠抑制在半導體晶圓W 和聚焦環8之間的邊界部分中的急劇的電場變化，例如也 可以抑制電場往第1 7圖所示的情況相反的方向傾斜之情 -17- 201243942 形。 電場模擬的結果’自第2圖所示的傾斜部1 〇 b之半導 體晶圓W的被處理面算起的高度h，理想爲設在〇<hS 6mm的範圍’更理想的範圍是2mm $ 4mn^又，同樣 的，第2圖所示的傾斜部i〇b的水平方向的長度1，理想 爲設定在〇.5mm $ 1 $ 9mm的範圍，更理想爲的範圍是 1mm S 1 $ 6mm。關於此傾斜部10b的水平方向的長度1， 根據半導體晶圓W和聚焦環8之間的間隔C 1，也有可能 設定爲1 = 〇。亦即，雖然此情況成爲沒有傾斜部1 〇 b的形 狀’但是藉由調整半導體晶圓W的端部和聚焦環8之間 的間隔C 1 ’能夠抑制在此部分中的急劇的電場的變化。 再者’第2圖所示的傾斜部1 〇b的下側端部的高度d，理 想爲設定在OSdSlmm的程度。 又’在半導體晶圓W和聚焦環8之間，由於產生電 位差，所以若半導體晶圓W和聚焦環8過於接近，則在 半導體晶圓W上會有產生電弧的可能性。另一方面，半 導體晶圓W和聚焦環8若過於離開，則藉由前述電場所 產生的對於半導體晶圓W背面側之電漿的侵入防止效果 降低。因此，第2圖所示的半導體晶圓W端部和聚焦環8 之間的間隔C1，理想爲設定在0.3 mm S Cl S 1.5 mm的範 圍，更理想爲設定在1.0mmSClS1.5mm的範圍。再者， 關於第2圖所示的半導體晶圓W的端部背面和聚焦環8 之間的間隔C2，同樣地爲了不要產生異常放電，理想爲 設定成0.3mm $ C2 :又，根據同樣的理由，關於第2圖所 -18- 201243942 示的間隔C3’理想爲設定成〇.4mm^C3。 第5圖係表示調查在半導體晶圓w的周邊部之電場 的傾斜之結果；在第5圖（a)的圖表中的縱軸係表示電 場的角度（第2圖所不的角度Θ)、橫軸則表示晶圓上的 位置（如第2圖所示，將半導體晶圓w的端部設爲〗0mm 之其內周部的位置）。 又’在第5圖中，以四方形的記號來表示的曲線A 係表示第1 5圖所示構成的聚焦環的情況、以圓形的記號 來表示的曲線B係表示第17圖所示構成的聚焦環的情況 、以三角形的記號來表示的曲線C和倒三角形的記號來表 不的曲線D係表示關於本實施形態的構成的聚焦環的情 況。再者，三角形記號係表示第2圖所示的丨的長度爲 1mm、h的長度爲3.6mm的情況；倒三角形的記號則表示 第2圖所示的1的長度爲2mm、h的長度爲3.6mm的情況 b 圓 晶 、 澧 a)導 C 半 圖在 5 ， 第況 如情 的 環201243942 VI. [Technical Field] The present invention relates to a focus ring and a plasma processing apparatus which are disposed in a processing chamber for performing a predetermined plasma treatment such as etching treatment on a substrate such as a semiconductor substrate. . [Prior Art] Conventionally, a plasma processing apparatus such as an etching processing apparatus is commonly used in a process of a microcircuit of a semiconductor device or the like. In such a plasma processing apparatus, a substrate to be processed such as a semiconductor wafer is placed in a processing chamber configured to hermetically seal the inside thereof, and plasma is generated in the processing chamber to cause the plasma to be processed. On the substrate, plasma treatment such as etching can be performed. Further, in such a plasma processing apparatus, an annular member called a focus ring that surrounds the periphery of the semiconductor wafer, which is a substrate to be processed, is disposed. The purpose of the focus ring is to close the plasma and to alleviate the discontinuity caused by the creeping effect of the bias in the surface of the semiconductor wafer, so that the peripheral portion of the semiconductor wafer can be uniformly formed in the same manner as the central portion. And good handling. The above-mentioned focus ring is known to be arranged such that it can enclose the semiconductor wafer and bring the dielectric close to the plasma, and the plasma is displaced in the upper axial direction, and the plasma is moved away from the lower electrode to cause the reaction in the plasma. The concentration of the peripheral portion of the semiconductor wafer is not concentrated on the periphery of the lower electrode (see, for example, Patent Document 1). -5- 201243942 Further, as described above, since one of the purposes of the focus ring is to alleviate the discontinuity of the bias voltage, the surface (top surface) of the focus ring is substantially the same as the processing surface of the semiconductor wafer to be processed. The plane, that is, the surface of the focus ring (top surface) and the processing surface of the semiconductor wafer, are about the same height. Further, a test has been known in which the surface (top surface) of the focus ring is made higher than the processing surface of the semiconductor wafer, or the discontinuity of the bias voltage is selected by selecting the material (for example, see Patent Document 2). [Patent Document 1] Japanese Patent Publication No. 2001-5-1646 (P. 13-41, pp. 1-7) [Patent Document 2] Japanese Patent Publication No. 2003-5 03 84 No. 1 (No. 12-22) [Page 2, Fig. 2-6] [Explanation] [Problems to be Solved by the Invention] As described above, in the conventional plasma processing apparatus, a focus ring is used, and by using such a focus ring, Increased processing uniformity. In the fifth embodiment, an example of a conventional focus ring is shown. As shown in the figure, on the mounting table 100 which also serves as a lower electrode, for example, it is arranged to surround the periphery of the semiconductor wafer W as a substrate to be processed. A ring-shaped focus ring 101 is formed of a conductive material such as ruthenium. Further, in the example shown in Fig. 15, the height of the top surface of the focus ring 101 is set to be approximately the same as the height of the processing surface (surface) of the semiconductor wafer W; as a result, the electric field above the focus ring 101, It becomes substantially the same as the electric field above the surface of the semiconductor wafer W, and the discontinuity due to the bias effect of the bias -6-201243942 is alleviated, as indicated by the broken line in the figure, above the semiconductor wafer W and focusing Above the ring 1〇1, approximately the same height of the plasma sheath is formed. With such a plasma sheath, ions are incident perpendicularly to the surface of the semiconductor wafer W even at the edge portion of the semiconductor wafer W as indicated by the arrow in the figure. However, in the case of using the focus ring 101 having the above configuration, so-called deposition of adhering substances composed of a CF-based polymer or the like occurs on the back side of the peripheral portion (edge portion) of the semiconductor wafer W. When the cause of such deposition is examined in detail, in the case of using the focus ring 101 configured as described above, since the semiconductor wafer W and the focus ring 101 have approximately the same potential, the enlarged view of FIG. 6 is on the periphery of the semiconductor wafer W. An electric field between the portion (edge portion) and the inner peripheral portion of the focus ring 101, which is indicated by a broken line in the figure, is formed. Therefore, as indicated by the solid arrows in the figure, the plasma becomes easy to intrude into the semiconductor crystal from the intermediate portion between the peripheral portion (edge portion) of the semiconductor wafer W and the inner peripheral portion of the focus ring 1 〇1. In the state of the back side of the circle W, the deposition of the plasma on the back side of the semiconductor wafer W on the back side of the peripheral portion (edge portion) of the semiconductor wafer W is also estimated. The present invention has been developed in order to deal with such conventional problems, and an object of the invention is to provide a focus ring and a plasma processing apparatus capable of performing the same as a central portion of a semiconductor wafer even in a peripheral portion of a semiconductor wafer. Performing a good and uniform treatment not only improves the in-plane uniformity of the treatment, but also reduces the occurrence of deposition on the back side of the peripheral portion of the semiconductor wafer as compared with the prior art. 201243942 (Means for Solving the Problem) That is, the invention of claim 1 is a focus ring for mounting in a processing chamber for accommodating a substrate to be processed and applying a predetermined plasma treatment An annular focus ring that surrounds the lower electrode of the substrate to be processed and that surrounds the periphery of the substrate to be processed, and includes: a lower member formed of a dielectric; and a lower member disposed thereon The upper member is an upper member formed of a conductive material; the upper member is formed with an inclined portion whose outer peripheral side is higher than the inner peripheral side, and the outer peripheral side end portion of the inclined portion is configured to be at least a position higher than a surface to be processed of the substrate to be processed, and disposed at a predetermined interval from a peripheral portion of the substrate to be processed; and an outer peripheral side of the inclined portion of the processed surface of the substrate to be processed The height h is formed within the range of 〇<h$6 mm. The invention of claim 2 is the focus ring according to the first aspect of the invention, wherein the conductive member is provided between the lower electrode and the lower member. Further, the invention of claim 3 is directed to the focus ring according to claim 2, wherein the conductive member is made of ruthenium or iridium rubber, and the invention of claim 4 is applied. The focus ring according to the first, second or third aspect of the invention, wherein the outer peripheral side of the inclined portion is formed to be a flat portion higher than the processed surface of the substrate to be processed -8-201243942 The invention of claim 5 is directed to the focus ring of claim 1, wherein the conductive material is tantalum, carbon or S i C. Further, the invention of claim 6 is directed to the height h of the outer peripheral side of the inclined portion of the processed surface of the substrate to be processed, in the focus ring of the first, second or third aspect of the patent application. The system is constructed within the range of 2 S h $ 4 mm. Further, the invention of claim 7 is directed to the focus ring according to the first, second or third aspect of the invention, wherein the length 1 of the inclined portion in the longitudinal section of the upper member is formed in the horizontal direction. Within the range of 〇.5mm. The invention of claim 8 is directed to the focus ring of claim 1, wherein the predetermined interval c1 between the upper member and the peripheral portion of the substrate to be processed is It is constructed within a range of 0.3mm$ CIS 1.5mm. Further, the invention of claim 9 is directed to the focus ring of claim 1, 2 or 3, wherein the lower member is a high frequency combination of the plasma and the lower electrode, and is The high frequency applied to the lower electrode increases the impedance. Further, the invention of claim 10 is a plasma processing apparatus characterized by comprising: a processing chamber for accommodating a substrate to be processed and performing a predetermined plasma treatment; a lower electrode, the lower portion The electrode system is disposed in the processing chamber' and -9-201243942 is placed on the substrate to be processed: a lower member, which is formed of a dielectric, is an annular member, and is disposed at the lower electrode And surrounding the periphery of the substrate to be processed; and an upper member disposed on an upper portion of the lower member, and an annular member formed of a conductive material has an outer peripheral side formed on a top surface thereof An inclined portion higher than the inner peripheral side, and an outer peripheral end portion of the inclined portion is formed at least at a position higher than a surface to be processed of the substrate to be processed, and is disposed to be adjacent to a peripheral portion of the substrate to be processed The height h of the outer peripheral side of the inclined portion with respect to the surface to be processed of the substrate to be processed is set to be within the range of 〇<h$6 mm. The invention is directed to the plasma processing apparatus according to the first aspect of the invention, wherein a conductive member is provided between the lower electrode and the lower member, and the patent is applied. The invention is directed to the plasma processing apparatus according to claim 11, wherein the conductive member is made of tantalum or niobium rubber. The invention is directed to the plasma processing apparatus according to claim 10, wherein the outer peripheral side of the inclined portion of the upper member is treated as described above. The flat surface of the substrate to be processed is higher. Further, the invention of claim 14 is directed to the plasma processing apparatus of claim 10, 11 or 12, wherein the conductive material of the above-mentioned guide-10-201243942 is 矽, carbon or S i C. The invention is directed to the plasma processing apparatus according to claim 10, wherein the outer peripheral side of the inclined portion with respect to the surface to be processed of the substrate to be processed is The height h is constructed to be in the range of 4 mm. The invention is directed to the plasma processing apparatus according to claim 10, wherein the longitudinal direction of the inclined portion in the longitudinal section of the upper member is 1 in the horizontal direction, The system is constructed in the range of 0.5 mmSl$9 mm. The invention is directed to the plasma processing apparatus according to claim 10, wherein the upper side member and the peripheral portion of the substrate to be processed have a predetermined interval C. 1, the system is constructed in the range of 0.3 mm S CIS 1.5 mm. The invention is directed to the plasma processing apparatus of claim 10, wherein the lower member is a high frequency combination of the plasma and the lower electrode. And for the high frequency applied to the lower electrode, the impedance is increased. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Fig. 1 is a schematic view showing a schematic configuration of the entire plasma processing apparatus (etching apparatus) according to the embodiment of the present invention; in this figure, the symbol 1 indicates a cylindrical processing chamber (vacuum chamber); Cabin, material example -11 - 201243942 If it is formed of aluminum or the like, it is configured to be airtightly closed to form a processing chamber. In the inside of the vacuum chamber 1, a mounting table 2 is provided. The mounting table 2 is formed of a conductive material such as aluminum, and serves as a lower electrode. The mounting table 2 is placed via an insulating plate 3 such as ceramics. It is supported in the vacuum chamber 1; on the semiconductor wafer W mounting surface of the mounting table 2, an electrostatic chuck (not shown) for absorbing and holding the semiconductor wafer W is provided. Further, inside the mounting table 2, a heat medium flow path 4 for circulating an insulating fluid as a temperature-controlled heat medium, and a gas flow path 5 for sputum are provided. The temperature control gas such as gas is supplied to the back surface of the semiconductor wafer W, and 'the insulating fluid that is controlled at a predetermined temperature is circulated in the heat medium flow path 4, and the mounting table 2 is controlled to a predetermined temperature; The gas for temperature control is supplied between the mounting table 2 and the back surface of the semiconductor wafer W via the gas flow path 5 to promote heat exchange therebetween, and the semiconductor wafer W can be controlled to be precise and efficiently. temperature. Further, the high-frequency power source (RF power source) 7 is connected to the mounting table 2 via the matching unit 6, and the high-frequency power of a predetermined frequency can be supplied from the high-frequency power source 7. Further, a focus ring 8 is provided on the upper peripheral portion of the mounting table 2. The focus ring 8' is an annular lower member 9 formed of a dielectric material (for example, a ceramic such as quartz or alumina, or a resin such as VES PEL (registered trademark); and a lower member 9 disposed thereon. The upper part of the ring, and the upper part of the ring formed of a conductive material (such as tantalum, carbon, SiC, etc.)! 〇 -12- 201243942; and is placed around the semiconductor wafer w which can surround the substrate to be processed. As shown in FIG. 2, the upper member 10 of the top surface is formed as a flat portion 10a higher than the surface to be processed of the semiconductor wafer W, and the inner peripheral portion of the flat portion 10a is formed. The inclined portion 1 Ob whose inclination is higher on the outer peripheral side than the inner peripheral side is formed. Further, the upper member 10 is disposed between the upper member 10 and the peripheral portion of the semiconductor wafer W such that the interval C 1 is formed. Further, in Fig. 2, P denotes plasma; and in the portion of the focus ring 8, the mounting table (lower electrode) 2, the high-frequency power applied from the high-frequency power source 7 is passed through the lower side. The member 9 is bonded at a high frequency and is interposed therebetween by the lower member 9 (dielectric), and the impedance is increased for this high frequency. Here, the reason why the focus ring 8 is formed as described above will be described. As described above, as shown in FIGS. 15 and 16, in the focus ring 101, since the semiconductor wafer W and the focus ring 110 are approximately at the same potential, the plasma becomes easily entangled in the semiconductor due to the state of the electric field. The back side of the end of the wafer W. Therefore, as shown in Fig. 17, a focus ring 110 having a structure in which the conductive ring 112 is placed on the upper portion of the dielectric ring 111 is used, and a potential difference is provided between the semiconductor wafer W and the conductive ring 1 1 2 as shown in the figure. The electric field of the power line from the end of the semiconductor wafer W toward the conductive ring 112 is formed as indicated by the dashed arrow in the middle. Thus, it is known by the electric field 'the fact that the plasma can be prevented from being wound around the back side of the end portion of the semiconductor wafer w. However, in the case of using the focus ring 110 constructed as described above, as shown by the broken line in FIG. 17, the electric-13-201243942 plasma sheath generated above the semiconductor wafer w, and formed in the focus ring Since the thickness of the plasma sheath on the 110 is different, the electric field is inclined at the peripheral portion of the semiconductor wafer W, and thus the ion entering angle colliding from the upper surface toward the surface of the semiconductor wafer W is inclined, and etching is performed obliquely to cause etching treatment. The problem of reduced uniformity. Therefore, in the present embodiment, the focus ring 8 having the above-described configuration is used to suppress the electric field from tilting in the peripheral portion of the semiconductor wafer W while suppressing the plasma from being wound around the end portion of the end surface of the semiconductor wafer W. The case where the uniformity of the etching treatment is suppressed is suppressed. Further, an exhaust ring 11 formed in a ring shape and having a plurality of exhaust ports is formed outside the focus ring 8, and the exhaust ring 11 is connected to the exhaust system 13 via the exhaust port 11 A vacuum pump or the like constitutes a vacuum exhaust that can perform a processing space in the vacuum crucible 1. On the other hand, in the ceiling portion of the vacuum chamber 1 above the mounting table 2, the shower head 14 is disposed opposite to the mounting table 2, and the mounting table 2 and the air jet head 14 function as a pair of electrodes (upper electrode). And the function of the lower electrode). Further, the high frequency power source 16 is connected to the air jet head 14 via the matching unit 15. The air jet head 14 is provided with a plurality of gas discharge ports 17' on its bottom surface and a gas introduction portion 18 at its upper portion. Further, a gas diffusion gap 19 is formed inside the gas supply pipe 20, and the gas supply pipe 2 is connected to the other end of the gas supply pipe 20. The gas supply system 21 is composed of a mass flow controller (MFC) 22 for controlling a gas flow rate, a processing gas supply source 23 for supplying a processing gas such as etching, and the like. Next, the procedure of the etching process performed by the etching apparatus configured as described above will be described. First, a gate valve (not shown) provided in the vacuum chamber 1 is opened, and a semiconductor wafer is transferred by a transfer mechanism (not shown) via a load lock vacuum chamber (not shown) disposed adjacent to the gate valve. W is carried into the vacuum chamber 1 and placed on the mounting table 2. Then, after the transport mechanism is retracted to the outside of the vacuum chamber 1, the gate valve is closed. Thereafter, the inside of the vacuum chamber 1 is exhausted to a predetermined degree of vacuum through the exhaust port 12 by the vacuum pump of the exhaust system 13, and a predetermined processing gas is supplied from the processing gas supply source 23 into the vacuum chamber 1. In this state, a predetermined high-frequency power having a low frequency is supplied from the high-frequency power source 7 and a high-frequency power having a high frequency is supplied from the high-frequency power source 16 to generate an electric power to perform semiconductor by plasma. When the etching process of the wafer W is performed, the supply of the high-frequency power from the high-frequency power sources 7 and 16 is stopped, the etching process is stopped, and the semiconductor crystal is sequentially reversed in the order described above. When the circle W is carried out of the vacuum chamber 1 and the etching process is performed by the above-described plasma, the focus ring 8 of the present embodiment is placed on the mounting table by the lower member 9 formed of the dielectric as described above. 2, since the upper member 1 is disposed on the lower member 9, the impedance of the portion of the upper member 1 is higher than that of the semiconductor wafer W (for the high frequency power applied to the mounting table 2) The impedance -15-201243942) becomes higher, and as a result, the potential is lowered, and a potential difference is generated between the semiconductor wafer W and the upper member 10, and the electric field formed by the potential difference acts to suppress the plasma from being wound around the periphery of the semiconductor wafer w. Back side , While the case of CF-based polymer or the like is deposited on the back surface side can suppress the occurrence of the peripheral portion of the semiconductor wafer w. The end portion (〇.〇mm) of the horizontal portion on the back side of the peripheral portion of the semiconductor wafer W shown in Fig. 3, the portion inside the 1.0 mm from the inside, the portion inside the 0.5 mm, and the end face 30 are measured. The deposition amount of the portion of ° and 45°' and the results are not shown in Fig. 4. In Table 1, the comparative example shows the results of the case where the focus ring 101 having the configuration shown in Figs. 15 and 16 is used; and the first and second embodiments show the focus ring using the above-described configuration shown in Figs. 8 cases; and Examples 1, 2 show ashing and ashing, respectively. Further, in the graph of Fig. 4, the vertical axis indicates the deposition amount, the horizontal axis indicates the position on the semiconductor wafer W, the solid line A indicates a comparative example, the broken line B indicates the first embodiment, and the chain C indicates the second embodiment. As shown in Fig. 4, in the case of using the focus ring 8, the amount of deposition can be significantly reduced as compared with the case where the focus ring 101 is applied. -16- 201243942 0.5 Coffee 0.0〇» 30* 45* Comparative Example 27.0 73.05 121.5 184.3 Example 1 0 61.0 61.5 25.5 Example 2 0 14.5 26.0 0 (Table 1) Further, in the present embodiment, by the above The lower side member 9 formed of the dielectric is interposed therebetween, and a potential difference is generated between the semiconductor wafer w and the upper member 1 ;; on the top surface of the upper member 10, the outer peripheral side thereof is formed to be higher and inclined than the inner peripheral side. The inclined portion 10b has a flat portion 丨0a higher than the processed surface of the semiconductor wafer W on the outer peripheral side ' of the inclined portion 1 Ob. Thus, by having a portion higher than the surface to be processed of the semiconductor wafer W on the top surface of the focus ring 8, the boundary portion of the plasma formed above the focus ring 8 can be raised to the semiconductor wafer W. The boundary portion of the upper plasma is 'about the same height, and the inclination of the electric field in the peripheral portion of the semiconductor wafer W can be suppressed. Further, the focus ring 8 is formed at a position higher than the surface to be processed of the semiconductor wafer W, and the flat portion 10a of the side member 10 is raised to increase the height of the plasma sheath, and the height of the plasma sheath is changed. It is moderated by the presence of the inclined portion 1 Ob; thereby, it is possible to suppress a sharp electric field change in the boundary portion between the semiconductor wafer W and the focus ring 8, and for example, it is also possible to suppress the electric field to the seventh embodiment. The situation shown in the opposite direction is inclined -17- 201243942 shape. As a result of the electric field simulation, the height h from the surface to be processed of the semiconductor wafer W of the inclined portion 1 〇b shown in Fig. 2 is desirably set to a range of 〇 <hS 6 mm, and a more desirable range is 2 mm. $4mn^ Again, in the horizontal direction, the length 1 of the inclined portion i〇b shown in Fig. 2 is desirably set in the range of 〇.5 mm $ 1 $ 9 mm, and more preferably the range is 1 mm S 1 $ 6mm. Regarding the length 1 of the inclined portion 10b in the horizontal direction, it is also possible to set 1 = 根据 depending on the interval C1 between the semiconductor wafer W and the focus ring 8. That is, although this case becomes the shape without the inclined portion 1 〇b, the sharp electric field change in this portion can be suppressed by adjusting the interval C 1 ' between the end portion of the semiconductor wafer W and the focus ring 8 . Further, the height d of the lower end portion of the inclined portion 1 〇b shown in Fig. 2 is desirably set to an extent of OSdSlmm. Further, since a potential difference is generated between the semiconductor wafer W and the focus ring 8, if the semiconductor wafer W and the focus ring 8 are too close, an arc may be generated on the semiconductor wafer W. On the other hand, if the semiconductor wafer W and the focus ring 8 are too apart, the effect of preventing the intrusion of the plasma on the back side of the semiconductor wafer W by the electric field is lowered. Therefore, the interval C1 between the end portion of the semiconductor wafer W and the focus ring 8 shown in Fig. 2 is desirably set to a range of 0.3 mm S Cl S 1.5 mm, and more desirably set to a range of 1.0 mm SClS 1.5 mm. Further, the interval C2 between the end surface of the semiconductor wafer W and the focus ring 8 shown in Fig. 2 is similarly set so as to prevent abnormal discharge, and is preferably set to 0.3 mm $ C2 : For the reason, the interval C3' shown in Fig. 2-18-201243942 is ideally set to 〇.4mm^C3. Fig. 5 is a view showing the result of investigating the inclination of the electric field in the peripheral portion of the semiconductor wafer w. The vertical axis in the graph of Fig. 5(a) indicates the angle of the electric field (the angle Θ in Fig. 2). The horizontal axis indicates the position on the wafer (as shown in Fig. 2, the end of the semiconductor wafer w is set to the position of the inner peripheral portion of 0 mm). In addition, in the fifth drawing, the curve A indicated by the square symbol indicates the case of the focus ring formed as shown in Fig. 5, and the curve B indicated by the circle symbol indicates the figure shown in Fig. 17. The case of the focus ring formed, the curve C indicated by the triangular symbol, and the curve of the inverted triangle indicate the case of the focus ring of the configuration of the present embodiment. Further, the triangular symbol indicates that the length of the crucible shown in Fig. 2 is 1 mm and the length of h is 3.6 mm; the symbol of the inverted triangle indicates that the length of 1 shown in Fig. 2 is 2 mm, and the length of h is 3.6mm case b crystal, 澧a) guide C half figure at 5, the situation of the ring
, 周 示的 焦變 聚斜 的傾 示的 所場 圖電 7 的 第中 用部 使邊 大；在最大的情況，Θ爲82度左右；也就是說，產生面 向內側傾斜8度左右。相對於此，在本實施形態中，如第 5圖（a) 、（c)所示，即使在最大的情況，Θ也爲88度 左右；也就是說，能夠將面向內側的傾斜抑制在最大爲2 度左右。 再者，實際上，藉由蝕刻在半導體晶圓W上形成洞 孔，測量該洞孔從垂直算起的傾斜，其結果也大槪與上述 -19- 201243942 電場的傾斜的結果一致。 如以上所述，若根據本實施形態，與以往相比，能夠 降低對半導體晶圓的周邊部背面側之沉積的發生，並藉由 抑制在半導體晶圓的周邊部中的電場的傾斜，即使是在半 導體晶圓的周邊部，也能夠進行大槪垂直的鈾刻，而能夠 提高處理的面內均勻性。 另外，如上述般地藉由將聚焦環8作成具有傾斜部 10b和平坦部l〇a的構造，能夠增長聚焦環8的壽命。亦 即，藉由採用上述構成，當消耗聚焦環8 (上側構件1 0 ) 時，能夠抑制在聚焦環8上方的電漿鞘高度的降低，即使 是在聚焦環8已經消耗一定程度的情況，也能夠使在半導 體晶圓W的周邊部的離子入射角保持在垂直附近。 以下，說明關於調査由於聚焦環的消耗對電漿鞘的影 響以及對於離子往半導體晶圓W表面的入射角之影響。 首先，如第6圖所示，關於其頂面爲平坦的聚焦環 101，調查關於頂面的高度和在半導體晶圓w的周邊部中 的離子的入射角（圖中以虛線的箭頭表示）之間的關係。 再者，作爲上述調查對象的具體的製程，係形成接觸 孔、貫穿孔等的製程；壓力約爲2〜1 1 Pa、高頻側的RF 功率密度爲3〜5 W、低頻側的RF功率密度爲3〜5 W、半 導體晶圓W的溫度爲80〜12(TC、電極間距離爲25〜 70mm' 氣體系統爲 C4F6 或 C5F8/CxHyFz(C2F6) /Ar/〇2: 30 〜50/10 〜30/500 〜1500/30 〜50sccm 等的製程。 在上述製程中被形成半導體晶圓 W (直徑 200〜 -20- 201243942 300mm)上方的電發鞘的厚度，由於約爲3mm，所以離子 的入射角，關於從厚度3mm的電漿鞘的上端部，自半導 體晶圓W的周邊算起1mm的位置處入射的氬離子，係根 據在半導體晶圓W表面的入射位置，也就是以垂直地入 射的情況作爲原點，而根據自原點算起的直徑方向的變位 量來加以評價。再者，第6圖中，往圖中左側方向變位設 爲負、往右側方向變位設爲正。 上述的情況，聚焦環頂面的高度（將半導體晶圓 W 的處理面（表面）設爲原點，往上方向表示正方向、往下 方向表示負方向）爲+0.3 mm的情況，離子的入射位置的 變位量成爲+〇.〇3mm ;而在聚焦環頂面的高度爲- 0.4mm的 情況，離子的入射位置的變位量成爲-〇.〇5mm。 因此，將離子的入射位置的變位量在+〇.〇3mm〜 -0.05mm範圍，假定爲聚焦環的壽命，來進行比較。 再者，如上所述，頂面爲平坦的聚焦環101，其離子 的入射位置的變位量在+0.03〜-0.05mm的範圍內之情況 ，由於係聚焦環頂面的高度是在+〇.3mm〜-0.4mm的範圍 內，所以在初期狀態，當將聚焦環1 〇1的高度設定爲 + 0 · 3 m m的情況，聚焦環頂面的消耗量在0.7 m m的時候便 應該要交換。 接著，關於與上述聚焦環8同樣的形狀亦即其頂面具 有平坦部和傾斜部之聚焦環，變更第2圖所示的1和h， 說明關於調查聚焦環的頂面（平坦部的表面）和半導體晶 圓W的處理面之間的高度t、及離子的入射位置的變位量 -21 - 201243942 之間的關係之後的結果》再者，聚焦環係假定自初期的狀 態便消耗相似的形狀。 第7圖係表示在上述1爲3mm (電漿鞘厚度相同）的 情況下，調査將h設爲0.5mm (曲線A ) 、1.0mm (曲線 B) 、1.5mm (曲線 C) 、2.0mm (曲線 D) 、2.5mm (曲 線E) 、3.0mm (曲線F)的情況下之高度t和變位量之 間的關係的結果之圖；在該圖中，縱軸係表示離子的入射 位置的變位量（mm )、橫軸係表示聚焦環頂面的高度t ( mm)。再者，爲了進行比較，在圖中以虛線表示前述頂 面爲平坦的聚焦環101的情況。 如該圖所示，h越深則曲線的傾斜越緩，聚焦環頂面 的高度變化時的離子的變位量的變化變少。所以，在上述 範圍內，h越深則聚焦環的壽命變成越長，而可以使交換 周期變長。再者，若以數値來表示第7圖所示的結果，則 h = 0.5的情況，高度t的容許範圍：-0.3〜+ 〇.55mm( 〇.85mm ) h= 1.0的情況，高度t的容許範圍：-0.1〜+0.8mm ( 〇,9mm) h=l .5的情況，高度t的容許範圍：〇〜+1 .〇mm (1.0mm) h = 2.0的情況，高度t的容許範圍：〇〜+ l.lmm ( 1.1mm) h = 2.5的情況，高度t的容許範圍：〇〜+ l.lmm ( 1.1mm) h = 3.0的情況，高度t的容許範圍：-〇〜+1.2mm( -22- 201243942 1.2mm ) 如上所述，當將1設爲與電漿鞘厚度相同的3 mm的 情況，即使h爲0.5mm’局度t的容許範圍爲〇.85mm; 與頂面爲平坦的聚焦環的情況（高度t的容許範圍0.7mm )相比，顯見有明顯的效果。又，藉由將h設爲3.0mm， 高度t的容許範圍變成1.2mm，與頂面爲平坦的聚焦環的 情況相比，能夠將高度t的容許範圍擴大至1.7倍程度。 再者，上述h爲3 _0mm的情況，初期的聚焦環頂面 的高度t = +l .2mm。因此，傾斜部中的高度最低的部分（ 內周側端部）的初期高度，當以半導體晶圓W的處理面 的高度作爲基準的.情況，係位於1.2mm-3.0mm = -1.8mm的 高度，而在比半導體晶圓W的處理面的高度更低的位置 〇 第8圖係表示在上述1爲6mm(電漿鞘厚度的2倍） 的情況下，調查將h設爲0.5mm (曲線A) 、1.0mm (曲 線 B) 、1.5mm (曲線 C) 、2.0mm (曲線 D) 、2.5mm( 曲線E) 、3.0mm (曲線F)的情況下之高度t和變位量 之間的關係的結果之圖； 在該圖中，縱軸係表示離子的入射位置的變位量（ mm)、橫軸係表示聚焦環頂面的高度t( mm)。再者， 爲了進行比較，在圖中以虛線表示前述頂面爲平坦的聚焦 環1 0 1的情況。 如該圖所示，將1設爲6mm的情況，也與將丨設爲 3 m m的情況相同，h越深則曲線的傾斜越緩，聚焦環頂面 -23- 201243942 的高度變化時的離子的變位量的變化變少。In the maximum case, the Θ is 82 degrees or so; that is, the surface is inclined to the inside by about 8 degrees. On the other hand, in the present embodiment, as shown in Figs. 5(a) and 5(c), even at the maximum, the Θ is about 88 degrees; that is, the inclination toward the inside can be suppressed to the maximum. It is about 2 degrees. Further, actually, a hole is formed in the semiconductor wafer W by etching, and the inclination of the hole from the vertical is measured, and the result is also in agreement with the result of the tilt of the electric field described above in -19-201243942. As described above, according to the present embodiment, it is possible to reduce the occurrence of deposition on the back surface side of the peripheral portion of the semiconductor wafer, and to suppress the tilt of the electric field in the peripheral portion of the semiconductor wafer, even if it is conventionally In the peripheral portion of the semiconductor wafer, it is also possible to perform uranium engraving in a large vertical direction, and it is possible to improve the in-plane uniformity of the process. Further, by forming the focus ring 8 as a structure having the inclined portion 10b and the flat portion 10a as described above, the life of the focus ring 8 can be increased. That is, by adopting the above configuration, when the focus ring 8 (upper member 10) is consumed, it is possible to suppress a decrease in the height of the plasma sheath above the focus ring 8, even if the focus ring 8 has consumed a certain degree, It is also possible to maintain the incident angle of ions at the peripheral portion of the semiconductor wafer W in the vicinity of the vertical. Hereinafter, the influence of the consumption of the focus ring on the plasma sheath and the influence of the incidence angle of ions on the surface of the semiconductor wafer W will be described. First, as shown in FIG. 6, regarding the focus ring 101 whose top surface is flat, the height with respect to the top surface and the incident angle of ions in the peripheral portion of the semiconductor wafer w (indicated by a broken arrow in the figure) are investigated. The relationship between. Further, the specific process to be investigated is a process of forming contact holes, through holes, and the like; the pressure is about 2 to 1 Pa, and the RF power density on the high frequency side is 3 to 5 W, and the RF power on the low frequency side. The density is 3~5 W, the temperature of the semiconductor wafer W is 80~12 (TC, the distance between electrodes is 25~70mm', the gas system is C4F6 or C5F8/CxHyFz(C2F6) /Ar/〇2: 30~50/10 Process of ~30/500 to 1500/30 to 50sccm, etc. The thickness of the electric hair sheath above the semiconductor wafer W (diameter 200 to -20-201243942 300mm) formed in the above process is about 3 mm, so the ion The incident angle, with respect to the upper end portion of the plasma sheath having a thickness of 3 mm, argon ions incident at a position of 1 mm from the periphery of the semiconductor wafer W are based on the incident position on the surface of the semiconductor wafer W, that is, vertically The incident state is evaluated as the origin, and is evaluated based on the amount of displacement in the diameter direction from the origin. In addition, in the sixth figure, the displacement in the left direction is set to negative and the direction is shifted to the right. Positive. In the above case, the height of the top surface of the focus ring (will be semiconductor wafer W When the processing surface (surface) is the origin, the forward direction indicates the positive direction, and the downward direction indicates the negative direction) is +0.3 mm, the displacement amount of the incident position of the ions becomes +〇.〇3 mm; and the focus ring When the height of the top surface is -0.4 mm, the displacement amount of the incident position of the ions becomes -〇.〇5 mm. Therefore, the displacement amount of the incident position of the ions is in the range of +〇.〇3 mm to -0.05 mm, assuming For comparison, the life of the focus ring is compared. Further, as described above, the top surface is a flat focus ring 101, and the displacement amount of the incident position of the ions is in the range of +0.03 to -0.05 mm. The height of the top surface of the focus ring is in the range of +〇.3mm to -0.4mm, so in the initial state, when the height of the focus ring 1 〇1 is set to + 0 · 3 mm, the consumption of the top surface of the focus ring When the amount is 0.7 mm, it should be exchanged. Next, the same shape as the focus ring 8 described above, that is, a focus ring having a flat portion and an inclined portion on the top surface thereof, and 1 and h shown in Fig. 2 are changed. Investigate the top surface of the focus ring (the surface of the flat portion) and the semiconductor wafer W The result of the relationship between the height t between the faces and the amount of displacement of the incident position of the ions - 21 - 201243942" Furthermore, the focus ring system assumes that a similar shape is consumed from the initial state. In the case where the above 1 is 3 mm (the thickness of the plasma sheath is the same), it is investigated that h is set to 0.5 mm (curve A), 1.0 mm (curve B), 1.5 mm (curve C), 2.0 mm (curve D), and 2.5. A graph showing the relationship between the height t and the displacement amount in the case of mm (curve E) and 3.0 mm (curve F); in the figure, the vertical axis indicates the amount of displacement of the incident position of the ions (mm) The horizontal axis represents the height t (mm) of the top surface of the focus ring. Further, for comparison, the case where the top surface of the focus ring 101 is flat is indicated by a broken line in the figure. As shown in the figure, the deeper the h, the slower the inclination of the curve, and the change in the amount of displacement of the ions when the height of the top surface of the focus ring changes is small. Therefore, in the above range, the deeper h is, the longer the life of the focus ring becomes, and the longer the exchange period can be. In addition, if the result shown in Fig. 7 is expressed by a number ,, the case where h = 0.5, the allowable range of the height t: -0.3 to + 〇.55 mm (〇.85 mm) h = 1.0, the height t Allowable range: -0.1 to +0.8mm ( 〇, 9mm) h = l .5, the allowable range of height t: 〇 ~ +1 . 〇 mm (1.0mm) h = 2.0, the tolerance of height t Range: 〇~+ l.lmm (1.1mm) h = 2.5, the allowable range of height t: 〇~+ l.lmm (1.1mm) h = 3.0, the allowable range of height t: -〇~+ 1.2mm ( -22- 201243942 1.2mm ) As described above, when 1 is set to the same thickness as the plasma sheath of 3 mm, even if h is 0.5 mm, the allowable range of the degree t is 〇.85 mm; In the case where the surface is a flat focus ring (the allowable range of height t is 0.7 mm), it is apparent that there is a remarkable effect. Further, by setting h to 3.0 mm, the allowable range of the height t becomes 1.2 mm, and the allowable range of the height t can be expanded to about 1.7 times as compared with the case where the top surface is a flat focus ring. Further, in the case where h is 3 _0 mm, the height of the top surface of the initial focus ring is t = +1.2 mm. Therefore, the initial height of the portion (the inner peripheral end portion) having the lowest height among the inclined portions is based on the height of the processed surface of the semiconductor wafer W, and is located at 1.2 mm - 3.0 mm = -1.8 mm. The height is lower than the height of the processing surface of the semiconductor wafer W. Fig. 8 shows that when the above 1 is 6 mm (two times the thickness of the plasma sheath), it is investigated that h is set to 0.5 mm ( Between height A and displacement of curve A), 1.0mm (curve B), 1.5mm (curve C), 2.0mm (curve D), 2.5mm (curve E), 3.0mm (curve F) A graph of the result of the relationship; in the figure, the vertical axis indicates the amount of displacement (mm) of the incident position of the ions, and the horizontal axis indicates the height t (mm) of the top surface of the focus ring. Further, for comparison, a case where the top surface is a flat focus ring 1 0 1 is indicated by a broken line in the figure. As shown in the figure, when 1 is set to 6 mm, the same as the case where 丨 is set to 3 mm, the deeper the h is, the more slowly the slope of the curve is, and the ion at the height of the top surface of the focus ring -23-201243942 changes. The change in the amount of displacement is less.
再者，若以數値來表示第8圖所示的結果，貝IJ h = 0.5的情況，高度t的容許範圍：-0.3〜+ 0.65mm( 0.95mm ) h= 1.0的情況，高度t的容許範圍：0〜+1 .〇mm ( 1.0mm ) h=1.5的情況，高度t的容許範圍：+0.2〜+ l，3mm ( 1.1mm) h = 2.0的情況，高度t的容許範圍：+0.3〜+1.6mm( 1.3mm) h = 2.5的情況’高度t的容許範圍：+0.4〜+ 2.〇mm( 1 · 6mm ) h = 3.0的情況’高度t的容許範圍：+0.5〜+ 2.1mm ( 1 -6mm ) 如上所述’當將1設爲與電漿鞘厚度的2倍亦即6mm 的情況，即使h爲0.5 mm，高度t的容許範圍爲0 95mm ;與頂面爲平坦的聚焦環的情況（高度t的容許範圍 相比’顯見有明顯的效果。又，藉由將h設爲 2·5〜3.0mm，高度t的容許範圍變成16mm，與頂面爲平 坦的聚焦環的情況相比’能夠將高度t的容許範圍擴大至 2倍以上。 再者’以往例如處理時間的積算（累計）時間在4 〇 〇 』時左右，便進行聚焦環的交換。因此，能夠將如此的聚 焦環的交換時間延長至800小時以上的程度。 -24- 201243942 第9圖係表示將縱軸設爲聚焦環（F/R )的消耗容許 範圍△(mm)、將縱軸設爲h (推拔切削深度）（mm) ，而上述1爲3mm的情況（圖中以四方形的符號來表示 )和6mm的情況（圖中以圓形的符號來表示）、以及根 據這些資料而被推定之推拔切削位置1爲9mm的情況（ 圖中以虛線表示）之間的關係。 如該圖所示，h在一定深度的範圍內，越深則聚焦環 的消耗容許範圍△變大，但是在h爲2.5〜3.0mm左右， 則漸傾向飽和。 又，1越長則聚焦環的消耗容許範圍△有變大的傾向 ，理想爲至少將其設定爲與電漿鞘的厚度相同程度（3mm )以上，更理想爲設定爲電漿鞘的厚度的2倍程度（6mm )以上。 如上所述，藉由作成具有傾斜部和平坦部的形狀之聚 焦環，能夠增大聚焦環的消耗容許範圍△。藉此，與以往 相比，能夠使聚焦環的交換循環長期化，而能夠謀求運轉 費用的降低和裝置運轉率的提高。又，自聚焦環壽命的長 期化的觀點，作爲其材質，理想爲使用CVD-SiC ;特別是 由於製造具有與Si的電阻係數（1〜30 Ω)同等的電阻係 數之CVD-SiC成爲可能，所以理想爲使用具有如此的電 阻係數的CVD-SiC。若使用如此的CVD-SiC來構成聚焦 環，則可以得到與使用S i的情況同樣的電特性，而且與 使用Si的情況相比，能夠有2〜3倍的壽命。 另外，上述構成的聚焦環8，此聚焦環8的部分的阻 -25- 201243942 抗有最佳的範圍，理想爲將阻抗的値調整在此最佳的範圍 內。而且，聚焦環8，可以選擇由電介質所形成的下側構 件9的材質，來改變其（電）介質常數；或是藉由改變其 厚度，來調節阻抗。亦即’阻抗Z可以藉由改變由夾著下 側構件9所形成的電容C的値，來進行調整。因此，例如 第10圖所示的聚焦環8，藉由使用厚度d變薄的下側構 件9，並在其下設置導電性構件3 0，來改變電容c，能夠 將阻抗Z調整成所希望的値。又，藉由使導電性構件30 如此地介於下側構件9和載置台2之間，能夠改善下側構 件9和載置台2之間的熱傳導性，將下側構件9控制在規 定溫度，而能夠防止由於過熱而對製程造成不良的影響。 此情況，作爲導電性構件3 0，理想爲使用熱傳導性良好 的材質，例如矽或矽橡膠等的材質。 在此，在半導體晶圓W的下側部分，實際上也設置 用來構成靜電夾盤之絕緣性構件（厚度例如〇.6mm);由 於此絕緣性構件的影響，產生與上述同樣的阻抗。將此半 導體晶圓W的部分的阻抗設爲Z0，若要將阻抗z的値調 整成（Ζ/Ζ0 ) =60的程度，則將下側構件9的頂面（或底 面）的面積設爲S、厚度設爲d、介質常數設爲e、真空 的介質常數設爲ε0，則由於Ζ=ε0. ε (S/d),所以在 下側構件9的材質爲水晶（石英），內徑大約爲3 0 0 m m ，外徑大約爲360mm的情況，其厚度理想爲設定在5〜 10mm程度，更理想爲設定在7〜9mm。 接著，說明關於其他的實施形態。第1 1圖係模式地 -26- 201243942 表示此實施形態的聚焦環的剖面構成。如前所述，載置著 半導體晶圓W之載置台2，係藉由絕緣板3而被支持，而 高頻電源7則與載置台2連接。 進而，在載置台2的上側周邊部，設置聚焦環50。 此聚焦環5 0，係由：以電介質（例如石英、氧化鋁等的 陶瓷、VES PEL (登錄商標）等的樹脂）所形成的環狀的 下側構件5 1 ;及被配置在此下側構件5 1的上部，而由導 電性材料（例如矽、碳、SiC等）所形成的環狀的上側構 件52所構成；並且被載置成可以包圍被處理基板亦即半 導體晶圓W的周圍。 上述上側構件52，例如介由高頻接地用構件53，此 高頻接地用構件5 3係由鋁等的導電性材料所形成，並藉 由陶瓷的熔射膜（例如Al/Al2〇3、Y203等的FCC (細密 陶瓷塗膜））等的絕緣層（絕緣膜）將其表面包覆，而對 於高頻電力，被連接至接地電位。此絕緣層，其形成目的 在於保護高頻接地用構件53，使其免受電漿的影響，並 防止直流電流流過。亦即，此絕緣層具有使直流電流無法 通過之充分的厚度，直流電流被阻擋在此絕緣層而無法傳 播。另一方面，作爲表面波而可以經由固體表面傳播的高 頻（RF )，則可以在高頻接地用構件5 3的表面層傳播； 該高頻接地用構件5 3，係作爲高頻的接地經路。進而， 在高頻接地用構件5 3和地線之間，爲了阻礙高頻的回路 ，也可以夾著對應用來生成電漿所施加的高頻電力的頻率 之高通濾波器或低通濾波器等的頻率截止濾波器、頻率衰 -27- 201243942 減濾波器等。又，在高頻接地用構件5 3和地線之間，設 置開關手段，與製程方法連動，而可以在規定的時序，將 高頻控制成降低至接地或是沒有接地。在此高頻接地用構 件5 3和載置台2之間以及上側構件52的外周側（高頻接 地用構件53的上側），配置由被形成環狀的電介質（例 如石英、氧化鋁等的陶瓷、VES PEL (登錄商標）等的樹 脂）所形成的絕緣構件5 4、5 5。如此的絕緣構件5 4，係 用來使直流電壓成分不會自載置台2往外側洩漏。又，絕 緣構件55，其作用係使得電漿不會過度地往外周方向擴 展，限制電場以防止電漿過度地擴展而自排氣擋板（未圖 示）洩漏至排氣側。 將縱軸設爲電壓、橫軸設爲時間週期之第12圖的圖 形，係表示半導體晶圓W和聚焦環5 0及電漿的電位（電 壓）之時間的變化的狀態之圖。如該圖的曲線A所示， 半導體晶圓W的電位，係對應自高頻電源7被施加的高 頻的頻率（例如2MHz)而變化。 另一方面’聚焦環50的上側構件52，由於相對於高 頻電力係被作成接地電位’所以其電位係如直線B所示地 成爲一定。因此，高頻的循環，在正側的時候或是在負側 的時候’皆可以如圖中的箭頭所示，能夠增大半導體晶圓 W和上側構件5 2之間的電位差。 再者’在該圖中，曲線C係表示電漿電位的變化、曲 線D係表示第2圖所示的聚焦環8的上側構件1 〇的電位 的變化。如曲線D所示，第2圖所示的聚焦環8的情況 -28- 201243942 ，高頻的循環在變成正側的時候’半導體晶圓w和上側 構件1 0之間的電位差變小。藉由如上述般地將上側構件 5 2相對於高頻電力作成接地電位’能夠抑制如此的伴隨 著高頻的振動之電位差的變動。 將縱軸設爲聚合物厚度、將橫軸設爲斜面位置之第 13圖（A)的圖形，係表示在第13圖（B)所示的半導體 晶圓的斜面部之〇、30、45、90度的位置處之測量聚合物 的附著量的結果。就第13圖（A )而言’實線E係使用 第15圖所示的習知的聚焦環101的情況、實線F係使用 第2圖所示的聚焦環8的情況、實線G係表示使用第1 1 圖所示的聚焦環50的情況。如此個所示，使用聚焦環50 的情況，能夠增高半導體晶圓和聚焦環之間的電場強度， 藉此防止電漿的繞進，由於能夠減少在其間的自由基的量 ，故比使用聚焦環8的情況，更能減少在晶圓斜面部之聚 合物的沉積量。 再者’在上述實施形態中，已經說明了藉由高頻接地 用構件53’相對於高頻電力，將上側構件52連接至接地 電位的情況’但是也可以不使用如此構造的高頻接地用構 件5 3，而利用其他的方法，相對於高頻電力，將上側構 件52連接至接地電位。 第1 4圖（a )係模式地表示關於其他實施形態的聚焦 環ό 0的剖面構成。如前所述，載置著半導體晶圓w之載 置台2’係藉由絕緣板3而被支持，而高頻電源7則與載 置台2連接。 -29- 201243942 進而’在載置台2的上側周邊部，設置聚焦環60。 此聚焦環6 0 ’係由：以電介質（例如石英、氧化鋁等的 陶瓷、VES PEL (登錄商標）等的樹脂）所形成的環狀的 下側構件6 1 ;及被配置在此下側構件6 1的上部，而由導 電性材料（例如矽、碳、S i C等）所形成的環狀的上側構 件62所構成； 並且被載置成可以包圍被處理基板亦即半導體晶圓W 的周圍。 上述上側構件62，例如介由高頻接地用構件63，此 高頻接地用構件63係由鋁等的導電性材料所形成，並藉 由陶瓷的熔射膜（例如A1/A1203、Y203等的FCC (細密 陶瓷塗膜））等的絕緣層（絕緣膜）將其表面包覆，而對 於高頻電力’被連接至接地電位。此絕緣層，其形成目的 在於保護高頻接地用構件63，使其免受電漿的影響，並 防止直流電流流過。亦即，此絕緣層具有使直流電流無法 通過之充分的厚度，直流電流被阻擋在此絕緣層而無法傳 播。另一方面，作爲表面波而可以經由固體表面傳播的高 頻（RF )，則可以在高頻接地用構件63的表面層傳播； 該高頻接地用構件63，係作爲高頻的接地經路。在此高 頻接地用構件6 3和載置台2之間以及上側構件62的外周 側（高頻接地用構件63的上側），配置由被形成環狀的 電介質（例如石英、氧化鋁等的陶瓷、VES PEL (登錄商 標）等的樹脂）所形成的絕緣構件64、65。如此的絕緣 構件64，係用來使直流電壓成分不會自載置台2往外側 -30- 201243942 洩漏。又，絕緣構件65，其作用係使得電漿不會過度地 往外周方向擴展，限制電場以防止電漿過度地擴展而自排 氣擋板（未圖示）洩漏至排氣側。 進而，在本實施形態中，在下側構件61和上側構件 62之間’設置規定的間隔D ;此規定的間隔D大約設爲 0 · 5 mm。又’隔著此間隔D之下側構件6 1和上側構件62 互相面對面的部分的直徑方向的長度L，係設爲5〜10mm 。又’上側構件62的下端，係構成位於比半導體晶圓w 的頂面更高1.5〜2.5mm(圖中的H)的位置。作成如此 的構成的理由，係如以下所述。 亦即，爲了減少前述的半導體晶圓的斜面部（第13 圖（B )的90°、45°、30°處）以及半導體晶圓端部背面（ 第13圖（B)的0°處）的聚合物的附著量，在電漿處理 中，希望將下側構件61的溫度保持在比較低的溫度例如 比100 °C低的溫度，進而更理想爲保持在70 °C以下的溫度 。另一方面，上側構件62，在電漿處理中，希望保持在 比較高的溫度例如2 5 0 °C以上。其理由爲：藉由將上側構 件62的溫度設爲25 0°C以上，促進氟自由基和Si的結合 ，能夠減少氟自由基的量，藉此在光阻或是SiN等的化學 反應性強的蝕刻應用中，能夠抑制蝕刻率在半導體晶圓的 周邊部上升的現象。如此，爲了將下側構件61的溫度和 上側構件62的溫度維持在相異的溫度，而在下側構件6 i 和上側構件62之間，設置規定間隔D。又，爲了使上側 構件62的溫度上升，需要提高如圖中的箭頭所示地自載 -31 - 201243942 置台2通過下側構件6 1、上側構件62、高頻接地用構件 63的路徑而流動高頻（頻率例如爲2MHz)施加電壓，藉 由焦耳熱加熱上側構件62。因此，需要降低上述路徑的 阻抗。爲了作成可以滿足此種條件，間隔D理想爲設成 大約爲0.5mm程度》 也就是說，爲了滿足此條件而將間隔D設爲0.5mm 程度，係基於當施加2MHz的高頻電力時，爲了將上側構 件62加熱至規定溫度也就是250°C以上，相對於電漿阻 抗Zp，至少需要3〜10倍的阻抗。於是，由於高頻爲交 流，負載效果不僅是電阻，也需要考慮靜電容量（電容） 或電感（線圈），而且若以綜合這些因素的阻抗（對於交 流之電流對抗成分）來考量，則可以如下述般地說明。將 上側構件62和高頻接地用構件63之間的接合部分的阻抗 設爲Z1，將間隔D的阻抗設爲Z2，Z2至少具有Z1的10 倍的阻抗之高電阻，由於自控制性的觀點來考量是理想的 ，所以若設成Z2> > Zl、Z22 ΙΟχΖΙ，則如第14圖（b) 所示，爲了要控制Z1+Z2 > ZP的公式可以成立，阻抗〔 Ω〕可以根據Ζ= ε 0S/D的公式來求得。（ε 0 =真空的介 質常數、S =面積〔m2〕、D =間隔〔m〕） 下側構件61的表面積，在200mm晶圓和300mm晶 圓的情況，係分別相異，所以若將所希望的下側構件6 1 的表面積帶入上述公式中，便可以根本地決定間隔D»也 就是說，不僅是半導體晶圓，也可以應用於對面積更大的 LCD面板等進行電漿處理之基板處理裝置的下側構件中。 -32- 201243942 藉此，上側構件62和下側構件6 1，不但由於未接觸而能 夠採用沒有傳熱的構成’自高頻電源7產生的表面波亦即 高頻，藉由靜電誘導原理通過電容（間隔D)而傳至上側 構件62。又，在間隔D之處若夾著絕熱材，則該處的介 質常數係根據絕熱材的介質常數而被限制，而若如本實施 形態般地構成真空電容，則利用控制處理室內的真空度便 能夠可變控制介質常數ε，所以控制性優異。 再者，爲了減少熱傳導，防止熱流失，也可以在上側 構件62和高頻接地用構件63之間設置間隔。又，只要可 以將下側構件6 1和上側構件62控制成上述的溫度，也可 以採用其他的方法。 又，爲了控制半導體晶圓的周邊部的電場，以進行如 前所示地大約垂直的蝕刻，如上所述，上側構件62的下 端係構成位於比半導體晶圓W的頂面更高1.5〜2.5 mm ( 圖中的Η)的位置處。 若根據上述構成的本實施形態，除了能夠減少在晶圓 斜面部之聚合物的沉積量以外，並能抑制光阻的蝕刻率在 半導體晶圓的周邊部上升的現象，而且即使在半導體晶圓 的周邊部，也能夠進行大約垂直的蝕刻，而能夠提高處理 的面內均勻性。 (產業上的利用可能性） 關於本發明的聚焦環及電漿處理裝置，可以利用於半 導體裝置的製造產業中。因此，具有產業上的利用性。 -33- 201243942 (發明之效果） 若根據本發明，即使是在半導體晶圓的周邊部’也能 夠與半導體晶圓的中央部同樣地進行良好且均勻的處理’ 不但能夠提高處理的面內均勻性’並且與以往相比’能夠 減少在半導體晶圓的周邊部背面側之沉積的發生。 【圖式簡單說明】 第1圖係表示本發明的一實施形態之電漿處理裝置的 槪略構成的圖。 第2圖係將第1圖的電漿處理裝置的聚焦環的重要部· 分加以擴大表示的圖。 第3圖係用來說明沉積的測量部位的圖。 第4圖係表示在第3圖的測量部位中的沉積的測量結 果。 第5圖係表示在晶圓上的各位置中的電場的角度的圖。 第6圖係用來說明離子的入射角的變位量的評價方法 的圖。 第7圖係表示離子的入射角的變位量和聚焦環的高度 之關係的圖。 第8圖係表示離子的入射角的變位量和聚焦環的高度 之關係的圖。 第9圖係表示推拔切削深度和聚焦環的消耗量容許範 圍之間的關係的圖。 -34- 201243942 第10圖係用來說明阻抗的調整方法的圖。 第11圖係表示關於其他實施形態的聚焦環的構成的 圖。 第1 2圖係表示各部的電位的週期變動態樣之圖。 第1 3圖係表示測量對晶圓的斜面部之聚合物的附著 量的結果之圖》 第1 4圖係表示關於其他實施形態的聚焦環的構成的 圖。 第15圖係表示習知的聚焦環的構成的圖。 第16圖係用來說明第15圖的聚焦環中的電場的狀態 之圖。 第17圖係表示在使用電介質的聚焦環中的電場和電 漿鞘的狀態之圖。 【主要元件符號說明】 W :半導體晶圓 1 :真空艙 2 :載置台 8 :聚焦環 9 :下側構件 1 0 :上側構件 l〇a :平坦部 l〇b :傾斜部 1 4 :噴氣頭 -35-Furthermore, if the result shown in Fig. 8 is expressed by a number, the case where the shell IJ h = 0.5, the allowable range of the height t: -0.3 to + 0.65 mm (0.95 mm) h = 1.0, the height t Allowable range: 0 to +1. 〇mm (1.0mm) h=1.5, the allowable range of height t: +0.2~+ l, 3mm (1.1mm) h = 2.0, the allowable range of height t: + 0.3~+1.6mm (1.3mm) h = 2.5 case 'allowable range of height t: +0.4~+ 2.〇mm(1 · 6mm) h = 3.0 case 'allowable range of height t: +0.5~+ 2.1mm (1 -6mm ) As described above, 'When 1 is set to 2 times the thickness of the plasma sheath, that is, 6 mm, even if h is 0.5 mm, the allowable range of height t is 0 95 mm; flat with the top surface The case of the focus ring (the allowable range of the height t is obviously obvious compared to 'the obvious. Again, by setting h to 2·5 to 3.0 mm, the allowable range of the height t becomes 16 mm, and the top surface is flat. In the case of the ring, the allowable range of the height t can be expanded by a factor of two or more. In the past, for example, when the integrated (accumulated) time of the processing time is about 4 〇〇, the focus ring is exchanged. Therefore, the exchange time of such a focus ring can be extended to 800 hours or more. -24- 201243942 Fig. 9 shows the vertical axis as the allowable range of the focus ring (F/R) Δ (mm), The vertical axis is set to h (pushing depth of cut) (mm), and the above 1 is 3 mm (indicated by a square symbol in the figure) and 6 mm (indicated by a circular symbol in the figure), and Based on these data, it is estimated that the relationship between the cutting position 1 and the cutting position 1 is 9 mm (indicated by a broken line in the figure). As shown in the figure, h is within a certain depth range, and the deeper the focus ring is allowed to be consumed. Although the range Δ is large, the saturation tends to be saturated when h is about 2.5 to 3.0 mm. Further, the longer the length of 1 is, the more the allowable range Δ of the focus ring tends to be larger, and it is preferable to set it at least with the plasma sheath. The thickness is equal to or greater than (3 mm) or more, and more preferably set to be twice (6 mm) or more the thickness of the plasma sheath. As described above, the focus ring having the shape of the inclined portion and the flat portion can be increased. The allowable range of the consumption of the focus ring is Δ. The ratio of the switching cycle of the focus ring can be made longer, and the operating cost can be reduced and the device operating rate can be improved. Further, from the viewpoint of the long-term life of the focusing ring, it is preferable to use CVD-SiC as a material thereof. Since it is possible to manufacture CVD-SiC having a resistivity equivalent to that of Si (1 to 30 Ω), it is desirable to use CVD-SiC having such a resistivity. When such a CVD-SiC is used to form the focus ring, the same electrical characteristics as in the case of using Si can be obtained, and it is possible to have a life of 2 to 3 times as compared with the case of using Si. Further, in the focus ring 8 constructed as described above, the resistance of the portion of the focus ring 8 is in the optimum range, and it is desirable to adjust the 値 of the impedance within the optimum range. Further, the focus ring 8 can be selected from the material of the lower member 9 formed of a dielectric to change its (electro) dielectric constant; or the impedance can be adjusted by changing its thickness. That is, the impedance Z can be adjusted by changing the 値 of the capacitance C formed by sandwiching the lower member 9. Therefore, for example, the focus ring 8 shown in Fig. 10 can be adjusted to the desired impedance by changing the capacitance c by using the lower member 9 having a reduced thickness d and providing the conductive member 30 under it. Hey. Further, by causing the conductive member 30 to be interposed between the lower member 9 and the mounting table 2, the thermal conductivity between the lower member 9 and the mounting table 2 can be improved, and the lower member 9 can be controlled to a predetermined temperature. It can prevent adverse effects on the process due to overheating. In this case, as the conductive member 30, a material having good thermal conductivity, for example, a material such as tantalum or niobium rubber is preferably used. Here, in the lower portion of the semiconductor wafer W, an insulating member (having a thickness of, for example, 66 mm) for constituting the electrostatic chuck is actually provided; and the same impedance as described above is generated by the influence of the insulating member. The impedance of the portion of the semiconductor wafer W is Z0, and if the 阻抗 of the impedance z is adjusted to (Ζ/Ζ0) = 60, the area of the top surface (or the bottom surface) of the lower member 9 is set to S, the thickness is d, the dielectric constant is e, and the dielectric constant of the vacuum is ε0. Since Ζ=ε0. ε (S/d), the material of the lower member 9 is quartz (quartz), and the inner diameter is approximately In the case of 300 mm and an outer diameter of about 360 mm, the thickness is desirably set to about 5 to 10 mm, and more desirably set to 7 to 9 mm. Next, other embodiments will be described. Fig. 1 is a schematic diagram showing the cross-sectional configuration of the focus ring of this embodiment. As described above, the mounting table 2 on which the semiconductor wafer W is placed is supported by the insulating plate 3, and the high-frequency power source 7 is connected to the mounting table 2. Further, a focus ring 50 is provided on the upper peripheral portion of the mounting table 2. The focus ring 50 is an annular lower member 5 1 formed of a dielectric material (for example, a ceramic such as quartz or alumina or a resin such as VES PEL (registered trademark); and is disposed on the lower side thereof. The upper portion of the member 51 is composed of an annular upper member 52 formed of a conductive material (for example, tantalum, carbon, SiC, etc.), and is placed so as to surround the substrate to be processed, that is, the periphery of the semiconductor wafer W. . The upper member 52 is formed, for example, by a high-frequency grounding member 53 made of a conductive material such as aluminum, and is formed of a ceramic spray film (for example, Al/Al 2 〇 3, An insulating layer (insulating film) such as FCC (fine ceramic coating film) such as Y203 coats the surface thereof, and is connected to a ground potential for high-frequency power. This insulating layer is formed to protect the high-frequency grounding member 53 from the influence of the plasma and to prevent the direct current from flowing. That is, the insulating layer has a sufficient thickness that the direct current cannot pass, and the direct current is blocked in the insulating layer and cannot be propagated. On the other hand, a high frequency (RF) that can propagate through a solid surface as a surface wave can propagate on the surface layer of the high-frequency grounding member 53; the high-frequency grounding member 53 is used as a ground for high-frequency grounding. The road. Further, a high-pass filter or a low-pass filter corresponding to a frequency for generating high-frequency power applied by the plasma may be interposed between the high-frequency grounding member 53 and the ground line in order to block the high-frequency circuit. Equal frequency cut-off filter, frequency fading -27- 201243942 minus filter, etc. Further, a switching means is provided between the high-frequency grounding member 53 and the ground line in conjunction with the manufacturing method, and the high frequency can be controlled to be grounded or not grounded at a predetermined timing. A dielectric (for example, a ceramic such as quartz or alumina) is formed between the high-frequency grounding member 53 and the mounting table 2 and the outer peripheral side of the upper member 52 (the upper side of the high-frequency grounding member 53). Insulating members 504, 55 formed of a resin such as VES PEL (registered trademark). Such an insulating member 504 is used to prevent the DC voltage component from leaking to the outside from the mounting table 2. Further, the insulating member 55 functions to prevent the plasma from excessively expanding in the outer peripheral direction, restricting the electric field to prevent the plasma from excessively expanding and leaking from the exhausting baffle (not shown) to the exhaust side. The graph in which the vertical axis is the voltage and the horizontal axis is the time period of Fig. 12 is a view showing a state in which the semiconductor wafer W and the focus ring 50 and the potential (voltage) of the plasma change. As shown by the curve A in the figure, the potential of the semiconductor wafer W changes in accordance with the high frequency (e.g., 2 MHz) to which the high frequency power source 7 is applied. On the other hand, since the upper member 52 of the focus ring 50 is grounded at a ground potential with respect to the high-frequency power system, its potential is constant as indicated by the straight line B. Therefore, the high frequency cycle, either on the positive side or on the negative side, can increase the potential difference between the semiconductor wafer W and the upper side member 52 as indicated by the arrows in the figure. Further, in the figure, the curve C indicates a change in the plasma potential, and the curve D indicates a change in the potential of the upper member 1 〇 of the focus ring 8 shown in Fig. 2 . As shown by the curve D, in the case of the focus ring 8 shown in Fig. 2, -28-201243942, when the high-frequency cycle becomes the positive side, the potential difference between the semiconductor wafer w and the upper member 10 becomes small. By setting the upper member 52 to the ground potential with respect to the high-frequency power as described above, it is possible to suppress the fluctuation of the potential difference accompanying the high-frequency vibration. The figure of Fig. 13(A) in which the vertical axis is the polymer thickness and the horizontal axis is the bevel position is shown as the slanting face, 30, 45 of the semiconductor wafer shown in Fig. 13(B). The result of measuring the amount of adhesion of the polymer at a position of 90 degrees. In the case of Fig. 13 (A), the case where the solid line E is the conventional focus ring 101 shown in Fig. 15 , the case where the solid line F is the focus ring 8 shown in Fig. 2, and the solid line G are used. The case of using the focus ring 50 shown in Fig. 1 is shown. As shown in the figure, in the case where the focus ring 50 is used, the electric field intensity between the semiconductor wafer and the focus ring can be increased, thereby preventing the plasma from being wound, and since the amount of radicals therebetween can be reduced, the focus is used. In the case of the ring 8, the amount of deposition of the polymer on the bevel of the wafer is more reduced. In the above-described embodiment, the case where the upper member 52 is connected to the ground potential with respect to the high-frequency power by the high-frequency grounding member 53' has been described. However, the high-frequency grounding of the structure may not be used. The member 53 is connected to the ground potential with respect to the high frequency power by another method. Fig. 14(a) schematically shows the cross-sectional configuration of the focus ring ό 0 of the other embodiment. As described above, the mounting table 2' on which the semiconductor wafer w is placed is supported by the insulating plate 3, and the high-frequency power source 7 is connected to the mounting table 2. -29- 201243942 Further, a focus ring 60 is provided on the upper peripheral portion of the mounting table 2. The focus ring 60 0 ' is an annular lower member 6 1 formed of a dielectric material (for example, a ceramic such as quartz or alumina or a resin such as VES PEL (registered trademark); and is disposed on the lower side thereof. The upper portion of the member 61 is composed of a ring-shaped upper member 62 formed of a conductive material (for example, tantalum, carbon, Si C , etc.); and is placed so as to surround the substrate to be processed, that is, the semiconductor wafer W Around. The upper member 62 is formed, for example, by a high-frequency grounding member 63 made of a conductive material such as aluminum, and is formed of a ceramic melt film (for example, A1/A1203, Y203, etc.). An insulating layer (insulating film) such as FCC (fine ceramic coating film) is coated on its surface, and is connected to a ground potential for high-frequency power. This insulating layer is formed to protect the high-frequency grounding member 63 from the influence of the plasma and to prevent the direct current from flowing. That is, the insulating layer has a sufficient thickness that the direct current cannot pass, and the direct current is blocked in the insulating layer and cannot be propagated. On the other hand, a high frequency (RF) that can propagate through a solid surface as a surface wave can propagate on the surface layer of the high-frequency grounding member 63. The high-frequency grounding member 63 serves as a grounding path for high-frequency grounding. . A dielectric (for example, a ceramic such as quartz or alumina) is formed between the high-frequency grounding member 63 and the mounting table 2 and the outer peripheral side of the upper member 62 (upper side of the high-frequency grounding member 63). Insulating members 64 and 65 formed of a resin such as VES PEL (registered trademark). Such an insulating member 64 is used to prevent the DC voltage component from leaking from the mounting table 2 to the outside -30-201243942. Further, the insulating member 65 functions to prevent the plasma from excessively expanding in the outer circumferential direction, restricting the electric field to prevent the plasma from excessively expanding and leaking from the exhaust damper (not shown) to the exhaust side. Further, in the present embodiment, a predetermined interval D is provided between the lower member 61 and the upper member 62; the predetermined interval D is set to approximately 0.5 mm. Further, the length L in the diameter direction of the portion where the lower member 6 1 and the upper member 62 face each other across the interval D is set to 5 to 10 mm. Further, the lower end of the upper member 62 is located at a position higher than the top surface of the semiconductor wafer w by 1.5 to 2.5 mm (H in the figure). The reason for such a configuration is as follows. That is, in order to reduce the aforementioned inclined surface portion of the semiconductor wafer (at 90°, 45°, and 30° of FIG. 13(B)) and the back surface of the semiconductor wafer (at 0° of FIG. 13(B)) In the plasma treatment, it is desirable to maintain the temperature of the lower member 61 at a relatively low temperature, for example, a temperature lower than 100 ° C, and more preferably at a temperature lower than 70 ° C. On the other hand, in the plasma processing, the upper member 62 is desirably kept at a relatively high temperature, for example, 250 °C or higher. The reason for this is that the temperature of the upper member 62 is set to 25° C. or more to promote the bonding of the fluorine radical and Si, and the amount of the fluorine radical can be reduced, whereby the chemical reactivity such as photoresist or SiN can be achieved. In a strong etching application, it is possible to suppress the phenomenon that the etching rate rises in the peripheral portion of the semiconductor wafer. Thus, in order to maintain the temperature of the lower member 61 and the temperature of the upper member 62 at different temperatures, a predetermined interval D is provided between the lower member 6i and the upper member 62. Further, in order to increase the temperature of the upper member 62, it is necessary to increase the flow of the lower member 61, the upper member 62, and the high-frequency grounding member 63 from the mounting table -31 - 201243942 as shown by the arrow in the figure. A high frequency (frequency is, for example, 2 MHz) is applied, and the upper member 62 is heated by Joule heat. Therefore, it is necessary to reduce the impedance of the above path. In order to satisfy such a condition, the interval D is desirably set to about 0.5 mm. That is, the interval D is set to 0.5 mm in order to satisfy this condition, based on when high frequency power of 2 MHz is applied, Heating the upper member 62 to a predetermined temperature, that is, 250 ° C or higher, requires at least 3 to 10 times the impedance with respect to the plasma impedance Zp. Therefore, since the high frequency is AC, the load effect is not only the resistance, but also the electrostatic capacity (capacitance) or the inductance (coil), and if the impedance of these factors is integrated (for the alternating current against the component), it can be as follows Explain in general. The impedance of the joint portion between the upper member 62 and the high-frequency grounding member 63 is Z1, the impedance of the interval D is Z2, and Z2 has a high resistance of at least 10 times the impedance of Z1, from the viewpoint of self-control. The consideration is ideal, so if Z2> > Zl, Z22 ΙΟχΖΙ, as shown in Figure 14 (b), in order to control Z1 + Z2 > ZP formula can be established, the impedance [ Ω ] can be based on Ζ = ε 0S / D formula to find. (ε 0 = dielectric constant of vacuum, S = area [m2], D = interval [m]) The surface area of the lower member 61 is different in the case of a 200 mm wafer and a 300 mm wafer, so The surface area of the desired lower member 61 is brought into the above formula, and the interval D» can be fundamentally determined, that is, not only a semiconductor wafer but also a plasma treatment for a larger LCD panel or the like. In the lower member of the substrate processing apparatus. -32- 201243942 Thereby, the upper member 62 and the lower member 161 can be used not only by contact but also by a surface wave generated by the high-frequency power source 7 without heat transfer, that is, a high frequency, by the principle of electrostatic induction The capacitor (interval D) is transmitted to the upper member 62. Further, when the heat insulating material is interposed between the spaces D, the dielectric constant at that place is limited according to the dielectric constant of the heat insulating material, and if the vacuum capacitor is configured as in the present embodiment, the degree of vacuum in the control chamber is controlled. Since the medium constant ε can be variably controlled, the controllability is excellent. Further, in order to reduce heat conduction and prevent heat loss, a space may be provided between the upper member 62 and the high-frequency grounding member 63. Further, as long as the lower member 61 and the upper member 62 can be controlled to the above temperatures, other methods can be employed. Further, in order to control the electric field of the peripheral portion of the semiconductor wafer to perform an approximately vertical etching as described above, as described above, the lower end of the upper member 62 is formed to be 1.5 to 2.5 higher than the top surface of the semiconductor wafer W. The position of mm (Η in the figure). According to the embodiment of the above configuration, in addition to reducing the deposition amount of the polymer on the wafer slope portion, the etching rate of the photoresist can be suppressed from rising in the peripheral portion of the semiconductor wafer, and even in the semiconductor wafer The peripheral portion can also be etched approximately vertically, and the in-plane uniformity of the treatment can be improved. (Industrial Applicability) The focus ring and the plasma processing apparatus of the present invention can be utilized in the manufacturing industry of semiconductor devices. Therefore, it has industrial applicability. -33-201243942 (Effects of the Invention) According to the present invention, even in the peripheral portion of the semiconductor wafer, the processing can be performed in a uniform and uniform manner in the same manner as the central portion of the semiconductor wafer. The 'ability' and the occurrence of deposition on the back side of the peripheral portion of the semiconductor wafer can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a schematic configuration of a plasma processing apparatus according to an embodiment of the present invention. Fig. 2 is a view showing an enlarged view of an important portion of a focus ring of the plasma processing apparatus of Fig. 1; Figure 3 is a diagram for explaining the measurement site of deposition. Fig. 4 shows the measurement results of the deposition in the measurement site of Fig. 3. Figure 5 is a graph showing the angle of the electric field at various locations on the wafer. Fig. 6 is a view for explaining a method of evaluating the amount of displacement of the incident angle of ions. Fig. 7 is a graph showing the relationship between the amount of displacement of the incident angle of ions and the height of the focus ring. Fig. 8 is a graph showing the relationship between the amount of displacement of the incident angle of ions and the height of the focus ring. Fig. 9 is a view showing the relationship between the push depth and the allowable range of the consumption of the focus ring. -34- 201243942 Figure 10 is a diagram for explaining the method of adjusting the impedance. Fig. 11 is a view showing the configuration of a focus ring according to another embodiment. Fig. 12 is a diagram showing a periodic dynamic sample of the potential of each portion. Fig. 13 is a view showing the result of measuring the amount of adhesion to the polymer of the slant surface of the wafer. Fig. 14 is a view showing the configuration of the focus ring of the other embodiment. Fig. 15 is a view showing the configuration of a conventional focus ring. Fig. 16 is a view for explaining the state of the electric field in the focus ring of Fig. 15. Fig. 17 is a view showing the state of an electric field and a plasma sheath in a focus ring using a dielectric. [Description of main component symbols] W: Semiconductor wafer 1: Vacuum chamber 2: Mounting table 8: Focus ring 9: Lower member 10: Upper member l〇a: Flat portion l〇b: Inclined portion 1 4 : Jet head -35-