201243853 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種移位暫存器電路，尤指一種用來提供 複數掃描訊號與複數發光訊號之移位暫存器電路。 【先前技術】 平面顯示裝置(FlatPanel Display)具有外型域、省電以及無 賴射等優點，所以被廣泛地應麟電腦、行動電話、個人數位 助理（PDA)、平面電視等電子產品上。在各種平醜示裝置中，主 動式矩_細^裝 t(Aetive Matrix Q_e _ Emitting D—〇LED)更具有自發光、高亮度、高發光效率、高對比 反應速度快、廣視角、以及可使用溫度範圍大等進一步之優點，因 :在平面顯示裝置的市場上極具競爭性。—般而言，主動式矩陣有 =光顯稀置包含有魏晝料元、移鱗姑電仙及資料驅 = 器伽來產生複數倾訊號至複數晝素私。移位 用來產生複數掃描訊號饋人複數晝素單元以控制複數 貝„寫人運作。此外，移位暫存器電路另用來產生複數發光 訊號’據吨供概畫麵元的發絲能” 對輸嫩進行電路概咖侧= 有技術係以互補式金氧半娜現201243853 VI. Description of the Invention: [Technical Field] The present invention relates to a shift register circuit, and more particularly to a shift register circuit for providing a plurality of scan signals and a plurality of illuminating signals. [Prior Art] Flat Panel Display (FlatPanel Display) has advantages such as external type, power saving and non-radiation, so it is widely used in electronic products such as Yinglin computer, mobile phone, personal digital assistant (PDA), and flat panel TV. In various flat and ugly devices, the active moment Q_e _ Emitting D-〇LED has more self-illumination, high brightness, high luminous efficiency, high contrast response speed, wide viewing angle, and Further advantages of using a wide temperature range are due to the fact that it is highly competitive in the market for flat panel display devices. In general, the active matrix has a = light thin set containing the Wei Wei material element, the shifting scales and the data drive = the gamma to generate the complex number of signals to the plural. The shift is used to generate a complex scan signal to feed a plurality of pixel units to control the operation of the plurality of pixels. In addition, the shift register circuit is additionally used to generate a plurality of light-emitting signals. Circuitry on the side of the tenderness = technical system with complementary galvanite
Sem—_c_f_ 料崎 訊瓣光訊號’亦即此種習知移位伽電路包含== 201243853 -N型電晶體，故需較複雜之半導體製程。 【發明内容】 依據本㈣之實_，聽露來提供複數職訊號與複 數發光訊號之移位暫存器電路。此種移位暫存器電路包含複數級移 位暫存器，每一級移位暫存器包含第一下拉單元、輸入單元、第一 控制單元、第-上拉單元、第二上拉單元、第二下拉軍元、以及第 二控制單元。第-下拉單元係絲根據驅動控制電壓與第一時脈以 下拉對應掃描訊號。電連接於第一下拉單元的輸入單元係用來根據 輸入訊號，反相於第-時脈之第二時脈以輸出驅_制電壓。電連 接於輸入單元的第-控制單元係用來根據驅動控制電壓以提供第一 控制訊^電連接於第-控制單元、輸入單元與第一下拉單元的第 -上拉單7L制來根據第—控觀軌上拉驅動㈣賴與對應掃 描訊號。電連接於第-下拉單元的第二上拉單元係用來根據對應掃 描訊號以上拉對應發轨號。接於第二上拉單元的第二下拉單 元係用來根據第二控舰齡ΧΊτ拉對紐光滅。電連接於第二下 拉單元的第二控制單元_來根據對麟描訊號與第二時脈以提供 第二控制訊號。 μ 【實施方式】 下文依本發明移位暫存器電路特舉實施例配合所附圖式作詳 細說明，但所提供之實關並義以限制本發贿涵蓋的範圍。 第1圖為本發明第-實施例之移位暫存器電路的示意圖。如第 201243853 1圖所示’移位暫存器電路100包含複數級移位暫存器，為方便說 明，移位暫存器電路100只顯示第㈣)級移位暫存器⑴、第N級 Πί ^ 112、以及第_)級移位暫存器113，其中只有第N級 ==存11 U2顯和部魏單元架構，其餘級移㈣存器係類似 ^ Ν級移位暫存器112，不另贅述。在移位暫存器電路卿的運 第Ν級移位暫存器112係用來根據第㈣)級移位暫存器山 sstr掃^瓣息·1、第㈣級移位暫存器113產生之掃描訊號 以1 μ夺脈CK1、及反相於第一時脈cki之第二時脈㈤ 推。知描訊號ssn與發光訊號EMn，其餘級移位暫存器可同理類 第N級移位暫存器112包含第—τ拉單元.輸人單元⑵、 上拉早心0、第—控鮮元135 '第二上拉單元⑽、第二下 ^早:、第二控制單元15Q、穩壓單元155、以及第三上拉單元 據斤電連接於第㈣級移位暫存器lu的輸入單元125係用來根 接SS厂與第二時脈CK2以輸出驅動控制電壓VQn。電連 25與掃料❿之第—下拉單元則_據驅 線LS = ’η與第—時脈CK1以下拉掃描訊號娜，其中掃描 制單傳輸掃描訊號娜。電連接於輸入單元125的第-控 35細來根據鶴控織壓、贿供第— :的控制單元135、輸入單 控制電壓130係用來根據第—控制訊號SC1以上拉驅動 電壓VQn與掃描訊號SSn。 電連接於第一下拉單元120與傳輪線LEn的第二上拉單元14〇 201243853 係用來根據掃描訊號SSn以上拉發光訊號EMn，其中傳輸線LEn 係用以傳輸發光訊號EMn。電連接於第一下拉單元丨2〇的第二控制 單元150係用來根據掃描訊號SSn與第二時脈CK2以提供第二控制 訊號SC2。電連接於傳輸線LEn與第二控制單元15〇的第二下拉單 元145係用來根據第二控制訊號SC2以下拉發光訊號EMn。電連接 於掃描線LSn與第(N+1)級移位暫存器113的第三上拉單元16〇係 用來根據掃描訊號SSn+Ι以上拉掃描訊號SSn。電連接於輸入單元 I25與第-下拉單元W的穩壓單元⑸係用來根據掃描訊號撕 以穩壓驅動控制電壓VQn。 在第1圖的實施例中’第一下拉單元120包含第一電晶體121， 第一上拉單元130包含第二電晶體131與第三電晶體132，第一控 制單元135包含第四電晶體136與第五電晶體137，第二上拉單元 140包含第六電晶體141，第二下拉單元145包含第七電晶體146， 第二控制單元150包含第八電晶體151與第九電晶體152，第三上 拉單元160包含第十電晶體161 ’輸入單元125包含第十一電晶體 126與第十二電晶體127 ’穩壓單元155包含第十三電晶體156。請 注意，上述或以下所述之每一電晶體可為薄膜電晶體(ThinFilmSem__c_f_ 崎崎 瓣光光信号', that is, the conventional shift gamma circuit contains == 201243853 -N type transistor, which requires a more complicated semiconductor process. SUMMARY OF THE INVENTION According to the reality of (4), the shift register circuit for providing multiple job signals and complex illumination signals is provided. The shift register circuit comprises a plurality of shift register, each shift register comprises a first pull-down unit, an input unit, a first control unit, a first pull-up unit, and a second pull-up unit. , a second pull down army element, and a second control unit. The first-pull-down unit wire pulls down the corresponding scan signal according to the driving control voltage and the first clock. The input unit electrically connected to the first pull-down unit is configured to invert the second clock of the first clock to output the drive voltage according to the input signal. a first control unit electrically connected to the input unit is configured to provide a first control signal electrically connected to the first control unit, the input unit and the first pull-down unit of the first pull-down unit according to the driving control voltage. The first-control track-up pull-up drive (4) depends on the corresponding scan signal. The second pull-up unit electrically connected to the first-pull-down unit is configured to pull the corresponding track number according to the corresponding scan signal. The second pull-down unit connected to the second pull-up unit is used to pull the illuminator according to the second control ship age ΧΊτ. The second control unit _ electrically connected to the second pull-down unit provides a second control signal according to the lining signal and the second clock. [Embodiment] Hereinafter, the specific embodiment of the shift register circuit according to the present invention will be described in detail in conjunction with the drawings, but the scope provided is intended to limit the scope of the present bribe. Figure 1 is a schematic diagram of a shift register circuit of the first embodiment of the present invention. As shown in FIG. 201243853, the 'shift register circuit 100 includes a plurality of stages of shift registers. For convenience of explanation, the shift register circuit 100 only displays the (4)th stage shift register (1), the Nth. Level ^ ί ^ 112, and _) stage shift register 113, wherein only the Nth level == save 11 U2 display and the Wei unit structure, the remaining stage shift (four) register is similar to the Ν stage shift register 112, no further details. The shift register register 112 of the shift register circuit is used to shift the register sstr according to the (4)th stage shift, and the (fourth) stage shift register 113 The generated scan signal is pushed by 1 μ pulse CK1 and inverted to the second clock (5) of the first clock cki. Knowing signal ssn and illuminating signal EMn, the remaining stage shift register can be similarly class N shift register 112 includes the first - τ pull unit. Input unit (2), pull up early heart 0, first control Fresh element 135 'second pull-up unit (10), second lower ^ early:, second control unit 15Q, voltage stabilizing unit 155, and third pull-up unit are connected to the fourth (fourth) stage shift register lu The input unit 125 is used to connect the SS factory with the second clock CK2 to output the driving control voltage VQn. The first connection-pull-down unit of the electrical connector 25 and the scanning device _ is driven by the driving line LS = 'η and the first-time clock CK1 to scan the signal signal Na, wherein the scanning system transmits the scanning signal signal Na. The first control 35 is electrically connected to the input unit 125. The control unit 135 and the input control voltage 130 are used to pull the driving voltage VQn and scan according to the first control signal SC1. Signal SSn. The second pull-up unit 14 201243853 electrically connected to the first pull-down unit 120 and the transfer line LEn is used to pull the illumination signal EMn according to the scan signal SSn, wherein the transmission line LEn is used to transmit the illumination signal EMn. The second control unit 150 electrically connected to the first pull-down unit 系2〇 is configured to provide the second control signal SC2 according to the scan signal SSn and the second clock CK2. The second pull-down unit 145 electrically connected to the transmission line LEn and the second control unit 15 is used to pull down the illumination signal EMn according to the second control signal SC2. The third pull-up unit 16 electrically connected to the scan line LSn and the (N+1)th stage shift register 113 is configured to pull the scan signal SSn according to the scan signal SSn+. The voltage stabilizing unit (5) electrically connected to the input unit I25 and the pull-down unit W is used to drive the control voltage VQn according to the scanning signal. In the embodiment of FIG. 1 , the first pull-down unit 120 includes a first transistor 121, the first pull-up unit 130 includes a second transistor 131 and a third transistor 132, and the first control unit 135 includes a fourth battery. The crystal 136 and the fifth transistor 137, the second pull-up unit 140 includes a sixth transistor 141, the second pull-down unit 145 includes a seventh transistor 146, and the second control unit 150 includes an eighth transistor 151 and a ninth transistor 152. The third pull-up unit 160 includes a tenth transistor 161. The input unit 125 includes an eleventh transistor 126 and a twelfth transistor 127. The voltage stabilizing unit 155 includes a thirteenth transistor 156. Please note that each of the transistors described above or below may be a thin film transistor (ThinFilm)
Transistor，TFT)或場效電晶體(Field Effect Tmnsistor ; FETV 第一電晶體121具有一用來接收第一時脈ckI的第一端、一 用來接收驅動控制電壓VQn的閘極端、及一用來輸出掃描訊號SSn 的第二端。第十一電晶體126具有一用來接收掃描訊號ssw的第 知、一用來接收第二時脈CK2的閘極端、及一電連接於第十二電 aa體127的第二端。第十二電晶體127具有一電連接於第十一電晶 201243853 體126之第二端的第-端…用來接收第二時脈如關極端、及 -電連接於第-電晶體121之閘極端的第二端。第十電晶體ΐ6ι且 有-電連接於第-電晶體121之第二端的第—端、_用來接收掃描 訊號SSn+Ι的閘極端、及一用來接收高參考電壓Vgh的第二端。 第二電晶體131具有一電連接於第一電晶體121之第二端的第一 端、-用來接收第-控制訊號⑽的閘極端、及—用來接收高參考 電壓漏的第：端。第三電晶體132具有—電連接於第十二電晶 體127之第二端的第一端、一用來接收第一控制訊號们的間極 端、及一用來接收高參考電壓VGH的第二端。 第四電晶體136包含第-端、第二端及閘極端，其中第一端與 閘極端用來接收低參考電壓VGL，第二制來輸出第—控制訊號、 SCI。第五電晶體137具有—電連接於第四電晶體⑶之第二端的 =一端、一用來接收驅输制電壓VQn的閘極端、及一用來接收高 考電壓VGH的第二端。第六電晶體⑷具有—用來接收高參考 堡VGH的第-端、—用來接收掃描訊號ssn的閘極端、及 錢出發光訊號缝的第二端。第七電晶體146具有一電連接於第 2晶體141之第二端的第—端、—用來接收第二控制訊號SC2的 =端、及-用來接收低參考電壓VGL的第二端。第人電晶體⑸ =一用來輸出第二控制訊號SC2的第—端、—用來接收第二時脈 的閘極端、及―用來接收低參考電壓vgl的第二端。第九電 1 152具有—電連接於第八電晶體⑸之第-端的第-端、—用 ^接收掃福訊號SSn的間極端、及一用來接收高參考電壓卿的 系一端。 201243853 第十二電晶體156包含第一端、第二端及閘極端，其中第一端 與閘極端用來接收掃描訊號SSn’第二端電連接於第十二電晶體127 之第端。第十二電晶體156可將具低電壓準位之掃描訊號SSn傳 輸至第十一電晶體127之第一端，用來降低第十二電晶體127之沒 源極壓差以抑制漏電流，進而達到驅動控制電壓VQn之穩壓效果。 在另一實施例中，第十三電晶體156與第十二電晶體127係可省略， 而第十電晶體126之第二端則直接輕接至第一電晶體121之間極 端、第五電晶體137之閘極端及第三電晶體132之第一端，並使用 具低漏電流特性之第十—電晶體126以達到驅動控制電壓vQn之穩 壓效果。 u 立第2圖為第i圖所示之移位暫存器電路的工作相關訊號波形示 思、圖’其中k軸為時間軸。在第2圖中，由上往下的訊號分別為第 一啸⑶卜第二時脈①缯描訊號撕小驅動控制電壓，、 掃描訊號SSn、發光訊號EMn、以及掃描訊號SSn+1。參閱第2圖 :、第1圖’於時丰又T1内’掃描訊號SSn-ι與第二時脈CK2均由高 準位切換為低準位，故可導通第十一電晶體126與第十二電晶體 以下拉驅動控制賴VQn至第一低電壓準位W。此時，具第一低 電鲜位VL1之驅動控制輕VQn可導通第五電晶體137以上拉 第-控制訊號sci至高參考電歷VGH，進而截止第二電晶體i3i 與第三電晶體132。 於時段T2内，第二時脈CK2由低準位切換為高準位，據以截 止第十-電曰曰體126與第十二電晶體m，從而使驅動控制電座_ 成為浮接頓，謂第-時脈CKI由高準位切換為低準位，故可藉 11 201243853 由第-電晶體121之元件電容轉合作用，將驅動控制電壓⑽從第 -低電壓準位VL1下拉至第二減壓準位VL2，並據以導通第一電 晶體m ’將掃描訊號SSn從高準位下拉至低準位。此時，具低準 位之掃描訊號SSn可導通第六電晶體141，進而將發光訊號齡從 低準位上拉至向準位。具低準位之掃描訊號sSn另可導通第九電晶 體I52以上拉第一控制訊號SC2至高參考電壓VGH，從而截止第 七電晶體146。此外，掃描訊號SS讀時段Τ2 β之低電壓準位可導 通第十三電晶體156，進而將第忙f晶體127之第_端的電壓下 拉至低電壓準位，用來降低第十二電晶體127之縣極壓差以減少 漏電流’如此即可達到,鶴控制龍VQn之穩壓效果。 於時段T3内，具低準位之掃描訊號撕+1可導通第十電晶體 I6卜據以將掃描訊號SSn上拉至高參考電壓VGH，進而截止第六 電晶體141與第九電晶體152。此時，因第二時脈㈤纟高準位: 換為低準位’故可導通第八電晶體⑸町拉第二控制訊號奶至 低參考賴VGL，具低參考輕VGL之第二控制峨奶即 導通第七電晶體⑷叮拉發光訊號EMn至低參考 。 請注意，如第1圖所示，第N級移位暫存器112的所 均為p型電晶體，亦即第N級移位暫存器丨12係基於只包含-晶體的電路以提供互為反相的掃描訊號SSn與發轨號EMn里電 理’其餘級移位暫存器亦可基於只包含p型電晶體的電路同 為反相卿描訊號婦光城，因此可㈣簡化半導料程以供互 生產成本。此外，所屬技_域中具有通常知識者可根降低 位暫存器112所揭露的雜而姆地完成只包含 級移 土电日日體的對等 12 201243853 器電 移位暫存料路’所以基於只包含N型電晶_對等移位暫存 路亦不脫離本發明之精神和範圍。 第3圖為本發明第二實施例之移位暫存器電路的示意圖。如第 3圖所示’移位暫存器電路勘包含複數級移位暫存器，為方便說 月移位暫存器電路2〇〇只顯不第㈣)級移位暫存器叫、第n級 移位暫存II 212、以及第_)級移位暫存器213，其中只有第n級 移=暫存H 212顯補部功能單元架構，其餘級移位暫存器係類似 於第N級移位暫存器212，不另贅述。在移位暫存器電路勘的運 作中’第N級移位暫存器212係用來根據第_級移位暫存器如 產生之啟始脈波訊號STn_卜第_)級移位暫存器213產生之掃描 訊號SSn+卜第—時脈㈤、及反相於第-時脈αα之第二時脈 CK2以產生掃描訊號SSn、發光訊號ΕΜη及啟始脈波訊號阳，其 餘級移位暫存器可同理類推。 α第N、,及移位暫存II 212係類似於第丨圖所示之第^級移位暫 存器^，主要差異在於將輸人單元125 為輸人單元225，將第 —上拉早凡16G置換為第三上拉單元，並另包含進位單元挪。 電連接於第_級移位暫存㈣的輸人單元225侧來根據啟始 脈波訊號STn-1與第二時脈CK2以輸出驅動控制電壓,。電連 ^雜入單元225的進位單元27〇係用來根據驅動控制輕VQn 〃、第夺脈cki以輸出啟始脈波訊號sTn。電連接於第一下拉單元 ⑽進位單疋別與第讲+1)級移位暫存器2丨3的第三上拉單元· 係用來根據掃描訊號SSn+1以上拉掃描訊號娜及啟始脈波訊號 13 201243853 在第3圖的實施例中，輸入單元225包含第十一電晶體226與 第十二電晶體227,進位單元包含第十四電晶體271，第三上拉單元 260包含第十電晶體261與第十五電晶體262。第十一電晶體226 具有一用來接收啟始脈波訊號STnd的第一端、一用來接收第二時 脈CK2的閘極端、及一電連接於第十二電晶體227的第二端。第十 二電晶體227具有一電連接於第十一電晶體226之第二端的第一 端、一用來接收第二時脈CK2的閘極端、及一電連接於第一電晶體 121之閘極端的第二端。第十四電晶體271具有一用來接收第一時 脈cki的第一端、一用來接收驅動控制電壓VQn的閘極端、及一 用來輸出啟始脈波訊號STn的第二端。第十電晶體261具有一電連 接於第-電晶體121之第二端的第—端、—用來接收掃描訊號沾州 的閘極端、及-用來接收高參考電壓VGH的第二端。第十五電晶 體262具有-電連接於第十四電晶體271之第二端的第一端、一電 連接於第十電晶體261之閘極端的閘極端、及一用來接收高參考電 壓VGH的第二端。在另一實施例中，第十電晶體261之閘極端係 電連接於第_)級移位暫存器213以接收啟始脈波訊號st㈣。 由於啟始脈波訊號STn·卜啟始脈波訊號STn及啟始脈波訊號 S=1之波形實質上分湖於掃描訊號心丨、掃描訊號哪及掃 插訊號SSn+1之波形，故第N級移位暫存器212之電路工作原理可 據上述第N級移位暫存器112之電路工作原理而同理類推。此 外，如第3圖所示’第N級移位暫存器212的所有電晶體均為p型 電晶體’也就是說’第N級移位暫存器212亦基於只包含p型電晶 體的電路啸供互献相崎麻號SSn與發光峨驗，並另^Transistor (TFT) or field effect transistor (Field Effect Tmnsistor; FETV first transistor 121 has a first terminal for receiving the first clock cKI, a gate terminal for receiving the driving control voltage VQn, and a use The second end of the scan signal SSn is output. The eleventh transistor 126 has a first known signal for receiving the scan signal ssw, a gate terminal for receiving the second clock CK2, and an electrical connection to the twelfth electrode. The second end of the aa body 127. The twelfth transistor 127 has a first end electrically connected to the second end of the eleventh electromorphic 201243853 body 126... for receiving the second clock, such as the extremes, and - the electrical connection The second end of the gate terminal of the first transistor 121. The tenth transistor is electrically connected to the first end of the second end of the first transistor 121, and the gate terminal for receiving the scan signal SSn+Ι And a second terminal for receiving the high reference voltage Vgh. The second transistor 131 has a first end electrically connected to the second end of the first transistor 121, and a gate terminal for receiving the first control signal (10) And - the first end used to receive the high reference voltage drain. The third transistor 132 has - electricity a first end connected to the second end of the twelfth transistor 127, an intermediate terminal for receiving the first control signal, and a second end for receiving the high reference voltage VGH. The fourth transistor 136 includes a terminal, a second terminal and a gate terminal, wherein the first terminal and the gate terminal are used to receive the low reference voltage VGL, and the second terminal is used to output the first control signal, SCI. The fifth transistor 137 has an electrical connection to the fourth battery. a = end of the second end of the crystal (3), a gate terminal for receiving the drive voltage VQn, and a second terminal for receiving the DC voltage VGH. The sixth transistor (4) has - for receiving the high reference Fort VGH a first end, a gate terminal for receiving the scanning signal ssn, and a second end for the light emitting signal slit. The seventh transistor 146 has a first end electrically connected to the second end of the second crystal 141, Receiving the = terminal of the second control signal SC2, and - the second terminal for receiving the low reference voltage VGL. The first transistor (5) = one for outputting the first end of the second control signal SC2, - for receiving the first The gate terminal of the second clock and the second terminal for receiving the low reference voltage vgl. The ninth electric 1 152 has an electric terminal connected to the first end of the first end of the eighth transistor (5), an intermediate terminal for receiving the buffing signal SSn, and a terminal for receiving the high reference voltage. 201243853 The twelve transistor 156 includes a first end, a second end, and a gate terminal, wherein the first end and the gate terminal are configured to receive the second end of the scan signal SSn' electrically connected to the first end of the twelfth transistor 127. The transistor 156 can transmit the scan signal SSn having a low voltage level to the first end of the eleventh transistor 127 to reduce the source-to-source voltage difference of the twelfth transistor 127 to suppress leakage current, thereby driving Control voltage VQn voltage regulation effect. In another embodiment, the thirteenth transistor 156 and the twelfth transistor 127 may be omitted, and the second end of the tenth transistor 126 is directly connected to the first transistor 121 between the extreme and the fifth. The gate terminal of the transistor 137 and the first end of the third transistor 132, and the tenth transistor 126 of the low leakage current characteristic are used to achieve the voltage regulation effect of the driving control voltage vQn. u Figure 2 shows the operation-related signal waveform of the shift register circuit shown in Figure i, where the k-axis is the time axis. In Fig. 2, the signals from top to bottom are the first whistle (3), the second clock 1 scan signal, the small drive control voltage, the scan signal SSn, the illuminating signal EMn, and the scan signal SSn+1. Refer to Figure 2: Figure 1 'Yu Shifeng and T1' scan signal SSn-ι and second clock CK2 are switched from high level to low level, so the eleventh transistor 126 and the first can be turned on. The twelve transistor pull drive controls the VQn to the first low voltage level W. At this time, the driving control light VQn having the first low electric fresh bit VL1 can turn on the fifth transistor 137 to pull the first control signal sci to the high reference electric power VGH, thereby turning off the second transistor i3i and the third transistor 132. During the period T2, the second clock CK2 is switched from the low level to the high level, thereby terminating the tenth-electrode body 126 and the twelfth transistor m, thereby causing the drive control pedestal _ to become floating , that the first-clock CKI is switched from the high level to the low level, so the component capacitor of the first transistor 121 can be transferred by 11 201243853, and the driving control voltage (10) is pulled down from the first low voltage level VL1. The second decompression level VL2, and according to the first transistor m' is turned on, the scan signal SSn is pulled from the high level to the low level. At this time, the scan signal SSn having a low level can turn on the sixth transistor 141, thereby pulling the illuminating signal age from the low level to the up level. The scan signal sSn having a low level can further turn on the ninth transistor I52 to pull the first control signal SC2 to the high reference voltage VGH, thereby turning off the seventh transistor 146. In addition, the low voltage level of the scan signal SS read period Τ2 β can turn on the thirteenth transistor 156, thereby pulling down the voltage at the _th terminal of the busy f crystal 127 to a low voltage level, thereby reducing the twelfth transistor. 127 county extreme pressure difference to reduce leakage current 'this can be achieved, crane control dragon VQn voltage regulation effect. During the period T3, the scan signal torn +1 with a low level can turn on the tenth transistor I6 to pull up the scan signal SSn to the high reference voltage VGH, thereby turning off the sixth transistor 141 and the ninth transistor 152. At this time, because the second clock (five) 纟 high level: changed to low level ', it can turn on the eighth transistor (5) to pull the second control signal milk to the low reference VL, the second control with low reference light VGL The milk is turned on to the seventh transistor (4) to pull the illuminating signal EMn to the low reference. Please note that as shown in FIG. 1, all of the p-type transistors of the Nth stage shift register 112, that is, the Nth stage shift register 丨12 are based on a circuit including only - crystals. The mutually inverting scan signal SSn and the track number EMn are the same. The remaining stage shift register can also be based on the circuit containing only the p-type transistor, which is the reverse phase of the signal, so it can be simplified. Semi-conductive material for mutual production costs. In addition, the general knowledge in the domain of the technology domain can reduce the uncovering of the bit-transfer device 112 to complete the peer-to-peer 12 201243853 electric shift temporary storage path. Therefore, the present invention does not depart from the spirit and scope of the present invention based on the inclusion of only the N-type electro-crystals. Figure 3 is a schematic diagram of a shift register circuit in accordance with a second embodiment of the present invention. As shown in Figure 3, the 'shift register circuit includes a multi-level shift register. To facilitate the monthly shift register circuit 2, only the fourth (fourth) level shift register is called. The nth stage shift register II 212 and the _) stage shift register 213, wherein only the nth stage shift = the temporary H 212 display part functional unit architecture, and the remaining stage shift register is similar to The Nth stage shift register 212 will not be described again. In the operation of the shift register circuit, the 'Nth stage shift register 212 is used to shift the start pulse signal STn_b according to the _ stage shift register. The scan signal SSn+Bu-clock (5) generated by the register 213 and the second clock CK2 inverted from the first-clock αα generate the scan signal SSn, the illuminating signal ΕΜη and the start pulse signal yang, and the remaining stages The shift register can be analogized by analogy. αN,, and shift temporary storage II 212 is similar to the first stage shift register ^ shown in the figure, the main difference is that the input unit 125 is the input unit 225, and the first pull-up The early 16G is replaced by the third pull-up unit, and the carry unit is additionally included. The input unit 225 side electrically connected to the first stage shift register (4) outputs the control voltage according to the start pulse signal STn-1 and the second clock CK2. The carry unit 27 of the electrical connection unit 225 is configured to output the start pulse signal sTn according to the drive control light VQn 〃 and the first pulse cki. The third pull-up unit electrically connected to the first pull-down unit (10) and the third pull-up unit of the +1)-stage shift register 2丨3 is used to pull the scan signal according to the scan signal SSn+1 Initiating pulse wave signal 13 201243853 In the embodiment of FIG. 3, the input unit 225 includes an eleventh transistor 226 and a twelfth transistor 227, the carry unit includes a fourteenth transistor 271, and the third pull-up unit 260 A tenth transistor 261 and a fifteenth transistor 262 are included. The eleventh transistor 226 has a first end for receiving the start pulse signal STnd, a gate terminal for receiving the second clock CK2, and a second end electrically connected to the twelfth transistor 227. . The twelfth transistor 227 has a first end electrically connected to the second end of the eleventh transistor 226, a gate terminal for receiving the second clock CK2, and a gate electrically connected to the first transistor 121. Extreme second end. The fourteenth transistor 271 has a first end for receiving the first clock cki, a gate terminal for receiving the drive control voltage VQn, and a second terminal for outputting the start pulse signal STn. The tenth transistor 261 has a first end electrically connected to the second end of the first transistor 121, a gate terminal for receiving the scanning signal, and a second terminal for receiving the high reference voltage VGH. The fifteenth transistor 262 has a first end electrically connected to the second end of the fourteenth transistor 271, a gate terminal electrically connected to the gate terminal of the tenth transistor 261, and a terminal for receiving the high reference voltage VGH. The second end. In another embodiment, the gate terminal of the tenth transistor 261 is electrically coupled to the stage _) shift register 213 to receive the start pulse signal st (d). Since the waveforms of the start pulse signal STn·Bu start pulse signal STn and the start pulse signal S=1 are substantially divided into the waveforms of the scanning signal heart, the scanning signal and the sweep signal SSn+1, The circuit operation principle of the Nth stage shift register 212 can be analogized according to the circuit working principle of the Nth stage shift register 112. In addition, as shown in FIG. 3, all of the transistors of the Nth stage shift register 212 are p-type transistors, that is, the 'Nth stage shift register 212 is also based on containing only p-type transistors. The circuit whistle and mutual contribution to the Sakisaki SSn and the illuminating test, and another ^
14 201243853 供用j動第㈣級移位暫存器213的啟始脈波訊號sTn，所以仍 可顯著簡化半導體軸崎低生產成本。 第4圖為本發明第三實施例之移位暫存器電路的示意圖。如第 4圖所示，移位暫存器電路·包含複數級移位暫存器，為方便說 明，移位暫存器電路3〇〇只顯示第附)級移位暫存器州、第N級 移位暫存器312、以及第_)級移位暫存器313，其中只有第難 移位暫存ϋ 3i2顯和部功能單元架構，其餘級移位暫存器係類似 於第N級移位暫存$ 312，不另贅述。在移位暫存器電路的運 作中’第Ν級移位暫存器3!2係用來根據第㈣級移位暫存器祀 產生之啟鎌波峨STn]、_+1)級移位暫存^ 313產生之掃描 訊號SSn+卜第-_CK卜及反相於第—時脈㈤之第二時脈 CK2以產生掃描訊號SSn、發光訊號EMn及啟始脈波訊號㈣，其 餘級移位暫存器可同理類推。 。第N級移位暫存器312係類似於第3圖所示之第N級移位暫 存器212 ’主要差異在於將第一上拉單元13〇置換為第一上拉單元 330並將第—上拉單元260 f換為第三上拉單元挪。電連接於第 -控制單元135、輸入單元2M、第-下拉單元12G與進位單元27〇 的第-上拉單元330係用來根據第一控制訊號sci卩上拉驅動控制 電壓VQn、掃描訊號SSn及啟始脈波訊號STi^電連接於輸入單元 225、第一下拉單元12〇、進位單元27〇與第⑽+丨)級移位暫存器μ) 的第一上拉單元360係用來根據掃描訊號s§n+i以上拉驅動控制電 壓VQn、掃描訊號SSn及啟始脈波訊號STn。 在第4圖的實施例中，第一上拉單元33〇包含第二電晶體”卜 201243853 第三電晶體332與第十六電晶體333，第三上拉單元36〇包 電晶體36卜第十五電晶體362與第十七電晶體如。第二電 331具有-電連接於第一電晶體121之第二端的第一端、一用I 收第一控制訊號sa的閘極端、及一用來接收高參考龍= 第一端。第三電晶體332具有-電連接於第十二電晶體227之第: 端的第-端、-用來接收第-控制訊號SC1的間極端、及一: 收高參考電Μ權的第二端。第十六電晶體333具有一電連接於接 第十四電晶體271之第二端的第一端、一用來接收第一控制訊號 sci的閘極端、及—用來接收高參考鶴vgh的第二端。， 第十電晶體361具有-電連接於第一電晶體121之第二端的第 一端、一用來接收掃描訊號SSn+1的閘極端、及一用來接收高 電壓VGH的第二端。第十五電晶體362具有一電連接於第十四電 晶體⑺之第二端的第—端、—電連接於第十電晶體361之問極端 的閘極端、及-用來接收高參考電壓VGH的第二端。第十七電晶 體363具有-電連接於第十二電晶體如之第二端的第一端、一電 連接於第十電晶體361之閘極端的閘極端、及一用來接收高參考電 壓VGH的第二端。在另一實施例中，第十電晶體36ι之問極端係 電連接於第(N+1)級移位暫存器313以接收啟始脈波訊號st㈣。 基本上，第N級移位暫存器312之電路工作原理係類似於上述 第N、’及移位暫存器212之電路工作原理。此外，如第4圖所示，第 N級^位暫存器312的所有電晶體均為p型電晶體，故第n級移位 暫存益3U亦基於只包含p型電晶體的電路以提供互為反相的掃描 Λ號SSn與發光峨EMn，並另提供用來驅動第_)級移位暫存 201243853 器313的啟始脈波訊號STn，所以仍可顯著簡化半導體製程 生產成本。 、降低 綜上所示，本發明移位暫存器可基於只包含p型電晶體或N型 電晶體的電_提供互為反相崎描峨與發光訊號至晝素單元， 使晝素單7〇可據以執行發光控概倾電晶體臨界賴 故可顯著簡化半導體製程以降低生產成本。 雖然本發明已以實關揭露如上，然其麟狀限定本發明， 任何具有核明所馳術躺之通私财，在不雜本發明之精 神和範_ ’當可作各種更動麵飾，因此本發明之保護範圍當視 後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖為本發明第—實施例之移位暫存器電路的示意圖。 第2圖為第丨圖所示之移位暫存器電路缸作相關訊號波形示意 圖’其中橫軸為時間軸。 第3圖為本發明第二實施例之移位暫存器電路的示意圖。 第4圖為本發明第三實施例之移位暫存器電路的示意圖。 【主要元件符號說明】 100、200、300 移位暫存器電路 111 211、311 第(N-1)級移位暫存器 112 > 212 ' 312 第N級移位暫存器 17 201243853 113 、 213 、 313 第(N+1)級移位暫存器 120 第一下拉單元 121 第一電晶體 125 ' 225 輸入單元 126 ' 226 第十一電晶體 127 、 227 第十二電晶體 130、330 第一上拉單元 131 、 331 第二電晶體 132 、 332 第三電晶體 135 第一控制單元 136 第四電晶體 137 第五電晶體 140 第二上拉單元 141 第六電晶體 145 第二下拉單元 146 第七電晶體 150 第二控制單元 151 第八電晶體 152 第九電晶體 155 穩壓單元 156 第十三電晶體 160、260、360 第三上拉單元 18 201243853 161 ' 261 ' 361 262 、 362 270 271 333 363 CK1 CK2 EMn-1、EMn、 EMn+1 LEn-1 ' LEn ' LEn+1 LSn-卜 LSn、LSn+1 SCI SC2 SSn-2、SSn-1、SSn、 SSn+1 、 SSn+2 STn-2、STn-卜 STn、 STn+1 T 卜 T2、T314 201243853 The starting pulse signal sTn of the (fourth) stage shift register 213 is used, so that the semiconductor axis low production cost can be significantly simplified. Figure 4 is a schematic diagram of a shift register circuit of a third embodiment of the present invention. As shown in FIG. 4, the shift register circuit includes a plurality of shift register registers. For convenience of explanation, the shift register circuit 3 only displays the state-level shift register state, the first The N-stage shift register 312 and the _)-stage shift register 313, wherein only the first difficult shift temporary storage ϋ 3i2 display and the functional unit structure, the remaining shift register is similar to the Nth The level shift is temporarily stored at $312, and will not be described again. In the operation of the shift register circuit, the 'level shift register 3! 2 is used to shift the start wave 峨 STn], _+1) according to the (fourth) stage shift register 祀The scan signal SSn+b-_CKb generated by the temporary storage ^313 is inverted and the second clock CK2 of the first-clock (5) is inverted to generate the scan signal SSn, the illumination signal EMn and the start pulse signal (4), and the remaining stages are shifted. The bit register can be analogized by analogy. . The Nth stage shift register 312 is similar to the Nth stage shift register 212 shown in FIG. 3. The main difference is that the first pull up unit 13 is replaced by the first pull up unit 330 and the first - The pull-up unit 260f is replaced by a third pull-up unit. The first-up pull-up unit 330 electrically connected to the first control unit 135, the input unit 2M, the pull-down unit 12G and the carry unit 27A is configured to pull up the driving control voltage VQn and the scan signal SSn according to the first control signal sci卩And the first pulse-up signal STi^ is electrically connected to the input unit 225, the first pull-down unit 12A, the carry unit 27A, and the (10)+丨 stage shift register μ). The driving control voltage VQn, the scanning signal SSn and the starting pulse signal STn are pulled according to the scanning signal s§n+i. In the embodiment of FIG. 4, the first pull-up unit 33A includes a second transistor "201243853 third transistor 332 and a sixteenth transistor 333, and the third pull-up unit 36 includes a transistor 36" The fifteenth transistor 362 and the seventeenth transistor, the second electric 331 has a first end electrically connected to the second end of the first transistor 121, a gate terminal for receiving the first control signal sa by I, and a The third transistor 332 has a first end connected to the first end of the twelfth transistor 227, an intermediate terminal for receiving the first control signal SC1, and a first terminal. The second end of the reference power is raised. The sixteenth transistor 333 has a first end electrically connected to the second end of the fourteenth transistor 271, and a gate terminal for receiving the first control signal sci And a second terminal for receiving the high reference crane vgh. The tenth transistor 361 has a first end electrically connected to the second end of the first transistor 121, and a gate for receiving the scan signal SSn+1. Extremely, and a second end for receiving a high voltage VGH. The fifteenth transistor 362 has an electrical connection to the fourteenth transistor (7) a first end of the second end, a gate terminal electrically connected to the terminal of the tenth transistor 361, and a second terminal for receiving the high reference voltage VGH. The seventeenth transistor 363 has an electrical connection to the first The twelve transistor has a first end of the second end, a gate terminal electrically connected to the gate terminal of the tenth transistor 361, and a second terminal for receiving the high reference voltage VGH. In another embodiment, The tenth transistor 36i is electrically connected to the (N+1)th stage shift register 313 to receive the start pulse signal st(4). Basically, the circuit operation of the Nth stage shift register 312 It is similar to the circuit operation principle of the Nth, 'and shift register 212 described above. In addition, as shown in FIG. 4, all the transistors of the Nth stage register 312 are p-type transistors, so The n-th shift temporary storage benefit 3U is also based on a circuit including only a p-type transistor to provide mutually inverted scanning apostrophes SSn and illuminating 峨EMn, and is additionally provided for driving the _)th shift temporary storage 201243853 The start pulse signal STn of the device 313 can still significantly simplify the production cost of the semiconductor process. The shift register can be based on a power supply that only contains a p-type transistor or an N-type transistor, and provides an anti-phase-striping and illuminating signal to the pixel unit, so that the pixel can be used to perform illumination control. The critical value of the tilting crystal can significantly simplify the semiconductor process to reduce the production cost. Although the present invention has been disclosed above in a practical manner, the invention is limited to the invention, and any of the nuclear technologies that have the nuclear power is not miscellaneous. The spirit and scope of the present invention can be used as a variety of modifiers, and the scope of the present invention is defined by the scope of the appended claims. [FIG. 1] The first embodiment of the present invention is the first embodiment of the present invention. A schematic diagram of a shift register circuit. Figure 2 is a schematic diagram of the relevant signal waveform of the shift register circuit cylinder shown in Figure 其中, where the horizontal axis is the time axis. Figure 3 is a schematic diagram of a shift register circuit in accordance with a second embodiment of the present invention. Figure 4 is a schematic diagram of a shift register circuit of a third embodiment of the present invention. [Major component symbol description] 100, 200, 300 shift register circuit 111 211, 311 (N-1)-stage shift register 112 > 212 ' 312 N-th shift register 17 201243853 113 213, 313 (N+1)th stage shift register 120 first pull-down unit 121 first transistor 125' 225 input unit 126' 226 eleventh transistor 127, 227 twelfth transistor 130, 330 first pull-up unit 131, 331 second transistor 132, 332 third transistor 135 first control unit 136 fourth transistor 137 fifth transistor 140 second pull-up unit 141 sixth transistor 145 second pull-down Unit 146 seventh transistor 150 second control unit 151 eighth transistor 152 ninth transistor 155 voltage stabilization unit 156 thirteenth transistor 160, 260, 360 third pull-up unit 18 201243853 161 ' 261 ' 361 262 , 362 270 271 333 363 CK1 CK2 EMn-1, EMn, EMn+1 LEn-1 ' LEn ' LEn+1 LSn-b LSn, LSn+1 SCI SC2 SSn-2, SSn-1, SSn, SSn+1, SSn +2 STn-2, STn-b STn, STn+1 T Bu T2, T3
VGHVGH
VGL VL1 VL2 第十電晶體 第十五電晶體 進位單元 第十四電晶體 第十六電晶體 第十七電晶體 第一時脈 第二時脈 發光訊號 傳輸線 掃描線 第一控制訊號 第二控制訊號 掃描訊號 啟始脈波訊號 時段 向參考電壓 低參考電壓 第一低電壓準位 第二低電壓準位 19 201243853 驅動控制電壓 VQn 20VGL VL1 VL2 Tenth transistor Fifteenth transistor carry unit Fourteenth transistor Sixteenth transistor Seventeenth transistor First clock Second clock Illumination signal Transmission line Scanning line First control signal Second control signal Scan signal start pulse wave signal period to reference voltage low reference voltage first low voltage level second low voltage level 19 201243853 drive control voltage VQn 20