TW201242003A - Method for producing semiconductor device and semiconductor device - Google Patents

Abstract

A method for producing semiconductor device of this invention includes a step of forming a conductive layer (7) and a first semiconductor layer (5a) containing a donor impurity or an acceptor impurity on a first semiconductor substrate, a step of reducing a second insulating layer (8) so as to cover the first semiconductor layer (5a), a step of reducing the thickness of the first semiconductor substrate (9) to a predetermined thickness, a step of forming a pillar-shaped semiconductor (1a) having a pillar-shaped structure on the first semiconductor layer (5a) from the first semiconductor substrate, a step of forming a first semiconductor area (6a) in the pillar-shaped semiconductor (1a) by diffusing an impurity from the first semiconductor layer (5a), and a step of forming pixels of a solid imaging device by using the pillar-shaped semiconductor (1a) in which the impurity has been diffused.

Description

201242003 VI. [Technical Field] The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, and more particularly to a transistor having a channel region formed in a semiconductor having a columnar structure ( Transi s tor) semiconductor device mounting method and semiconductor device. [Prior Art] A solid-state image sensing device such as a CCD or a CMOS type is widely used for a video camera, a stereo camera, and the like. Brigade's requirements for high-resolution, high-speed operation, and high sensitivity of solid-state image sensing devices are required. As shown in Fig. 17, a solid-state image sensing device in which a halogen is formed in one columnar semiconductor 110 is known (for example, refer to the patent document). In this halogen structure, a silicium layer 51 which functions as a signal line of a solid-state image sensing device is formed on a semiconductor substrate. Further, a column is connected to the N+ type germanium layer 51. The semiconductor is 11 〇. The germanium-shaped semiconductor 110 is formed with a M?s transistor formed of a p-type germanium layer 52, insulating films 53a and 53b, and gate conductor layers 54a and 54b for removing stored charges. Further, a photodiode which is connected to the M?s transistor and stores a charge generated by irradiation of a light beam (electromagnetic energy wave) is formed on the columnar semiconductor 11 system. This photodiode system is composed of a p-type germanium layer 52 and an N-type litmus layer 58a, 58b. Furthermore, a P-type semiconductor 52 surrounded by the photo-electric body is turned on, a photo-electric body is set as a gate, and a photodiode 323818 4 201242003 is formed. The P+ type 石 layer 56 connected to the halogen selection lines 57a and 57b and the p type 矽 layer 52 near the N+ type 矽 layer 51 are respectively set as the source electric field effect of the source & (10) π illusion and drain. Transistor (junction transistor).

The basic operation of the solid-state image sensing device is: storing the signal charge generated by the beam irradiation (in this case, electrons) in the signal charge storage operation of the photodiode; flowing near the N+ type Shixi layer 51 The source/no-pole current between the p-type shixi^52 and the p+-type shihua layer 56 is modulated by the polarity of the photodiode corresponding to the stored photodiode voltage of the signal charge, and The signal readout operation is performed as the signal current reading; and the readout operation is green, and the conduction (10)) is applied to the gate conductor layers 54a and 54b of the MOS transistor, and is stored in the photodiode. The signal signal of the body is removed from the reset action of the N+_ layer 51. In the two-dimensional solid-state image sensing device, Fig. 17 is arranged in a smooth shape. Further, the #4 system is transmitted to the electrical transmission provided in the sensing circuit via the _ layer 51, and the button operation is performed. Further, the number of primes of the sensing device or the reading per unit time requires high-speed operation of the signal reading operation. Therefore, S plus is the resistance of the N+ type germanium layer 51 belonging to the signal line. In order to achieve such a low-resistance diagram of the N+-type sapphire layer 51, it is conceivable to make the structure of the back surface of the _shi shi layer (four) formed on the 夕夕 substrate 6〇, the signal line ^ ^ is determined by the metal layer 59, so that the above-mentioned signal reading can be realized by the 323818 speed action 201242003. However, it is difficult to form a joint with the metal of the r-type...

In order to form the metal layer 59 on the substrate (10), it is possible to form a metal layer (10) on the semiconductor substrate and form a metal layer (10) on the oxide substrate (4) as shown in the figure. The semiconductor substrate 61 is connected to the semiconductor substrate: 'the pixel is formed in a portion indicated by a broken line in the (10) figure in the semiconductor substrate 64. The one-point key line (4) shown in the (10) figure shows the polishing of the conductor substrate 64, _, or other separation method, the semiconductor substrate 64 is formed into a state of a predetermined height. ... And in the case of such a manufacturing method, the metal layer 59 is directly connected to the semiconductor layer, so the metal layer 59 and the semiconductor The two expansion coefficients of the substrate 64 are different, and the semiconductor substrates 61 and 64 are bent, cracked, or peeled off. As shown in the first drawing, in order to operate the south speed of the signal reading operation, development does not occur. The method of directly bonding the metal layer 59 to the back surface of the Ν+-type slab layer 51 by bending, cracking, or peeling is of a technical significance. * And, there is a strong demand for solving such a problem. To achieve The semiconductor device other than state image sensing apparatus, or provided in a semiconductor circuit device of high integration member 7G product of higher performance.

Further, in order to realize high-speed operation of the signal reading operation, there is a SGT belonging to a vertical MOS transistor having a side surface of a columnar semiconductor having a k-shaped structure as a channel region and having a gate electrode surrounding the channel region. (Surrounding Gate Transistor, wraparound gate transistor) (Simplified as "SGT" in 323818 201242003) (for example, in the case of SGT, such as SGT, it is shown in Figure 19, and the document 2 is shown. ). A planar ruthenium film 67 is formed on the substrate 66, and a columnar structure is formed by embedding the yttrium oxide columnar layer 68. In the planar surface-like smectic film 67 and the P+-type sap diffusion layer 6 which functions as a immersive function, a ρ+_diffusion layer 形成 which functions as a material secret is formed in the upper part of the columnar layer. A gate insulating layer 7 is formed on the outer peripheral portion of the columnar layer 68, and a gate electrode 72 is formed on the outer peripheral portion of the inter-electrode insulating layer 71. Thereby, a P-type channel SGT in which a columnar shape (4) (10) between the P + -type schist material diffusion layer 69 and the F-clear diffusion layer 7 作 is used as a channel is formed. Further, a nitrided (^ν) film 73 and an oxidized stone (Si〇2) are formed around the gate electrode 72, the P+ type germanium diffusion layer 7〇, and the P-wave diffusion layer 69. Membrane 74. A contact hole 75 is formed in the ruthenium oxide film 74, and the P-type shi-diffusion layer 70 is connected to the source metal wiring 76 via the contact hole 75. Thereby a p-type channel sgt is formed. The P+ pear-dip diffusion layer 69 shown in Fig. 19 is connected to a metal wiring (not shown) at a predetermined portion in which the planar ruthenium film 67 is extended on the same plane. In the semiconductor device having the SGT, 'the high-speed operation for realizing further signal reading operation' is required to connect the P+ type germanium diffusion layer 69 to the metal wiring in the manner of the P+ type germanium diffusion layer 70. Performed at short distances. However, in the case of the SGT shown in Fig. 19, between the metal wiring and the P+ type germanium diffusion layer 69 or the P+ type germanium diffusion layer 69, there is a limit corresponding to the SGT channel. Distance resistance. In the semiconductor device having the SGT, in the same manner as the solid-state image sensing device, in order to realize high-speed operation of the signal reading operation, the metal layer must be directly bonded to the P+ type germanium diffusion layer 69. The back side seeks to reduce the resistance. (Prior Art Document) (Patent Document) Patent Document 1: International Publication No. 2009/034623 Patent Document 2: US Patent Application Publication No. 2010/0213539 (A1) No. (Non-Patent Document)

Non-Patent Document 1: Hidekazu Takahashi, Masakuni Kinosita, Kazumichi Morita, Takahiro Shirai, Tosiaki Sato, Takayuki Kimura, Hiroshi Yuzurihara, Shunsuke Inoue, Member, IEEE, and Shigeyuki Matsumoto: MA 3. 9-//m Pixel Pitch VGA Format 10 -b Digital Output CMOS Image Sensor With 1. 5 Transistor/Pixel", IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, pp. 2417-2425 (December 2004) Non-Patent Document 2: M. Bruel: "Silicon on Insulator material tecnology", Electronics Letters Vol. 31, No. 14, pp. 1201-1202 (6th July, 1995) Non-Patent Document 3: Takao Yonehara, Kiyofumi Sakaguchi, and Nobuhiko Sato : "Epitaxial layer transfer by bond And etch back of porous Si”, Appl· Phys. Lett. Vol. 64, 323818 8 201242003

No. 16, pp. 2108-2110 (18 April, 1994) [Problem to be Solved by the Invention] In a two-dimensional solid-state image sensing device, as described above, by a halogen signal (signal current) The N+ type germanium layer 51 functioning as a signal line is transmitted to an external circuit provided around the photosensitive area to perform a signal reading operation. Furthermore, the resetting operation is also performed by electrical transfer of pixels and external circuits of the photosensitive area. The responsiveness of this electrical transmission is greatly affected by the resistance and parasitic capacitance of the wiring between the connected pixels and the peripheral circuits. In order to increase the number of primes of the solid image sensing device, or the number of readouts per unit time, it is required to reduce the resistance of the wiring. (w), nickel (Ni), etc. are used for a smaller resistance value. Therefore, in the solid-state image sensing device shown in Fig. 17 and in the solid-state image sensing device shown in Fig. 17, the resistance is almost determined by the resistance of the N+ type germanium layer 51. The N+ type germanium layer 51 is formed by ion doping (ion implantation) of a donor impurity such as phosphorus (?) or arsenic (As) to a germanium (si) semiconductor, so that it cannot be made. The resistance value of the N+ type bismuth layer 51 is higher than that of the metal of the general semiconductor device (3ΐι1ιηίιηιιη) (Αυ, steel (Cu), crane (four)

323818 9 201242003 The low degree of low body. Further, as described above, in the SGT shown in Fig. 19, the P + -type germanium diffusion layer 69 is also connected to the metal wiring at the extended portion of the planar germanium film 67. As a result of the connection between the P + -type germanium diffusion layer 69 and the metal wiring, the metal wiring can not be connected by the P + -type germanium diffusion layer 70 at a short distance, so that there is an equivalent to The resistance of the metal wiring and the channel of the SGT closest to the end of the P+ type Schiffon diffusion layer 69. Therefore, in order to achieve further high-speed operation in a semiconductor device having an SGT, it is necessary to reduce this resistance. The present invention has been made in view of the above circumstances, and it is an object of the invention to provide a semiconductor device which realizes high-volume operation and high-speed operation. In order to achieve the above object, a method of manufacturing a semiconductor device according to a first aspect of the present invention is characterized in that a first insulating layer is formed on a predetermined region on a semiconductor substrate by removing the predetermined region a first insulating layer φ to form a first insulating layer forming/removing step of the insulating layer removing region, or removing a portion of the semiconductor substrate in a thickness direction from a periphery of the predetermined region, and removing the semiconductor substrate from the semiconductor substrate a second insulating layer forming/removing step of forming a first insulating layer; the first semiconductor layer forming step of forming a first containing donor impurity or acceptor impurity on the semiconductor substrate in such a manner as to cover at least the predetermined region a semiconductor layer; a conductor layer forming step of forming a conductor layer on the first semiconductor layer; a forming step of forming the conductor layer and the first semiconductor layer into a predetermined shape; and a second insulating layer forming step of forming the foregoing 323818 10 201242003 a conductor layer of a predetermined shape and a first semiconductor layer a method of forming a second insulating layer, the planarizing step of planarizing the surface of the second insulating layer; and subsequently, the step of bonding the surface of the planarized second insulating layer to the substrate; the thinning step, Thinning the semiconductor substrate to a predetermined thickness; forming a columnar semiconductor on the first semiconductor layer, forming a columnar semiconductor having a columnar structure from the semiconductor substrate; and forming a circuit element in the foregoing The columnar semiconductor is formed of the above-mentioned circuit 70, and further includes: a first semiconductor region forming step of at least: after the seventh semiconductor layer forming step, the first semiconductor layer including the donor impurity or the bulk impurity is used The impurities are diffused to form the first semiconductor region in the columnar semiconductor. Preferably, the step of forming the circuit component comprises: forming a third insulating layer in the peripheral portion of the columnar semiconductor: and forming a third insulating layer on the periphery of the third insulating layer; and the step of the gate conductor layer; The upper portion is a step of forming a surface portion of the columnar semiconductor to form a fourth semiconductor region of a front type; and a portion of the front portion of the third insulating layer is formed opposite to the first region. The step of conducting a third semiconductor region. Preferably, the forming step comprises: forming a mutual conductance 2 three-insulating layer in the columnar semi-conductive portion and forming an outer circumference of the third insulating layer, d: forming the semiconductor into the conductive, 4=: Preferably, the semiconductor region is the same 323818 month circuit component forming step, comprising: a sixth symmetry-centering above the body of the stiff semi-conducting semiconductor 201242003 and an opposite conductivity type T region of the first semiconductor region The steps. The half::first-semiconductor layer forming step preferably comprises: in the foregoing step. In the same layer, a second semiconductor layer functioning as a resistor is formed, and the following step is preferably the first semiconductor layer forming step; the first semiconductor layer functioning as a capacitor electrode is formed as a capacitor Step 1 of the insulating film functioning as the insulating film =: The layer forming step includes forming the above-mentioned insulating film and the step of forming the conductor layer functioning as a capacitor electrode as follows: The first-insulating layer forming step is a package factory, wherein the thickness of the fourth and second layers on the semiconductor substrate and the first insulating layer are thin, and the first step is performed as a capacitor insulating film; the conductor layer is formed. The step includes: the step of forming a conductor layer functioning as a capacitor electrode; and the step of forming a second insulating layer/wire step comprising forming a donor impurity or a receptor impurity in the capacitor region And the capacitance forming step of the impurity layer of 'forming & It is better to read the function of the electric valley electrode. The following steps are preferred: setting the mask alignment mark forming area on the front conductor substrate to set the area of the mask mark formation area = step by step a fresh hole, a production-removal layer, an insulating layer, and a step of exposing the above-mentioned conductor to the exposed portion; the hole is etched through the front mask to form an insulating layer removal region by 323818 12 201242003, a mask alignment mark forming step of the mask alignment mark formed by at least one of the first insulating layer and the conductive layer; and mask aligning of the mask with the mask alignment mark as a reference Mask alignment steps. Preferably, the step of embedding the transparent insulator in the mask alignment hole is performed; and in the mask alignment mark forming step, the insulating layer is removed through the transparent insulator, and the foregoing a mask/alignment mark formed by at least one of the first insulating layer and the conductor layer; in the mask alignment step, the mask pair of the mask is performed based on the mask alignment mark quasi. Preferably, the step of: forming the undoped donor impurity between the first or second insulating layer forming/removing step and the foregoing first semiconductor layer forming step to cover the insulating layer removing region And the step of the second semiconductor layer of the acceptor impurity. Preferably, the second insulating layer forming/removing step includes: a semiconductor substrate etching step of etching the semiconductor substrate forming a periphery of the region of the columnar semiconductor; and forming the foregoing on the semiconductor substrate passing through the etched region a step of forming the first insulating layer on the first semiconductor layer exposed on the etching and the first insulating layer on the periphery of the exposed semiconductor substrate; Preferably, the second insulating layer forming/removing step includes: selectively oxidizing a region around the semiconductor substrate in a region where the columnar semiconductor is formed to form a selective oxide layer as the first insulating layer. 323818 13 201242003 Preferably, the separated first step == step is formed by forming at least two or more mutually adjacent regions of the semiconducting, "image layer region" on the mutually separated regions forming the columnar semiconductor; and Forming: the semiconductor layer of the semiconductor substrate described above is surrounded by the first insulating layer, and the plurality of semiconductor layers separated from each other on the first-first channel before exposure and mixed with the donor or the acceptor a semiconductor device which is a layer and a semiconductor device which is connected to the first semiconductor layer and which is connected to the first semiconductor layer, is a semiconductor device manufactured according to the present invention, which is characterized by the manufacturing method of the present invention, on a semiconductor region The semiconductor system includes a semiconducting conductor region formed in the opposite body type of the first body or the intrinsic semiconductor region, and a front conductor layer. a first semiconductor region; a semiconductor region formed by the second magnetic field wave is formed for storing an electric crystal by irradiating an electric fruit crystal, and a plurality of electric poles are formed; The first-semiconductor region: the diode functions as an interpole, and the former electrode and the other of the third semiconductor regions are used as source means to extract the flow energy, and are configured to be stored by The channel of the aforementioned diode semiconductor region is used as a signal charge removing means. The two currents and the shape function by using the gate conductor layer as a gate, and the first semiconductor region and the fourth semiconductor region function as a source and the other as a 汲Extremely functional brain cell, applied to the aforementioned open conductor layer

The semiconductor device of the third aspect of the present invention is manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention. The semiconductor device of the third aspect of the present invention is manufactured by the method of manufacturing the semiconductor device according to the first aspect of the present invention. In the semiconductor device, the columnar semiconductor system includes a second semiconductor region formed of the opposite conductivity type or intrinsic semiconductor formed on the first semiconductor region, and formed with MOS The transistor functions as the gate by the gate conductor layer, and functions as a source of the first semiconductor region and the fifth semiconductor region, and functions as a drain. A semiconductor device according to a fourth aspect of the present invention is the semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention, characterized in that the columnar semiconductor is in the first semiconductor region and the first semiconductor Between the regions, the third semiconductor region formed of the conductive or intrinsic semiconductor is formed by the first semiconductor region; and the second semiconductor region and the sixth semiconductor region are formed with the second electrode of the present invention. The semiconductor device of the fifth aspect of the invention is a semiconductor device manufactured by the method for fabricating a semiconductor device according to the present invention. The semiconductor semiconductor layer is formed on the first semiconductor layer. The plurality of columnar semiconductors are composed of a plurality of first columnar semiconductors which are == impurities before the first semiconductor, and are formed of conductors. A semiconductor device in which the A-domain is doped with a plurality of second column-shaped half-phases of the donor impurity is a semiconductor device manufactured according to the manufacturing method of the present invention 323818. 201242003 is characterized in that: In the semiconductor semiconductor layer, a plurality of the pillars, a plurality of pillars, and a plurality of columnar semiconductors are formed, and a plurality of the first region and a plurality of the conductive layers are connected to each other. The semiconductor device according to the seventh aspect of the invention is the semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present invention, wherein a plurality of the pillars are formed on the first semiconductor layer. The columnar semiconductor system includes: a second semiconductor region, a semiconductor or an intrinsic semiconductor having a target semiconductor region on the = or the first semiconductor region; and a fifth semiconductor region = second In the semiconductor region; the third insulating layer 'is formed on the outer peripheral portion of the first semiconductor; and the gate conductor is formed on the outer periphery of the second insulating layer; the system is formed with an MGS transistor, which is: a body layer The gate functions as a gate, and the first half body region X and the other fifth semiconductor region function as a source to function as a source, and the other function as a poleless electrode; and the first semiconductor layer The plurality of columnar semiconductors are continuously connected to each other, and the first semiconductor layer formed by the connection is connected to each other via an interface formed on the insulating layer. Lai wiring layer to the external circuits. The semiconductor device according to the eighth aspect of the present invention is the semiconductor device of the method for manufacturing a semiconductor device according to the first aspect of the present invention, characterized in that the plurality of columns are formed on the first semiconductor layer a semiconductor; the pure half (four) system includes a second semiconductor region, and 323818 16 201242003 is composed of a semiconductor or an intrinsic semiconductor formed on the first semiconductor region and having a conductivity opposite to the first semiconductor region; a semiconductor region formed on the second semiconductor region; a third insulating layer formed on an outer peripheral portion of the second semiconductor region; and a gate conductor layer formed on an outer peripheral portion of the third insulating layer; An MOS transistor is formed, wherein the gate conductor layer functions as a gate, and one of the first semiconductor region and the fifth semiconductor region functions as a source, and the other serves as a gate. The first half of the conductor layer is formed by continuously connecting the plurality of columnar semiconductors And the first semiconductor layer via contact holes formed based insulating layers are connected to an interconnection layer for connecting the gate of the transistor to a predetermined. (Effects of the Invention) According to the present invention, it is possible to provide a semiconductor device which realizes high integration and high-speed operation. [Embodiment] φ is described below with reference to Figs. 1 to 16 for a method of manufacturing a semiconductor device according to an embodiment of the present invention. (First Embodiment) A method of manufacturing a solid-state image sensing device according to a first embodiment of the present invention is shown in Figs. 1A to 1L. In the method of manufacturing the solid-state image sensing device of the present embodiment, as shown in FIG. 1A, the doping of the high-concentration hydrogen ion (H+) ions to the first semiconductor substrate 1 composed of the P-type germanium is predetermined. The depth is such that the separation layer 2 for separating the first semiconductor substrate 1 into the upper and lower portions is formed (refer to 323818 17 201242003 Non-Patent Document 2). Further, on the first semiconductor substrate 1, a first hafnium oxide layer 3 belonging to an insulating film is formed by a thermal oxidation or a CVD (Chemical Vapor Deposition) chemical vapor deposition method. Further, the first semiconductor substrate 1 can replace the P-type germanium with an intrinsic semiconductor (i-type germanium) which does not substantially contain impurities. Next, as shown in FIG. 1B, in the first yttria layer 3, yttrium oxide is formed by removing yttrium oxide (SiCh) which is equivalent to a portion of the drain line for forming a solid-state image sensing device. The hole 4 of the region 48 (see Fig. 11A, Fig. 13A) is removed. Next, as shown in Fig. 1B, the polycrystalline germanium layer 5 is formed on the first hafnium oxide layer 3 and the first semiconductor substrate 1 by a CVD method so as to cover the holes 4. Next, as shown in FIG. 1C, on the first semiconductor substrate 1 and the first ruthenium oxide layer 3, doping impurity ions such as scales (P) or banks (As) are doped to the polycrystalline germanium layer 5. The N polycrystal layer 5a which becomes the signal line of the solid-state image sensing device is formed. Then, as shown in FIG. 1D, a gas (he) or a CVD method is used on the N+ polycrystalline slab layer 53 to form a crane (W) and a Siiiicide tungsten (WSi). A single layer composed of (Ni), Shihwa nickel (10), or the like, or a metal layer composed of a plurality of such layers. #图1E, by using a mask etching (etChing) process, N+ polycrystalline (4) 5a and metal layer 7 are left, 4, and the N+ polycrystalline stone The layer 5a and the metal layer 7 are formed into a predetermined shape. On the N+ polycrystalline stellite layer, 323818 201242003 has a solid-state image sensing device for the source or the drain of the electric field effect transistor of the junction. Next, as shown in Fig. 1F, a second hafnium oxide layer 8 belonging to an insulating film is formed by a CVD method so as to cover the N+ polycrystalline germanium layer 5a, the metal layer 7, and the first hafnium oxide layer 3. Further, the surface of the second hafnium oxide layer 8 is planarized by CMP (Chemical Mechanical Polishing). Next, as shown in FIG. 1G, a second semiconductor substrate 9 composed of germanium (Si) and having a surface that has been flattened is prepared, and the planarized surface of the second semiconductor substrate 9 and the second tantalum oxide are prepared. The planarized surfaces of layer 8 are followed by crimping. In this subsequent processing, the difference in thermal expansion coefficient between each other is small, and the ruthenium layer of the second semiconductor substrate 9 and the ruthenium layer of the second ruthenium oxide layer 8 are mutually connected, so that the thermal expansion coefficient of the two subsequent members is not easily obtained. A laminate structure that causes bending, cracking, and peeling. φ Next, as shown in FIG. 1H, the first semiconductor substrate 1 is thinned to the lower portion of the first semiconductor substrate 1 by the heat treatment at 400 ° C to 600 ° C with the separation layer 2 as a boundary. The predetermined thickness (in the case of the 1Hth diagram, the vertical relationship of the patterns of the 1Ath to 1Gth drawings is reversed and displayed). Here, the N+ polycrystalline germanium layer 5a is the N+ type germanium layer 51 shown in Fig. 14. In the present embodiment, the N+ polycrystalline germanium layer 5a is bonded to all of the formation regions of the N+ polycrystalline germanium layer 5a. Metal layer 7. Next, as shown in FIG. 2, in the first semiconductor substrate 1, the layer of the layer directly above the N+ polycrystalline germanium layer 5a remains, and 323818 19 201242003

The area of the upper layer cut layer (4) is removed by money to form a complete Wla having a columnar structure. This miscellaneous H

The P-type germanium layer 3 shown in Fig., Fig. 1L and the like. 〒, attack is the 1K and then 'as shown in Fig. 1J, the heat treatment is carried out to make the 7-layer 5a of the polycrystalline layer of the mineralization to the outside, and the _ impurity is from the column 1a, and is adjacent to the column below the column An N+ diffusion layer 6a is formed. Bufangkou P knife

Next, as shown in Fig. 1K, thermal oxidation is performed to form an insulator n-type (1), 1Ga, and iGb in the outer periphery of the stone slab. Further, the gate conductor layers 11a and 11b are formed outside the third oxygen-cut layers 1Qa and i()b by a vapor deposition method or a CVD method. Next, as shown in the first ικ图, an N-type is formed by doping a donor impurity ion such as phosphorus (8) or Kun (As) to a portion above the gate conductor layers 11a and Ub0ij and forming a surface portion of the Shi Xizhu la. Layers 12a, 12b. The N-type germanium layers 12a, 12b, and the P-type germanium layer 3矽枉 of the 矽枉la form a photodiode as a signal for storing a signal charge (in this case, an electron) in response to incident light.

The charge device No. 2 is stored in the column ia (p-type layer 3〇) between the N+ diffusion layer 6a and the p+ type layer 13a. Next, as shown in the first yoke diagram, in the column lala, by doping boron (B) and other acceptor impurity ions to the upper portion of the third yttria layer iOa, l〇b, The p+ type germanium layer 13a is formed. And, this? The + type germanium layer 13a is electrically connected to the pixel selection metal wirings 14a and 14b. Further, as shown in FIG. 1L, the outer peripheral portion ' of the column lb constituting the solid-state image sensing device and the outer peripheral portion ' of the column lb constituting the other pixel is formed by thermal oxidation. The third yttrium oxide layer 1 〇 c, 323818 20 201242003 1 〇 d ° 抑 1 , similar to the hybrid ^ is formed by the steps shown in the first A to IK diagram. The gate/conductor layer Uc is formed by the vapor deposition method or the (10) method in the outer peripheral portion of the third oxidized oxide layer 1〇c, 1〇d, as shown in Fig. 1L.

Next, as shown in FIG. 1L, a donor impurity ion such as phosphorus (p) or arsenic (As) is doped to the upper portion of the gate conductor layers Uc and 11d and is formed as a surface portion of the stone pillar la. N type stone layer 12c, 12d. Thus, the N-type sap layer c 1 and the Shi Xi column lb open the photodiode as a signal charge storage means for storing the signal charge (in this case, electrons) in response to the incident light. The signal charge is stored in the Shi Xizhu lb (P-type ruthenium layer 30) between the N+ diffusion layer 6ab and the P+ type shoal layer i3b. Next, as shown in FIG. 1L, in the top of the third yttria layer l〇c, l〇d, the dopant impurity ions such as boron (b) are doped to the column lb. The P+ type germanium layer 13b is formed. Further, the P + -type germanium layers 13a and 13b are electrically connected to the halogen-selective metal wirings 14c and 14d. The plurality of pixels of the solid-state image sensing device are formed by the above steps. Further, in the present embodiment, in the step shown in Fig. 1J, the donor impurity is thermally diffused from the N+ polycrystalline layer 5a to the Shih-kil la by heat treatment to form the N+ diffusion layer 6a in the column la. . The present invention is not limited thereto, and the donor impurities may be diffused from the N+ polycrystalline germanium layer 5a into the first semiconductor substrate 1 by heat treatment at any stage after the formation of the N+ polycrystalline germanium layer 5a shown in FIG. 1C. An N+ diffusion layer 6a is formed. That is, after the step of forming the N+ polycrystalline germanium layer 5a in 323818 21 201242003 shown in the ic diagram, the impurity is diffused from the N+ polycrystalline germanium layer 5a containing the donor impurity to form N+ in the column. Diffusion layer 6a. For example, the Ν+diffusion layer 6a may be formed after the step stone = pillar la (P-type ruthenium layer 30) in the stage shown in Fig. Further, the heat treatment for forming such an N+ diffusion layer 6a may be performed only once or may be carried out plural times. , ^ The solid-state image sensing device of the present embodiment is formed in accordance with the steps shown in Figs. 1A to 1L. Furthermore, Yu Gonggong

Dan has π each column la, lb is formed into a solid image sensing device. In the form of a solid-state image sensing device, the pattern of the solid-state image sensing device is formed by referring to the first figure, which is formed under the 矽 column Η, lb, and joined to each other by the polycrystalline shi layer 5& and the metal layer 7 And electrically connecting the N+ diffusion layers 6a and 6ab of the two columns & Accordingly, the signal line composed of the n+ multi-layer 5a and the metal layer 7 is reduced in resistance, and the solid-state image sensing device is driven at a high speed. In the present embodiment, a contact electric field effect transistor is formed in the inner layers of the XI XI column and the lb. In the case of the junction electric field effect transistor, a photodiode system composed of N-type layer 12a, 12b (12c, 12d) and a P-type layer 3 作为 is used as a gate, and a p+ type 矽 layer 13 &丨% is used as the drain, and the N+ diffusion layers 6a and 6b function as the source. Further, in the columns la and lb, the channel of the electric field effect transistor of the junction is formed. Further, in the present embodiment, a channel through which the electric field effect transistor is caused to flow in the columns 1a and 1b is provided, and is changed in accordance with the amount of signal charge stored in the photodiode. The current is taken as a signal to take out the external circuit '323818 22 201242003' as a signal extraction means. The above-mentioned ί 二图: shows that the Shi Xizhu 1a and lb are formed with a signal transistor for storing the signal charge stored in the upper electrode of the upper electrode as a signal charge removing means. "To remove this MO S transistor, it is formed around the third oxide 々 s 1Π lnu 1 极 pole guide BM 1 (the gates lb, 11C, lld of the outer peripheral surface of M as the gate, N+) The diffusion layer is, for example, == and the pole: and _ layer core, 12 Bu, and coffee are used as the source, and the p-type layer is formed in the p-type layer 30. In this embodiment, it is as shown in FIG. 1G. It is to be noted that the second oxide layer of the second semiconductor substrate 9 and the second oxide # 8 on the first semiconductor substrate 1 are connected between the planarized surfaces of the second semiconductor substrate 1. Thus, in the present embodiment, In the entire semiconductor substrate 1 and the second semiconductor substrate 9, the first semiconductor substrate 1 is formed between the Si (矽) plane and the Si〇 2 (yttria) surface having high affinity (the second hafnium oxide layer 8). With the second semiconductor substrate 9, the laminated structure which is less likely to be bent, cracked, or peeled off is obtained. Further, in the present embodiment, the signal line N+ is formed in the pixel of the solid-state image sensing device. The polycrystalline germanium layer 5a is bonded to the metal layer 7. The N+ polycrystalline germanium layer 5a and the metal layer 7 can also be reached by The heat treatment of the step of the ικ diagram or the additional heat treatment, and the formation of the bismuth layer by the reaction of the Ν+ polycrystalline ruthenium layer 5a with the metal layer 7. In any case, n+ 夕, the burst layer 5a and the metal layer 7. Or such a shredded layer is reduced by 323818 23 201242003, which reduces the resistance between the element and the peripheral circuit of the pixel. Accordingly, compared with the solid-state image sensing device of the prior art, That is, in order to increase the number of pixels, or to increase the number of readouts per unit time, the high-speed operation of the solid-state image sensing device can be realized. Further, in the present embodiment, reference is made to FIG. 1K. The (four) junction (photodiode) composed of the p-type germanium layer 30 and the n-type germanium layers 12a and 12b, and the tantalum joint portion composed of the p-type germanium layer 30 and the ore diffusion layer 6a are formed by In the column 1& which is composed of a single crystal crucible, since the crucible interface is formed in a single crystal crucible in this manner, it can constitute a solid element of a solid-state photo sensing device having a low leakage current. In this embodiment, from the pillars la, which constitute the element The beam incident from the upper portion of lb (refer to the il diagram) reaches the stone ridge column la' belonging to the photoelectric conversion region and is reflected by the metal layer 7, so that the optical path length in the column la is increased, and the solid-state image is realized. The sensitivity of the sensing device is improved. Further, in the present embodiment, even if the heights of the columns la and lb are lowered, the sensitivity similar to that of the conventional example can be obtained, so that the same sensitivity as in the conventional example can be obtained. The manufacturing of the solid-state image sensing device is easy to use. In the present embodiment, as shown in FIG. 1B, the first yttrium oxide is formed by CVD by filling (covering) the holes 4. On the layer 3 and the first semiconductor substrate 1, a polycrystalline germanium layer 5 serving as an N+ polycrystalline germanium layer 5a is formed. Instead of forming the polycrystalline germanium layer 5 by the CVD method, it is also possible to form a single crystal germanium layer by epitaxial growth (e P i t a X i a 1). When the epitaxial growth is used, a single crystal germanium layer can be formed on the first hafnium oxide layer 3, so that a solid image can be formed in the same manner as the steps shown in FIGS. 1C to 1K after 323818 24 201242003. Measuring device. Further, in the first embodiment, in the first semiconductor substrate i, the lower portion is removed by the heat treatment of φ 400 to 6 〇 "c", whereby the first semiconductor substrate 1 is removed. Thinned to a predetermined thickness. The substrate is not limited thereto, and a substrate made of a (four) type substrate and a p-type layer formed by the growth of the p+ type substrate may be used as the first semiconductor substrate 1 by means of money etching and CMP. A thin film formation of the first semiconductor germanium is performed. (Second Embodiment) A method of manufacturing a semiconductor device having an SGT (Surrounding Gate Transistor) according to a second embodiment of the present invention will be described below with reference to Fig. 2 . In the first embodiment to the first embodiment, the steps shown in the first embodiment to the first embodiment are shown in the first embodiment to the first embodiment, and the steps shown in FIGS. 1A to 1J are %. The N+ polycrystalline germanium layer 5a constituting the signal line is replaced by the N+ polycrystalline germanium layer 55a which functions as a drain in the SGT. In the same manner as in the first embodiment (see the ljth diagram), the metal layer 7 is bonded to the N+ polycrystalline germanium layer 55a, and is thermally diffused by the donor impurity from the n+ polycrystalline germanium layer 55a. An N+ diffusion layer 6a is formed inside. In the present embodiment, in the step shown in FIG. 2, in the step shown in FIG. 2, the gate insulating layers 15a and 15b are formed on the outer peripheral portion of the column la by an oxidation method or a CVD method. The outer peripheral portions of the pole insulating layers 15a and 15b form gate conductor layers 16a and 16b that function as gates of the SGT. 323818 25 201242003 Next, in the column "La", an upper portion of the gate conductor layers 16a, 16b is formed as an SGT by ion doping of a donor impurity such as phosphorus (P) or arsenic (As). The source layer is the function of the 矽 type i7a. Next, a metal wiring layer 18a is formed on the N+ type germanium layer 17a by vapor deposition and pattern etching. According to the above, the N-channel type SGT is formed on the second semiconductor substrate 9. Here, the 'N+ diffusion layer 6a' and the N+ polycrystalline germanium layer 55a function as a source or a poleless in the n-channel type SGT. According to the present embodiment, in the SGT (N-channel type SGT), the metal layer 7 is bonded to the back surface of the N + polycrystalline germanium layer 5 5 a functioning as a drain. According to this configuration, the resistance from the metal layer 7 to the N+ diffusion layer 6a is reduced, so that the SGT which realizes the south speed operation can be obtained. (Third Embodiment) A method of manufacturing a semiconductor device having an SGT according to a third embodiment of the present invention will be described below with reference to Figs. 3A and 3B. In the present embodiment, the N-channel type SGT and the P-channel type SGT are formed on the same semiconductor substrate. The manufacturing steps of the semiconductor device of the present embodiment and its modifications are the same as those of the first embodiment except for the case described below. In the present embodiment, the N-channel type SGT and the p-channel type SGT are formed in the N-channel type SGT formation region ln and the p-channel type, respectively, on the first semiconductor substrate 1 with reference to FIGS. 3A and 3B. The SGT formation region lp 0 is an N-channel type in which the N-channel SGT formation region In is formed in the same manner as the steps shown in FIG. 1A to the second embodiment and the second embodiment 323818 26 201242003. SGT. On the other hand, the P-channel type SGT of the p-channel type SGT formation region lp is formed in substantially the same manner as the steps shown in Figs. 1A to 1J of the first embodiment and the second embodiment of the second embodiment. However, in the step corresponding to the 1st c diagram, the acceptor impurity such as ion-doped shed (B) is formed, and the polycrystalline layer 5 of the p-channel type SGT forming region lp is formed as a p-channel type SGT. Instead of forming the N+ polycrystalline dream layer 55a functioning as a barrier of the N-channel type SGT, the P+ diffusion layer ga and the P+ polycrystalline layer 55b functioning as a source. Then, as shown in FIG. 3B, the N-channel type SGT composed of the masts & and the masts are formed by the steps corresponding to the steps 1D to 5 and corresponding to the second graph. 15 p-channel type SGT. Further, in the case of the column lb, the n-type layer 30a is formed by the donor impurity such as ion-doping (As) in the column lb (p-type 矽) of the p-channel type SGT. Here, in the step corresponding to FIG. 1J, the donor impurities and the bulk impurities are thermally diffused into the impurities la, lb from the N-polycrystalline layer 55a, respectively, by heat treatment. A diffusion layer and a P diffusion layer 6b are formed. Further, in the step corresponding to the second drawing, the opening insulating layers (5), 15b 15C, 15d ' are formed in the outer peripheral portion of the stone ridges la, lb by thermal oxidation or CVD, and are insulated at the closed end. The outer circumferences of the layers 15a, 15b, 15c, and 15d are formed by the CVD method to form the interlayer conductor layers 16 & 16 16 . , 16 (1 (see 323818 27 201242003 according to Figure 3B). In the step shown in the t pit mB diagram, in Shi Xizhu h, ib, ion doping donor impurities by knife

The source polarization property forms a N+ type fragment 173 which functions as a channel type SGT type SGT, and/or functions as a P+ type 矽 layer 17b which functions as a P channel Λ, a pole or a drain.

In the step shown in FIG. 3B, it is electrically connected to the r-type layer 17a of the N-pass gsgt and the p+-type layer of the p-type SGT: by, for example, vapor deposition and Metal iridium is formed by etching: the line layer and the P-channel type SGT are formed on the N-channel type SGT second semiconductor substrate 9 in accordance with the above. In the present embodiment, the r polycrystalline germanium layer 55a and the n+ diffusing layer 6a and the r-type germanium layer 17& in the N-channel type SGT are not fused to each other. Functions as a source. Furthermore, if the p+ polycrystalline slab layer 55b & p+ diffusion layer 6b and the P+ type sap layer 17b in the p-channel SGT are in the absence of the pole, the other will serve as the source. Play the function. According to this embodiment, the N-channel type SGT and the P-channel type SGT can be easily formed on the second semiconductor substrate 9. In the present embodiment, after forming the column la (p-type layer 30) of the N-channel type SGT, it is attached to the column ib (P-type column) of the P channel type SGT by ion-doping phosphorus ( P) or arsenic (As) and other donor impurities form an N-type germanium layer 3〇a. The first semiconductor substrate 1 of FIG. 1A is set to 323818 28 201242003, which belongs to the undoped intrinsic semiconductor (4) instead of p and in the step corresponding to the second figure, in the N channel. Is the type SGT recorded by ion doping boron (8), etc. by _ mass (four) into? The layer 3 () is formed as a modification of the present embodiment by ion-doping a donor impurity such as phosphorus (7) or Shishen (10) in an ion channel P' of the P channel type SGT. Further, in the present embodiment, the intrinsic semiconductor can be used for both Shi Xizhu and lb, and the intrinsic semiconductors of the lb and lb (four) can be used as the channels of the N-channel type and the P-channel type SGT. (Fourth embodiment)

A method of manufacturing a semiconductor device having a plurality of SGTs according to a fourth embodiment of the present invention will be described with reference to FIG. In the same manner as the third embodiment, the N-channel SGT and the P-channel SGT are formed in the N-channel SGT formation region In and the P-channel SGT formation region ιρ (see FIG. 3A and FIG. 3B picture). In the present embodiment, the N-channel SGT and the P-channel SGT are formed on the second semiconductor substrate 9 belonging to the same semiconductor substrate in substantially the same manner as in the first and third embodiments (see FIGS. 1A to 1J). Figure, Figure 3A, Figure 3B). However, as shown in FIG. 4, as shown in FIG. 4, in a plurality of n-channel type sGTs and P-channel type SGTs, 'N+ polycrystalline slab layer 55a functioning as a source, The P polycrystalline slab layer 55b, which functions as a ruthenium, is electrically connected to each other by the elongated metal layers 7aa and 7bb. That is, in the present embodiment, in the step corresponding to the first DD, the method of 'covering the N-polycrystalline germanium layer 55a, the P+ polycrystalline germanium layer 55b 323818 29 201242003 The metal layer 7 is formed by a phase deposition method and a unique method. Further, the metal layer 7, the r polycrystalline layer (10), and the P polycrystalline layer 55b are formed into a predetermined shape by (4). Thereby, as shown in Fig. 4, the polycrystalline layer 55a, the p+ polycrystalline layer, and the first connecting metal layers 7a and 7b are respectively formed. In this embodiment, the splicer corresponds to the step of FIG. 3B, and referring to FIG. 4, the bismuth telluride layer 20 is formed on the first continuation metal layer 7a, and the ruthenium layer 2 is formed on the ruthenium layer 2 〇彤

丨91 夕 into contact hole 21c. Next, through the contact hole 21c and the first connection umbrella P+ household pure Weifang prefecture layer 7a 'the N polycrystalline Shiya layer 55a and P Xi', and the day Rishi layer 55b and the formation from each line layer 22c connection. The external metal of the upper part of the gasification layer is arranged in the fourth figure of the embodiment, and the metal layer 77aa is bonded to the layer fa of the N-channel type and the P-channel type SGTm crystal layer 55b. , 77bb. Further, the 'N+ diffusion layers h, 6b and the plurality of metal layers 7aa and 7bb are connected to each other in the la ' lb . In the fourth embodiment, in the fourth embodiment, the N+ diffusion layer 6a, +, and the crystal layer 55a are used as the source or the infinite pole of the N-channel type SGT, and P+ polycrystalline stone The layer 55b functions as a source or a drain of the P channel type SGT. As described above, according to the present embodiment, in the plurality of SGTs, the source and the non-polar phase composed of the n + polycrystalline slab layer 55a and the r polycrystalline slab layer 55b are not in the upper surface of the oxygen-cut layer 2G. The region in which the metal wirings a, 22b, and 22c are formed is connected to each other via a contact hole or the like, and is connected to each other by 323818 30 201242003, and is electrically connected to each other by extending the first connection metal layer 7a. According to this, the degree of integration of the circuit elements having the SGT can be improved. Further, the method of manufacturing the semiconductor device of the present embodiment is applicable to a method of manufacturing a solid-state image sensing device. In this case, for example, in the solid-state image sensing device in which a plurality of halogen signals are read by a magnifying MOS transistor described in Non-Patent Document 1, the bungee of each element is borrowed from each other. It is connected by the first connection metal layer 7a. At this time, the drain and source of each of the pixels are not necessarily connected to each other in a state of being connected to the other metal wires of the upper portion via the contact holes or the like. Therefore, it is possible to achieve further integration of the pixels of the solid-state imaging device. (Fifth Embodiment) A method of forming a resistor in a semiconductor device according to a fifth embodiment of the present invention will be described below with reference to Figs. 5A to 5C. The manufacturing steps of the semiconductor device according to the present embodiment and its modifications are the same as those in the first embodiment except for the case of the following description. φ In the present embodiment, the resistance of the circuit element belonging to the semiconductor device is formed by using the polycrystalline germanium layer 5 formed on the first semiconductor substrate 1 as shown in Fig. 1B. In the present embodiment, in the step shown in FIG. 1A, a separation layer 2 for separating the first semiconductor substrate 1 into upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1. And forming the first hafnium oxide layer 3 belonging to the insulator on the first semiconductor substrate 1. Next, in the step shown in FIG. 1B, a polycrystalline layer 5 is formed on the first hafnium oxide layer 3, and in the step shown in FIG. 1C, 323818 31 201242003 is multi-knotted here. The ruthenium layer 5' forms an N+ polycrystalline ruthenium layer 5a by ion doping the pepper impurities. ～Special application body In the present embodiment, in the steps shown in FIG. 1B and FIG. 1C, the polycrystalline germanium layer on the first yttria layer 3 is as shown in FIG. 5A.

The predetermined region of 5 is formed by ion-doping a donor impurity such as phosphorus (p) or arsenic (As) at a predetermined concentration to form an N-polycrystalline layer 2 such as 2 north. By means of the N+ polycrystalline germanium layer 23a, 23b, the polycrystalline germanium layer 23 doped with the donor impurity, or the polycrystalline litmus layer 23 doped with the impurity of the pre-tanning, The resistance value of the predetermined region (polycrystalline fragment 23) is decreased to form a resistor. Thus, the N+ polycrystalline germanium layer 23a, 23b, and the polycrystalline germanium layer 23 and the N+ polycrystalline germanium layer 5a (see the ic diagram) Similarly, it is formed of polycrystalline stone Xitang 5 (refer to FIG. 1B), and is located at the same layer as the N+ polycrystalline germanium layer 5a. Next, in the step shown in Fig. 1D, the metal wiring layers 24a and 24b located in the same layer as the gold layer 7 are formed on the N polycrystalline germanium layers 23a and 23b in the same manner as the metal layer 7. According to the present embodiment, the N+ polycrystalline germanium layer 23a, 23b and the polycrystalline germanium layer having a predetermined electric enthalpy and having a predetermined electric concentration doped by a predetermined concentration of the donor impurity in the polycrystalline germanium layer 5 are formed. twenty three. Further, the 'N+ polycrystalline germanium layers 23a and 23b and the polycrystalline germanium layer 23 are formed in the same layer as the N+ multiple crystal germanium layer 5a. According to this, it is possible to manufacture a resistor (circuit element) together with a semiconductor device such as a solid-state image sensing device or an SGT on the same semiconductor substrate, and the manufacturing steps can be simplified. Furthermore, in the present embodiment, the polycrystalline germanium layer 25 is formed by the steps shown in FIG. 323818 32 201242003 1B, and is formed into a predetermined shape by etching, and then deposited by vapor deposition. The metal wiring layers 26a and 26b connected to the polycrystalline germanium layer 25 are formed by a method or a CVD method. In this manner, the resistance of the semiconductor device can also be formed by the polycrystalline germanium layer 25. Further, in a modification of the embodiment, referring to FIG. 5C, a second hafnium oxide layer 8 is formed on the second semiconductor substrate 9, and the second hafnium oxide layer 8 is formed by the above method. N+ polycrystalline germanium layers 23a, 23b and polycrystalline germanium layer 23. Thereafter, a first hafnium oxide layer 3 may be formed on the N+ polycrystalline germanium layer 23a, 23b and the polycrystalline germanium layer 23, and a hafnium oxide layer 20 may be formed on the first hafnium oxide layer 3 (see FIG. 4). . Further, in the fifth graph, the resistors shown in Fig. 5A are formed of the N+ polycrystalline germanium layers 23a and 23b and the polycrystalline germanium layer 23. Further, in the present embodiment and the modification shown in Fig. 5C, a circuit element having a SGT or a metal wiring is formed on the first tantalum oxide layer 3 with reference to Fig. 4 . φ Further, in the modification shown in Fig. 5C, the multi-junction layer 23 constituting the resistor is formed below the first hafnium oxide layer 3 belonging to the insulator. According to the present modification, as shown in FIG. 5C, the Si 〇 2 layer (the first yttria layer 3) can be formed on the Si 〇 2 layer (the first ruthenium oxide layer 3) so as to overlap the polycrystalline ruthenium layer 23 constituting the resistor. Metal wiring layers 22a, 22b, 22c of circuit elements. According to this, it is possible to achieve further high integration of the semiconductor device (circuit element) having resistance. (Sixth Embodiment) A method of forming a capacitor in a semiconductor device according to an embodiment of the present invention will be described with reference to Figs. 6A to 6C. The manufacturing steps of the semiconductor device of the present embodiment are the same as those of the first embodiment except for the cases described below. In the present embodiment, the capacitance of the circuit element belonging to the semiconductor device is formed by using the polycrystalline germanium layer 5 formed on the first semiconductor substrate 1 as shown in Fig. 1B. In the present embodiment, in the step shown in FIG. 1A, a separation layer 2 for separating the first semiconductor substrate 1 into upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1. And forming the first hafnium oxide layer 3 belonging to the insulator on the first semiconductor substrate 1. Next, in the step shown in FIG. 1B, a polycrystalline germanium layer 5 is formed on the first hafnium oxide layer 3, and in the step shown in FIG. 1C, the polycrystalline germanium layer 5 is The N+ polycrystalline germanium layer 5a is formed by ion doping a donor impurity such as phosphorus (P) or arsenic (As). Here, in the step shown in Fig. 1C, referring to Fig. 6A, a capacitor yttria layer 27 is formed on the surface layer portion of the N+ polycrystalline ruthenium layer 5a by thermal oxidation or CVD. Next, referring to Fig. 6B, a capacitor yttria layer 27 functioning as a capacitor insulating film is formed into a predetermined shape by using a mask to form a capacitance region of the capacitor. Further, in the step shown in Fig. 1D, the metal layer 28 functioning as a capacitor electrode is formed on the capacitor yttria layer 27 formed into a predetermined shape by a vapor deposition method or a CVD method. This metal layer 28 is formed in the same layer as the metal layer 7 of the first embodiment. 323818 34 201242003 Next, by the steps shown in Figs. 1E to 1H and 4, a laminated structure as shown in Fig. 6C is formed. That is, the second hafnium oxide layer 8 is formed on the second semiconductor substrate 9, and in the inside of the second hafnium oxide layer 8, a metal layer 28 functioning as a capacitor electrode is provided in the capacitance region where the capacitance is formed. And a capacitor yttria layer 27 which is laminated on the metal layer 28 to function as a capacitor insulating film. Further, on the capacitor yttria layer 27 and the second yttria layer 8, a Φ structure in which an N+ polycrystalline ruthenium layer 5a, a first ruthenium oxide layer 3, and a ruthenium oxide layer 29 (ruthenium oxide layer 20) are sequentially laminated is obtained. . With this configuration, the metal layer 28 and the N+ polycrystalline germanium layer 5a function as capacitor electrodes, and the capacitor oxide layer 27 functions as a capacitance of the capacitor insulating film. In the first embodiment to the first embodiment of the method for manufacturing a solid-state image sensing device according to the first embodiment, the surface layer is formed of an insulating layer 27 added to the surface layer of the N+ polycrystalline germanium layer 5a. The step (Fig. 6A) and the step of forming the capacitor yttrium oxide layer 27 and the metal layer 28 (refer to Fig. 6B). According to this, a semiconductor device such as a halogen or SGT of a solid-state image sensing device is formed on the same semiconductor substrate to form a capacitor (circuit element), and the manufacturing steps are also simplified. (Seventh Embodiment) A method of forming a capacitor in a semiconductor device according to a seventh embodiment of the present invention will be described with reference to Figs. 7A and 7B. The manufacturing steps of the semiconductor device of the present embodiment are the same as those of the first embodiment except for the case described below. In the present embodiment, the capacitance of the circuit element belonging to the semiconductor device is formed by using the polycrystalline germanium layer 5 formed on the first semiconductor substrate 1 of 323818 35 201242003 as shown in Fig. 1B. In the present embodiment, in the step shown in FIG. 1A, a separation layer 2 for separating the first semiconductor substrate 1 into upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1, and A first ruthenium oxide layer 3 belonging to an insulator is formed on the first semiconductor substrate 1. Next, in the step shown in FIG. 1B, before forming the polycrystalline germanium layer 5, the capacitance-shaped region 100 shown in FIG. 7A is set on the first hafnium oxide layer 3, and is etched by etching. The yttrium oxide of this capacitance forming region 100 is removed, thereby forming a concave-shaped yttrium oxide layer removing region. That is, as shown in Fig. 1B, as shown in Fig. 7A, the yttrium oxide layers 101a, 101b remain around the yttrium oxide layer removal region, and the specific thickness of the yttrium oxide layers 101a, 101b is made. The thinner ruthenium oxide layer 103 remains in the yttrium oxide layer removal region. Further, the yttrium oxide layers 101a and 101b are used as a mask, and the P+ diffusion layer 102 is formed by the yttrium oxide layer 103 by ion doping or thermally diffusing the acceptor impurities such as boron (B). The capacitor forms the surface layer of the first semiconductor substrate 1 of the region 100. Further, referring to Fig. 1B, a polycrystalline germanium layer 5 is formed on the first hafnium oxide layer 3 by filling a region in which the hafnium oxide layer is removed. Next, in the step shown in FIG. 1C, the polycrystalline layer 5 is formed by ion doping with a donor impurity such as phosphorus (P) or arsenic (As) to form an N+ polycrystalline germanium layer 104. (Refer to Figure 7A). Next, in the step shown in FIG. 1D, the metal layer 105 is formed on the N+ polycrystalline germanium layer 104 by vapor deposition or CVD (refer to 323818 36 201242003 7 8). It is formed in the same layer as the metal layer 7 of the first embodiment. Then, in the same manner as the step shown in FIG. 1E, the N+ polycrystalline litchi layer 1G4 and the N+ Asahi layer 1〇4 are formed on the N+ polycrystalline layer 1〇4 in the formation of the capacitor, and are used as capacitor electrodes. The functional metal layer ι〇5 is formed into a predetermined shape. After passing through the first to fourth embodiments of the first embodiment, referring to FIG. 7B, the p+ diffusion layer 1〇2 remains on the side of the stone pillar to cover the p+ diffusion layer 102. The ruthenium oxide layer 1〇7 is formed in the same manner as the oxidized stone layer l〇la, 101b. 108 i is referred to as * 7B, 'the formation of contact holes in the oxidized stone layer 107 is 1〇9 ΓΡ contact holes 1〇8, and the metal wiring on the oxidized stone layer 107 is as described above, as shown in Fig. 7B. In the capacitor formation region 100 (see Fig. 7A), an N+ polycrystalline schist layer 1〇4, a metal layer 1〇5, and a p+/political layer 1〇2 are formed as capacitor electrodes, and the yttrium oxide layer is formed. La, the oxidized stone layer between the b layers functions as a capacitor insulating film. In the present embodiment, boron (8) or the like is used by masking the yttrium oxide layers 10a and 1b 2 The acceptor impurity is ion-doped or thermally dispersed to the first semiconductor substrate 1 to form the P+ diffusion layer 102. It is not limited to sound, and may be derived from a high-twisting layer from a uniform thickness: the first oxygen-cut layer 3 (refer to the fourth layer) before forming the yttrium oxide layer 1〇1, 1〇1b. In a predetermined area other than the region 100, 323818 乂37 201242003 is formed into the P+ diffusion layer 102. According to the present embodiment, according to the structure shown in Fig. 7B, the connection between the capacitors and the extraction of the electric signals to the external circuit can be performed from any place of the semiconductor device by the contact holes 108. According to this, it is possible to further integrate the circuit elements. (Eighth Embodiment) A method of forming a diode in a semiconductor device according to an eighth embodiment of the present invention will be described below with reference to Figs. 8A to 8C. The manufacturing steps of the semiconductor device of the embodiment ® and its modifications are the same as those of the first embodiment except for the case described below. In the present embodiment, the diode of the circuit element belonging to the semiconductor device is formed by using the polycrystalline germanium layer 5 formed on the first semiconductor substrate 1 as shown in Fig. 1B. In the present embodiment, the second ruthenium oxide layer 8 is formed on the second semiconductor substrate φ 9 as shown in FIG. 8A by the steps shown in FIGS. 1A to II of the first embodiment, and A metal layer 7, an N+ polycrystalline germanium layer 5a, and a column la are sequentially formed in the diode forming region 100a from below. Further, on the second hafnium oxide layer 8, a first hafnium oxide layer 3 is formed around the N+ polycrystalline hafnium layer 5a. Next, in the structure shown in FIG. 8A, in the case where the pillars la are formed by the intrinsic enthalpy, the P-type shown in FIG. 8B is formed by ion-doping the acceptor impurities such as boron (B). Layer 30. Further, when the column column la is formed into a P type as in the first embodiment, ion doping of the acceptor impurity is not required. 323818 38 201242003 Next, referring to 帛8B ffl, heat treatment is performed to thermally diffuse donor impurities from the n+ polycrystalline germanium layer 5a into the p-type germanium layer 30', and the N+ diffusion layer h is formed in the p-type germanium layer 30 (column) Below the la). Next, referring to FIG. 8B, a p+ type germanium layer 31' is formed by ion doping an acceptor impurity such as boron (B) at a portion above the p-type germanium layer 3〇 (column 1&) and by gas The phase deposition method and the shoe engraving form a metal layer 32 on the p+ type. Next, referring to the rib pattern, the oxidized stone layer 33 is formed to cover the P-type germanium layer 30 and the metal layer 32, and the contact holes 34 are sequentially formed on the metal layer 32 in the oxidized layer 33, Metal wiring layer 35. Accordingly, the metal wiring layer 35 and the metal layer are electrically connected via the contact hole 34. In the present embodiment, the pn junction diode is formed by the P + -type germanium layer 31 and the p-type germanium layer 30. According to the present embodiment, it is possible to form not only a solid-state scene, but also a semiconductor device such as a semiconductor device of a sensing device, and a diode device (circuit element), and a manufacturing step can be formed on the same semiconductor substrate. Simplified. In the eighth embodiment, a modification of this embodiment in which a piN photodiode is formed in the column la is shown. In this modification, the 夕 柱 la la 所示 所示 所示 la la la la la la la la la la la la la la la la la la la la la la la la la la la la la la la la la la la la la la la la A p+ type germanium layer 31 is formed. Further, a plN photodiode is formed by the i-type germanium layer 3〇b&p+ type germanium layer 31. In the PIN photodiode, referring to Fig. 8C, the light beam is incident from the upper portion of the P+ type germanium layer 31. Therefore, the metal layer 32 for connecting the P-type germanium layer 31 and the external circuit is formed in the outer peripheral region of the p + -type germanium layer 31 in a manner of not inhibiting the incident of the light beam by 323818 39 201242003. According to the PIN photodiode of the present modification, the depletion layer is formed in the entire or wide-area region of the i-type germanium layer 3〇b, so that the photoelectric conversion region can be widely protected, and the capacitance-forming region is equivalent. Since the thickness of the depletion layer of the thickness is large, it is possible to reduce the capacitance. Further, the PIN photodiode system is formed as a beam connection photodetector on the same semiconductor substrate as the circuit element of the semiconductor device. • Since the PIN photodiode system of this modification functions as a beam switch, there is no RC delay due to the resistance/electric valley of the input circuit wiring, and the circuit input unit can be speeded up and the entire circuit can be realized. High speed. According to the present modification, not only a semiconductor device such as a pixel of a solid-state image sensing device or a SGT but also a PIN diode (circuit element) can be formed on the same semiconductor substrate, and the manufacturing steps can be simplified. φ (Ninth Embodiment) A CMOS inverter circuit using SGT according to the ninth embodiment of the present invention will be described with reference to Figs. 9A to 9C. A CMOS inverter circuit using SGT of this embodiment is shown in Fig. 9A. As shown in Fig. 9A, the P channel type MOS transistor 37a and the N channel type MOS transistor 37b are connected in series. The gates of the P-channel type MOS transistor 37a and the N-channel pear transistor 37b are fast-connected to each other via the gate connection wiring 38, and the gate connection wiring 38 is connected to the input terminal wiring Vi. The source of the p-channel MOS transistor 37a is connected to the power terminal 323818 40 201242003. The drain of the Vdd°P channel type MOS transistor 37a and the drain of the N-channel transistor 37b are connected via the drain connection wiring 39. The source terminal wiring Vss is connected to the output terminal wiring Vo' and is connected to the source of the N-channel type MOS transistor 37b to be a ground potential. Figure 9B shows a side configuration diagram of a CMOS inverter circuit using this SGT. As shown in Fig. 9B, contact holes 4le, _ pillars 40a, contact holes 41a, contact holes 41b, and contact holes 4ld are arranged in a line. • The input terminal wiring Vi is used to turn on the electric signal (gate voltage) from the contact hole 41c. The power supply terminal wiring Vdd is a one for supplying a power supply voltage from the contact hole 4la. The ground terminal wiring Vss is a ground connection for connecting via the contact hole 41b. The output terminal wiring ν is a person for outputting a telecommunication signal from the connection hole 41d. The contact hole 41c is formed on the gate connection wiring 38 φ which connects the gates of the P channel type MOS transistor 37a and the N channel type MOS transistor 37b to each other. The Shi Xizhu 4〇a system constitutes a p-channel type MOS transistor 37a. Contact holes are formed on the mast 40a. The mast 40b constitutes an N-channel type MOS electroforming body 37b. The contact hole 41b is formed on the mast 4〇b. The contact hole 4ld is formed on the drain connection wiring 39 which interconnects the drain of the P channel type MOS transistor 37a and the drain of the N channel type M 〇 transistor 37b. Further, the input terminal is arranged so as to extend in a direction orthogonal to the row direction of the contact hole 41b and the contact hole 41d.

Vi, power terminal wiring Vdd, ground terminal wiring vss, and wheel early wiring Vo (refer to Fig. 9A). 323818 201242003 Figure 9C is a cross-sectional structural diagram of Figure 9B. The method of forming the CMOS inverter circuit described above will be described with reference to Fig. 9C. In the present embodiment, the steps of forming the CMOS inverter circuit are the same as those in the first embodiment except for the case described below. In the present embodiment, the CMOS inverter circuit having the P-channel type MOS transistor 37a and the N-channel type MOS transistor 37b shown in Fig. 9C is an N-channel type MOS transistor of the circuit shown in Fig. 3B. The left-right positional relationship with the P-channel type MOS transistor is exchanged, and is formed in the same manner as the third embodiment shown in Figs. 3A and 3B ® . In the following, the portions indicated by the same or corresponding reference numerals in the above embodiments are omitted. As shown in Fig. 9C, the P+ diffusion layer 6b functioning as a drain in the P channel type MOS transistor 37a, the P+ polycrystalline germanium layer 55b, and the n-channel type MOS transistor 37b function as a drain. A drain connection wiring 39 is formed under the N+ diffusion layer 6a and the N+ polycrystalline germanium layer 55a. The surface of the N+ polycrystalline germanium layer 55a and the P+ polycrystalline germanium layer 55b is bonded to the surface of the bottom layer, and the drain line is connected. The 39°N+ polycrystalline germanium layer 55a and the P+ polycrystalline germanium layer 55b are connected via the drain connection wiring 39. connection. Further, the terminal connection wiring is applied, and the jade is formed on the insulating layer 43b, and is penetrated and oxidized. The contact hole 41d of the layer 45 is connected to the output terminal wiring layer v. Further, the gate conductor layers 16ba and 16bb of the 'P channel type MOS transistor 37a and the gate conductor layer 16 and 16ab' of the N channel type M 〇 transistor 37b pass through the gate formed on the insulating layer 43a. Connect the wiring and connect them. Further, the metal wiring layer 18b formed on the N+ diffusion layer 6a and the p+ type germanium layer nb of the drain of the gate connection wiring 38 and the p-channel type transistor 323818 42 201242003 body 37a becomes the N channel type MOS battery. The mine diffusion layer 6a of the drain of the crystal 37b, the metal wiring 18a formed on the N+ type germanium layer 17a, and the drain connection wiring 39 are connected via the contact holes 41c, 41a, 41b, and 41d penetrating the ruthenium oxide layer 45, respectively. The input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vo formed on the yttrium oxide layer 45. The input terminal wiring layer vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer v are mutually parallel-connected (see Fig. 9C). According to the present embodiment, the P+ diffusion layer 6a, the p+ polycrystalline germanium layer 55b functioning as a poleless function, and the N+ diffusion layer functioning as a drain in the N channel type MOS transistor 37b in the P channel type MOS transistor 37a. 6a, the N+ polycrystalline germanium layer 55a is connected in a state of being close to each other, and is electrically connected by a drain connection wiring 39 having a low resistance. According to this configuration, it is possible to obtain a product φ body circuit having a CMOS inverter circuit which realizes high speed and high integration. (Tenth Embodiment) A CMOS inverter circuit having a two-stage structure according to a tenth embodiment of the present invention will be described below with reference to Figs. 10A to 10D. In the following, portions and configurations denoted by the same or corresponding reference numerals to the ninth embodiment will be omitted. In Fig. 10A, a two-stage CMOS inverter circuit used in the present embodiment is shown.

As shown in Fig. 10A, the P-channel type MOS transistors 37a, 37c and the N 323818 43 201242003 channel type MOS transistors 37b, 37d are connected in series in the first stage and the second stage, respectively. The gates of the first-stage p-channel MOS transistor 37a and the N-channel MOS transistor 37b are connected to the input terminal wiring Vi via the gate connection wiring 38a. The gates of the second-stage P-channel type MOS transistor 37c and the N-channel type MOS transistor 37d are connected to the output terminal wiring Vo of the first stage via the gate connection wiring 38b. The respective drains of the p-channel type MOS transistors 37a and 37c of the first and second stages are connected to the power supply terminal wiring Vdd. The respective sources of the P-channel type MOS transistors 37b and 37d of the first and second stages are connected to the ground terminal wiring Vss. In the first stage, the drain of the P-channel type MOS transistor 37a and the drain of the N-channel type transistor 37b are connected to the output terminal wiring Vo of the first stage via the drain connection wiring 39a. In the second stage, the drain of the P-channel type transistor 37c and the step of the N-channel type transistor 3 7d are connected to the output terminal wiring Vout via the "" and the connection wiring 3 9b. A plan view of the CMOS inverter circuit is shown in Fig. 10B. As shown in FIG. 10B, the gate 40a constituting the first-stage P-channel type MOS transistor 37a and the gate connection wiring 38a constituting the mast 40b of the N-channel type MOS transistor 37b are formed with contact holes. 41c, and the contact hole 41c is connected to the input terminal wiring Vi. The gate connection wiring 38a connects the gates of the P channel type MOS transistor 37a and the N channel type MOS transistor 37b to each other. In the first stage, the drain of the P-channel type MOS transistor 37a and the drain of the N-channel MOS transistor 37b are connected via the first stage of the drain connection 323818 44 201242003 line 39a. A contact hole 41e is formed on the gate 40c constituting the second-stage P-channel type MOS transistor 37c, and the gate connection wiring 38b constituting the shi- ike column 40d of the N-channel type MOS transistor 37d, and the contact hole 41 is formed. The e is connected to the output terminal wiring ν〇 of the first stage (see Fig. 10A). The drain connection wiring of the first stage is connected to the gate quick-connect wiring 38b via the contact hole 41e (see Fig. 10C). The gate connection wiring 38b connects the second-stage P-channel type MOS transistor 37c and the gate of the N-channel type MOS transistor 37d to each other. Contact holes 41a and 41c are formed in each of the Shishi columns 40a and 40c of the P-channel type MOS transistors 37a and 37c of the first and second stages, respectively. The contact holes 41a and 41c are connected to the power supply terminal wiring layer Vdd. Contact holes 41b and 41d are formed in the masts 40b and 40d of the P-channel type MOS transistors 37b and 37d of the first and second stages, respectively. The contact holes 41b, 41d are all connected to the ground terminal wiring JVs. φ is formed in the second-stage drain connection wiring 39b with the contact hole 41 dead, and the contact hole 41f is connected to the output terminal wiring layer Vout. Further, the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer v〇ut are wired in parallel with each other. Fig. 10C is a cross-sectional structural view taken along line c-C of Fig. 10B, and the CMOS inverter circuit having the above-described two-stage structure will be described with reference to Fig. 10C. In the present embodiment, the CMOS inverter circuit of the two-stage structure is formed in the same manner as in the first embodiment. 323818 45 201242003 As shown in FIG. 10C, the 'CMOS inverter circuit having the P channel type MOS transistor 37a and the N channel type MOS transistor 37b' is the N channel of the CMOS inverter circuit shown in FIG. 3B. The left-right positional relationship between the MOS transistor and the P-channel MOS transistor is exchanged, but is formed in the same manner as the third embodiment shown in Figs. 3A and 3B. As shown in Fig. 10C, in the first stage, the gate conductor layers 16ba, 16bb surrounding the outer circumference of the Shishi column 40a of the P channel type MOS transistor 37a, and the 围绕 surrounding the N channel type MOS transistor 37b. The outer perimeter of the column 40b

The pole conductor layers 16aa and 16ab are connected via the gate connection wiring 38a. The oxidized layer 45 formed on the gate connection wiring 38a is formed with a contact hole 41b connected to the metal wiring layer 18a on the n-channel type MOS transistor 37b. The contact hole 41b is connected to the ground terminal wiring Vss of the n-channel type MOS transistor 37b. Further, in the first 〇c diagram, a ruthenium oxide layer 43 is formed between the first ruthenium oxide layer 3 and the gate connection wiring 38a. In the first stage, the p+ polycrystalline germanium layer 5形成 which is formed at the lower end of the sample 40a of the P channel type M〇s transistor 37a and functions as a drain, and the impurity formed in the N channel type MOS transistor The lower end portion of the crucible is electrically connected to the metal wiring layer 42 of the first-stage non-polar connection wiring 39a, and is electrically connected to the metal wiring layer 42 and the metal wiring layer 42. The two-stage P-channel type M0S electro-crystal spectrum is connected to the wiring coffee, and the m:: poles are connected to each other by poles (refer to the figure of the second figure, the =). The contact hole of the layer 45 is called the P-channel type M of the first slave. The 夕S-electrode 37a of the 〇S transistor 37a is 323818 46 201242003 A contact hole 41a is formed, and the contact hole 41a is connected to the power terminal wiring layer Vdd. A contact hole 41b' is formed on the Shishizhu 4〇b of the N-channel type MOS transistor 37b of the first stage, and the contact hole 41b is connected to the ground terminal wiring layer Vss. A contact hole 41f is formed in the second-stage drain connection wiring 39b, and an output terminal wiring layer Vout is connected to the contact hole 41f on the yttria layer 45 (see FIGS. 10A and 10B). In addition, the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vout are wired in parallel with each other (see FIG. 10B). According to the present embodiment, the metal wiring layer 42 functioning as the first-stage P-channel MOS transistor 37a and the drain connection wiring 39a of the N-channel MOS transistor 37b is directly connected to the second segment via the contact hole 41e. The inter-pole connection wiring 38b of the P-channel type MOS transistor 37c and the N-channel type MOS transistor 37d. With this configuration, it is not necessary to raise the metal wiring layer 42 (39a) to the wheel terminal wiring layer vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss via the contact holes formed in the oxidized φ layer 45, Since the output terminal wiring layer V〇ut (see FIG. 10B) is in the same layer, the southerness of the circuit elements can be realized. (Eleventh Embodiment) A method of forming a mask alignment mark on a semiconductor substrate according to the first embodiment of the present invention will be described below with reference to Figs. 11A and 11B. The steps which are not shown in Fig. 11A are those corresponding to (4) shown in Fig. 1H of the first embodiment. The other steps are the same as in the first embodiment except for the case of the following description 323818 47 201242003. As shown in Fig. 11A, a second hafnium oxide layer 8 is formed on the second semiconductor substrate 9. A first ruthenium oxide layer 3 and a first semiconductor substrate 1 are sequentially formed on the second hafnium oxide layer 8. As shown in Fig. 11A, at a predetermined position on the first semiconductor substrate 1, a mask alignment mark forming region 47a for mask alignment and a circuit forming region 47b for forming a circuit are provided.

In the mask alignment mark forming region 47a shown in Fig. 11A, a yttrium oxide layer removing region 48 is formed in the first yttria layer 3 (see Fig. 1B). In the central portion of the yttrium oxide layer removing region 48, a marking metal layer 49a and a marking polycrystalline ruthenium layer 49b are formed in a laminated state. The ruthenium oxide layer removal region 48 is formed at the same time as the source or the drain hole 4 of the junction electric field effect transistor of the halogen formed with the solid-state image sensing device as shown in Fig. 1B. On the other hand, as shown in Fig. 11A, the metal layer 7 and the N+ polycrystalline germanium layer 5a are formed in a layered state in the central portion of φ of the circuit formation region 47b (refer to Fig. 1H). In the state shown in Fig. 11A, the first semiconductor substrate 1 of the mask alignment mark forming region 47a is etched, and the mask alignment hole 50 is formed at a predetermined position as shown in Fig. 11B. Thereby, the mark metal layer 49a, the mark polycrystalline germanium layer 49b, and the ruthenium oxide layer removal region 48 are exposed through the mask alignment holes 50. Next, any one of the mark metal layer 49a, the mark polycrystalline germanium layer 49b, and the yttrium oxide layer removal region 48 in the mask alignment hole 50 will be used as a mask alignment for 323818 48 201242003. Mark and align the mask with the light mask. Next, the light mask is superimposed on the region where the photoresist is formed and irradiated with the light beam, thereby dubbing the circuit. On the other hand, when the mask alignment hole 5G is not present, the photoresist is coated on the first semiconductor substrate 1 and will be applied to the product, and the θ is a resist, and will be located in the first semiconductor. The mark metal layer 49a, the mark multi-junction W layer 49b, and the oxidized stone layer removal region 48 under the substrate are masked and aligned. This situation

At this time, since the first semiconductor substrate 1 is composed of germanium and absorbs light of blue light and ultraviolet light is large, it is used to penetrate :::= infrared light in the mask alignment. Therefore, the resolution of the mark image is lowered and the mask alignment accuracy is lowered. In the present embodiment, the mask is formed in the mask alignment mark layer, so that the multi-junction (4) 49b and the oxygen-cut rod image, _ can be marked in the Shih-shi layer removal region where the absorption of the ray and the ultraviolet light is large. Therefore, the material alignment accuracy can be improved by high resolution ^(10). Further, according to the present embodiment, the photoresist is directly formed on the oxygen, so that the positioning accuracy of the π-th removing layer 48a and the stone pillar can be improved.乡,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, the same. 323818 As shown in Fig. U, the blue or ultraviolet light is transparent. 49 201242003 The insulating layer 50a is buried in the mask alignment hole 50 shown in Fig. 11B. Here, the transparent insulating layer 50a is made of a Si 2 film. Thereafter, the Si〇2 film and the surface of the first semiconductor substrate 1 are planarized by CMP. The embedding step of masking the Si〇2 film of the alignment hole 50 is performed before referring to Fig. II, before the formation of the pillars la having the electric field effect electric crystals formed thereon. According to this modification, by masking the transparent insulating layer 50a in the alignment hole 50, the photoresist of the cover mask alignment mark forming region 47a and the circuit formation region #47b can be thinned and uniformly formed. Therefore, compared with the eleventh embodiment, the mask alignment accuracy can be further improved. (Twelfth Embodiment) A method of manufacturing a semiconductor device according to a twelfth embodiment of the present invention will be described with reference to Figs. 13A and 13B. Fig. 13A is a diagram corresponding to the steps shown in Fig. 1B of the first embodiment. The other steps are the same as those of the first φ 1 embodiment except for the case described below. In the present embodiment, in the step shown in FIG. 13A, a separation layer 2 for separating the first semiconductor substrate 1 into upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1, and A first ruthenium oxide layer 3 belonging to an insulator is formed on the first semiconductor substrate 1. Next, as shown in Fig. 13A, in the first yttria layer 3, the holes 4 are formed by removing yttrium oxide (Si 〇 2) in a predetermined region. Next, as shown in FIG. 13A, the hole 4 (the yttrium oxide layer removing region 48) is filled in the first yttria layer 3 and the first semiconductor substrate 1 323818 50 201242003 by a CVD method. The multijunction is not doped with donor impurities or acceptor impurities. The multi-corrugated layer 111 is formed by a polycrystalline germanium layer 106 on the surface of the multi-CVD method and the donor impurity as shown in the figure (10). y is formed to be doped with the donor impurity. Next, the metal layer 7 is formed on the N+ polycrystalline layer 106 in the same manner as the step shown in Fig. 1D. ' ’ _ Dan Kao forms a semiconductor device in the same manner as steps 1E to II. According to the present embodiment, a plurality of junctions are formed between the first layer of the substrate, the ++ conductor substrate 1 and the Ν+polycrystalline lanthanum: an undoped impurity is formed. In the case where the multi-layered layer of the sugar step shown in the figure is used as a diffusion source, the diffusion depth of the donor impurity toward the Shixi column la can be adjusted. For example, in the step shown in the first G11, on the first semiconductor substrate, it is expected that the N+ diffusion layer is formed by the condition that the second semiconductor soil is dried, such as the substrate 9 and the second hafnium oxide layer 8. Diffusion into a desired depth reading is effective in order to suppress the depth of the spurs. In order to spread the surface of the body, it is also possible to use p+ polycrystalline 矽. In the case of ~4 layers of 111 + which are not doped with donor impurities or acceptor substances, even if the impurities are not actively doped, a small amount of impurities are contained, and the effect of this embodiment is affected. (Thirteenth Embodiment) A method of manufacturing a semiconductor device according to a thirteenth embodiment of the present invention will be described below with reference to Figs. 14A, 14B, a leg diagram, and a (10) diagram. 323818 51 201242003 Fig. 14A is a diagram corresponding to the step shown in Fig. 1C of the first embodiment. Fig. 14B corresponds to the eleventh step (the steps shown in the figure. The other steps are specifically described below. The present embodiment is the same as the first embodiment. In the present embodiment, as shown in FIG. 14A, the surface of the first semiconductor substrate 1 corresponds to the periphery of the region 4a of the hole 4 of the first B-Fig. STI (Shall〇w Trench Isolation)

Oxidized stone layer 3a. Specifically, for example, first, the stellite semiconductor substrate 1 on the periphery of the region 4a is etched. Next, the ruthenium oxide layer is deposited by a CVD (Chemical Vapor Deposition) method, and the surface is smoothed by CMp (Chemical Mechanical Policing) to form the first oxidized layer 3a. This material (4) substrate 丨, which is a mask and is oriented in a vertical direction, is preferably formed in the form of a taper. Thereby, the bottom of the first oxygen-cut layer 3a can be positioned closer to the inner side of the #conductor substrate than the surface of the (four) conductor wire of the region 4a. Thereafter, a multi-junction (four) layer containing a donor impurity (corresponding to the polycrystalline germanium layer 5a of Fig. 1C) is formed. Thereafter, the enthalpy structure of 帛14B is formed by the same steps as those shown in Fig. 1D to Fig. If the 14th map of the 1st map is compared, the 14th and 1st maps have the following (1). In contrast, in the 14th map, r polycrystals grow in the _ ° 曰 layer 5aa, the metal layer 7aa In the first K-figure, the if polycrystalline litchi layer 5a and the metal layer 7 are formed in a convex shape upward. (2) The diffusion layer 6aa is formed as an inverse trapezoid with respect to N+ 323818 52 201242003 in the first step of 'the first oxidized stone layer 3'. In the 1K figure, the Ν+ diffusion layer 5a is along the first ruthenium oxide layer. The side surface of the layer 3 is formed in a trapezoidal shape. (3) With respect to the 14B, the gate conductor layers 11aa and 11bb are in contact with the first hafnium oxide layer 3a, and in the 1Kth diagram, the gate conductor layers 11a and 11b It is separated from the first ruthenium oxide layer 3. By the difference of (1) to (3), according to the present embodiment, the following advantages can be obtained. That is, (1) the N+ diffusion layer 6aa is derived from NT The polycrystalline germanium layer 5aa is formed by thermal diffusion, and is a layer in which no donor impurity is present before heat treatment of thermal diffusion, and may have the same layer as the polycrystalline germanium layer 111 of the 13th embodiment of the twelfth embodiment. Therefore, even if the polycrystalline germanium layer 111 is not used, the N+ diffusion layer 6aa whose diffusion layer ends are located at the lower positions of the gate conductor layers 11aa and 11bb can be formed. (2) Aligned with the position of the N+ diffusion layer 6aa with money When the formation of Shi Xizhu 1 a, even if the side of the 夕 la la is biased toward the inside of the N+ diffusion layer 6aa, The ruthenium oxide layer 3a belongs to the N+ diffusion layer having a thickness or is formed by atrophy toward the inner side, so that the ruthenium etching hardly reaches the metal layer 7aa (in the case of the 1Kth diagram, the la column la deviates from the N+ polycrystalline ruthenium layer 5a) In the position, since the N+ polycrystalline layer 5a is directly exposed, it is easily etched to the N+ polycrystalline germanium layer 5a and the metal layer 7) present thereunder. (3) Due to the gate conductor layers 11aa, 11bb and There is no need to form a gap between the first hafnium oxide layer 3a, so that a gate conductor wiring layer can be easily formed on the gate conductor layers 11aa, 11bb and the first hafnium oxide layer 3a. Also 323818 53 201242003, that is, the ικ图In order to reduce the leakage current, the position of the boundary surface of the PN junction of the N+ diffusion layer 6a and the P layer 矽 layer 30 must be formed inside the column la, so the first yttria layer 3 and the gate conductor layer must be made. 11a and lib are separated. Another manufacturing method of the semiconductor device according to the thirteenth embodiment will be described with reference to FIGS. 15A and 15B. Fig. 15A is a step corresponding to the first embodiment of the first embodiment. And Figure 15B corresponds to the one shown in Figure 1K. The other steps are the same as those in the first embodiment except for the case of the following description. In the present embodiment, as shown in Fig. 15A, the local Oxidation of Silicon, Shi Xi The local oxidation method forms the first oxide layer 3b in the peripheral region of the region 4a. In the LOCOS method, a thin oxide layer and a nitride layer are formed on the region 4a, followed by oxidation treatment. The ruthenium oxide layer 3b is formed. Thereafter, the N+ polycrystalline germanium layer 5bb is formed through the same steps as in the first panel. After φ, the steps shown in Fig. 15D to Fig. 1K are obtained, whereby the halogen structure shown in Fig. 15B can be obtained. If the 1Kth image and the 15th image are compared, the 15Bth image and the 1stKth image are different from the following two points. (1) With respect to Fig. 15B, the N+ diffusion layer 6aa surrounded by the first hafnium oxide layer 3a is formed into an inverse trapezoid as in the case of Fig. 14B, and in the 1Kth diagram, the N+ diffusion layer 5a is along the first The side surface of the oxygen stone layer 3 is formed in a trapezoidal shape. (2) With respect to Fig. 15B, the gate conductor layers 11aa, 11bb are in contact with the first hafnium oxide layer 3b, and in the 1Kth diagram, the gate conductor layers 11a, 323818 54 201242003 lib and the first hafnium oxide Layer 3 is separated. According to the difference between (1) and (3), the present embodiment has the following advantages. That is, (1) as in Fig. 14B, the r diffusion layer 6bb is formed by thermal diffusion from the r polycrystal layer 5bb, and is a layer in which no donor impurity exists before the heat treatment of thermal diffusion. Further, it has the same function as that of the polycrystalline germanium layer 111 of the 13th embodiment of the twelfth embodiment. Therefore, even if the polycrystalline germanium layer 111 is not used, the N+ diffusion layer 6bb in which the end portions of the diffusion layer are located below the gate conductor layers 11aa and 11bb can be formed. (2) Similarly to Fig. 14B, when the column la is formed by etching at the position of the N+ diffusion layer 6bb, even if the side surface of the column la is biased toward the inner side of the N+ diffusion layer 6bb, the first yttrium oxide layer 3b is also It belongs to the N+ diffusion layer 6bb having a thickness, or is formed by atrophy toward the inner side, so that it is difficult to reach the metal layer 7aa. (3) As in the case of Fig. 14B, since no gap is formed between the gate conductor layers 11aa, 11bb and the first tantalum oxide layer 3a, gates are formed above the gate conductor layers 11aa, 11bb and the first tantalum oxide 3b. The pole conductor layer wiring system is easy to handle. (Fourteenth Embodiment) A method of manufacturing a semiconductor device according to a fourteenth embodiment of the present invention will be described below with reference to Figs. 16A and 16B. The present embodiment is characterized in that two or more impurity regions are formed at the bottom of the mast. Fig. 16A shows a cross-sectional structural view corresponding to Fig. 1C. The 323818 55 201242003 one hole 4b1 and the second hole 4b2 are formed in a region of the first yttria layer 3b corresponding to the hole 4 of the first B-layer, and the surface of the P-type germanium semiconductor substrate 1 is exposed. Thereafter, an acceptor ion (in this case, a side B ion) is doped to the first region B1 containing the first hole 4b1 to form a P+ polycrystalline germanium layer 5b1, and a donor ion is formed. (At this time, an As (ion) ion) is doped to the N+ polycrystalline germanium layer 5b containing the second region B2 of the second hole. The doping of the acceptor ion and the donor ion is performed by doping the other ion after the ion doping of one of the ions is completed. • Next, as shown in Fig. 16B, a P+ polycrystalline germanium is formed on the P+ polycrystalline germanium layer 5b1, the N+ polycrystalline germanium layer 5b2, and the first germanium oxide layer 3b surrounding the periphery of the holes 4b1, 4b2. Layer 5bbl, metal layer 7b1 and N+ polycrystalline germanium layer 5bb2, metal layer 7b2. Next, the P+ diffusion layer 6b1 formed by thermal diffusion from the p+ polycrystalline germanium layer 5bbl and the thermal diffusion from the N+ polycrystalline germanium layer 5bb2 are formed by the same steps as those of the first to the first FIGS. The formed N+ diffusion φ layer 6b2 is formed at the bottom of the mast ia. In such a solid-state image sensing device, the P+ diffusion layer 6b1 and the P+ polycrystalline layer 5bbl function as the drain of the electric field effect transistor for signal readout, and the N+ diffusion layer 6b2 and the N+ polycrystal layer The layer 5bb2 functions as a drain for removing the electric signal stored in the photodiode composed of the N-type germanium layers 12a and 12b and the p-type germanium layer 30. Further, the p+ multi-crystallized layer 5bbl and the N+ polycrystalline germanium layer 5bb2 are connected to the metal layers 7b1 and 7b2, and are wired to an external circuit. Accordingly, the 323818 56 201242003 resistor formed on the signal readout line and the signal charge removal line formed from the pixel to the external circuit is reduced, thereby realizing high-speed driving of the solid-state image sensing device. Further, according to the present embodiment, in the same manner as the above-described step, two or more impurity regions can be formed at the bottom of Shi Xizhula. Further, the present embodiment can of course be applied to an embodiment other than the present embodiment, and for example, a method of manufacturing a semiconductor device in which a circuit element other than the optical image sensing device is formed on the mast. Further, in the first embodiment and the embodiment related to the i-th embodiment, the first hafnium oxide layer 3 is formed by thermal oxidation, positive electrode oxidation, or CVD (Chemical VaP〇rD printing). 1 yttrium oxide layer. The structure is not limited thereto, and may be constituted by a multi-layer structure with another insulating film such as a tantalum nitride (SiN) film. Further, the present invention is not limited to the embodiments described in the above-described second to twelfth embodiments, and various modifications are possible. In the above embodiment, the first semiconductor substrate 1 is of a p-type conductivity type. The first semiconductor substrate 1 may be an i-type (intrinsic type) belonging to the intrinsic φ semiconductor. Further, it is also possible to form an N-type conductivity type in accordance with the circuit elements formed on the first semiconductor substrate 1. Similarly, in the embodiment using the 3B, 4, 9C, and ith diagrams, the channel system of the P-channel MOS transistor is formed as an N-type 30 layer 30a, and N The channel of the channel type MOS transistor is formed as a P-type germanium layer 30, but all of them can be formed into a soil type stone which belongs to the intrinsic semiconductor. In the above-described embodiment, in the pixel of the solid-state image sensing device formed by Shi Xizhu, in the first embodiment, the N+ polycrystalline germanium layer 5a, gold 323818 57 201242003 is a layer 7, N+ diffusion. The layer 6a is set as an individual material layer, but may be heat treated according to the steps between the ID map and the 1K pattern, by the metal material of the metal layer 7 (Ni, W, etc.) and the N+ polycrystalline germanium layer 5a. Alternatively, all or a part of the metal layer 7, the N+ polycrystalline fine layer 5a, or the N+ diffusion layer 6a may be changed to a lithiation layer (NiSi, WSi, etc.) by reaction with a part of the N+ diffusion layer 6a. Furthermore, it can also be based on the 1st, 2nd, 3rd, 4th, 8th, 8th, 8th, 9th, 10th, 11th, and 12th. In the heat treatment performed in each step, the metal layer 7, the N+ polycrystalline layer 5a is reacted by the reaction of the metal material of the metal layer 7 with the N+ polycrystalline germanium layer 5a or with a portion of the N+ diffusion layer 6a. Or all or part of the N+ diffusion layer 6a is changed to a deuterated layer (NiSi, WSi, etc.). According to these, it is also possible to obtain a function of reducing the resistance value of a part of the signal line (electrical wiring). In the above embodiment, as shown in FIG. 1H, the separation layer 2 formed by injecting high-concentration hydrogen ion (H+) ions into a predetermined depth of the first semiconductor substrate 1 is heat-treated by 400 to 60 (TC). The first semiconductor substrate 1 is separated into upper and lower sides, and the first semiconductor substrate 1 is thinned to a predetermined thickness. The present invention is not limited thereto, and a porous layer may be formed in the separation layer 2 as shown, for example, in Non-Patent Document 3. In the method, the first semiconductor substrate 1 is thinned to a predetermined thickness. Alternatively, the first semiconductor substrate 1 may be separated into upper and lower layers. Further, the second semiconductor substrate 9 may be a semiconductor different from the germanium. For example, a compound semiconductor such as tantalum carbide (SiC), an insulator, or an organic resin body. According to this configuration, the circuit element formed on the first semiconductor substrate 1 can be held. 323818 58 201242003 Further, 'the second oxidized stone layer 8, The Oxide layer 2, 29, and 45 may be formed of a plurality of layers of other insulating films such as a tantalum nitride (SiN) film. Further, 'N+ polycrystalline layer 5a, 55a, p+ polycrystalline dream layer is used by Ion doping is formed. It is not limited to this, and it can also be formed by the thermal expansion of (4) into the doped polycrystalline layer of the impurity. Such a doped polycrystalline dream layer can also be tested in other embodiments. Furthermore, in Figure 1B, the polycrystalline germanium layer 5 is applied by CVD.

form. The structure is not limited thereto, and the polycrystal (4) 5 can also be formed by the growth of the crystal. At this time, the 'single crystal slab layer is grown on the first semiconductor, and the polycrystalline platy layer is formed on the oxygen cut layer 3 in accordance with the growth conditions. At this time, the single crystal (four) is a source of diffusion toward the donor or acceptor. Further, it may be carried out in such a manner that the (four) layer is not formed on the first oxygen cut layer 3 in accordance with the growth conditions (temperature) of the single crystal layer. The manner in which the (four) layer is uniquely formed on the first oxygen-cut layer 3 in this manner is also applicable to other embodiments of the present specification. Furthermore, in the first FIG. 1G, the second semiconductor substrate core composed of Shi Xi is bonded to the second oxide (4) 8 which is planarized by the CMP, but the oxide layer may be insulated or oxidized by CVD or CVD. After the layer is formed on the surface of the second semiconductor substrate 9, the second semiconductor substrate 9* the second layer 8 is bonded. Further, in Fig. 9C, the gate connection wiring 39 and the output terminal wiring line Vo are connected via the contact hole 41d. The present invention is not limited thereto, and the drain connection wiring 39 and the output terminal wiring Vo may be connected to the bottom of the contact hole 4U in contact with the N+ polycrystalline layer 55a on the gate connection wiring 39. 323818 59 201242003 constitutes '(4) The crystal hard layer 5 is small, so that the circuit element < high speed operation can also be realized. Further, in the case of 帛HK:, the drain connection metal wiring layer 42 (10) a) and the second-stage gate connection wiring 3 = contact holes are called. The heart is limited to this, but also holes,,,

The bottom portion is connected to the metal wiring layer 42 in a manner in which the (tetra) polycrystalline stone layer is in contact with each other. According to this configuration, since the resistance of the N+ polycrystalline rhyme is sufficiently small, the village realizes high-speed operation of the circuit components. Further, the gate conductor layers 11a, lib, 11c, lid, l6a, bumps, 16c, and 16d shown in Figs. 1L, 2, and 3B are as shown in the first aspect. The gate connection wirings 38 and 38a shown in the figure are formed by a vapor deposition method or a method (10). The structure is not limited thereto, and may be composed of a single layer or a plurality of metal layers of different types or as a polycrystalline layer doped with impurities or a multilayer of the polycrystalline layer and the metal layer. Further, the closed-end connecting wirings 38, 38a, 38b may be made of different materials depending on the (four)-channel type and the p-channel type. The use of different materials for the gate connection wirings 38, 38a, 38b in accordance with the N-channel type and the P-channel type is also applicable to other embodiments of the present specification. Furthermore, the two-stage CM〇s inverters shown in Fig. 10B and Fig. 1C can also be constructed as follows. That is, the P+ type 矽 layer 17b and the N+ type 矽 layer of each of the upper portions of the 夕 柱 column 4 〇 a ' of the p-channel type electroencephalogram body 37a and the column 4 〇 b of the N channel type MOS transistor 37 b 17a is connected to the output terminal wiring layer V〇ut of the first stage via the contact holes 41a and 41b formed in the yttrium oxide layer 45. Further, the metal layer 46b connected to the P+ polycrystalline layer 55b and the P+ diffusion layer 6b at the lower portion of the mast 40a of the p-channel type m〇s transistor 37a 323818 201242003 is used as the power terminal wiring layer Vdd. The metal layer 46a' connected to the N+ polycrystalline germanium layer 55a and the N+ diffusion layer 6a in the lower portion of the mast 40b of the N-channel type MOS transistor 37b is referred to as a ground terminal wiring layer Vss. Also in this configuration, the same effects as those shown in Fig. 10C can be obtained. Further, in the pixel structure shown in FIG. 1K, in order to perform self-integration of the gate conductor layers 11a and 11b and the N+ diffusion layer 6a serving as a signal line, after forming the gate conductor layers 11a and 11b, The ion doping of arsenic (As) or the deposition of the As-doped yttrium oxide layer as a diffusion source forms an n+-type germanium layer in the 矽枉la between the gate conductor layers 11a and 11b and the r diffusion layer 6a. Further, in the first embodiment of Fig. II, the first semiconductor substrate 1 is etched to the surface of the first ruthenium oxide layer 3 to form the masts la, but the processing can reach the first oxidation 7 The surface of layer 3 is stopped before =: line. For example, as shown in Fig. 14A, the pin is doped by doping: and the N-type 7 layer is formed on the non-side and the remaining 9 layers. Impurities, in the SGT shown in Fig. 2, in order to carry out the interpoles 6a, 16b and become the drain or the source... the diffusion layer h - 曰 can be doped by ions of As, or will be stacked As#, the integration 'is a diffusion source, and a gate layer is formed in the gate conductor layer 16a, 16b and the miscellaneous layer as the pillar layer la. A further example of the solid-state image sensing device formed by the i-th embodiment shown in FIG. 1K can be used in the N-type layer 12a of the method 323818. The outer peripheral portion of 12b forms a conductive layer which is transparent and electrically dipoles 518 π second yttria layer 201242003 10a, 10b to reflect the light beam. This prevents color mixing. Further, it is also possible to form a P+ type germanium layer connected to the P+ type germanium layer 13a in the masts la of the outer peripheral portions of the N type germanium layers 12a and 12b, thereby achieving low afterimage/low noise ( The structure of noise). In this way, the structure in which the function of the solid-state image sensing device is further improved can be appropriately formed in Shi Xizhu 1 a. Furthermore, the technical idea of the present invention is of course applicable not only to circuit elements of one embodiment on the same substrate, but also to circuit elements in which a plurality of embodiments are formed. Further, in the respective manufacturing steps of the respective embodiments, when the same configuration is manufactured, the order can be appropriately changed. Further, various embodiments and modifications can be made without departing from the spirit and scope of the invention. Furthermore, the above embodiments are intended to describe one embodiment of the invention, and are not intended to limit the scope of the invention. (Industrial Applicability) The present invention is applicable to a semiconductor device including a transistor in which a channel region is formed in a semiconductor having a columnar structure. [Fig. 1A] Fig. 1A is a cross-sectional view showing a method of manufacturing the solid-state image sensing device according to the first embodiment of the present invention. Fig. 1B is a plan view showing a method of manufacturing the solid-state image sensing device according to the first embodiment. Fig. 1C is a cross-sectional view for explaining a method of manufacturing the solid-state image sensing device of the first embodiment. Fig. 1D is a cross-sectional view for explaining a method of manufacturing the solid-state image sensing device of the first embodiment. 323818 62 201242003 Fig. 1E is a cross-sectional view for explaining a method of manufacturing the solid-state image sensing device of the i-th embodiment. Fig. 1F is a cross-sectional view for explaining a method of manufacturing the solid-state image sensing device of the first embodiment. Fig. 1G is a cross-sectional view for explaining a method of manufacturing the solid-state image sensing device of the first embodiment. Fig. 1H is a cross-sectional view for explaining a method of manufacturing the solid-state image sensing device of the first embodiment. Fig. 11 is a cross-sectional view for explaining a method of manufacturing the solid-state image sensing device of the first embodiment. Fig. 1J is a cross-sectional view for explaining a method of manufacturing the solid-state image sensing device of the first embodiment. Fig. 1K is a cross-sectional view for explaining a method of manufacturing the solid-state image sensing device of the first embodiment. Fig. 1L is a cross-sectional view for explaining a method of manufacturing the solid-state image sensing φ device of the first embodiment. Fig. 2 is a plan view showing the structure of the N-channel type SGT according to the second embodiment of the present invention. Fig. 3A is a cross-sectional view showing a method of forming an N-channel type SGT and a P-channel type SGT on the same substrate in the third embodiment of the present invention. Fig. 3B is a cross-sectional view showing a method of forming an N-channel type SGT and a P-channel type SGT on the same substrate in the third embodiment. Fig. 4 is a cross-sectional view showing a method of manufacturing a semiconductor device having a structure in which a plurality of SGTs are connected by a metal wiring layer according to a fourth embodiment of the present invention, 323818 63 201242003. Fig. 5A is a cross-sectional view showing a method of forming a resistor in a semiconductor device according to a fifth embodiment of the present invention. Fig. 5B is a cross-sectional view for explaining a method of forming a resistor in a semiconductor device according to the fifth embodiment. Fig. 5C is a cross-sectional view for explaining a method of forming a resistor in a semiconductor device according to the fifth embodiment. Fig. 6A is a cross-sectional view showing a method of forming a capacitance type into a semiconductor by the sixth embodiment of the present invention. Fig. 6B is a cross-sectional view for explaining a method of forming a capacitor in a semiconductor device according to the sixth embodiment. Fig. 6C is a cross-sectional view for explaining a method of forming a capacitor in a semiconductor device according to the sixth embodiment. Fig. 7A is a plan view showing a method of forming a capacitor in a semiconductor device according to a seventh embodiment of the present invention. Φ Fig. 7B is a cross-sectional view for explaining a method of forming a capacitor in a semiconductor device according to the seventh embodiment. Fig. 8A is a cross-sectional view showing a method of forming a diode in a semiconductor device according to an eighth embodiment of the present invention. Fig. 8B is a cross-sectional view for explaining a method of forming a diode in a semiconductor device according to the eighth embodiment. Fig. 8C is a cross-sectional view showing a method of forming a p I n diode in a semiconductor device in a modification of the eighth embodiment. Fig. 9A is a circuit diagram for explaining a phase circuit of a CMOS reverse 323818 64 201242003 according to a ninth embodiment of the present invention. Fig. 9B is a circuit plan layout diagram for explaining a CMOS inverter circuit of the ninth embodiment. Fig. 9C is a cross-sectional view showing a method of forming a CMOS inverter circuit in a semiconductor device according to the ninth embodiment. Fig. 10A is a circuit diagram showing a CMOS inverter circuit constructed in the second stage of the tenth embodiment of the present invention. Fig. 10B is a circuit plan layout diagram of the Φ CMOS inverter circuit for explaining the two-stage structure of the tenth embodiment. Fig. 10C is a cross-sectional view showing a method of forming a CMOS inverter circuit having a two-stage structure according to the tenth embodiment. Fig. 11A is a cross-sectional view showing a method for improving the positional accuracy of the mast of the eleventh embodiment of the present invention. Fig. 11B is a cross-sectional view showing a method of forming a mask alignment mark on a semiconductor substrate in the eleventh embodiment. Fig. 12 is a cross-sectional view showing a manufacturing method for improving the positional accuracy of the mast in the modification of the eleventh embodiment. Figure 13A is a cross-sectional view showing a method of manufacturing a semiconductor device according to a twelfth embodiment of the present invention. Fig. 13B is a cross-sectional view for explaining a method of manufacturing the semiconductor device of the twelfth embodiment. Figure 14A is a cross-sectional view showing a method of manufacturing a semiconductor device according to a thirteenth embodiment of the present invention. Fig. 14B is a cross-sectional view showing a manufacturing method for explaining a semiconductor device of the thirteenth embodiment, 323818 65 201242003. Fig. 15A is a cross-sectional view for explaining a method of manufacturing the semiconductor device of the thirteenth embodiment. Fig. 15B is a cross-sectional view for explaining a method of manufacturing the semiconductor device of the thirteenth embodiment. Fig. 16A is a cross-sectional view for explaining a method of manufacturing the semiconductor device of the thirteenth embodiment. Fig. 16B is a cross-sectional view showing a method of manufacturing the semiconductor device of the thirteenth embodiment. Fig. 16C is a cross-sectional view for explaining a method of manufacturing the semiconductor device of the thirteenth embodiment. Fig. 17 is a cross-sectional view showing the structure of a pixel of a solid-state image sensing device of a conventional example. Fig. 18A is a cross-sectional view showing a pixel in which a solid-state image sensing device of a conventional example is operated at a high speed. % Fig. 18B is a view for explaining the next steps of the semiconductor substrate for obtaining a high-speed operation of the solid-state image sensing device of the conventional example. Figure 19 is a cross-sectional view of a pixel having a conventional SGT. [Main component symbol description] 1 First semiconductor substrate h, lb, 40a, 40b, 40c, 40d

In N channel type SGT formation region lp P channel type SGT formation region 323818 66 201242003 2 Separation layer 3, 3a, 3b, 29, 101a, 101b First hafnium oxide layer 4 Hole 5, 23 Polycrystalline hafnium layer 5a, 5b, 5aa , 5b2, 5bb2, 23a, 23b, 51, 55a, 104 N+ polycrystalline germanium layer 5bl, 5bbl, 55b P+ polycrystalline germanium layer 6a, 6aa, 6ab, 6b2, 6bb N+ diffusion layer 6b, 6b 102 102 P+ diffusion layer 7, 7a, 7b, 7M, 7b2, 7aa, 7bb, 26a, 26b, 28, 32, 46a, 59, 105 metal layers 7a, 7b, 7aa, 7bb first connection metal layer 8 second hafnium oxide layer 9 Two semiconductor substrates 10a, 10b, 10c, 10d third oxide layer 11a, lib, 11c, lid, llaa, llbb, 16a, 16b, 16c, 16d, 16aa, 16ab, 16ba, 16bb, 54a, 54b gate conductor layer ^ 12a, 12b, 12c, 12d N-type germanium layer 13a, 13b, 17b, 31, 56 P+ type germanium layer 14a ' 14b ' 14c ' 14d pixel select metal wiring layer 15a, 15b, 15c, 15d, 71 gate insulating Layers 17a, 51 N+ type layer 18a, 18b, 22a, 22b, 22c, 24a, 24b, 26a, 26b, 35, 42, 109 metal wiring layers 20, 29, 33, 43, 45, 62, 101a, 101b , 10 3, 107 yttrium oxide layer 21c, 34, 41a, 41b, 41c, 41d, 41e, 41f, 75, 108 contact hole 323818 67 201242003 27 capacitor yttrium oxide layer 30, 52 P-type enamel layer 30a, 58a, 58b N-type 矽Layer 3〇bi type germanium layer 37a, 37c P channel type MOS transistor 37b ' 37d N channel type MOS transistor 38, 38a, 38b Gate connection wiring 39, 39a, 39b Dip connection wiring

47a 47b 49a 50 53a, 60 mask alignment mark formation region circuit formation region 48 mark metal layer 49b mask alignment hole 50a 53b insulating film 57a, 57b substrate 61, 64 ruthenium oxide layer removal region mark polycrystalline dream layer transparent insulation Layered germanium selection line semiconductor substrate 66 buried oxide film substrate 67 planar stone film 68 PM0S columnar layer 69, 70 P+ type stone diffusion layer 72 gate electrode 73 tantalum nitride (SiN) film

74 Oxide oxide (Si〇2) film 76 Source metal wiring 1 Tantalum capacitor formation region 106 (doped with donor impurities) N+ polycrystalline germanium layer 110 Columnar semiconductor 111 (undoped donor impurity or acceptor Polycrystalline layer

Vi input terminal wiring (layer)

Vdd power terminal wiring (layer)

Vss ground terminal wiring (layer)

Vo, Vout output terminal wiring (layer) 323818 68

Claims (1)

201242003 VII. Patent application scope: 1. A method for manufacturing a semiconductor device, comprising: forming a first insulating layer on a semi-conducting county plate to remove a first-insulating layer on the above-mentioned dare region to form an insulating periphery toward a thickness direction The second insulating layer forming/removing step of removing the semi-conducting plate in the front plate of the first knife-1 edge guide plate is formed; the body layer forming step of the domain is to cover at least the predetermined area=quality: the first == Forming a bulk conductor layer forming step on the substrate, forming a conductive layer forming step on the first semiconductor layer to form the conductor layer and the first semiconductor layer to cover the conductor formed into the predetermined shape Forming a second insulating layer in a manner of a layer and a first semiconductor layer; and performing a flattening step of affixing a surface of the second insulating layer to the flattened second insulating layer; a step of thinning the semiconductor substrate to a predetermined thick columnar semiconductor forming step on the first semiconductor layer, 323818 1 20 1242003 forming a columnar semiconductor having a right-handed and columnar structure from the semiconductor substrate; a circuit element forming step, the circuit element; and, (4) forming a first semiconductor region forming step, at least in the foregoing After the formation step of the body layer, the white 4 person senses #r, f筮g 3 narrate the donor impurity or the acceptor impurity The -th conductor layer diffuses the impurity to form the first semiconductor region in the columnar semiconductor. 2·=Please refer to the manufacturing method of the semiconductor device according to Item 1, and the step of forming the circuit 7L includes: forming a third insulating layer on the outer peripheral portion of the columnar semiconductor, and forming an insulating layer in the month a step of forming a gate conductor layer on the outer peripheral portion, wherein the upper portion of the conductor layer is the columnar semiconductor a step of forming a fourth semiconductor region of the same conductivity type as the first semiconductor region, and forming a first description of the upper portion of the third insulating layer The semiconductor region is a step of a third semiconductor region of opposite conductivity type. The method for manufacturing a semiconductor device according to Item 1, wherein the circuit element forming step includes: 4. forming a third insulating layer on a peripheral portion of the columnar semiconductor, and describing the third insulating layer a step of forming a gate conductor layer on the outer periphery of the insulating layer; in the form of 323818 2 201242003 and forming: the step region of the upper portion of the third insulating layer of the conductor is the fifth half of the same conductivity type: patent! The method for manufacturing a semiconductor device according to the above item, wherein the circuit element forming step comprises: Conductor::: A step of forming a sixth semiconductor region of the opposite conductivity type from the upper portion of the columnar semiconductor. The method of manufacturing the semiconductor device according to the first aspect of the invention, wherein the first semiconductor layer forming step comprises: A forming in the same layer as the first semiconductor The step of functioning as a second semiconductor layer of the power. 6' If you apply for a special! The method of manufacturing a semiconductor device according to any one of the preceding claims, wherein the semiconductor layer forming step includes forming a predetermined region on the first semiconductor layer functioning as a capacitor electrode as a capacitor The step of forming an insulating film for the insulating film; the step of forming the conductor layer includes the step of forming a conductor layer functioning as a capacitor electrode together with the first semiconductor layer on the (IV) insulating film. The method of manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the first insulating layer forming/removing step includes 'on the semiconductor substrate and the first Forming a fourth insulating layer together with an insulating layer, and forming a fifth insulating layer which is thinner than the fourth insulating layer and functions as a capacitor insulating film in a predetermined capacitance forming region; the conductor layer is formed The step of forming a conductor layer functioning as a capacitor electrode on the fifth insulating layer; the first or second insulating layer forming/removing step includes forming a donor impurity or a dopant in the capacitor formation region A capacitance forming step of a bulk impurity and an impurity layer functioning as a capacitor electrode. The method of manufacturing a semiconductor device according to any one of claims 1 to 7, further comprising: a mask alignment mark formation region in which a mask alignment mark formation region is set on the semiconductor substrate a step of forming a mask alignment hole in the mask alignment mark forming region, and exposing at least one of the insulating layer removal region, the first insulating layer, and the conductor layer; a mask alignment forming mark forming step of the mask alignment mark formed by at least one of the insulating layer removal region, the first insulating layer, and the conductive layer; and the mask The alignment mark is the reference for the mask alignment step of the mask alignment of the mask. 9. The method for fabricating a semiconductor device according to claim 8, further comprising: 323818 4 201242003, the step of embedding the transparent insulator in the mask alignment hole; and in the mask alignment mark forming step, Forming, by the transparent insulator, a mask alignment mark formed by at least one of the insulating layer removal region, the first insulating layer, and the conductor layer; in the mask alignment step, the aforementioned The mask alignment marks are used as a reference for the mask alignment of the mask. The method of manufacturing a semiconductor device according to any one of claims 1 to 9, further comprising: the first or second insulating layer forming/removing step and the first semiconductor layer forming step The step of forming the second semiconductor layer not doped with the donor impurity and the acceptor impurity is formed to cover the removed region of the insulating layer. A semiconductor device manufactured by the method of manufacturing a semiconductor device according to claim 2, wherein the columnar semiconductor system includes the first semiconductor region formed on the first semiconductor region a semiconductor region is a second semiconductor region formed by an opposite conductivity type semiconductor or an intrinsic semiconductor; and the second semiconductor region and the fourth semiconductor region are formed to store a signal charge generated by irradiating electromagnetic energy waves a polar body; a junction electric field effect transistor; wherein the diode functions as a gate, and one of the first semiconductor region and the third semiconductor region serves as a source' Each of the functions of the 323818 5 201242003 is configured to take out a current flowing through the channel formed in the second semiconductor region and changing according to the amount of signal charge stored in the diode; and forming a signal a charge removing means which functions by using the gate conductor layer as a gate and The MOS transistor in which one of the first semiconductor region and the fourth semiconductor region functions as a source and the other functions as a drain, and a voltage is applied to the gate conductor layer, thereby being stored in the diode The signal charge is removed from the aforementioned first semiconductor region. A semiconductor device according to the third aspect of the invention, wherein the columnar semiconductor system is provided on the first semiconductor region; The first semiconductor region is a second semiconductor region composed of an opposite conductivity type or an intrinsic semiconductor; and a MOS transistor is formed, wherein the gate conductor layer functions as a gate, and the first semiconductor region and the foregoing One of the fifth semiconductor regions functions as a source, and the other functions as a drain. A semiconductor device according to the fourth aspect of the invention, wherein the columnar semiconductor is provided between the first semiconductor region and the sixth semiconductor region. A second semiconductor region formed of an opposite conductivity type or an intrinsic semiconductor from the first semiconductor region; and a diode formed by the second semiconductor region and the sixth semiconductor region 323818 6 201242003. A semiconductor device, which is produced by the method for manufacturing a semiconductor device according to the first or third aspect of the invention, wherein: the plurality of columns are formed on the first/semiconductor layer Semiconductor The double-branched columnar semiconductor system is composed of a plurality of first columnar semiconductors doped with the # impurity in the first semiconductor= domain, and a plurality of first impurity semiconductors doped with the donor impurity in the first semi-conductive region The second braided semiconductor is composed of. A semiconductor device manufactured by the method of manufacturing a semiconductor device according to any one of the preceding claims, wherein: the plurality of semiconductor layers are formed on the semiconductor layer And the two or one of the plurality of the first semiconductor regions and the plurality of the conductive layers are connected to each other in the plurality of columnar semiconductors. A semiconductor device, which is produced by the method for fabricating a semiconductor device according to claim 3, wherein: the plurality of columnar semiconductors are formed on the first semiconductor layer; The columnar semiconductor system includes: a second semiconductor d-domain, (4) a semiconductor electrically formed on the first semiconductor region opposite to the first semiconductor region, or an intrinsic 323818 7 201242003 semiconductor; a fifth semiconductor region The second semiconductor region and the second insulating layer are formed on the outer periphery of the second semiconductor. The gate conductor layer is formed on the outer peripheral portion of the third insulating layer and is formed with a MOS transistor. The gate conductor layer functions as a gate, and functions as a source of the semiconductor region and the semiconductor region of the fifth semiconductor region, and the other function is not functioning; and, ... The first semiconductor layer is formed in a continuous manner throughout the plurality of columnar halves, and the foregoing is formed in a connected manner. The first semiconductor layer is connected to a wiring layer for connection to an external circuit via a contact hole formed in the insulating layer. 17. A semiconductor device comprising: a method of manufacturing a semiconductor device according to claim 3, wherein a plurality of the columnar semiconductors are formed on the first semiconductor layer; Each of the columnar semiconductor systems includes: the second semiconductor region ′ is formed of a semiconductor or an intrinsic semiconductor formed on the first semiconductor region and opposite to the first semiconductor region; and the fifth semiconductor region is formed in the foregoing a second semiconductor region; 323818 8 201242003 a third insulating layer formed on an outer peripheral portion of the second semiconductor region; and a gate conductor layer formed on an outer peripheral portion of the third insulating layer; and a MOS is formed The transistor functions as a gate of the gate conductor layer, and functions as one of the first semiconductor region and the fifth semiconductor region as a source, and functions as a drain as the other; and The first semiconductor layer is formed to be continuously connected over the plurality of columnar semiconductors, and the foregoing A semiconductor layer formed by a line through the contact hole of the insulating layer are connected to an interconnection layer for connecting the gate of the transistor to a predetermined. 18. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating layer forming/removing step comprises: etching a semiconductor substrate on a periphery of a region in which the columnar semiconductor is formed. a substrate etching step; a step of forming the first insulating layer on the semiconductor substrate over the etched region; and the semiconductor substrate exposed by the etching and the first insulating layer on the periphery of the exposed semiconductor substrate Forming the aforementioned first semiconductor layer. 19. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating layer forming/removing step comprises: 323818 9 201242003 forming a periphery of the semiconductor substrate in a region of the columnar semiconductor The step of selectively oxidizing to form a selective oxide layer as the foregoing first insulating layer. The method of manufacturing a semiconductor device according to claim 1, further comprising: forming at least two regions of the first insulating layer separated from each other to form the semiconductor in a region of the columnar semiconductor a step of forming on the substrate; and forming a plurality of the foregoing, surrounded by the first insulating layer of the mutually separated regions, and separated from each other on the surface of the exposed semiconductor substrate and doped with a donor or a receptor a first semiconductor layer, and a step of connecting to the aforementioned semiconductor layer of the first semiconductor layer. 323818 10