201240084 六、發明說明： 【發明所屬之技術領域】 ，尤指一種具有金屬閘極 本發明疋關於一種半導體元件 之半導體元件及其製作方法。 【先前技術】201240084 VI. Description of the Invention: The technical field to which the invention pertains is, in particular, a semiconductor element having a metal gate and a method of fabricating the same. [Prior Art]
PiC著半導體7L件尺寸持續微縮，傳統方法中利用降低閘 極介f層”低二氧化⑦層厚度，以糾最佳化目的之 方法’係面臨到因電子的穿隧效應（tunneling effect)而導致漏 電抓過大的物理限制。為了有效延展邏輯元件的世代演進， 问，I電吊數(以下簡稱為high K)材料因具有可有效降低物理 極限尽度並且在;I：目同的等效氧化厚度(equivalent⑽此 thickness’ α下簡稱為Ε〇τ)下，有效降低漏電流並達成等效 電谷以控制通道開關等優點，而被用以取代傳統二氧化 或氮氧化矽層作為閘極介電層。 9 而傳統的閘極材料多晶矽則面臨硼穿透(b〇r〇n penetration)效應，導致元件效能降低等問題；且多晶矽閘。 更遭遇難以避免的空乏效應（depletion effect)，使得等致的° 極介電層厚度增加、閘極電容值下降，進而導致元件驅動Z 力的衰退等困境。針對此問題，半導體業界更提出以新的％ 極材料，例如利用具有功函數^〇1^ functi〇n)金屬層的金屬 201240084 閘極來取代傳統的多晶矽閘極，用以作為匹配High-K閘極 介電層的控制電極。 然而，即使利用high-K閘極介電層取代傳統二氧化矽 或氮氧化矽閘極介電層，並以具有匹配功函數之金屬閘極取 代傳統多晶矽閘極，如何持續地增加半導體元件效能及確保 其可靠度仍為半導體業者所欲解決的問題。 【發明内容】 因此本發明是揭露一種具有金屬閘極之半導體元件及 其製作方法，以改良現有製程中所遇到的瓶頸。 本發明較佳實施例是揭露一種半導體元件，其包含一基 底、一閘極結構設於基底上以及一第一遮蓋層設於閘極結構 之側壁表面。其中閘極結構包含一高介電常數介電層，且第 一遮蓋層係為一無氧(oxygen-free)遮蓋層。 本發明另一實施例是揭露一種製作半導體元件的方 法，其包含有下列步驟。首先提供一基底，然後形成一閘極 結構於基底表面，且閘極結構包含一高介電常數介電層。接 著形成一第一遮蓋層於閘極結構之側壁，再形成一輕摻雜汲 極於閘極兩側之基底中。 4 201240084 【實施方式】 s青參照第1圖至第6圖，第1圖至第6圖為本發明較佳 實施例製作一具有金屬閘極之半導體元件示意圖，且本較佳 實施例採用後閘極(gate-first)製程搭配前高介電常數介電層 (high-Kfirst)製程。如第1圖所示，首先提供一基底1〇〇，例 如一矽基底或一絕緣層上覆石夕（silicon-on-insulator，SOI)基 底專’且基底100内形成有複數個用來提供電性絕緣的淺溝 隔離（shallow trench isolation, STI) 102。 接著形成一由氧化物、氮化物等之介電材料所構成的閘 極絕緣層104在基底100表面’用來當作一介質層（interfadal layer) ’並再依序形成一由高介電常數介電層ι〇6、一多晶石夕 層108以及一硬遮罩11〇所構成的堆疊薄膜在閘極絕緣層 104上。其中，多晶石夕層1 〇8是用來做為一犧牲層’其亦可 由不具有任何摻質（undoped)的多晶矽材料、具有N+摻質的 多晶矽材料所構成或非晶矽材料所構成。 在本實施例中，高介電常數介電層1〇6可以是一層或多 層的結構，其介電常數大致大於2〇。高介電常數介電層1〇6 可以是一金屬氧化物層，例如一稀土金屬氧化物層，且可選 自由氧化铪(hafnium oxide，Hf〇2)、矽酸铪氧化合*(hafnium silicon oxide，HfSiO)、矽酸铪氮氧化合物（hafnium siHc〇n oxynitride，HfSiON)、氧化鋁（aluminum oxide，A10)、氧化鑭 201240084 (lanthanum oxide，La2〇3)、铭酸鋼（lanthanum aluminum oxide， LaAlO)、氧化钽(tantalum oxide，Ta2〇3)、氧化錯(zirconium oxide，Zr〇2)、石夕酸錯氧化合物（zirconium silicon oxide， ZrSiO)、錯酸給(hafnium zirconium oxide, HfZrO)、錄絲組氧 4匕物（strontium bismuth tantalate，SrBi2Ta209, SBT)、錯鈦酸 鉛（lead zirconate titanate，PbZrxTii.xOh PZT)以及鈦酸鋇總 (barium strontium titanate，BaxSn.xTiOh BST)等所組成的群 組。硬遮罩110則由二氧化矽（Si〇2)、氮化矽（siN)、碳化矽 (SiC)或氮氧化矽（SiON)所構成。 接著如第2圖所示，形成一圖案化光阻層（圖未示）在硬 遮罩110上，並利用圖案化光阻層當作遮罩進行一圖案轉移 製程，以單次姓刻或逐次姓刻步驟，去除部分的硬遮罩11〇、 多晶矽層108、高介電常數介電層106及閘極絕緣層1〇4， 並剝除此圖案化光阻層，以於基底上形成一閘極結構112。 然後覆蓋一由氮化矽所構成的第一遮蓋層114於閘極結 構112側壁及基底1〇〇表面，並進行一輕摻雜離子佈植，將 N型或p型摻質植入閘極結構112兩側的基底1〇〇中，以形 成一輕摻雜汲極116。 如第3圖所示，依序形成一由氧化矽所構成的第二遮蓋 層118及一由氮化矽所構成的第三遮蓋層12〇於基底1〇〇上 6 201240084 並覆蓋閘極結構112及第* 二遮蓋層118車交佳由氧化遮蓋層114。在本實施例中，第 蓋層114具有不同餘刻率。斤構成’且與設於其下的第一遮 隨後如第4圖所示，弁淮 7L運仃—乾蝕刻製程去除 遮蓋層120並停在第二遮蓋屛 ^ 刀弟一 i盂層U8表面，接著進行另一乾 刻製程去除部分第二遮蓋層118及第一遮蓋層m，最 進行-濕式清洗製程去除上賴刻製賴㈣合物以 以及一由剩餘第三遮蓋 於問極結構U2側壁形成一由L型第一遮蓋層所構成的第一 側壁子122、一 L型第二遮蓋層118 層120所構成的第二側壁子124。 然而，除了上述步驟，本發明另一實施例又可選擇先進 行一乾蝕刻製程去除部分第三遮蓋層12〇並停在第二遮蓋層 118表面，然後進行另一乾蝕刻製程去除部分第二遮蓋層 118，最後再以一濕式清洗製程去除部分第一遮蓋層114，以 製作上述的L型第一側壁子122、L型第二遮蓋層118及第 二側壁子124。 然後可進行一離子佈植，將N型或p型摻質植入上述側 壁子兩側的基底中以形成一源極/汲極區域126。在本較佳實 施例中，亦可結合選擇性應力系統(selective strainscheme， SSS)等製私’例如利用選擇性蟲晶成長（seiectiVe epitaxial 201240084 growth, SEG)方法來製作源極及極區域 。例如，當源極/汲極 區域需為P 極時，可利用包含有錯化梦(8心） 之蠢晶層形成源極你極區域；而當源極/練區域需為- N 型源極/波極時，則可湘包含碳化邦iC)有之i晶層形成 源極/汲極區域。此外’源極/沒極區域126表面另分別形成 有一金屬梦化物（圖未示）。形成上述㈣之後，可於基底 100上依序形成一接觸洞触刻停止層（c〇ntact etch stop 1叮打， CESL) 128 與一内層介電（inter_iayer dielectric，ile>m 13〇。 由於形成上述元件之步驟亦為熟習該項技藝者所知，故於此 亦不再贅述。 如第5圖所示，接下來進行一平坦化製程，例如利用一 化學機械研磨製程移除部分ILD層130、部分CESL 128與 圖案化硬遮罩11 〇，直至暴露出多晶石夕層1 〇8。隨後更利用 一適合之蝕刻製程移除多晶矽層108，而形成一閘極溝渠 132。此時高介電常數介電層106可作為一蝕刻停止層，用 以保護下方的閘極絕緣層104不受钮刻製程的之影響。由於 上述平坦化製程與蝕刻製程亦為熟習該項技藝者所知者，故 於此亦不再贅述。 然後如第6圖所示，於閘極溝渠132内依序形成一功函 數金屬層134 ' —阻障層136以及一用以填滿閘極溝渠132 的低阻抗金屬層138。其中，功函數金屬層134可視製程需 8 201240084 求包含P塑功函數金屬或N型功函數金屬。最後，再藉由一 平坦化製程移除多餘的低阻抗金屬層138、阻障層136與功 函數金屬層134，完成金屬閘極140與具有金屬閘極140之 半導體元件之製作。 請再參照第7圖至第12圖，第7圖至第12圖為本發明 另一實施例製作一具有金屬閘極之半導體元件示意圖’且本 實施例同樣採用後閘極(gate_first)製程搭配前高介電常數介 電層（high-K first)製程。 如第7圖所示，首先提供一基底2〇〇，例如一石夕基底或 一絕緣層上覆矽基底等，且基底200内形成有複數個用來提 供電性隔離的淺溝絕緣(shallow trench isolation，STI)202。 接著形成一由氧化物、氮化物等之介電材料所構成的 極絕緣層204在基底200表面，當作一介質層⑽抓咖 layer)，並再依序形成一由高介電常數介電層2〇6、一 β 208 p； Tt 义日日石夕 曰以及-硬遮罩210所構成的堆疊薄膜在間極絕❹ 上。其中，乡晶矽層208是用來做為 θ 由不具有任何摻質(u—ed)的多以材料、=亦可 多晶石夕材料所構成或非晶石夕材料所構成。4 dN+推質的 如第8圖所示’形成一㈣化心層⑽未示)在硬遮罩 201240084 210上，並利用圖案化光阻層當作遮罩進行-圖荦轉移製 程，以早次蝕刻或逐次蝕刻步驟’去除部分的硬遮罩則、 多副通、高介電常數介電層2〇6及 並剝除此圖案化光阻層，以於其念L…丄 、黍原上形成一閘極結構212。 然後覆蓋-聽切所構成㈣1 極結構212側壁及基底200表 層（圖未不）於閘 並進仃一回姓玄彳锻短，去 除部分設於基底200表面的第 #八程去 〇1/1 遮盍層以於閘極結構212侧 壁形成一第一側壁子214。接荽、A χ 進仃一輕摻雜離子佈植，將 Ν型或Ρ型摻質植入閘極結構 雕卞驟 再212兩側的基底200中，以形 成一輕摻雜汲極216。然後形忐 成一由氧化矽所構成的第二遮 蓋層218並覆蓋閘極結構212、# 第一側壁子214及基底200 表面。 隨後如第9圖所示，形忐 由氮化秒所構成的第·•遮蓋 層220於基底200上並覆蓋笛The size of the 7L component of the semiconductor is continuously reduced by the PiC. In the conventional method, the method of reducing the thickness of the gate layer of the gate layer of "lower than 7 layers of silicon dioxide for optimization purposes" is faced with the tunneling effect of electrons. Leading to leakage and grasping large physical limitations. In order to effectively extend the evolution of logic components, Q, I electric crane number (hereinafter referred to as high K) material has the ability to effectively reduce the physical limit and is in the same; Oxidation thickness (equivalent (10) this thickness' α is abbreviated as Ε〇τ), effectively reducing the leakage current and achieving the equivalent electric valley to control the channel switch, etc., and is used to replace the traditional dioxide or oxynitride layer as the gate Dielectric layer. 9 The traditional gate material polysilicon is faced with boron penetration (b〇r〇n penetration), which leads to problems such as lower component efficiency; and polycrystalline gates. It encounters an inevitable depletion effect. This leads to an increase in the thickness of the equipolar dielectric layer and a decrease in the gate capacitance value, which leads to the dilemma of the component driving Z-force. In response to this problem, the semiconductor industry has proposed The % pole material, for example, uses a metal 201240084 gate with a metal function of the work function to replace the conventional polysilicon gate as a control electrode for matching the High-K gate dielectric layer. Even if the high-K gate dielectric layer is used to replace the conventional germanium dioxide or yttria gate dielectric layer, and the metal gate with matching work function is substituted for the conventional polysilicon gate, how to continuously increase the efficiency of the semiconductor device and It is a problem that the reliability of the semiconductor industry is still solved by the semiconductor industry. SUMMARY OF THE INVENTION The present invention therefore discloses a semiconductor device having a metal gate and a method of fabricating the same to improve the bottleneck encountered in the prior art process. A preferred embodiment discloses a semiconductor device including a substrate, a gate structure disposed on the substrate, and a first capping layer disposed on a sidewall surface of the gate structure. The gate structure includes a high-k dielectric layer And the first cover layer is an oxygen-free cover layer. Another embodiment of the invention discloses a method for fabricating a semiconductor device, which includes The following steps: firstly providing a substrate, then forming a gate structure on the surface of the substrate, and the gate structure comprises a high-k dielectric layer. Then forming a first mask layer on the sidewall of the gate structure, forming a light The doping is performed on the substrate on both sides of the gate. 4 201240084 [Embodiment] Referring to FIGS. 1 to 6 , FIGS. 1 to 6 are diagrams showing a metal gate in accordance with a preferred embodiment of the present invention. A schematic diagram of a semiconductor device, and the preferred embodiment uses a gate-first process in conjunction with a high-kfirst process. As shown in FIG. 1, a substrate is first provided. For example, a silicon-on-insulator (SOI) substrate is formed on a substrate or an insulating layer, and a plurality of shallow trench isolation (STI) for providing electrical insulation is formed in the substrate 100. ) 102. Then, a gate insulating layer 104 composed of a dielectric material such as an oxide or a nitride is formed on the surface of the substrate 100 to serve as an interfadal layer and sequentially form a high dielectric constant. A stacked film of a dielectric layer ι6, a polycrystalline layer 108, and a hard mask 11 is formed on the gate insulating layer 104. Wherein, the polycrystalline layer 1 〇 8 is used as a sacrificial layer 'which may also be composed of a polycrystalline germanium material having no undoped, a polycrystalline germanium material having an N+ dopant, or an amorphous germanium material. . In the present embodiment, the high-k dielectric layer 1〇6 may be one or more layers having a dielectric constant substantially greater than 2 Å. The high-k dielectric layer 1〇6 may be a metal oxide layer, such as a rare earth metal oxide layer, and optionally free hafnium oxide (Hf〇2), hafnium silicon oxide* (hafnium silicon) Oxide, HfSiO), hafnium siHc〇n oxynitride (HfSiON), aluminum oxide (A10), ruthenium oxide 201240084 (lanthanum oxide, La2〇3), lanthanum aluminum oxide (lanthanum aluminum oxide, LaAlO), tantalum oxide (Ta2〇3), zirconium oxide (Zr〇2), zirconium silicon oxide (ZrSiO), hafnium zirconium oxide (HfZrO), Consortium bismuth tantalate (SrBi2Ta209, SBT), lead zirconate titanate (PbZrxTii.xOh PZT) and barium strontium titanate (BaxSn.xTiOh BST) Group. The hard mask 110 is composed of germanium dioxide (Si〇2), tantalum nitride (siN), tantalum carbide (SiC) or hafnium oxynitride (SiON). Then, as shown in FIG. 2, a patterned photoresist layer (not shown) is formed on the hard mask 110, and a patterned transfer process is performed using the patterned photoresist layer as a mask, with a single last name or Step by step, removing part of the hard mask 11 〇, the polysilicon layer 108, the high-k dielectric layer 106 and the gate insulating layer 1 〇 4, and stripping the patterned photoresist layer to form on the substrate A gate structure 112. Then, a first capping layer 114 made of tantalum nitride is coated on the sidewalls of the gate structure 112 and the surface of the substrate 1 and a lightly doped ion implantation is performed to implant the N-type or p-type dopant into the gate. The substrate 1 on both sides of the structure 112 is formed to form a lightly doped drain 116. As shown in FIG. 3, a second capping layer 118 made of yttrium oxide and a third capping layer 12 made of tantalum nitride are sequentially formed on the substrate 1 20126 201240084 and cover the gate structure. 112 and the second cover layer 118 are provided with an oxidized cover layer 114. In the present embodiment, the first cap layer 114 has a different residual ratio. The jin constitutes 'and the first cover disposed under it as shown in Fig. 4, the 弁 7 7L 仃 仃 dry etching process removes the cover layer 120 and stops at the surface of the second cover 屛 ^ 弟 一 盂 U layer U8 Then, another dry etching process is performed to remove a portion of the second covering layer 118 and the first covering layer m, and the most wet-cleaning process is performed to remove the upper layer and the first layer is covered by the remaining third layer. The sidewall defines a second sidewall 124 formed by a first sidewall 122 of an L-shaped first covering layer and an L-shaped second covering layer 118. However, in addition to the above steps, another embodiment of the present invention may further perform a dry etching process to remove a portion of the third mask layer 12 and stop on the surface of the second mask layer 118, and then perform another dry etching process to remove a portion of the second mask layer. 118. Finally, a portion of the first mask layer 114 is removed by a wet cleaning process to form the L-shaped first sidewall spacer 122, the L-type second mask layer 118, and the second sidewall spacer 124. An ion implantation can then be performed to implant an N-type or p-type dopant into the substrate on either side of the side walls to form a source/drain region 126. In the preferred embodiment, the source and the polar regions may be fabricated by a selective strain system (SSS) or the like, for example, by using a selective crystal growth (SeiectiVe epitaxial 201240084 growth, SEG) method. For example, when the source/drain region needs to be a P-pole, the source region can be formed by using a stupid crystal layer containing a mischievous dream (8 hearts); and the source/practice region needs to be a -N source. In the case of a pole/wave, it can include a carbonized state, iC), and a layer of i forms a source/drain region. In addition, a metal dream compound (not shown) is formed on the surface of the source/no-polar region 126, respectively. After forming the above (4), a contact hole stop stop layer (CESL) 128 and an inner layer dielectric (inter_iayer dielectric, ile>m 13〇) may be sequentially formed on the substrate 100. The steps of the above-described components are also known to those skilled in the art, and thus will not be described herein. As shown in FIG. 5, a planarization process is subsequently performed, for example, a portion of the ILD layer 130 is removed by a chemical mechanical polishing process. And a portion of the CESL 128 and the patterned hard mask 11 〇 until the polycrystalline layer 1 〇 8 is exposed. The polysilicon layer 108 is then removed by a suitable etching process to form a gate trench 132. The dielectric constant dielectric layer 106 can serve as an etch stop layer for protecting the underlying gate insulating layer 104 from the indentation process. The planarization process and the etching process are also known to those skilled in the art. Therefore, as shown in FIG. 6, a work function metal layer 134' - a barrier layer 136 and a barrier layer 132 for filling the gate trench 132 are sequentially formed in the gate trench 132. Low impedance metal layer 138. In the process, the work function metal layer 134 can be used to process a plastic or a N-type work function metal. Finally, a redundant low-resistance metal layer 138, a barrier layer 136, and a planarization process are removed. The work function metal layer 134 completes the fabrication of the metal gate 140 and the semiconductor device having the metal gate 140. Referring again to FIGS. 7 to 12, FIGS. 7 to 12 are another embodiment of the present invention. A schematic diagram of a semiconductor device having a metal gate' and this embodiment also employs a gate-first process in conjunction with a high-k first process. As shown in FIG. 7, a substrate is first provided. 2〇〇, for example, a stone substrate or an insulating layer overlying the substrate, and the substrate 200 is formed with a plurality of shallow trench isolation (STI) 202 for providing electrical isolation. A pole insulating layer 204 composed of a dielectric material such as a nitride or a nitride is used as a dielectric layer (10) on the surface of the substrate 200, and a high-k dielectric layer 2〇6 is sequentially formed. a β 208 p; Tt Yiri Day The stacked film formed by Shi Xi and the hard mask 210 is extremely thin. Among them, the bismuth layer 208 is used as θ, which is composed of a material which does not have any dopant (u-ed), or a polycrystalline stone material or an amorphous material. 4 dN+ push quality as shown in Fig. 8 'forms a (four) core layer (10) not shown) on the hard mask 201240084 210, and uses the patterned photoresist layer as a mask to perform the pattern transfer process to Sub-etching or successive etching step 'removing part of the hard mask, multiple pairs of pass-through, high-k dielectric layer 2〇6 and stripping the patterned photoresist layer for its L...丄,黍原A gate structure 212 is formed thereon. Then, the cover-and-hook structure is formed. (4) The side wall of the 1-pole structure 212 and the surface layer of the base 200 (not shown) are placed in the gate and the forehead is forged short, and the first part of the surface of the substrate 200 is removed. The concealing layer forms a first sidewall 214 on the sidewall of the gate structure 212. A lightly doped ion implant is implanted into the substrate 200, and the germanium or germanium dopant is implanted into the substrate 200 on both sides of the gate structure to form a lightly doped drain 216. Then, a second mask layer 218 composed of yttrium oxide is formed and covers the gate structure 212, the first sidewall 214, and the surface of the substrate 200. Then, as shown in Fig. 9, a shape of the second cover layer 220 composed of nitriding seconds is placed on the substrate 200 and covers the flute.
復盍第二遮蓋層218。在本實施例中， 由於第二遮蓋層218是由氧彳卜伙 L 吐 ^ 化矽所構成，因此與設於其上的 第三遮蓋層220較佳具有不同触刻率 如第10圖所示，先進行— 蓋層220並停在第二遮蓋層21S刻製程去除部分第1 製程去除科㈣二遮B 21/面，_再祕一濕钱刻The second cover layer 218 is recaptured. In this embodiment, since the second covering layer 218 is composed of the oxygen mask, the third covering layer 220 disposed thereon preferably has different etch rates as shown in FIG. Show, first proceed - cover layer 220 and stop in the second cover layer 21S engraving process to remove part of the first process removal section (four) two cover B 21 / face, _ re-secret a wet money engraved
^览曰218，以於間極結構侧壁212形 成一第一側壁子214、一 L沏笛 "/L 土弟二遮蓋層218以及一由氮化 201240084 矽所構成的第二側壁子222。 然後可進行一離子佈植，將N型或P型摻質植入上述側 壁子兩側的基底中以形成一源極/汲極區域226。在本實施例 中’亦可結合選擇性應力系統(selective strain scheme, SSS) 等製程’例如利用選擇性蠢晶成長(selective epitaxiai growth， SEG)方法來製作源極/汲極區域。例如，當源極/汲極區域226 需為一 p型源極/汲極時，可利用包含有鍺化矽（SiGe)之磊晶 層形成源極/沒極區域；而當源極/没極區域226需為一 N型 源極/汲極時，則可利用包含碳化矽（Sic)有之磊晶層形成源 極/汲極區域。此外，源極/汲極區域226表面可分別形成有 金屬石夕化物（圖未示）。形成上述元件之後，可於基底2〇〇 上依序开)成一接觸洞姓刻停止層（contact etch stop layer， CESL)228 與一内層介電（inter-iayer dieiectric，ild)層 230。 由於形成上述元件之步驟亦為熟習該項技藝者所知，故於此 亦不再贅述。 如第11圖所示，接下來進行一平坦化製程，例如利用 一化學機械研磨製程移除部分ILD層23〇、部分CESL228 與硬遮罩21G’直至暴露出多晶⑪層·。隨後更利用一適 "* I程移除多晶石夕層208，而形成一閘極溝渠232。 it寺面"電令數介電層可作為一餘刻停止層，用以保護 下方的閘極絕緣層綱不受制製程的之影響。由於上述平 201240084 坦化製程與蝕刻製程亦為熟習該項技蓺者 衣有所知者，故於此亦 不再贅述。 然後如第η圖所示，於閘極溝渠232内依序形成一功 函數金制234、-阻障層236以及—用卩填滿間極溝渠攻 的低阻抗金屬層238。其中’功函數金屬層咖可視製程需 求包含Ρ型功函數金屬或Ν型功函數金屬。最後，再藉由一 平坦化製程移除多餘的低阻抗金屬層攻、阻障層说與功 函數金屬層234’完成金屬閘極與具有金屬閘極鳩 半導體元件的製作。 細上所述 , ㈣較佳於製作輕摻㈣極前先於閘極) 構側壁形成-由無氧遮蓋層用來保護閘極結構中的高介電 常數介電層。在本發明之實施例中，無氧遮蓋層較佳由^ 石夕所構成’且較佳貼附並接觸閘極結構中的硬遮罩、多^ 層、高介電常數介電層及閘極絕緣層。由於習知製程在製子 輕摻雜汲極前於閘極結構的側壁處通常不具有任何用來保 護尚介電常數介電層的材料層’例如本案所揭露的遮蓋層 使高介電常數介電層容易在後續諸如輕摻雜離子佈植的濕 式清洗、氧剝&、形成側壁子等製程中的濕式清洗步驟中初 去除。因此藉由上述實施例於製作輕摻雜汲極前先於閘極結 構側壁开》成一用來保護閘極結構的無氧遮蓋層，本發明可有 效改善上述缺點並避免高介電常數介電層於製程十受到損 12 201240084 害0 另外需注意的是，上述實施例所揭露製作半導體元件的 步驟雖以後閘極(gate_first)製程搭配前高介電常數介電層 (high-K first)製程為例，但不侷限於此，本發明又可將上述 實施例應用至前閘極(gate-first)製程及後高介電常數介電層 (high-K last)製程，此變化型均屬本發明所涵蓋的範圍。其 中，前閘極製程之閘極結構較佳包含一閘極絕緣層、一高介 電常數介電層設於閘極絕緣層上以及一多晶矽閘極設於高 介電常數介電層上，且高介電常數介電層較佳為一一字型高 介電常數介電層。而在後高介電常數介電層製程中，閘極結 構則包含一閘極絕緣層、一高介電常數介電層設於閘極絕緣 層上以及一金屬閘極設於高介電常數介電層上，其中高介電 常數介電層則較佳為一 U型高介電常數介電層。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第6圖為本發明較佳實施例製作—具有金屬問極之 半導體元件示意圖。 第7圖至第12圖為本發明另—實施例製作—具有金屬問極 之半導體元件示意圖。 13 201240084 【主要元件符號說明】 100 基底 102 淺溝隔離 104 閘極絕緣層 106 高介電常數介電層 108 多晶矽層 110 硬遮罩 112 閘極結構 114 第一遮蓋層 116 輕換雜汲極 118 第二遮蓋層 120 第三遮蓋層 122 第一側壁子 124 第二側壁子 126 源極/沒極區域 128 接觸洞蝕刻停止層 130 内層介電層 132 閘極溝渠 134 功函數金屬層 136 阻障層 138 低阻抗金屬層 140 金屬閘極 200 基底 202 淺溝隔離 204 閘極絕緣層 206 高介電常數介電層 208 多晶矽層 210 硬遮罩 212 閘極結構 214 第一側壁子 216 輕摻雜汲極 218 第二遮蓋層 220 第三遮蓋層 222 第二側壁子 226 源極/沒極區域 228 接觸洞蝕刻停止層 230 内層介電層 232 閘極溝渠 234 功函數金屬層 236 阻障層 14 201240084 238 低阻抗金屬層 240 金屬閘極 15The 曰 218 is formed such that a first sidewall 214, an L whistle "/L turbid cover layer 218, and a second sidewall 222 formed by nitriding 201240084 形成 are formed on the sidewall structure 212 of the interpole structure. . An ion implantation can then be performed to implant an N-type or P-type dopant into the substrate on either side of the side walls to form a source/drain region 226. In the present embodiment, a source/drain region may be fabricated by a selective epitaxi growth (SEG) method, for example, in conjunction with a selective strain scheme (SSS) process. For example, when the source/drain region 226 needs to be a p-type source/drain, the epitaxial layer containing germanium telluride (SiGe) can be used to form the source/drain region; and when the source/none When the pole region 226 needs to be an N-type source/drain, the source/drain region can be formed by using an epitaxial layer containing tantalum carbide (Sic). Further, a metal ceramsite (not shown) may be formed on the surface of the source/drain region 226, respectively. After forming the above-mentioned components, a contact etch stop layer (CESL) 228 and an inter-iayer die- ties (ild) layer 230 may be formed on the substrate 2 依 sequentially. Since the steps of forming the above-described components are also known to those skilled in the art, they will not be described again. As shown in Fig. 11, a planarization process is subsequently performed, for example, by removing a portion of the ILD layer 23, a portion of the CESL 228, and the hard mask 21G' by a chemical mechanical polishing process until the polycrystalline 11 layer is exposed. The polycrystalline layer 208 is then removed using a suitable "*I process to form a gate trench 232. It temple surface " electric order dielectric layer can be used as a residual stop layer to protect the underlying gate insulation layer from the manufacturing process. Since the above-mentioned flat 201240084 process and etching process are also known to those skilled in the art, they will not be described here. Then, as shown in the figure η, a work function gold 234, a barrier layer 236, and a low-resistance metal layer 238 filled with inter-pole trenches are sequentially formed in the gate trench 232. Among them, the work function metal layer coffee process requires a 功 type work function metal or a 功 type work function metal. Finally, the excess low-impedance metal layer attack, the barrier layer and the work function metal layer 234' are used to complete the fabrication of the metal gate and the metal gate semiconductor device by a planarization process. As described above, (4) is preferably formed before the light-doped (four) poles are formed before the gates - the anaerobic mask layer is used to protect the high-k dielectric layer in the gate structure. In an embodiment of the invention, the oxygen-free cover layer is preferably composed of a thin mask, and preferably adheres to and contacts the hard mask, the multi-layer, the high-k dielectric layer and the gate in the gate structure. Extremely insulating layer. Since the conventional process does not have any material layer for protecting the dielectric constant dielectric layer at the sidewall of the gate structure before the lightly doped gate is fabricated, such as the mask layer disclosed in the present disclosure, the high dielectric constant is The dielectric layer is easily removed initially in a subsequent wet cleaning step in a process such as wet cleaning, oxygen stripping, and sidewall forming, such as lightly doped ion implantation. Therefore, the present invention can effectively improve the above disadvantages and avoid high dielectric constant dielectric by forming an oxygen-free shielding layer for protecting the gate structure before the light-doped drain is fabricated by the above embodiment. The layer is damaged by the process 12 201240084 ○ 0 It should be noted that the steps of fabricating the semiconductor device disclosed in the above embodiments are as follows: the gate_first process is matched with the high-k first process. For example, but not limited thereto, the present invention can also apply the above embodiments to a gate-first process and a high-k last process, both of which are The scope of the invention is covered. The gate structure of the front gate process preferably includes a gate insulating layer, a high-k dielectric layer disposed on the gate insulating layer, and a polysilicon gate disposed on the high-k dielectric layer. The high-k dielectric layer is preferably a one-word high-k dielectric layer. In the post-high-k dielectric layer process, the gate structure includes a gate insulating layer, a high-k dielectric layer is disposed on the gate insulating layer, and a metal gate is disposed on the high dielectric constant. On the dielectric layer, the high-k dielectric layer is preferably a U-type high-k dielectric layer. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the patent scope of the present invention are intended to be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 through 6 are schematic views of a semiconductor device having a metal interrogation fabricated in accordance with a preferred embodiment of the present invention. Figures 7 through 12 are schematic views of a semiconductor device having a metal interrogation fabricated in accordance with another embodiment of the present invention. 13 201240084 [Description of main components] 100 Substrate 102 Shallow trench isolation 104 Gate insulating layer 106 High-k dielectric layer 108 Polysilicon layer 110 Hard mask 112 Gate structure 114 First cover layer 116 Light-changing germanium 118 Second cover layer 120 third cover layer 122 first side wall 124 second side wall 126 source/nothing area 128 contact hole etch stop layer 130 inner layer dielectric layer 132 gate trench 134 work function metal layer 136 barrier layer 138 low-impedance metal layer 140 metal gate 200 substrate 202 shallow trench isolation 204 gate insulating layer 206 high-k dielectric layer 208 polysilicon layer 210 hard mask 212 gate structure 214 first sidewall sub-216 lightly doped bungee 218 second cover layer 220 third cover layer 222 second side wall 226 source/nothing area 228 contact hole etch stop layer 230 inner layer dielectric layer 232 gate trench 234 work function metal layer 236 barrier layer 14 201240084 238 low Impedance metal layer 240 metal gate 15