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TW201240043A - Integral circuit device - Google Patents

Integral circuit device Download PDF

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Publication number
TW201240043A
TW201240043A TW100111301A TW100111301A TW201240043A TW 201240043 A TW201240043 A TW 201240043A TW 100111301 A TW100111301 A TW 100111301A TW 100111301 A TW100111301 A TW 100111301A TW 201240043 A TW201240043 A TW 201240043A
Authority
TW
Taiwan
Prior art keywords
metal pad
pad
integrated circuit
metal
circuit device
Prior art date
Application number
TW100111301A
Other languages
Chinese (zh)
Other versions
TWI424544B (en
Inventor
Tai-Hung Lin
Chang-Tien Tsai
Original Assignee
Novatek Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Novatek Microelectronics Corp filed Critical Novatek Microelectronics Corp
Priority to TW100111301A priority Critical patent/TWI424544B/en
Priority to US13/423,264 priority patent/US8618660B2/en
Publication of TW201240043A publication Critical patent/TW201240043A/en
Priority to US14/062,899 priority patent/US9041201B2/en
Application granted granted Critical
Publication of TWI424544B publication Critical patent/TWI424544B/en
Priority to US14/666,322 priority patent/US20150194399A1/en
Priority to US14/740,286 priority patent/US9627337B2/en
Priority to US15/412,072 priority patent/US9881892B2/en

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    • H—ELECTRICITY
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An integral circuit including a substrate, a first internal bonding pad, a second internal bonding pad, an external bonding pad and a bonding wire is provided. A first circuit, a second circuit, at least one internal circuit and an electrostatic discharge circuit are embedded in the substrate. The first internal bonding pad is disposed on a surface of the substrate and electrically connected to the first circuit. The second internal bonding pad is disposed on the surface of the substrate and electrically connected to the second circuit. The first internal bonding pad is electrically connected to the second internal bonding pad via the bonding wire. The first internal bonding pad is electrically connected to the electrostatic discharge circuit via the internal circuit. The electrostatic discharge circuit is electrically connected to the external bonding pad. The external bonding pad is used for electrically connecting an external package lead.

Description

201240043 in ν ι-/υι 0-042 34937twf.doc/I 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種積體電路裝置，且特別是有關於 一種以打線取代部分内連線的積體電路裝置。 、 【先前技術】 積體電路裝置的㈣的電性傳遞常用金屬内連 達成，而其連接的方式和途彳蝴透過賴魏軟辦 做出實際圖面。這些金屬内連線是以微影蝕 3 生，因此配置方式、長度和寬度都會受到製程能力的限= ^限制了連接的電性表現。另一方面，在積體電路裝置盘 if Γ端子的電性傳遞方面，則常用打線技術來達 成。打線技術是利用打線製程所產生的金屬線來連 好的電性表現，在設計上也少了限制而有更佳的設 【發明内容】 與靜種賴電路裝置，具雜㈣電性表現 本^的積體電路衫包括—基材、—第—内接塾、 路、二第接ΐ二外接塾以及—打線。基材内埋一第一電 内垃轨第—電 至 内連線與一靜電防護電路。第一 塾配置Γ電性連接第一電路。第二内接 、基材的表面並概連接第二電路。外接塾配置於 4201240043 in ν ι-/υι 0-042 34937twf.doc/I VI. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit device, and in particular to a partial replacement of a wire by a wire Line integrated circuit device. [Prior Art] The electrical transmission of (4) of the integrated circuit device is usually achieved by the internal connection of the metal, and the way of connection and the way of making it through the Lai Wei soft office to make the actual picture. These metal interconnects are micro-etched, so the configuration, length and width are limited by the process capability = ^ limits the electrical performance of the connection. On the other hand, in the electrical transmission of the if Γ terminal of the integrated circuit device, the wire bonding technique is commonly used. The wire-bonding technology uses the metal wire generated by the wire-bonding process to connect the electrical performance. The design is also less restrictive and has better settings. [Inventive content] and static seed circuit device, with miscellaneous (four) electrical performance ^ The integrated circuit board includes - the substrate, the first - the inner joint, the road, the second and the second outer joint, and - the wire. A first electric internal rail is embedded in the substrate to the internal interconnection and an electrostatic protection circuit. The first 塾 configuration is electrically connected to the first circuit. The second inscribed, the surface of the substrate is substantially connected to the second circuit. External port is configured in 4

201240043 NVT-2010-042 34937twf.doc/I 基材的表面。第一内接墊經由打線電性連接第二内接墊。 第一内接墊經由内連線電性連接靜電防護電路。靜電防護 電路電性連接外接墊。外接墊用以電性連接一外部封裝接 腳。 在本發明之一實施例中，第一電路為邏輯電路、數位 電路或記憶體電路。 在本發明之一實施例中，第二電路為邏輯電路、數位 電路或記憶體電路。 在本發明之一實施例中，第一内接墊包括一第一金屬 塾、一第二金屬塾與一介電層，第一金屬塾電性連接第二 金屬墊，介電層位於第一金屬墊與第二金屬墊之間。此外， 第一金屬墊例如具有一打線接合區與一導通區，第一内接 墊更包括多個導通件，貫穿介電層並連接第一金屬墊的導 通區與第二金屬墊。另外，導通區例如位於打線接合區的 一側。導通區環繞打線接合區。再者，第二金屬墊例如具 有多個開孔，位於打線接合區下方。此外，第一金屬墊與 第二金屬墊的材質例如為銅。另外，第一金屬墊的材質例 如為鋁，第二金屬墊的材質為銅。 在本發明之一實施例中，第二内接塾包括一第一金屬 塾、一第二金屬墊與一介電層，第一金屬塾電性連接第二 金屬塾，介電層位於第一金屬塾與第二金屬塾之間。 在本發明之一實施例中，外接墊包括一第一金屬墊、 一第二金屬塾與一介電層，第一金屬塾電性連接第二金屬 塾，介電層位於第一金屬墊與第二金屬塾之間。201240043 NVT-2010-042 34937twf.doc/I Surface of the substrate. The first inner pad is electrically connected to the second inner pad via a wire. The first inner pad is electrically connected to the static electricity protection circuit via an interconnect. The ESD protection circuit is electrically connected to the external pad. The external pad is used to electrically connect an external package pin. In one embodiment of the invention, the first circuit is a logic circuit, a digital circuit or a memory circuit. In one embodiment of the invention, the second circuit is a logic circuit, a digital circuit or a memory circuit. In an embodiment of the invention, the first inner pad includes a first metal iridium, a second metal lanthanum and a dielectric layer, the first metal lanthanum is electrically connected to the second metal pad, and the dielectric layer is located at the first Between the metal pad and the second metal pad. In addition, the first metal pad has, for example, a wire bonding region and a conductive region. The first inner pad further includes a plurality of conductive members extending through the dielectric layer and connecting the conductive region of the first metal pad and the second metal pad. Further, the conduction area is located, for example, on one side of the wire bonding zone. The conductive area surrounds the wire bonding area. Further, the second metal pad has, for example, a plurality of openings located below the wire bonding area. Further, the material of the first metal pad and the second metal pad is, for example, copper. Further, the material of the first metal pad is, for example, aluminum, and the material of the second metal pad is copper. In an embodiment of the invention, the second interconnector includes a first metal germanium, a second metal pad and a dielectric layer, the first metal germanium is electrically connected to the second metal germanium, and the dielectric layer is located at the first Between the metal crucible and the second metal crucible. In an embodiment of the invention, the external pad includes a first metal pad, a second metal pad and a dielectric layer, the first metal pad is electrically connected to the second metal pad, and the dielectric layer is located on the first metal pad and Between the second metal rafts.

201240043 NV1-2U10-042 34937twf.doc/I 在本發明之-實施例中，基材的表面 =環繞外接墊，線路淨空區的外 接外的ς 離介於2微米至5 〇微米。線路 ：，外、.彖的距 緣的距離較佳是1G微米。 °°纟卜緣與外接塾的外 基於上述，在本發明的積體電路褒置中， 用内接墊以及打線而電性連接 利 接有靜電防護電路二接塾之間連 ^ . 本冬明的積體電路裝置具有較 的電性表S ’且可避免内部電路受聰電的破壞。 ^讓本發明之上述賴和伽缺鶴錄，下文特 舉貫施例’並配合所附圖式作詳細說明如下。 【實施方式】 圖1A是本發明一實施例的積體電路裝置的剖面示意 圖1B疋圖1A的積體電路裝置的電路方塊圖。請參照 圖1A，本實施例的積體電路裝置1〇〇包括一基材ιι〇、一 第一内接墊120、一第二内接墊13〇、一外接墊14〇以及一 打線150。基材110内埋一第一電路16〇、一第二電路17〇、 至> 一内連線112與一靜電防護電路18〇。本實施例的基 材110還可包括多條内連線114。第一内接墊12〇配置於 基材110的表面並電性連接第一電路16化第二内接墊13〇 配置於基材U0的表面並電性連接第二電路170。外接墊 140配置於基材110的表面。第一内接墊〗2〇經由打線15〇 電性連接第二内接墊130。第一内接墊120經由内連線112 電性連接靜電防護電路180。靜電防護電路180電性連接 6 201240043201240043 NV1-2U10-042 34937twf.doc/I In the embodiment of the present invention, the surface of the substrate = surrounds the outer pad, and the external detachment of the line clearance area is between 2 micrometers and 5 micrometers. Line: The distance between the outer and outer edges is preferably 1G micron. The above is based on the above, in the integrated circuit device of the present invention, the inner pad and the wire are electrically connected to each other with an electrostatic protection circuit. The integrated circuit device of the Ming has a relatively electric meter S' and can prevent the internal circuit from being damaged by the Congdian. The above-mentioned Lai and Gamma of the present invention will be described in detail below with reference to the accompanying drawings. [Embodiment] FIG. 1A is a schematic block diagram of an integrated circuit device according to an embodiment of the present invention. FIG. 1B is a circuit block diagram of the integrated circuit device of FIG. Referring to FIG. 1A, the integrated circuit device 1 of the present embodiment includes a substrate ιι, a first inner pad 120, a second inner pad 13A, an outer pad 14A, and a wire 150. A first circuit 16A, a second circuit 17A, and an internal interconnection 112 and an electrostatic protection circuit 18 are embedded in the substrate 110. The substrate 110 of the present embodiment may also include a plurality of interconnects 114. The first inner pad 12 is disposed on the surface of the substrate 110 and electrically connected to the first circuit 16 and the second inner pad 13 is disposed on the surface of the substrate U0 and electrically connected to the second circuit 170. The external pad 140 is disposed on the surface of the substrate 110. The first inner pad is electrically connected to the second inner pad 130 via the wire 15 . The first inner pad 120 is electrically connected to the static electricity protection circuit 180 via the interconnecting wire 112. Electrostatic protection circuit 180 is electrically connected 6 201240043

NVT-2010-042 34937twf.doc/I 外接墊140。外接墊HO用以電性連接一外部封裴 T10。 、 在其他實施例中，外接墊140也可以直接經由内連線 112電性連接第一内接墊12〇而不經由靜電防護電路a… 請參照圖1A與圖1B，一外部系統si〇所提供的訊號 會先傳遞至外部封裝接腳T10，再從外部封裝接腳τι〇經 由打線、外接墊140與内連線114傳遞至靜電防護電: αο。接著，訊號再從靜電防護電路180經由内連線ιΐ2、 第一内接墊120與打線15〇傳遞至第二内接墊13〇，再從 第一内接墊130經由内連線114傳遞至第二電路17〇。 在本實施例的積體電路裝置100中，基材110内的第 ^電路16G與第二電路17()不僅可採用内連線的路徑進行 號傳遞’更可以經由第—内接墊12G '打線⑼與第二 内接墊130的路徑進行訊號傳遞。打線150是利用打線勢 ^斤形成的位於基材11Q之外的金屬線，打線15()的線寬 =較内連線的線寬大，因此打線15Q的電阻值較小而可赛 ^較佳的電性表現。另外，利用打線15〇來進行第一電ς 60_與，—電路17G之間的訊號傳遞’可避免採用内連線 二减傳遞時必須想瓶避·材丨動的各種電路的 〜少 >也可減V形成内連線所需的金屬層的數量而進—步 即省形成内連線所$ 置⑽的設計時程先罩數量，大幅縮短了積體電路裳 在本實__體電路農置巾，外驗14〇與第 接塾no之間存在靜電防護電路⑽。靜電防護電路NVT-2010-042 34937twf.doc/I External pad 140. The external pad HO is electrically connected to an external sealing T10. In other embodiments, the external pad 140 can also be directly connected to the first inner pad 12 via the interconnecting wire 112 without passing through the static electricity protection circuit a... Please refer to FIG. 1A and FIG. 1B, an external system si The signal provided is first transmitted to the external package pin T10, and then transmitted from the external package pin τι〇 to the static electricity protection via the wire bonding, the external pad 140 and the interconnecting wire 114: αο. Then, the signal is transmitted from the static electricity protection circuit 180 to the second inner pad 13A via the interconnecting line ι2, the first inner pad 120 and the wire 15〇, and then transmitted from the first inner pad 130 to the second inner pad 130 via the interconnect 114. The second circuit 17 is. In the integrated circuit device 100 of the present embodiment, the first circuit 16G and the second circuit 17 () in the substrate 110 can be transferred not only by the path of the interconnect, but also via the first inner pad 12G. The line (9) and the path of the second inner pad 130 are signaled. The wire 150 is a metal wire formed outside the substrate 11Q by using a wire punching force. The wire width of the wire 15 is larger than the wire width of the inner wire. Therefore, the wire 15Q has a small resistance value and can be better. Electrical performance. In addition, by using the wire 15 〇 to perform the signal transmission between the first electric ς 60_ and the circuit 17G, it is possible to avoid various circuits that must be avoided when the internal connection is reduced. It is also possible to reduce the number of metal layers required to form the interconnections, and to increase the number of design time intervals of the interconnects (10), which greatly shortens the integrated circuit in the real __ There is a static protection circuit (10) between the external test 14〇 and the first connection no. Electrostatic protection circuit

201240043 in v ι-ζυι0-042 34937twf.d〇c/I 180可避免第-電路160與第二電路17〇被從外部封 腳T10與外接墊140傳來的靜電破壞。 舉例而言，本實施例的第—電路⑽可以是邏輯電 路、數位電路、記憶體電路或其他電路。第二電路m也 可以是邏輯電路、數位電路、記憶體電路或其他電路。 圖2疋圖1A之第—内接墊的剖示圖，而圖3與圖4 分別是圖2的^個金屬塾的正視圖。請參照圖2，本實施 例的第-内接墊⑽包括—第—金屬墊122、—第二金屬 墊124與一介電層126 ’第一金屬墊122電性連接第二金 屬塾124’介電層126位於第一金屬墊122與第二金屬塾 124之間。由於第—内接塾m採用了雙層金屬塾的結構， 在進行打線製程時可降低打線的解力對於第—内接塾 120下方的結構的影響。因此，第一内接塾12〇下方也可 配置電路，有利於縮減積體電路裝置的辞體尺寸。 請參照圖2與圖3，第一金屬墊122例如具有一打線 接合區R12與一導通區R14。第一内接墊12〇更包括多個 導通件128 ’貫穿介電層126並連接第一金屬墊122的導 通區R14與第二金屬墊124。導通區RM位於打線接合區 R12的一側。打線接合區R12是後續進行打線製程時承受 衝擊力的區域，打線接合區R12不配置導通件128的設計 方式可提升第12G _衝擊強度，參照圖°2與 圖4 ’第二金屬塾124可具有多個 p 4)，位於打線接合區R12下方。開孔_二^^圖 内接塾120的耐衝擊強度。另外，第-金雜122的打線 8 201240043201240043 in v ι-ζυι0-042 34937twf.d〇c/I 180 can prevent electrostatic breakdown of the first circuit 160 and the second circuit 17A from the external package T10 and the external pad 140. For example, the first circuit (10) of the present embodiment may be a logic circuit, a digital circuit, a memory circuit, or other circuits. The second circuit m can also be a logic circuit, a digital circuit, a memory circuit or other circuits. 2 is a cross-sectional view of the first inner pad of FIG. 1A, and FIGS. 3 and 4 are front views of the metal cymbal of FIG. 2, respectively. Referring to FIG. 2, the first inner pad (10) of the embodiment includes a first metal pad 122, a second metal pad 124, and a dielectric layer 126. The first metal pad 122 is electrically connected to the second metal pad 124'. The dielectric layer 126 is located between the first metal pad 122 and the second metal pad 124. Since the first in-line 塾m adopts a double-layered metal crucible structure, the influence of the disengagement force of the wire bonding on the structure under the first inscribed crucible 120 can be reduced during the wire bonding process. Therefore, the circuit can also be arranged under the first internal connection 12〇, which is advantageous for reducing the size of the integrated circuit device. Referring to FIG. 2 and FIG. 3, the first metal pad 122 has, for example, a wire bonding region R12 and a conductive region R14. The first inner pad 12 further includes a plurality of vias 128' extending through the dielectric layer 126 and connecting the conductive regions R14 and the second metal pads 124 of the first metal pads 122. The conduction area RM is located on one side of the wire bonding area R12. The wire bonding zone R12 is an area that receives the impact force during the subsequent wire bonding process, and the design of the wire bonding zone R12 without the conduction member 128 can improve the 12G _ impact strength, referring to FIG. 2 and FIG. 4 'the second metal 塾 124 can be There are a plurality of p 4) located below the wire bonding zone R12. Opening _ two ^ ^ Figure The impact strength of the inner 塾 120. In addition, the first - Jinza 122 line 8 201240043

NVT-2010-042 34937twf.doc/I 接合區R12則保持完整以與打線保持最大的接觸面積而提 升電性表現。藉由上述設計，第一内接墊12〇會較具有彈 性而可減輕打線製程中施加在第一内接墊12〇上的應力的 衫響，以便於在第一内接墊12〇下方配置電路。請參照圖 2,第一金屬墊122與第二金屬墊124的材質例如都是銅。 或者，第一金屬墊122的材質為鋁，而第二金屬墊124的 材質為銅。 圖5是另一實施例的第一内接墊的第一金屬墊的正視 圖。凊參照圖5，本實施例的第一金屬墊的導通區R24是 %：繞打線接合區R22。當然’導通區R24與打線接合區R22 的相對位置也可採用其他適當的變化型態。 請參照圖1A，第二内接墊13〇與外接墊HO也都可 以採用類似第一内接墊丨2〇的結構，亦即由雙層金屬墊與 位於雙層金屬墊之間的介電層所構成，以提升第一内接墊 120的耐衝擊強度。 圖6是本發明另一實施例之基材的表面的局部示意 圖。請參照圖6，本實施例之基材的表面具有一線路淨空 區R30 ’環繞外接墊200。線路淨空區R30的外緣與外接 塾200的外緣的距離D10介於2微米至5〇微米，線路淨 空區R30的外緣與外接墊200的外緣的距離D10較佳是 10微来。線路淨空區R30可避免線路被打線製程的衝擊力 破壞。相似地，前述實施例的内接墊的外圍也可設置線路 淨空區。 圖7是本發明另一實施例之外接墊與其周邊線路的配NVT-2010-042 34937twf.doc/I The junction R12 remains intact to maintain maximum contact area with the wire for improved electrical performance. With the above design, the first inner pad 12 〇 is more elastic and can reduce the stress of the stress applied to the first inner pad 12 打 in the wire bonding process, so as to be disposed under the first inner pad 12 〇 Circuit. Referring to FIG. 2, the material of the first metal pad 122 and the second metal pad 124 is, for example, copper. Alternatively, the material of the first metal pad 122 is aluminum, and the material of the second metal pad 124 is copper. Figure 5 is a front elevational view of a first metal pad of a first inner pad of another embodiment. Referring to FIG. 5, the conduction region R24 of the first metal pad of the present embodiment is %: the winding bonding region R22. Of course, the relative position of the conducting region R24 to the wire bonding region R22 can also adopt other suitable variations. Referring to FIG. 1A, the second inner pad 13 〇 and the outer pad HO can also adopt a structure similar to the first inner pad , 2 ,, that is, a dielectric between the double metal pad and the double metal pad. The layers are formed to enhance the impact strength of the first inner pad 120. Fig. 6 is a partial schematic view showing the surface of a substrate of another embodiment of the present invention. Referring to Figure 6, the surface of the substrate of the present embodiment has a line clearance area R30' surrounding the outer pad 200. The distance D10 between the outer edge of the line clearance area R30 and the outer edge of the outer rim 200 is between 2 micrometers and 5 micrometers, and the distance D10 between the outer edge of the line clearance area R30 and the outer edge of the outer pad 200 is preferably 10 micrometers. The line clearance area R30 can prevent the line from being damaged by the impact of the wire-laying process. Similarly, the periphery of the inner pad of the foregoing embodiment may also be provided with a line clearance area. Figure 7 is a diagram showing the arrangement of an external pad and its peripheral lines according to another embodiment of the present invention.

201240043 MV 1-2010-042 34937twf,doc/I 置方式的示意圖。請參照圖6與圖7,圖6是以外接塾200 位於基材的最表層的部分來說明。然而，外接墊也可以如 圖2的實施例所述’採用雙層金屬墊的設計。外接墊採用 雙層金屬墊的設計時，下層金屬墊3〇〇與周圍的線路的關 係可參照圖7。亦即是，圖7中的下層金屬墊3〇〇僅相當 於圖2的第二金屬墊124，而下層金屬墊3〇〇上方會有相 當於圖2的第一金屬墊122的上層金屬墊。然而，圖7重 點在說明下層金屬墊3〇〇與同一層的其他線路的關係，故 在此並不繪示上層金屬墊。下層金屬墊3〇〇所在的金屬層 通常會形成有橫向和縱向交錯網狀格線(metal mesh)31〇， 常見有對地格線(ground mesh)或電源格線(p〇wer mesh)。這 些格線在遇到下層金屬墊300時，若非必須與下層金屬墊 3〇〇連接者，則應斷開而與下層金屬墊3〇〇保持一距離 D20 ’此距離D20介於0.5微米至10微米，此距離D2〇 較佳是2微米。 ，-，示上所述，在本發明的積體電路裝置中，内部電路矛 =接墊以及打線而電性連接，金屬打線可提供較佳㈣ ，表現，且設計限制較少而可縮短設計時程， ==層的數量而降低成本。另外，在本= 路’因此可避免_物刪的破壞。 雖:、、、:本發明已以實施例揭露如上，然其並 本發明，任何所屬技術領 ^ 本發明之精袖知〜哉者，在不脫葡 粍圍内，當可作些許之更動與潤飾，故^201240043 MV 1-2010-042 34937twf, Schematic diagram of the doc/I setting method. Please refer to FIG. 6 and FIG. 7. FIG. 6 is a view showing the portion of the outermost layer of the substrate 200 located on the outermost layer of the substrate. However, the outer pad can also be designed with a double metal pad as described in the embodiment of Fig. 2. When the outer pad is designed with a double metal pad, the relationship between the lower metal pad 3 and the surrounding circuit can be referred to FIG. That is, the lower metal pad 3 in FIG. 7 is only equivalent to the second metal pad 124 of FIG. 2, and the upper metal pad 3 has an upper metal pad corresponding to the first metal pad 122 of FIG. . However, Fig. 7 focuses on the relationship between the underlying metal pad 3's and other lines of the same layer, so the upper metal pad is not shown here. The metal layer on which the lower metal pad 3 is located is usually formed with a transverse and longitudinal staggered metal mesh 31〇, which is usually a ground mesh or a p〇wer mesh. When the underlying metal pad 300 is encountered, if it is not necessary to be connected to the underlying metal pad 3, it should be disconnected and kept at a distance D20 from the underlying metal pad 3'. The distance D20 is between 0.5 and 10 Micrometers, this distance D2 〇 is preferably 2 micrometers. In the integrated circuit device of the present invention, the internal circuit spear=pad and the wire are electrically connected, and the metal wire can provide better (4) performance, and the design limit is less, and the design can be shortened. Time course, == the number of layers to reduce costs. In addition, in this = road, it is therefore possible to avoid the destruction of the object deletion. Although: the present invention has been disclosed in the above embodiments, and the present invention, any of the technical know-hows of the present invention can be modified in some ways. With retouching, so ^

201240043 NVT-2010-042 34937twf.doc/I 發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A是本發明一實施例的積體電路裝置的剖面示意 圖。 圖1B是圖1A的積體電路裝置的電路方塊圖。 圖2是圖1A之第一内接塾的剖示圖。 圖3與圖4分別是圖2的兩個金屬墊的正視圖。 圖5是另一實施例的第一内接墊的第一金屬墊的正視 圖。 圖6是本發明另一實施例之基材的表面的局部示意 圖。 圖7是本發明另一實施例之外接墊與其周邊線路的配 置方式的示意圖。 【主要元件符號說明】 100 :積體電路裝置 110 :基材 120 :第一内接墊 122 :第一金屬墊 124 :第二金屬墊 126 :介電層 128 :導通件 130 :第二内接墊 11 201240043201240043 NVT-2010-042 34937twf.doc/I The scope of protection of the invention is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a schematic cross-sectional view showing an integrated circuit device according to an embodiment of the present invention. Fig. 1B is a circuit block diagram of the integrated circuit device of Fig. 1A. Figure 2 is a cross-sectional view of the first inner rim of Figure 1A. 3 and 4 are front elevational views of the two metal pads of Fig. 2, respectively. Figure 5 is a front elevational view of a first metal pad of a first inner pad of another embodiment. Fig. 6 is a partial schematic view showing the surface of a substrate of another embodiment of the present invention. Fig. 7 is a schematic view showing the arrangement of an external pad and its peripheral lines according to another embodiment of the present invention. [Main component symbol description] 100: integrated circuit device 110: substrate 120: first inner pad 122: first metal pad 124: second metal pad 126: dielectric layer 128: conductive member 130: second inscribed Mat 11 201240043

in ν ι-ζυι0-042 34937twf.doc/I 140、200 :外接墊 150 :打線 160 :第一電路 170 :第二電路 180 :靜電防護電路 300 :下層金屬塾 310 :格線 T10 :外部封裝接腳 R12、R22 :打線接合區 R14、R24 :導通區 R30 :線路淨空區 D10、D20 :距離 12In ν ι-ζυι0-042 34937twf.doc/I 140, 200: external pad 150: wire 160: first circuit 170: second circuit 180: static protection circuit 300: lower metal 塾 310: grid T10: external package Foot R12, R22: wire bonding zone R14, R24: conduction zone R30: line clearance zone D10, D20: distance 12

Claims (1)

201240043 NVT-2010-042 34937twf.doc/I 七、申請專利範圍： k —種積體電路裝置，包括 第—電路、至少—内連 一基材，内埋一第一電路、 線與一靜電防護電路； -電:第—内接塾’配置於該基材的表面並電性連接該第 二電路？—内接墊，配置於該基材的表面並電性連接該第 二卜接塾’配置於該基材的表面外部封裝接腳； 允二丁線’其中該第—内接墊經*該打線電性連接·^第 -内接墊’該第-内接塾經由該内連線電性連接雷 該靜電防護電路電性連接該外接墊，該外接Ϊ用 以電性連接一外部端子。 雙用 2.如申請專利範圍第i項所述之積體電路裝置， 該第一電路為邏輯電路、數位電路或記憶體電路。“ 3_如申請專利範圍第丨項所述之積體電路裝置， 該第二電路為邏輯電路、數位電路或記賴電路。〃 4·如申請專利範圍第}項所述之積體電 ϊ 接L包括一第一働、一第二金屬整與- :第ίϊί?塾電性連接該第二金屬墊，該介電層位於 该第一金屬墊與該第二金屬墊之間。 #楚喷專利範圍第4項所述之積體電路裝置，其中 “第-金屬墊具有—打線接合區與—導通區，該第 件，貫穿該介電層並連接該第-金屬塾 的4導通區與该第二金屬墊。 13 201240043 L· 0-042 34937twf.doc/l 6. 如申請專利範圍第5項所述之積體電路裝置，其中 該導通區位於該打線接合區的一側。 7. 如申請專利範圍第5項所述之積體電路裝置，其中 該導通區環繞該打線接合區。 8. 如申請專利範圍第5項所述之積體電路裝置，其中 該第二金屬墊具有多個開孔，位於該打線接合區下方。 9. 如申請專利範圍第4項所述之積體電路裝置，其中 該第一金屬墊與該第二金屬墊的材質為銅。 10. 如申請專利範圍第4項所述之積體電路裝置，其中 該第一金屬墊的材質為鋁，該第二金屬墊的材質為銅。' 11·如申請專利範圍第1項所述之積體電路裝置，其中 該第二内接墊包括一第一金屬墊、一第二金屬墊與一&amp;電 層，該第一金屬墊電性連接該第二金屬墊，該介電層 該第一金屬墊與該第二金屬墊之間。 、 12.如申請專利範圍第i項所述之積體電路裝置，其中 該外接墊包括一第一金屬墊、一第二金屬墊與一介電層， 該第一金屬墊電性連接該第二金屬墊，該介電層位於^第 一金屬墊與該第二金屬墊之間。 、 _ 13.如申睛專利範圍第丨項所述之積體電路裴置，其中 ，基材的表面具有一線路淨空區，環繞該外接墊該^路 淨空區的外緣與該外接墊的外緣的距離介於2 s 微米。 从不王ου 二14.如申請專利範圍第13項所述之積體電路裝置，其 ί該線路淨空區的外緣與該外接㈣外緣的轉為10 i 米0 14201240043 NVT-2010-042 34937twf.doc/I VII. Patent application scope: k—the integrated circuit device, including the first circuit, at least—interconnecting a substrate, embedding a first circuit, a line and an electrostatic protection Circuit: - Electricity: the first - the inner junction is disposed on the surface of the substrate and electrically connected to the second circuit? An inner pad disposed on a surface of the substrate and electrically connected to the surface of the second package 配置 disposed on the surface of the substrate; the second wire of the second inner wire The electrical connection of the wire is connected to the external pad via the interconnecting wire. The external terminal is electrically connected to an external terminal. Dual use 2. The integrated circuit device described in claim i, the first circuit is a logic circuit, a digital circuit or a memory circuit. "3_ The integrated circuit device as described in the scope of the patent application, the second circuit is a logic circuit, a digital circuit or a circuit. 〃 4 · The integrated circuit according to the scope of claim patent The connection layer L includes a first metal layer, a second metal layer and a second metal pad, and the dielectric layer is located between the first metal pad and the second metal pad. The integrated circuit device of the fourth aspect of the invention, wherein the "the first metal pad has a wire bonding region and a conducting region, the first member, the fourth conductive region penetrating the dielectric layer and connecting the first metal germanium. And the second metal pad. 6. The integrated circuit device of claim 5, wherein the conductive region is located on one side of the wire bonding region. 7. The integrated circuit device of claim 5, wherein the conductive region surrounds the wire bonding region. 8. The integrated circuit device of claim 5, wherein the second metal pad has a plurality of openings located below the wire bonding area. 9. The integrated circuit device of claim 4, wherein the first metal pad and the second metal pad are made of copper. 10. The integrated circuit device according to claim 4, wherein the first metal pad is made of aluminum, and the second metal pad is made of copper. The integrated circuit device of claim 1, wherein the second inner pad comprises a first metal pad, a second metal pad and an &amp; electric layer, the first metal pad The second metal pad is connected to the dielectric layer between the first metal pad and the second metal pad. 12. The integrated circuit device of claim 1, wherein the external pad comprises a first metal pad, a second metal pad and a dielectric layer, the first metal pad electrically connecting the first a metal pad, the dielectric layer being located between the first metal pad and the second metal pad. 13. The integrated circuit device of claim </ RTI> wherein the surface of the substrate has a line clearance area surrounding the outer edge of the outer pad and the outer pad The outer edge is between 2 s microns. [9] In the case of the integrated circuit device described in claim 13, the outer edge of the line clearance area and the outer edge of the external (four) turn are 10 i meters.
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TWI424544B (en) 2014-01-21
US8618660B2 (en) 2013-12-31
US9041201B2 (en) 2015-05-26
US20120248606A1 (en) 2012-10-04
US20140048935A1 (en) 2014-02-20

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