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TW201234664A - Semiconductor light emitting device and method for manufacturing same - Google Patents

Semiconductor light emitting device and method for manufacturing same Download PDF

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Publication number
TW201234664A
TW201234664A TW100131311A TW100131311A TW201234664A TW 201234664 A TW201234664 A TW 201234664A TW 100131311 A TW100131311 A TW 100131311A TW 100131311 A TW100131311 A TW 100131311A TW 201234664 A TW201234664 A TW 201234664A
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Taiwan
Prior art keywords
protective film
layer
contact electrode
opening
light emitting
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TW100131311A
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Chinese (zh)
Inventor
Yuko Kato
Hidefumi Yasuda
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Toshiba Kk
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Publication of TW201234664A publication Critical patent/TW201234664A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/832—Electrodes characterised by their material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/032—Manufacture or treatment of electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/831—Electrodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/8506—Containers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/852—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/855—Optical field-shaping means, e.g. lenses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls

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  • Led Device Packages (AREA)

Abstract

According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, an insulating film, a p-side contact electrode, an n-side contact electrode, a p-side metal protective film, and an n-side metal protective film. The semiconductor layer includes alight emitting layer. A second surface of the semiconductor layer is formed on a side opposite to the first surface. The second surface has a light emitting portion including the light emitting layer and a non-light emitting portion not including the light emitting layer. The p-side contact electrode is provided in contact with the light emitting portion inside a first opening of the insulating film. The n-side contact electrode is provided in contact with the non-light emitting portion inside a second opening of the insulating film. The p-side metal protective film covers a top surface and a side surface of the p-side contact electrode. The n-side metal protective film covers a top surface and a side surface of the n-side contact electrode.

Description

201234664 六、發明說明： 【發明所屬之技術領域】 此處所述之實施例大致關於半導體發光裝置及其製造 方法。 【先前技術】 在晶圓階段中集合實施封裝處理的晶圓級LED (發光 二極體）封裝技術中，實施形成包括發光層等的半導體層 、以及與該半導體層有歐姆接觸的接觸電極的處理；隨後 ，實施形成互連層、樹脂層、螢光體層等的處理。在形成 接觸電極之後有許多處理的情況中，或在這些處理係許多 步驟情況中，在這些處理中所使用的化學液體等可能會腐 蝕接觸電極。 [專利文獻] [文獻 1] JP-A 2010-141 176 [文獻 2] JP-A 2004- 1 03975 【發明內容】 依據一實施例，半導體發光裝置包括半導體層、絕緣 膜、P側接觸電極 、η側接觸電極 、ρ側金屬保護膜、 及 η側金屬保護膜。 該半導體層包括發光層、第一表面、及第二表面。該 第二表面係形成於該第一表面之相反側上。該第二表面具 -5- 201234664 有包括該發光層的發光部、以及不包括該發光層的非發光 部。該絕緣膜係設置在該第二表面上。該絕緣膜具有與該 發光部連接之第一開口、以及與該非發光部連接之第二開 口。該P側接觸電極係設置與該第一開口內的發光部接觸 。該η側接觸電極係設置與該第二開口內的非發光部接觸 。該Ρ側金屬保護膜覆蓋該Ρ側接觸電極的頂表面和側表 面。該η側金屬保護膜覆蓋該η側接觸電極的頂表面和側 表面。 【實施方式】 將參照圖式說明實施例。將以相同參考標號標示圖式 中相同的元件 。 圖1爲實施例之半導體發光裝置10的示意剖面圖。 半導體發光裝置10包括半.導體層4。半導體層4包 括第一表面4a和形成於在第一表面4a之相反側上之不平 坦結構中的第二表面。在該第二表面側上設置電極、互連 層、及樹脂層。光係主要從在該第二表面之相反側上的第 一表面4a發射到外面。 半導體層4包括第一半導體層1及第二半導體層2。 第一半導體層1及第二半導體層2均包括，例如，第三-五族氮化物半導體。第一半導體層1包括，例如，基礎緩 衝層、η型層等等；且該η型層作用如同橫向方向的電流 路徑。第二半導體層2具有發光層（主動層）3夾在η型 層和Ρ型層之間的堆疊結構。201234664 VI. Description of the Invention: TECHNICAL FIELD The embodiments described herein relate generally to semiconductor light emitting devices and methods of fabricating the same. [Prior Art] In a wafer level LED (Light Emitting Diode) packaging technique in which a package process is performed in a wafer stage, a semiconductor layer including a light emitting layer or the like and a contact electrode having ohmic contact with the semiconductor layer are implemented. Processing; Subsequently, a process of forming an interconnect layer, a resin layer, a phosphor layer, or the like is performed. In the case where there are many processes after the formation of the contact electrode, or in the case of many steps of these processes, the chemical liquid or the like used in these processes may erode the contact electrode. [Patent Document] [Document 1] JP-A 2010-141 176 [Document 2] JP-A 2004- 1 03975 SUMMARY OF THE INVENTION According to an embodiment, a semiconductor light-emitting device includes a semiconductor layer, an insulating film, a P-side contact electrode, The η side contact electrode, the ρ side metal protective film, and the η side metal protective film. The semiconductor layer includes a light emitting layer, a first surface, and a second surface. The second surface is formed on an opposite side of the first surface. The second surface member -5-201234664 has a light-emitting portion including the light-emitting layer, and a non-light-emitting portion not including the light-emitting layer. The insulating film is disposed on the second surface. The insulating film has a first opening connected to the light emitting portion and a second opening connected to the non-light emitting portion. The P-side contact electrode is disposed in contact with the light-emitting portion in the first opening. The n-side contact electrode is disposed in contact with the non-light emitting portion in the second opening. The side metal protective film covers the top surface and the side surface of the side contact electrode. The n-side metal protective film covers a top surface and a side surface of the n-side contact electrode. [Embodiment] An embodiment will be described with reference to the drawings. The same elements in the drawings will be denoted by the same reference numerals. 1 is a schematic cross-sectional view of a semiconductor light emitting device 10 of an embodiment. The semiconductor light emitting device 10 includes a semi-conductor layer 4. The semiconductor layer 4 includes a first surface 4a and a second surface formed in an uneven structure on the opposite side of the first surface 4a. An electrode, an interconnect layer, and a resin layer are provided on the second surface side. The light system is mainly emitted from the first surface 4a on the opposite side of the second surface to the outside. The semiconductor layer 4 includes a first semiconductor layer 1 and a second semiconductor layer 2. Each of the first semiconductor layer 1 and the second semiconductor layer 2 includes, for example, a third-five-nitride semiconductor. The first semiconductor layer 1 includes, for example, a base buffer layer, an n-type layer, and the like; and the n-type layer functions as a current path in the lateral direction. The second semiconductor layer 2 has a stacked structure in which a light-emitting layer (active layer) 3 is sandwiched between an n-type layer and a ruthenium-type layer.

-6 - 201234664 將半導體層4之第二表面圖案化成不平坦結構。該第 二表面包括形成於包括發光層3之突出結構中的發光部5 ，以及不包括發光層3的非發光部6。 P側接觸電極1 3係設置在第二半導體層2的頂表面 (發光部5的頂表面）上。η側接觸電極14係設置在第 一半導體層1的頂表面（非發光部6的頂表面）上。 Ρ側接觸電極13包括，例如，設置在第二半導體層2 之頂表面上的第一鎳（Ni)膜、設置在該第一鎳膜上的銀 (Ag)膜、以及設置在該銀膜上的第二鎳膜。 該第一鎳膜與第二半導體層2之頂表面有歐姆接觸， 第二半導體層2係，例如，第三-五族氮化物半導體。銀 對於600 nrn或更長的光的反射比爲98%，對於接近500 至600nm的光的反射比爲98%，而對於接近450至500nm 的光的反射比爲9 7%，且銀對於可視區域中的波長具有高 反射比。該第二鎳膜在下述之電鍍和濕蝕刻期間防止該銀 膜的硫化。 η側接觸電極14包括，例如，設置在第一半導體層1 之頂表面上的第一鈦（Ti)膜、設置在該第一鈦膜上的鋁 (A1)膜、設置在該鋁膜上的鉅膜、設置在該鉬膜上的第 二鈦膜、以及設置在該第二鈦膜上的鉑（Pt)膜。 該第一鈦膜與第一半導體層1之頂表面有歐姆接觸， 第一半導體層1係，例如，第三-五族氮化物半導體。該 鉬膜作用爲防止其上及其下之金屬形成合金的障壁金屬。 有發光部5之面積大於非發光部6之面積的情況；以 201234664 及發光部5之表面積小於非發光部6之表面積的情況。有 設置在發光部5中的P側接觸電極13之面積大於設置在 非發光部6中的η側接觸電極14之面積的情況；以及有 設置在發光部5中的Ρ側接觸電極13之面積小於設置在 非發光部6中的η側接觸電極14之面積的情況。在圖1 所示之半導體發光裝置10中’發光部5之面積大於非發 光部6之面積。 絕緣膜17係設置在半導體層4之第二表面上。絕緣 膜1 7爲諸如，例如，氧化矽膜的無機膜。絕緣膜1 7覆蓋 部分發光部5的頂表面以及部分非發光部6的頂表面。絕 緣膜17亦覆蓋具有突出結構之發光部5的側表面。 絕緣膜17具有第一開口 17a以及第二開口 17b。第 —開口 17a連接發光部5之頂表面；而第二開口 17b連接 非發光部6之頂表面。 第一開口 1 7a的內壁相對於發光部5之頂表面而傾斜 。具體地，第一閧口 17a之開口區域由發光部5之頂表面 側往絕緣膜1 7之頂表面側增加。換言之，圖1中第一開 口 17a之橫截面形成梯形結構。 同樣地，第二開口 1 7b之內壁相對於非發光部6之頂 表面而傾斜。具體地，第二開口 1 7b之開口區域由非發光 部6之頂表面側往絕緣膜1 7之頂表面側增加。換言之， 圖1中第二開口 1 7b之橫截面形成梯形結構。 在第一開口 17a內，ρ側接觸電極13與發光部5之 頂表面（第二半導體層2之頂表面）具有歐姆接觸。在第 -8- 201234664 二開口 17b內，η側接觸電極14與非發光部6之頂表面 (第一半導體層1之頂表面）具有歐姆接觸。 在發光部5側上的第一開口 17a之底面的平面尺寸大 於P側接觸電極13的平面尺寸；且第一開口 17a之內壁 與P側接觸電極1 3之側表面分離。 在非發光部6側上的第二開口 17b之底面的平面尺寸 大於η側接觸電極14的平面尺寸；且第二開口 17b之內 壁與η側接觸電極14之側表面分離。 絕緣膜1 7較ρ側接觸電極1 3厚；且第一開口 1 7a之 深度較P側接觸電極1 3之厚度大。絕緣膜1 7較η側接觸 電極14厚；且第二開口 17b之深度較η側接觸電極14之 厚度大。 Ρ側金屬保護膜1 5係設置在ρ側接觸電極1 3之頂表 面及側表面上。Ρ側金屬保護膜15亦設置在第一開口 17a 之內壁與P側接觸電極1 3之側表面之間的間隔中的發光 部5的頂表面上。ρ側金屬保護膜15亦設置在第一開口 1 7a之內壁上以塡充該間隔。部分ρ側金屬保護膜1 5亦 被設置以隆起在絕緣膜17的頂表面之上環繞第一開口 1 7 a 〇 換言之’ P側金屬保護膜15具有大於ρ側接觸電極 13及第一開口 17a之平面尺寸的平面尺寸，並覆蓋ρ側 接觸電極13之頂表面及側表面。 圖13A圖解半導體發光裝置1〇之主要元件之平面配 置的範例。圖13B圖解另一平面配置的具體範例。 -9- 201234664 如圖13A及13B所示，p側金屬保護膜15覆蓋p側 接觸電極13的四周或p側接觸電極13的整個側表面。 在圖1中，P側金屬保護膜15自p側接觸電極1 3側 依序包括，例如，第一鈦（Ti)膜、設置在該第一鈦膜上 的鉑（Pt)膜、設置在該鈾膜上的金（Au)膜、以及設置 在該金膜上的第二鈦膜。 在這些膜中’不遭受諸如氧化及硫化之反應的金膜爲 最厚。該第二鈦膜與下述之絕緣層（例如，聚亞醯胺）18 有優異密著性。可使用鎳（N i )膜或鉬（Μ 〇 )膜來取代 該第二鈦膜。 η側金屬保護膜1 6係設置在η側接觸電極1 4之頂表 面及側表面上。η側金屬保護膜16亦設置在第二開口 i7b 之內壁與η側接觸電極1 4之側表面之間的間隔中的非發 光部6的頂表面上。η側金屬保護膜16亦設置在第二開 口 17b之內壁上以塡充該間隔。部分η側金屬保護膜16 亦被設置以隆起在絕緣膜1 7的頂表面之上環繞第二開口 17b。 換言之’π側金屬保護膜16具有大於η側接觸電極 14及第二開口 17b之平面尺寸的平面尺寸，並覆蓋〇側 接觸電極14之頂表面及側表面。如圖13Α及13Β所示， η側金屬保護膜1 6覆蓋η側接觸電極1 4的整個側表面。 η側金屬保護膜1 6較η側接觸電極1 4厚》 在圖丨中’ η側金屬保護膜丨6自η側接觸電極1 4側 依序包括’例如’第一鈦（Ti)膜、設置在該第一鈦膜上 -10- 201234664 的鉑（Pt)膜、設置在該鉑膜上的金（Au)膜、以及設置 在該金膜上的第二鈦膜。 在這些膜中，不遭受諸如氧化及硫化之反應的金膜爲 最厚。該第二鈦膜與下述之絕緣層（例如，聚亞醯胺）18 有優異密著性。可使用鎳（Ni )膜或鉬（Mo )膜來取代 該第二鈦膜。 部分P側金屬保護膜1 5及部分η側金屬保護膜1 6係 以絕緣層1 8覆蓋。絕緣層1 8亦覆蓋絕緣膜1 7及第一半 導體層1之側表面。絕緣層1 8爲，例如，具有優異的超 精細開口之圖案化能力（patternability )的樹脂，例如聚 亞醯胺。或者，可使用諸如氧化矽、氮化矽等的無機物質 作爲絕緣層1 8。 絕緣層1 8具有達到p側金屬保護膜1 5的第一貫孔 1 8a以及達到η側金屬保護膜1 6的第二貫孔1 8b。絕緣層 18在p側金屬保護膜15和η側金屬保護膜16之相反側 上具有互連表面18c。p側重新互連層21和η側重新互連 層22係彼此分離地設置在互連表面18c上。 P側重新互連層21亦設置在第一貫孔18a之內，並 電連接至P側金屬保護膜1 5和p側接觸電極1 3。η側重 新互連層22亦設置在第二貫孔18b之內，並電連接至η 側金屬保護膜1 6和η側接觸電極1 4。ρ側重新互連層2 1 和η側重新互連層22係由，例如，銅（Cu )所製成。 金屬膜1 9係設置在ρ側重新互連層2 1和ρ側金屬保 護膜15之間、以及在ρ側重新互連層21和絕緣層18之 -11 - 201234664 間。金屬膜1 9包括自p側重新互連層2 1側依序設置的銅 (Cu)膜和鈦（Ti)膜。金屬膜19亦設置在η側重新互 連層22和η側金屬保護膜16之間、以及在η側重新互連 層22和絕緣層18之間。 Ρ側金屬柱23係設置在ρ側重新互連層2 1之表面上 ，在Ρ側金屬保護膜1 5之相反側上。金屬膜1 9、ρ側重 新互連層2 1、及ρ側金屬柱23係包括在實施例之ρ側互 連層中。 η側金屬柱24係設置在η側重新互連層22之表面上 ，在η側金屬保護膜16之相反側上。金屬膜1 9、η側重 新互連層22、及η側金屬柱24係包括在實施例之η側互 連層中。 設置樹脂層25作爲在絕緣層18之互連表面18c上、 在P側重新互連層21和η側重新互連層22之間、以及在 Ρ側金屬柱23和η側金屬柱24之間的第二絕緣層。 Ρ側金屬柱23在ρ側重新互連層2 1之相反側上的表 面係自樹脂層25暴露，並作用爲用於固定的ρ側外部端 子。η側金屬柱24在η側重新互連層22之相反側上的表 面係自樹脂層25暴露，並作用爲用於固定的η側外部端 子。Ρ側外部端子和η側外部端子係以諸如焊料、其他金 屬、導電材料等的接合劑結合至形成在固定基板上的墊片 。Ρ側外部端子和η側外部端子係形成在相同表面；且半 導體發光裝置10的固定表面爲實質平坦表面。 隨著Ρ側接觸電極13的面積增加，可能供應具有更 -12- 201234664 均勻分佈的電流至發光部5。發光部5的電流分佈取決於 第一貫孔1 8a的位置和數量。第一貫孔1 8a可在遠離p側 金屬柱23延伸之區域的位置被連接至p側金屬保護膜15 〇 可使用諸如，例如，銅之低電阻金屬來形成P側重新 互連層2 1和p側金屬柱2 3。p側重新互連層2 1和p側金 屬柱23的熱傳導及散熱增加，隨著p側重新互連層2 1和 P側金屬柱23的平面尺寸增加，可以有效率地釋放發光 部5的熱。 η側重新互連層22之在η側金屬保護膜1 6之相反側 上的表面積大於η側接觸電極14之面積。從而，針對設 置在窄於發光部5之非發光部6中的η側接觸電極14, 可透過η側重新互連層22來實現延長至更寬區域的電極 結構。 第一半導體層1透過η側接觸電極14、η側金屬保護 膜16、金屬膜19、及η側重新互連層22而電連接至η側 金屬柱24。包括發光層3的第二半導體層2透過ρ側接 觸電極1 3、ρ側金屬保護膜1 5、金屬膜1 9、及ρ側重新 互連層21而電連接至ρ側金屬柱23。 包括Ρ側重新互連層2 1和ρ側金屬柱2 3的ρ側互連 層較Ρ側接觸電極1 3厚。包括η側重新互連層22和η側 金屬柱24的η側互連層較η側接觸電極14厚。ρ側金屬 柱23較ρ側重新互連層21厚；且η側金屬柱24較η側 重新互連層22厚。ρ側金屬柱23、η側金屬柱24、及塡 -13- 201234664 充於P側金屬柱23和η側金屬柱24之間的樹脂層25增 加半導體發光裝置1〇的機械強度。 可使用銅、金、鎳、銀等作爲ρ側重新互連層21、η 側重新互連層2 2、ρ側金屬柱2 3、及η側金屬柱2 4的材 料。在這些材料中，當使用銅時，可得到與絕緣材料相同 之良好熱傳導性、高度遷移抗性、以及優異附著性。 樹脂層25強化ρ側金屬柱23和η側金屬柱24。令 人期望的是，樹脂層25具有與固定基板之熱膨脹係數相 近或相同的熱膨脹係數。此種樹脂層25之範例包括，例 如，環氧樹脂、矽氧樹脂、氟碳樹脂等。 依據實施例，即使在半導體層4係薄的且沒有支撐半 導體層4的基板的情況中，可能藉由係厚的ρ側金屬柱 23、η側金屬柱24、及樹脂層25來維持機械強度。 在半導體發光裝置10被固定至固定基板的情況中， 透過焊料等施加於半導體層4的壓力可藉由被ρ側金屬柱 23和η側金屬柱24吸收而減輕。 鏡片26和螢光體層27係設置在半導體層4之第一表 面4a上，作爲穿透發射自發光層3之光的透明體。鏡片 26係設置在螢光體層27上。或者，螢光體層27可被設 置於鏡片26上。可能使用僅有螢光體層27或僅有鏡片 26被設置在第一表面4a上的結構。 螢光體層27包括透明樹脂和散佈在該透明樹脂中的 螢光體。螢光體層27能夠吸收發射自發光層3的光以及 發射經過波長轉換的光。因此，半導體發光裝置10能夠 -14- 201234664 發射混合來自發光層3之光和螢光體層27之經過波長轉 換之光的混合光。 例如，在發光層3爲第三-五族氮化物半導體以及螢 光體爲組態成發射黃光的黃色螢光體的情況中，可得到白 色、燈等，如同混合來自發光層3的藍色光以及係螢光體 層27之經過波長轉換之光的黃色光的混合顏色。螢光體 層27可能具有包括多種類型之螢光體（例如，組態成發 射紅光的紅色螢光體、以及組態成發射綠光的綠色螢光體 )的結構。 發射自發光層3的光主要由第一表面4a透過螢光體 層27和鏡片26被發射至外面。 在實施例之半導體發光裝置10中，P側接觸電極13 之除了接觸第二半導體層2的表面以外的表面係以p側金 屬保護膜1 5覆蓋。同樣地，η側接觸電極1 4之除了接觸 第一半導體層1的表面以外的表面係以η側金屬保護膜 16覆蓋。 Ρ側金屬保護膜1 5和η側金屬保護膜1 6保護ρ側接 觸電極13和η側接觸電極14免於受到在形成這些接觸電 極之後所實施的下述過程中所使用的化學液體等的侵害。 Ρ側金屬保護膜1 5和η側金屬保護膜1 6主要包括，例如 ，不遭受諸如氧化及硫化之反應的金（Au )。 P側金屬保護膜15之下表面（在ρ側重新互連層21 側上的表面）具有碟狀結構；邊緣部分係較中央部分升高 °P側金屬保護膜15之下表面具有凹形結構。因此，較 -15- 201234664 容易保護P側接觸電極13，因爲化學液體等沿著輸送的 介面距離較長。因爲P側金屬保護膜15之下表面具有凹 形結構，化學液體不容易溢出到具有凹形結構的部分外° η側金屬保護膜16之下表面（在η側重新互連層22 側上的表面）具有碟狀結構；邊緣部分係較中央部分升高 。η側金屬保護膜16之下表面具有凹形結構。因此’較 容易保護η側接觸電極14，因爲化學液體等沿著輸送的 介面距離較長。因爲η側金屬保護膜16之下表面具有凹 形結構，化學液體不容易溢出到具有凹形結構的部分外。 Ρ側金屬保護膜1 5和η側金屬保護膜1 6的邊緣係上 升的，因爲ρ側金屬保護膜1 5和η側金屬保護膜1 6的邊 緣的外圍上升（擴展）到絕緣膜1 7之上。 金不容易與半導體層4(其係，例如，第三-五族氮 化物半導體）形成歐姆接觸。因而，ρ側接觸電極13和η 側接觸電極14包括與半導體層4有良好歐姆接觸的金屬 。即使在此種金屬容易遭受諸如氧化、硫化等反應的情況 中，仍可防止ρ側接觸電極13和η側接觸電極14的惡化 以及Ρ側接觸電極1 3和η側接觸電極1 4之電阻的增加， 因爲Ρ側接觸電極1 3的頂表面及側表面被ρ側金屬保護 膜1 5所覆蓋且η側接觸電極1 4的頂表面及側表面被η側 金屬保護膜16所覆蓋。因此，可防止半導體發光裝置10 之特性的惡化。 將參照圖2Α至圖9Β說明實施例之半導體發光裝置 10的製ia方法。在下述說明過程的圖式中，圖示部分晶 -16- 201234664 圓階段的區域。 圖2A說明一堆疊體，其中包括第一半導體層1和第 二半導體層2的半導體層4係形成在基板8的主表面上。 第一半導體層1形成在基板8的主表面上；而包括發光層 3的第二半導體層2形成在第—半導體層1之上。第—半 導體層1之接觸基板8的表面成爲半導體層4之第一表面 4 a ° 在第一半導體層1和第二半導體層2係，例如，第 三-五族氮化物半導體的情況中，可使用MOCVD (有機金 屬化學汽相沉積）將該等層沉積在例如，藍寶石基板、矽 基板上。 第一半導體層1包括，例如，基礎緩衝層和η型GaN 層。第二半導體層2包括發光層（主動層）3和p型GaN 層。發光層3可被組態成發出藍色、紫色、藍紫色、紫外 線光等。 接著，藉由，例如，使用未示出之光阻的RIE (反應 性離子蝕刻）移除部分第二半導體層2，如圖2 B所示， 來暴露部分第—半導體層1。第一半導體層1所暴露的部 分成爲不包括發光層3的非發光部6。殘留在突出結構中 的第二半導體層2成爲包括發光層3的發光部5。 接著如圖3A所示，絕緣膜17形成在包括發光部5 和非發光部6之半導體層4的第二表面的整個表面上。絕 緣膜17係，例如，氧化矽膜。 然後，如圖3 B所示，光阻遮罩51形成在絕緣膜17 -17- 201234664 上；且使用光阻遮罩51作爲遮罩來選擇性地蝕刻絕緣膜 1 7。在光阻遮罩51中產生開口 5 1 a。在絕緣膜17中產生 第一開口 17a在開口 51a的下方。第一開口M 7a達到發光 部5的頂表面（第二半導體層2的頂表面）。 接著，在第一開口 17a內形成p側接觸電極13於發 光部5的頂表面上。此時，留下在蝕刻時用來產生第一開 口 17a的光阻遮罩51;並且藉由，例如，使用光阻遮罩 5 1作爲遮罩的汽相沉積來形成p側接觸電極1 3。 絕緣膜17的蝕刻不僅在膜厚方向進行，亦在表面方 向中進行。因此，在絕緣膜17中產生的第一開口 17a的 寬度變成較光阻遮罩51的開口 51a大。絕緣膜17之面向 第一開口 1 7a的部分具有梯形結構。於光阻遮罩5 1之開 口 51a的實質正下方形成p側接觸電極13。因此，在第 一開口 1 7a之內壁和p側接觸電極1 3之側表面之間產生 間隔。 然後，如圖4A所示，在絕緣膜1 7和p側接觸電極 13上形成光阻遮罩61 ;並使用光阻遮罩61作爲遮罩來選 擇性地蝕刻絕緣膜1 7。在光阻遮罩6 1中產生開口 6 U。 在絕緣膜17中產生第二開口 17b在開口 61a的下方。第 二開口 17b達到非發光部6的前表面（第一半導體層1的 前表面）。 接著，在第二開口 1 7b內形成η側接觸電極14於非 發光部6的前表面上。此時，留下在蝕刻時用來產生第二 開口 17b的光阻遮罩61;並且藉由，例如，使用光阻遮-6 - 201234664 The second surface of the semiconductor layer 4 is patterned into an uneven structure. The second surface includes a light-emitting portion 5 formed in a protruding structure including the light-emitting layer 3, and a non-light-emitting portion 6 not including the light-emitting layer 3. The P-side contact electrode 13 is provided on the top surface (the top surface of the light-emitting portion 5) of the second semiconductor layer 2. The n-side contact electrode 14 is provided on the top surface (the top surface of the non-light-emitting portion 6) of the first semiconductor layer 1. The side contact electrode 13 includes, for example, a first nickel (Ni) film disposed on a top surface of the second semiconductor layer 2, a silver (Ag) film disposed on the first nickel film, and a silver film disposed thereon The second nickel film on. The first nickel film is in ohmic contact with the top surface of the second semiconductor layer 2, and the second semiconductor layer 2 is, for example, a third-five-nitride semiconductor. Silver has a reflectance of 98% for 600 nrn or longer, 98% for light near 500 to 600 nm, and 97% for light near 450 to 500 nm, and silver for visible The wavelengths in the region have a high reflectance. The second nickel film prevents vulcanization of the silver film during the plating and wet etching described below. The n-side contact electrode 14 includes, for example, a first titanium (Ti) film disposed on a top surface of the first semiconductor layer 1, an aluminum (Al) film disposed on the first titanium film, and disposed on the aluminum film a giant film, a second titanium film disposed on the molybdenum film, and a platinum (Pt) film disposed on the second titanium film. The first titanium film is in ohmic contact with the top surface of the first semiconductor layer 1, and the first semiconductor layer 1 is, for example, a third-five-nitride semiconductor. The molybdenum film functions as a barrier metal for preventing an alloy formed thereon and below. The case where the area of the light-emitting portion 5 is larger than the area of the non-light-emitting portion 6 is the case where the surface area of the light-emitting portion 5 is smaller than the surface area of the non-light-emitting portion 6 by 201234664. The area of the P-side contact electrode 13 provided in the light-emitting portion 5 is larger than the area of the n-side contact electrode 14 provided in the non-light-emitting portion 6; and the area of the side contact electrode 13 provided in the light-emitting portion 5 It is smaller than the area of the n-side contact electrode 14 provided in the non-light-emitting portion 6. In the semiconductor light-emitting device 10 shown in Fig. 1, the area of the light-emitting portion 5 is larger than the area of the non-light-emitting portion 6. The insulating film 17 is provided on the second surface of the semiconductor layer 4. The insulating film 17 is an inorganic film such as, for example, a hafnium oxide film. The insulating film 17 covers the top surface of the portion of the light-emitting portion 5 and the top surface of the portion of the non-light-emitting portion 6. The insulating film 17 also covers the side surface of the light-emitting portion 5 having the protruding structure. The insulating film 17 has a first opening 17a and a second opening 17b. The first opening 17a is connected to the top surface of the light-emitting portion 5; and the second opening 17b is connected to the top surface of the non-light-emitting portion 6. The inner wall of the first opening 17a is inclined with respect to the top surface of the light-emitting portion 5. Specifically, the opening area of the first opening 17a is increased from the top surface side of the light-emitting portion 5 toward the top surface side of the insulating film 17. In other words, the cross section of the first opening 17a in Fig. 1 forms a trapezoidal structure. Similarly, the inner wall of the second opening 17b is inclined with respect to the top surface of the non-light emitting portion 6. Specifically, the opening area of the second opening 17b is increased from the top surface side of the non-light-emitting portion 6 toward the top surface side of the insulating film 17. In other words, the cross section of the second opening 17b in Fig. 1 forms a trapezoidal structure. In the first opening 17a, the p-side contact electrode 13 has an ohmic contact with the top surface of the light-emitting portion 5 (the top surface of the second semiconductor layer 2). In the second opening 17b of the -8-201234664, the ?-side contact electrode 14 has an ohmic contact with the top surface (the top surface of the first semiconductor layer 1) of the non-light-emitting portion 6. The plane of the bottom surface of the first opening 17a on the side of the light-emitting portion 5 is larger than the plane size of the P-side contact electrode 13; and the inner wall of the first opening 17a is separated from the side surface of the P-side contact electrode 13. The planar size of the bottom surface of the second opening 17b on the side of the non-light-emitting portion 6 is larger than the planar size of the n-side contact electrode 14; and the inner wall of the second opening 17b is separated from the side surface of the n-side contact electrode 14. The insulating film 17 is thicker than the p-side contact electrode 13; and the depth of the first opening 17a is larger than the thickness of the P-side contact electrode 13. The insulating film 17 is thicker than the n-side contact electrode 14; and the depth of the second opening 17b is larger than the thickness of the n-side contact electrode 14. The side metal protective film 15 is provided on the top surface and the side surface of the p-side contact electrode 13. The side metal protective film 15 is also provided on the top surface of the light-emitting portion 5 in the space between the inner wall of the first opening 17a and the side surface of the P-side contact electrode 13. The p-side metal protective film 15 is also disposed on the inner wall of the first opening 17a to fill the space. A portion of the p-side metal protective film 15 is also provided to be raised above the top surface of the insulating film 17 around the first opening 17a. In other words, the 'P-side metal protective film 15 has a larger than p-side contact electrode 13 and the first opening 17a. The planar size of the planar size covers the top surface and the side surface of the p-side contact electrode 13. Fig. 13A illustrates an example of a planar configuration of main elements of the semiconductor light emitting device 1A. FIG. 13B illustrates a specific example of another planar configuration. -9- 201234664 As shown in Figs. 13A and 13B, the p-side metal protective film 15 covers the entire side surface of the p-side contact electrode 13 or the p-side contact electrode 13. In FIG. 1, the P-side metal protective film 15 is sequentially included from the p-side contact electrode 13 side, for example, a first titanium (Ti) film, a platinum (Pt) film provided on the first titanium film, and disposed on A gold (Au) film on the uranium film, and a second titanium film disposed on the gold film. The gold film which does not suffer from reactions such as oxidation and vulcanization in these films is the thickest. The second titanium film has excellent adhesion to the insulating layer (for example, polyammonium) 18 described below. A nickel (N i ) film or a molybdenum (ruthenium) film may be used instead of the second titanium film. The n-side metal protective film 16 is provided on the top surface and the side surface of the n-side contact electrode 14. The n-side metal protective film 16 is also disposed on the top surface of the non-light-emitting portion 6 in the space between the inner wall of the second opening i7b and the side surface of the n-side contact electrode 14. The η side metal protective film 16 is also disposed on the inner wall of the second opening 17b to fill the space. A portion of the n-side metal protective film 16 is also provided to swell around the second opening 17b over the top surface of the insulating film 17. In other words, the 'π side metal protective film 16 has a planar size larger than the planar size of the n-side contact electrode 14 and the second opening 17b, and covers the top surface and the side surface of the side contact electrode 14. As shown in FIGS. 13A and 13B, the n-side metal protective film 16 covers the entire side surface of the n-side contact electrode 14. The η-side metal protective film 16 is thicker than the η-side contact electrode 1-4. In the figure, the η-side metal protective film 丨6 sequentially includes, for example, a first titanium (Ti) film from the η-side contact electrode 14 side, A platinum (Pt) film provided on the first titanium film of -10-201234664, a gold (Au) film provided on the platinum film, and a second titanium film provided on the gold film. Among these films, the gold film which does not suffer from reactions such as oxidation and vulcanization is the thickest. The second titanium film has excellent adhesion to the insulating layer (for example, polyammonium) 18 described below. The second titanium film may be replaced with a nickel (Ni) film or a molybdenum (Mo) film. The partial P-side metal protective film 15 and the partial n-side metal protective film 16 are covered with an insulating layer 18. The insulating layer 18 also covers the side surfaces of the insulating film 17 and the first semiconductor layer 1. The insulating layer 18 is, for example, a resin having excellent patternability of ultrafine openings, such as polyamidamine. Alternatively, an inorganic substance such as ruthenium oxide, tantalum nitride or the like may be used as the insulating layer 18. The insulating layer 18 has a first through hole 18a reaching the p-side metal protective film 15 and a second through hole 18b reaching the n-side metal protective film 16. The insulating layer 18 has an interconnection surface 18c on the opposite side of the p-side metal protective film 15 and the n-side metal protective film 16. The p-side re-interconnect layer 21 and the n-side re-interconnect layer 22 are disposed on the interconnect surface 18c separately from each other. The P-side re-interconnect layer 21 is also disposed within the first through hole 18a, and is electrically connected to the P side metal protective film 15 and the p side contact electrode 13. The n-side heavy interconnect layer 22 is also disposed within the second through hole 18b, and is electrically connected to the n-side metal protective film 16 and the n-side contact electrode 14. The p-side re-interconnect layer 2 1 and the n-side re-interconnect layer 22 are made of, for example, copper (Cu). The metal film 19 is disposed between the p-side re-interconnect layer 2 1 and the p-side metal protective film 15 and between the p-side re-interconnect layer 21 and the insulating layer 18 - 201234664. The metal film 19 includes a copper (Cu) film and a titanium (Ti) film which are sequentially disposed from the p-side re-interconnect layer 2 1 side. The metal film 19 is also disposed between the n-side re-interconnecting layer 22 and the n-side metal protective film 16, and between the n-side re-interconnecting layer 22 and the insulating layer 18. The side metal pillars 23 are provided on the surface of the p-side re-interconnect layer 2 1 on the opposite side of the side metal protective film 15 . The metal film 194, the ρ-side re-interconnect layer 2 1 , and the ρ-side metal pillar 23 are included in the p-side interconnect layer of the embodiment. The n-side metal pillar 24 is provided on the surface of the n-side re-interconnect layer 22 on the opposite side of the n-side metal protective film 16. The metal film 19, the n-side re-interconnect layer 22, and the n-side metal pillar 24 are included in the n-side interconnect layer of the embodiment. The resin layer 25 is disposed as being on the interconnection surface 18c of the insulating layer 18, between the P-side re-interconnecting layer 21 and the n-side re-interconnecting layer 22, and between the Ρ-side metal pillar 23 and the η-side metal pillar 24 The second insulating layer. The surface of the side metal post 23 on the opposite side of the p-side re-interconnect layer 2 1 is exposed from the resin layer 25 and acts as a p-side external terminal for fixing. The surface of the n-side metal pillar 24 on the opposite side of the n-side re-interconnect layer 22 is exposed from the resin layer 25 and functions as a fixed n-side external terminal. The x-side external terminal and the n-side external terminal are bonded to a spacer formed on the fixed substrate with a bonding agent such as solder, other metal, a conductive material, or the like. The x-side external terminal and the n-side external terminal are formed on the same surface; and the fixing surface of the semiconductor lighting device 10 is a substantially flat surface. As the area of the side contact electrode 13 increases, it is possible to supply a current having a uniform distribution of -12 - 201234664 to the light emitting portion 5. The current distribution of the light-emitting portion 5 depends on the position and number of the first constant holes 18a. The first uniform hole 18 8 may be connected to the p-side metal protective film 15 at a position away from the region where the p-side metal pillar 23 extends. The P-side re-interconnect layer 2 1 may be formed using, for example, a low-resistance metal of copper. And p side metal column 2 3 . The heat conduction and heat dissipation of the p-side re-interconnect layer 2 1 and the p-side metal pillar 23 increase, and as the planar dimensions of the p-side re-interconnect layer 2 1 and the P-side metal pillar 23 increase, the light-emitting portion 5 can be efficiently discharged. heat. The surface area of the n-side re-interconnect layer 22 on the opposite side of the n-side metal protective film 16 is larger than the area of the n-side contact electrode 14. Thus, for the n-side contact electrode 14 disposed in the non-light-emitting portion 6 narrower than the light-emitting portion 5, the electrode structure extending to a wider region can be realized by the n-side re-interconnecting layer 22. The first semiconductor layer 1 is electrically connected to the n-side metal pillar 24 through the n-side contact electrode 14, the n-side metal protective film 16, the metal film 19, and the n-side re-interconnect layer 22. The second semiconductor layer 2 including the light-emitting layer 3 is electrically connected to the p-side metal pillar 23 through the p-side contact electrode 13, the p-side metal protective film 15, the metal film 19, and the p-side re-interconnect layer 21. The p-side interconnect layer including the side re-interconnect layer 2 1 and the p-side metal pillar 23 is thicker than the crotch side contact electrode 13. The n-side interconnect layer including the n-side re-interconnect layer 22 and the n-side metal pillar 24 is thicker than the n-side contact electrode 14. The p-side metal pillar 23 is thicker than the p-side re-interconnect layer 21; and the n-side metal pillar 24 is thicker than the n-side re-interconnect layer 22. The p-side metal pillar 23, the n-side metal pillar 24, and the 塡13-201234664 resin layer 25 filled between the P-side metal pillar 23 and the n-side metal pillar 24 increase the mechanical strength of the semiconductor light-emitting device 1A. Copper, gold, nickel, silver, or the like can be used as the material of the p-side re-interconnect layer 21, the n-side re-interconnect layer 2, the p-side metal pillar 23, and the n-side metal pillar 24. Among these materials, when copper is used, the same good thermal conductivity, high migration resistance, and excellent adhesion as the insulating material can be obtained. The resin layer 25 strengthens the p-side metal pillar 23 and the n-side metal pillar 24. It is desirable that the resin layer 25 have a coefficient of thermal expansion similar to or the same as that of the fixed substrate. Examples of such a resin layer 25 include, for example, an epoxy resin, a silicone resin, a fluorocarbon resin, and the like. According to the embodiment, even in the case where the semiconductor layer 4 is thin and there is no substrate supporting the semiconductor layer 4, it is possible to maintain mechanical strength by the thick p-side metal pillar 23, the n-side metal pillar 24, and the resin layer 25. . In the case where the semiconductor light-emitting device 10 is fixed to the fixed substrate, the pressure applied to the semiconductor layer 4 by solder or the like can be alleviated by being absorbed by the p-side metal pillar 23 and the n-side metal pillar 24. The lens 26 and the phosphor layer 27 are provided on the first surface 4a of the semiconductor layer 4 as a transparent body that penetrates the light emitted from the light-emitting layer 3. The lens 26 is disposed on the phosphor layer 27. Alternatively, the phosphor layer 27 can be placed on the lens 26. It is possible to use a structure in which only the phosphor layer 27 or only the lens 26 is disposed on the first surface 4a. The phosphor layer 27 includes a transparent resin and a phosphor dispersed in the transparent resin. The phosphor layer 27 is capable of absorbing light emitted from the light-emitting layer 3 and emitting wavelength-converted light. Therefore, the semiconductor light-emitting device 10 can emit mixed light of the wavelength-converted light from the light of the light-emitting layer 3 and the phosphor layer 27 by -14 - 201234664. For example, in the case where the light-emitting layer 3 is a third-five-nitride semiconductor and the phosphor is a yellow phosphor configured to emit yellow light, white, a lamp, or the like can be obtained as if the blue light from the light-emitting layer 3 is mixed. The mixed color of the colored light and the yellow light of the wavelength-converted light of the phosphor layer 27. The phosphor layer 27 may have a structure including a plurality of types of phosphors (e.g., a red phosphor configured to emit red light, and a green phosphor configured to emit green light). The light emitted from the light-emitting layer 3 is mainly emitted from the first surface 4a through the phosphor layer 27 and the lens 26 to the outside. In the semiconductor light-emitting device 10 of the embodiment, the surface of the P-side contact electrode 13 other than the surface contacting the second semiconductor layer 2 is covered with the p-side metal protective film 15. Similarly, the surface of the n-side contact electrode 14 other than the surface contacting the first semiconductor layer 1 is covered with the n-side metal protective film 16. The side metal protective film 15 and the n-side metal protective film 16 protect the p-side contact electrode 13 and the n-side contact electrode 14 from chemical liquids and the like used in the following processes performed after forming these contact electrodes. Infringement. The side metal protective film 15 and the n-side metal protective film 16 mainly include, for example, gold (Au) which does not suffer from reactions such as oxidation and vulcanization. The lower surface of the P-side metal protective film 15 (the surface on the side of the p-side re-interconnecting layer 21) has a dish-like structure; the edge portion is raised from the central portion; and the lower surface of the P-side metal protective film 15 has a concave structure. . Therefore, the P-side contact electrode 13 is easily protected from -15-201234664 because the distance of the chemical liquid or the like along the transport interface is long. Since the lower surface of the P-side metal protective film 15 has a concave structure, the chemical liquid does not easily overflow to the lower surface of the portion of the outer side of the metal protective film 16 having the concave structure (on the side of the n-side re-interconnecting layer 22) The surface has a dish-like structure; the edge portion is raised from the central portion. The lower surface of the η side metal protective film 16 has a concave structure. Therefore, it is easier to protect the η-side contact electrode 14 because the distance of the chemical liquid or the like along the transport interface is long. Since the lower surface of the η-side metal protective film 16 has a concave structure, the chemical liquid does not easily overflow outside the portion having the concave structure. The edges of the side metal protective film 15 and the n-side metal protective film 16 are raised because the periphery of the edge of the p-side metal protective film 15 and the n-side metal protective film 16 rises (expands) to the insulating film 17 Above. Gold does not readily form an ohmic contact with the semiconductor layer 4, which is, for example, a third-five group of nitride semiconductors. Thus, the p-side contact electrode 13 and the n-side contact electrode 14 include a metal having good ohmic contact with the semiconductor layer 4. Even in the case where such a metal is susceptible to a reaction such as oxidation, vulcanization or the like, deterioration of the p-side contact electrode 13 and the n-side contact electrode 14 and the resistance of the crotch-side contact electrode 13 and the n-side contact electrode 14 can be prevented. The increase is because the top surface and the side surface of the side contact electrode 13 are covered by the p-side metal protective film 15 and the top surface and the side surface of the n-side contact electrode 14 are covered by the n-side metal protective film 16. Therefore, deterioration of characteristics of the semiconductor light emitting device 10 can be prevented. A method of manufacturing the semiconductor light-emitting device 10 of the embodiment will be described with reference to Figs. 2A to 9B. In the diagram of the process described below, the area of the partial phase -16 - 201234664 round phase is illustrated. Fig. 2A illustrates a stacked body in which a semiconductor layer 4 including a first semiconductor layer 1 and a second semiconductor layer 2 is formed on a main surface of a substrate 8. The first semiconductor layer 1 is formed on the main surface of the substrate 8; and the second semiconductor layer 2 including the light-emitting layer 3 is formed over the first semiconductor layer 1. The surface of the contact substrate 8 of the first semiconductor layer 1 becomes the first surface 4 a of the semiconductor layer 4 in the case of the first semiconductor layer 1 and the second semiconductor layer 2, for example, a third-five-nitride semiconductor, The layers may be deposited on, for example, a sapphire substrate, a tantalum substrate using MOCVD (Organic Metal Chemical Vapor Deposition). The first semiconductor layer 1 includes, for example, a base buffer layer and an n-type GaN layer. The second semiconductor layer 2 includes a light emitting layer (active layer) 3 and a p-type GaN layer. The luminescent layer 3 can be configured to emit blue, purple, blue-violet, ultraviolet light, or the like. Next, a portion of the second semiconductor layer 2 is removed by, for example, RIE (Reactive Ion Etching) using a photoresist not shown, as shown in Fig. 2B, to expose a portion of the first semiconductor layer 1. The portion exposed by the first semiconductor layer 1 becomes the non-light emitting portion 6 excluding the light emitting layer 3. The second semiconductor layer 2 remaining in the protruding structure becomes the light-emitting portion 5 including the light-emitting layer 3. Next, as shown in FIG. 3A, an insulating film 17 is formed on the entire surface of the second surface of the semiconductor layer 4 including the light-emitting portion 5 and the non-light-emitting portion 6. The insulating film 17 is, for example, a hafnium oxide film. Then, as shown in Fig. 3B, a photoresist mask 51 is formed on the insulating film 17-17-201234664; and the insulating film 17 is selectively etched using the photoresist mask 51 as a mask. An opening 5 1 a is created in the photoresist mask 51. A first opening 17a is formed in the insulating film 17 below the opening 51a. The first opening M 7a reaches the top surface of the light-emitting portion 5 (the top surface of the second semiconductor layer 2). Next, a p-side contact electrode 13 is formed on the top surface of the light-emitting portion 5 in the first opening 17a. At this time, the photoresist mask 51 for generating the first opening 17a at the time of etching is left; and the p-side contact electrode 13 is formed by, for example, vapor deposition using the photoresist mask 51 as a mask. . The etching of the insulating film 17 is performed not only in the film thickness direction but also in the surface direction. Therefore, the width of the first opening 17a generated in the insulating film 17 becomes larger than the opening 51a of the photoresist mask 51. The portion of the insulating film 17 facing the first opening 17a has a trapezoidal structure. The p-side contact electrode 13 is formed substantially directly below the opening 51a of the photoresist mask 51. Therefore, a space is generated between the inner wall of the first opening 17a and the side surface of the p-side contact electrode 13. Then, as shown in Fig. 4A, a photoresist mask 61 is formed on the insulating film 17 and the p-side contact electrode 13, and the insulating film 17 is selectively etched using the photoresist mask 61 as a mask. An opening 6 U is created in the photoresist mask 61. A second opening 17b is formed in the insulating film 17 below the opening 61a. The second opening 17b reaches the front surface of the non-light-emitting portion 6 (the front surface of the first semiconductor layer 1). Next, an n-side contact electrode 14 is formed on the front surface of the non-light-emitting portion 6 in the second opening 17b. At this time, the photoresist mask 61 for generating the second opening 17b at the time of etching is left; and by, for example, using a photoresist

-18- 201234664 罩61作爲遮罩的汽相沉積.來形成n側接觸電極： 絕緣膜1 7的蝕刻不僅在膜厚方向進行，亦 向中進行。因此，在絕緣膜17中產生的第二開 寬度變成較光阻遮罩61的開口 61a大。絕緣膜 第二開口 17b的部分具有梯形結構。於光阻遮罩 口 61a的實質正下方形成η側接觸電極14。因 二開口 1 7b之內壁和η側接觸電極1 4之側表面 間隔。 可首先產生第二開口 1 7b ;且可在ρ側接角 之前形成η側接觸電極1 4。 可藉由將相同的光阻遮罩51用於第一開口 刻及Ρ側接觸電極1 3之形成，而減少處理過程 同樣地，可藉由將相同的光阻遮罩61用於第二 之蝕刻及η側接觸電極14之形成，而減少處理 目。 可想像到同時產生第一開口 1 7a和第二開口 後，在P側接觸電極1 3和η側接觸電極14之材 情況中，選自第一開口 1 7a和第二開口 1 7b之一 阻遮罩所覆蓋：且在此階段中，P側接觸電極1 : 接觸電極14形成在另一個開口中。然而’在產 以光阻遮罩覆蓋該開口的情況中’有機膜可能不 殘留在該開口的底面上。此可能導致接觸電極和 之間的接觸電阻的增加。 在實施例中，接續開口之蝕刻’使用相同的 I 4 〇 在表面方 口 17b 的 1 7之面向 :61之開 此，在第 之間產生 爵電極 13 17a之蝕 的數目。 開口 17b 過程的數 17b。然 料不同的 者可被光 3或η側 生開口並 受期望的 半導體層 光阻遮罩 -19- 201234664 形成接觸電阻。因此’該開口之底面並未被光阻遮罩覆 。因而，接觸電極可被形成於暴露的表面上，如同在蝕 過後一般；且可抑制接觸電阻的增加。 可同時產生第一開口 17a和第二開口 17b;在這些 口的蝕刻中所使用的光阻遮罩可保留如原狀：且接續該 刻，可由相同材料同時形成P側接觸電極1 3和η側接 電極1 4。 然後，在移除用於蝕刻絕緣膜1 7以及形成接觸電 的光阻遮罩之後，在絕緣膜17上形成光阻遮罩52，如 4Β所示。在光阻遮罩52中產生開口 52a和開口 52b。 形成光阻遮罩5 2，使得絕緣膜1 7之一部分自光阻 罩52之開口 52a和開口 52b暴露。在圖4B中，形成光 遮罩52，使得暴露第一開口 17a之內壁、第二開口 1 之內壁、及絕緣膜17之平坦部分（頂表面）。 接著，使用光阻遮罩52作爲遮罩來形成p側金屬 護膜1 5和η側金屬保護膜1 6。使用，例如，汽相沉積 同時形成Ρ側金屬保護膜1 5和η側金屬保護膜1 6。 光阻遮罩52中所產生的一個開口 52a係產生於絕 膜17中所產生的第一開口 17a的上方；且開口 52a的 度較第一開口 17a的寬度寬。p側接觸電極13之頂表 係暴露於開口 52a之底部部分。p側金屬保護膜15係 成於開口 52a之底部部分上。因此，p側金屬保護膜 覆蓋P側接觸電極13之頂表面。 如上所述，在第一開口 1 7a之內壁與p側接觸電 蓋 刻 開 蝕 觸 極 圖 遮 阻 7b 保 來 緣 寬 面 形 15 極 -20- 201234664 1 3之側表面之間產生間隔。該間隔亦暴露於開口 52a之 底部部分。因此，p側金屬保護膜1 5塡充該間隔並覆蓋P 側接觸電極1 3之側表面。 P側金屬保護膜15覆蓋在絕緣膜17之頂表面上延伸 自第一開口 17a之內壁的階梯狀部分；且p側金屬保護膜 15之平面尺寸大於p側接觸電極13之平面尺寸。第一開 口 1 7a之內壁係與p側接觸電極1 3之側表面分離。因此 ，在形成P側金屬保護膜1 5之前的階段中，p側接觸電 極13在厚度方向的整個側表面係暴露的。因此，p側金 屬保護膜15可完全地覆蓋p側接觸電極13之所有的暴露 表面。此時，P側金屬保護膜15具有凹形結構。 光阻遮罩52中所產生的另一個開口 52b係產生於絕 緣膜17中所產生的第二開口 17b的上方；且開口 52b的 寬度較第二開口 17b的寬度寬。η側接觸電極14之頂表 面係暴露於開口 5 2b之底部部分》η側金屬保護膜1 6係 形成於開口 52b之底部部分上。因此，η側金屬保護膜16 覆蓋η側接觸電極1 4之頂表面。 如上所述，在第二開口 17b之內壁與η側接觸電極 14之側表面之間產生間隔。該間隔亦暴露於開口 52b之 底部部分。因此，η側金屬保護膜1 6塡充該間隔並覆蓋η 側接觸電極1 4之側表面。 η側金屬保護膜16覆蓋在絕緣膜17之頂表面上延伸 自第二開口 17b之內壁的階梯狀部分；且η側金屬保護膜 16之平面尺寸大於η側接觸電極14之平面尺寸。第二開-18- 201234664 The cover 61 is vapor-deposited as a mask to form an n-side contact electrode: The etching of the insulating film 17 is performed not only in the film thickness direction but also in the middle direction. Therefore, the second opening width generated in the insulating film 17 becomes larger than the opening 61a of the photoresist mask 61. The portion of the second opening 17b of the insulating film has a trapezoidal structure. The n-side contact electrode 14 is formed substantially directly below the photoresist mask opening 61a. The inner wall of the two openings 17b and the side surface of the n-side contact electrode 14 are spaced apart. The second opening 17b may be first formed; and the n-side contact electrode 14 may be formed before the p-side angle. The same photoresist mask 61 can be used for the second process by using the same photoresist mask 51 for the first opening and the side contact electrode 13 to be formed. Etching and formation of the n-side contact electrode 14 reduces the processing purpose. It is conceivable that, in the case where the first opening 17a and the second opening are simultaneously generated, in the case of the material of the P-side contact electrode 13 and the η-side contact electrode 14, one selected from the first opening 17a and the second opening 17b Covered by the mask: and in this stage, the P-side contact electrode 1: The contact electrode 14 is formed in the other opening. However, the organic film may not remain on the bottom surface of the opening in the case where the photoresist mask is used to cover the opening. This may result in an increase in contact resistance between the contact electrodes and . In the embodiment, the etching of the subsequent openings ' uses the same I 4 〇 in the surface of the surface of the surface 17b of the surface 17: 61, which produces the number of etched electrodes 13 17a between the first. Number 17b of the opening 17b process. However, different ones can be opened by the light 3 or η and exposed by the desired semiconductor layer photoresist mask -19- 201234664 to form a contact resistance. Therefore, the bottom surface of the opening is not covered by the photoresist. Thus, the contact electrode can be formed on the exposed surface as if after the etching; and the increase in contact resistance can be suppressed. The first opening 17a and the second opening 17b may be simultaneously generated; the photoresist mask used in the etching of the openings may remain as it is: and thereafter, the P-side contact electrodes 13 and η sides may be simultaneously formed from the same material Connect the electrode 14 . Then, after the photoresist mask for etching the insulating film 17 and forming the contact electric power is removed, a photoresist mask 52 is formed on the insulating film 17, as shown in Fig. 4 . An opening 52a and an opening 52b are formed in the photoresist mask 52. A photoresist mask 52 is formed such that a portion of the insulating film 17 is exposed from the opening 52a and the opening 52b of the photoresist mask 52. In Fig. 4B, a light mask 52 is formed such that the inner wall of the first opening 17a, the inner wall of the second opening 1, and the flat portion (top surface) of the insulating film 17 are exposed. Next, the p-side metal film 15 and the n-side metal film 16 are formed using the photoresist mask 52 as a mask. The side metal protective film 15 and the ? side metal protective film 16 are simultaneously formed using, for example, vapor deposition. An opening 52a produced in the photoresist mask 52 is generated above the first opening 17a formed in the insulating film 17; and the opening 52a is wider than the width of the first opening 17a. The top surface of the p-side contact electrode 13 is exposed to the bottom portion of the opening 52a. The p-side metal protective film 15 is formed on the bottom portion of the opening 52a. Therefore, the p-side metal protective film covers the top surface of the P-side contact electrode 13. As described above, the inner wall of the first opening 17a is in contact with the p-side of the cover, and the contact between the side surface of the surface of the first surface of the first surface of the first opening 17a is etched. This interval is also exposed to the bottom portion of the opening 52a. Therefore, the p-side metal protective film 15 fills the space and covers the side surface of the P-side contact electrode 13. The P-side metal protective film 15 covers a stepped portion extending from the inner wall of the first opening 17a on the top surface of the insulating film 17; and the planar size of the p-side metal protective film 15 is larger than the planar size of the p-side contact electrode 13. The inner wall of the first opening 1 7a is separated from the side surface of the p-side contact electrode 13. Therefore, in the stage before the formation of the P-side metal protective film 15, the p-side contact electrode 13 is exposed on the entire side surface in the thickness direction. Therefore, the p-side metal protective film 15 can completely cover all the exposed surfaces of the p-side contact electrode 13. At this time, the P-side metal protective film 15 has a concave structure. The other opening 52b generated in the photoresist mask 52 is generated above the second opening 17b which is formed in the insulating film 17, and the width of the opening 52b is wider than the width of the second opening 17b. The top surface of the η-side contact electrode 14 is exposed to the bottom portion of the opening 52b. The η-side metal protective film 16 is formed on the bottom portion of the opening 52b. Therefore, the n-side metal protective film 16 covers the top surface of the n-side contact electrode 14. As described above, a space is generated between the inner wall of the second opening 17b and the side surface of the n-side contact electrode 14. This interval is also exposed to the bottom portion of the opening 52b. Therefore, the n-side metal protective film 16 fills the space and covers the side surface of the n-side contact electrode 14. The n-side metal protective film 16 covers a stepped portion extending from the inner wall of the second opening 17b on the top surface of the insulating film 17; and the planar size of the n-side metal protective film 16 is larger than the planar size of the n-side contact electrode 14. Second open

S -21 - 201234664 口 17b之內壁係與η側接觸電極14之側表面分離。因此 ，在形成η側金屬保護膜1 6之前的階段中，η側接觸電 極1 4在厚度方向的整個側表面係暴露的。因此，η側金 屬保護膜16可完全地覆蓋η側接觸電極14之所有的暴露 表面。此時，η側金屬保護膜16具有凹形結構。 然後，移除用於形成Ρ側金屬保護膜1 5和.η側金屬 保護膜16的光阻遮罩52(圖5Α)。 接續如圖5 Β所示，藉由，例如，使用光阻遮罩5 3的 反應性離子蝕刻（RIE)來產生穿透第一半導體層1的溝 槽62以達到基板8。在光阻遮罩53中產生開口 53a ;且 在開口 53a之下產生溝槽62。 溝槽62係產生於切割區域中，該切割區域係形成於 ，例如，在晶圓階段中之基板8上的晶格結構中。溝槽 62亦產生於，例如，晶格結構中，並將半導體層4分割 成在基板8上的複數個片段（clip)。 當形成P側接觸電極1 3、η側接觸電極1 4、p側金屬 保護膜15、及η側金屬保護膜16時所使用的光阻可輕易 地被塗覆至第二表面側上，該第二表面側在形成ρ側接觸 電極1 3、η側接觸電極1 4、ρ側金屬保護膜1 5、及η側 金屬保護膜16之後產生溝槽62的情況中，具有不大的不 平坦。 在形成光阻遮罩53之前，移除切割區域的絕緣膜17 ，如圖5 Α所示。在產生溝槽6 2的蝕刻期間，光阻遮罩 53亦在表面方向中被消耗。換言之，開口 53a之寬度自 -22- 201234664 以實線圖不的位置住以雙點虛線圖不的位置加寬。事先移 除切割區域之絕緣膜17，使得絕緣膜17不會藉由此時開 口 53a之加寬而被暴露。 在藉由光阻遮罩53之消耗而使得切割區域之絕緣膜 17被不期望地暴露的情況中，絕緣膜17實質地成爲之後 的餓刻遮罩；並如圖5B中的虛線所示，容易不期望地形 成一階梯在溝槽62之側壁中（第一半導體層丨之側表面 )。當以雷射剝離或化學濕蝕刻去除來移除下述之基板8 時，此階梯可能造成裂縫發生在半導體層4中。 可藉由事先移除絕緣膜17，使得絕緣膜17不被暴露 於在蝕刻期間加寬的光阻遮罩53之開口 53a內而避免上 述之問題。 溝槽62可在形成p側接觸電極13、η側接觸電極14 、Ρ側金屬保護膜15、及η側金屬保護膜16之前產生。 然後，移除光阻遮罩53 (圖6Α)。 接續如圖6Β所示，在第二表面側上的所有暴露部分 係被絕緣層18所覆蓋；且在絕緣層18中產生第一貫孔 1 8a和第二貫孔1 8b。第一貫孔1 8a達到ρ側金屬保護膜 1 5。第二貫孔1 8b達到η側金屬保護膜1 6 »將絕緣層1 8 塡入溝槽62中。 可使用諸如，例如，光敏聚亞醯胺、苯並環丁烯（ benzocyclobutene )等的有機材料作爲絕緣層1 8。在此情 況中，可不使用光阻而直接實施絕緣層18的曝光和顯影 。或者，可使用諸如氮化矽膜、氧化矽膜等的無機膜作爲 -23- 201234664 絕緣層18»在無機膜的情況中，藉由在圖案化該光阻之 後的蝕刻而得到第一貫孔1 8a及第二貫孔1 8b。 P側金屬保護膜1 5和η側金屬保護膜1 6的最外層表 面係諸如，例如，鈦（Ti )、鎳（Ni )、鉬（Mo )等與 聚亞醯胺有良好密著性的膜。 然後，金屬膜19形成於絕緣層18的頂表面（互連表 面18c)上，如圖7A所示。金屬膜19亦形成於第一貫孔 18a之內壁及底部部分上、以及第二貫孔18b之內壁及底 部部分上。金屬膜19作用爲電源層，其用於之後將實施 的電鍍。 作爲金屬膜1 9，例如，藉由濺鍍先形成鈦（Ti )膜 :接著藉由濺鍍在該鈦膜上形成銅（Cu)膜。 在形成金屬膜19之前，在p側金屬保護膜15暴露於 第一貫孔1 8a的頂表面上、以及η側金屬保護膜1 6暴露 於第二貫孔18b的頂表面上實施濺鍍蝕刻或硏磨。藉此， 移除金屬保護膜15及16之頂表面上造成金屬保護膜15 和16與設置於該等膜之上的互連層之間的接觸電阻增加 的絕緣膜殘留物和氧化物。 藉由將金屬保護膜15及16之最外層表面的鈦（Ti) 膜、鎳（Ni )膜、或鉬（Mo )膜形成爲，例如，1至 20nm薄，則以上述之濺鍍蝕刻或硏磨來移除金屬保護膜 15及16之最外層表面的膜係容易的。 藉由上述之濺鍍蝕刻或硏磨而將金（Au)的清洗表 面暴露於P側金屬保護膜1 5之最外層表面及η側金屬保 -24- 201234664 護膜1 6之最外層表面。藉由在金（Au)的乾淨表面上形 成與金有優越密著性的鈦（Ti)膜，及藉由在該鈦膜上形 成銅（Cu)膜，而形成金屬膜19。藉此，可改善金屬膜 19與金屬保護膜15及16之間的密著性，金屬膜19爲用 於電鍍之電源層。金屬膜19在不使用電鍍形成互連層的 情況中係不需要的。 然後，在金屬膜1 9上選擇性地形成光阻（未示出） ;並使用金屬膜19作爲電源層來實施銅電鍍。 藉此，形成P側重新互連層21和η側重新互連層2 2 ，如圖7Β所示。ρ側重新互連層21和η側重新互連層22 係由’例如，使用電鍍同時形成的銅材料所製成。或者， 可藉由使用濺鍍及/或汽相沉積來形成金屬膜及接著藉由 使用光阻之蝕刻或剝離來圖案化不需要的部分，而形成ρ 側重新互連層2 1和η側重新互連層22。 Ρ側重新互連層21係形成於第一貫孔18a之內及形 成於第一貫孔18a四周的金屬膜19上，並透過金屬膜19 .電連接至P側金屬保護膜1 5 » η側重新互連層22係形成 於第二貫孔18b之內及形成於第二貫孔18b四周的金屬膜 19上，並透過金屬膜19電連接至n側金屬保護膜16。 接著’如圖7 Β所示’選擇性地形成光阻5 4 ;並使用 金屬膜19作爲電源層來實施銅電鏟。藉此，形成ρ側金 屬柱23和η側金屬柱24。ρ側金屬柱23係形成於ρ側重 新互連層21上；而η側金屬柱24係形成於η側重新互連 層22上。 -25- 201234664 P側金屬柱2 3和η側金屬柱2 4係由使用電鍍同時形 成的銅材料所製成。或者，可藉由使用濺鍍及/或汽相沉 積來形成金屬膜及接著藉由使用光阻之蝕刻或剝離來圖案 化不需要的部分，而形成ρ側金屬柱23和η側金屬柱24 〇 當形成上述金屬膜1 9時，段差的可覆蓋性容易在絕 緣層18內在之段差（圖7Α中以虛線包圍的部分80及90 )大的部分惡化；且在80及90部分容易發生金屬膜19 之斷裂。 在金屬膜19中發生斷裂的情況中，允許從此斷裂位 置滲透電鍍液體。在圖7Β中，以粗線100圖示電鍍液體 的滲透路徑。 在實施例中，Ρ側接觸電極1 3的頂表面及側表面被ρ 側金屬保護膜15所覆蓋；而η側接觸電極14的頂表面及 側表面被η側金屬保護膜1 6所覆蓋。ρ側金屬保護膜1 5 和η側金屬保護膜16主要包括金（Au)，其具有較差的 諸如氧化及硫化之反應。因此，即使在允許電路液體滲透 的情況中，滲透的電路液體被ρ側金屬保護膜1 5和n側 金屬保護膜1 6阻擋，而不會達到ρ側接觸電極1 3和η側 接觸電極14。因此，可防止ρ側接觸電極1 3和η側接觸 電極14的腐蝕。 如上所述，在絕緣膜17中所產生的第一開口 17a之 內壁及第二開口 17b之內壁爲不垂直於第二表面但相對第 二表面傾斜的錐形表面。因此，以ρ側金屬保護膜15覆 -26- 201234664 膜 〇 屬 接 得 η 保 柱 圖 刻 連 接 膜 側 Ρ 接 25 側 重 蓋第一開口 1 7a之內壁段差的覆蓋性及以n側金屬保護 16覆蓋第二開口 17b之內壁段差的覆蓋性可爲良好的 因此，可藉由避免P側金屬保護膜15的斷裂及η側金 保護膜16的斷裂來完全地保護ρ側接觸電極13和η側 觸電極1 4不受到電鍍液體的侵害。 藉由Ρ側金屬保護膜15較ρ側接觸電極13厚，使 Ρ側金屬保護膜15的斷裂較不容易發生。同樣地，藉由 側金屬保護膜1 6較η側接觸電極14厚，使得η側金屬 護膜16的斷裂較不容易發生。 使用，例如，化學液體來移除被用來作爲ρ側金屬 23和η側金屬柱24之電鑛遮罩的光阻54。然後，如 8 Α所示，使用ρ側重新互連層21、η側重新互連層22 Ρ側金屬柱2 3、及η側金屬柱24作爲遮罩，使用濕蝕 來移除金屬膜19的暴露部分。藉此，分隔ρ側重新互 層21和η側重新互連層22之間透過金屬膜1 9的電連 此時，即使在允許用於移除光阻54及濕蝕刻金屬 19之化學液體滲透的情況中，化學液體的滲透會被ρ 金屬保護膜1 5和η側金屬保護膜1 6阻擋，而不會到達 側接觸電極1 3和η側接觸電極14。因此，可防止ρ側 觸電極1 3和η側接觸電極1 4的腐t虫。 然後，如圖8B所示，在絕緣層1 8上形成樹脂層 作爲第二絕緣層。樹脂層25覆蓋ρ側重新互連層2 1的 表面以及η側重新互連層22的側表面，並塡充在ρ側 -27- 201234664 新互連層21和η側重新互連層22之間。並且’樹 25覆蓋ρ側金屬柱23的側表面以及η側金屬柱24 表面，並塡充在Ρ側金屬柱23和η側金屬柱24之間 作用爲外部端子的Ρ側金屬柱23及η側金屬柱 當固定至固定基板時，係分隔一距離，使得Ρ側金 23及η側金屬柱24不因焊料而彼此短路。 然後，移除基板8 (圖9Α )。可能使用例如雷 離、化學濕蝕刻來移除基板8。具體地，從基板8的 面側朝向第一半導體層1照射雷射光。雷射光具有對 板8以及在第一半導體層1之吸收區域中能傳送的波 當雷射光到達基板8與第一半導體層1之間的介 ，接近介面的第一半導體層1藉由吸收雷射光的能量 解。例如，在第一半導體層1爲GaN的情況中，第 導體層1分解爲鎵（Ga)和氮氣。藉由此分解反應， 板8與第一半導體層1之間產生微間隔；基板8與第 導體層1分離。 藉由針對每個設定區域實施倍增而在整個晶圓上 雷射光的照射；移除基板8。 因爲藉由比半導體層4厚的ρ側金屬柱23、η側 柱24、及樹脂層25來強化形成在基板8之主要表面 上述之堆疊體，因此即使在沒有基板8的情況中維持 階段係可能的。 清洗從其上移除基板8之半導體層4的第一表后 。使用例如鹽酸等來移除附著在第一表面4a的鎵（ 脂層 的側 〇 24， 屬柱 射剝 背表 於基 長。 面時 而分 -半 在基 一半 實施 金屬 上的 晶圓 S 4a Ga ) -28- 201234664 若需要，使用例如KOH (氫氧化鉀）水溶液、TMAH (四甲基氫氧化銨）等來蝕刻第一表面4a。藉此，由於 隨著晶面取向而不同的餓刻率使得第一表面4 a中形成不 平坦（粗糙）。或者，可能藉由在使用光阻之圖案化之後 實施蝕刻而在第一表面4a中形成不平坦。藉由將形成於 第一表面4a中的不平坦而增加光提取效率。 然後，如圖9B所示，螢光體層27和鏡片26係形成 在第一表面4a上以及在切割區域之絕緣層18上。 形成螢光體層27之步驟包括，例如，使用諸如印刷 、裝塡、成型、壓縮成型等方法供應具有分散螢光體顆粒 之液體透明樹脂的步驟，及後續的熱固化步驟。透明樹脂 可傳送從發光層3所發出的光以及由螢光體所發出的光； 並且可使用，例如，諸如矽氧樹脂、丙烯酸樹脂、液體玻 璃等材料。 鏡片26對於從發光層3所發出的光係透明的；並且 可使用’例如，矽氧樹脂、丙烯酸樹脂、玻璃等。 然後，在溝槽62的位置切割樹脂層25、絕緣層1 8、 蛋光體層27、及鏡片26，以切單（singulate)爲複數個 半導體發光裝置10。例如，使用切割刀來實施切割。或 者’使用雷射照射來實施切割。 當切割時，基板8已經被移除。此外，可避免切割時 對半導體層4的損害，因爲半導體層4不存在於係切割區 域的溝槽62中。 -29- 201234664 切單後的半導體發光裝置10可具有包括 層4的單‘晶片結構或是包括複數個半導體層4 構。 不需要針對每個切單後的單獨裝置實施互 並且因爲直到切割之前的上述各步驟係在晶圓 施，因此可能大幅降低生產成本。在切單階段 互連和封裝。因此，可增加生產力；並因而容 〇 依據實施例，p側金屬保護膜1 5和η側 1 6保護ρ側接觸電極1 3和η側接觸電極14 形成這些接觸電極之後所實施的步驟中所使用 等的侵害。Ρ側金屬保護膜1 5和η側金屬保護 護Ρ側接觸電極1 3和η側接觸電極1 4免於在 滲透進絕緣層1 8的硫等的侵害。因此，可防丄 電極13和η側接觸電極14的腐蝕以及電阻增〕 如圖1 〇中所示，在第二半導體層2側上 17a之底部的內壁不需要與ρ側接觸電極13 開。同樣地，在第一半導體層1側上的第二開I 部的內壁不需要與η側接觸電極14之側表面分 在此情況中，同樣藉由形成第一開口 1 7a 形表面而在第一開口 17a之內壁與ρ側接觸電 表面之間產生間隔。可藉由將P側金屬保護膜 間隔而以ρ側金屬保護膜1 5覆蓋ρ側接觸電極 面。 一個半導體 的多晶片結 連及封裝， 階段集體實 中已經完成 易降低價格 金屬保護膜 免於受到在 的化學液體 ;膜16亦保 空氣中受到 t P側接觸 to ° 的第一開口 之側表面分 口 17b之底 開。 之內壁爲錐 極1 3之側 1 5塡入該 1 3之側表 -30- 201234664 同樣地，藉由形成第二開口 17b之內壁爲錐形表面而 在第二開口 1 7b之內壁與η側接觸電極1 4之側表面之間 產生間隔。可藉由將η側金屬保護膜1 6塡入該間隔而以 η側金屬保護膜1 6覆蓋η側接觸電極1 4之側表面。 如圖1所示，藉由將在第二半導體層2側上的第一開 口 17a之底部的內壁與ρ側接觸電極13之側表面分開，ρ 側接觸電極1 3的整個側表面可完全地被p側金屬保護膜 1 5覆蓋。 同樣地，藉由將在第一半導體層1側上的第二開口 1 7b之底部的內壁與η側接觸電極1 4之側表面分開，η側 接觸電極14的整個側表面可完全地被η側金屬保護膜16 覆蓋。 並且，如圖11所示，在第一表面4a上可殘留薄的基 板8。可使用例如用於拋光半導體晶圓背面的硏磨器來硏 磨基板8。 基板8係例如藍寶石基板，並可傳送從氮化物半導體 型發光層發射的光。在此情況中，因爲沒有螢光體層’依 從半導體發光裝置發射具有波長與從該發光層發射之光的 波長相同的光到外面。藉由留下基板8可增加機械強度， 而且結構可具有高可靠度。 此外，如圖12所示，螢光體層27可形成於基板8上 。藉由留下基板8，可以穩定地維持半導體層4，而不需 設置P側互連層、η ·側互連層、及樹脂層。在此情況中’ ρ側金屬保護膜1 5作用爲Ρ側外部端子；而η側金屬保 -31 - 201234664 護膜1 6作用爲η側外部端子。換言之，p側金屬保護膜 15和η側金屬保護膜16以焊料等被接合到固定基板的墊 片。 第一表面4a上並不總是需要基板8、鏡片26、及螢 光體層27之任一項》 下述之紅色螢光體層、黃色螢光體層、綠色螢光體層 、及藍色螢光體層可被使用作爲上述之螢光體層。 紅色螢光體層可包含，例如，.CaAlSiN3 : Eu之以氮 化物爲基的螢光體、或以Si A1 ON爲基的螢光體。 在使用以SiΑΙΟΝ爲基的螢光體的情況中，可使用： (Mi.xj Rx ) aiAlSib,〇ciNdi 組成公式（1 ) (其中Μ爲除了 Si和A1之外的至少一種金屬元素，且 可能期望Μ爲選自Ca及Sr之至少一者；R爲發光中心 元素，且可期望R爲Eu; X、al、bl、cl、及dl滿足下 列關係：x大於0且小於1，a 1大於0.6且小於0.9 5，b 1 大於2且小於3.9，cl大於0.25且小於0.45，dl大於4 且小於5 · 7 )。 藉由使用組成公式（1 )之以SiAlON爲基的螢光體 ，可改善波長轉換效率的溫度特性；並可進一步增加高電 流密集區中的效率。 黃色螢光體層可包含，例如，（Sr，Ca,Ba) 2Si〇4: Eu 之矽酸鹽基螢光體。The inner wall of the S-21 - 201234664 port 17b is separated from the side surface of the n-side contact electrode 14. Therefore, in the stage before the formation of the η-side metal protective film 16 , the η-side contact electrode 14 is exposed on the entire side surface in the thickness direction. Therefore, the n-side metal protective film 16 can completely cover all the exposed surfaces of the n-side contact electrode 14. At this time, the n-side metal protective film 16 has a concave structure. Then, the photoresist mask 52 for forming the side metal protective film 15 and the .n side metal protective film 16 is removed (Fig. 5A). Next, as shown in Fig. 5, the substrate 8 is formed by, for example, reactive ion etching (RIE) using a photoresist mask 5 3 to penetrate the trench 62 of the first semiconductor layer 1. An opening 53a is created in the photoresist mask 53; and a groove 62 is created below the opening 53a. The trenches 62 are created in a dicing region formed, for example, in a lattice structure on the substrate 8 in the wafer stage. The trenches 62 are also formed, for example, in a lattice structure, and the semiconductor layer 4 is divided into a plurality of clips on the substrate 8. The photoresist used when forming the P-side contact electrode 13 , the n-side contact electrode 14 , the p-side metal protective film 15 , and the n-side metal protective film 16 can be easily applied to the second surface side, which The second surface side has a small unevenness in the case where the groove 62 is formed after the formation of the p-side contact electrode 13 , the n-side contact electrode 14 , the p-side metal protective film 15 , and the n-side metal protective film 16 . Before the photoresist mask 53 is formed, the insulating film 17 of the dicing region is removed, as shown in FIG. During the etching that produces the trenches 6, the photoresist mask 53 is also consumed in the surface direction. In other words, the width of the opening 53a is widened from the position where the solid line is not in the range of -22-201234664, and the position of the double-dotted line is not widened. The insulating film 17 of the dicing region is removed in advance so that the insulating film 17 is not exposed by the widening of the opening 53a at this time. In the case where the insulating film 17 of the dicing region is undesirably exposed by the consumption of the photoresist mask 53, the insulating film 17 substantially becomes a hungry mask; and as shown by a broken line in FIG. 5B, It is easy to undesirably form a step in the sidewall of the trench 62 (the side surface of the first semiconductor layer 丨). When the substrate 8 described below is removed by laser lift-off or chemical wet etching removal, this step may cause cracks to occur in the semiconductor layer 4. The above problem can be avoided by removing the insulating film 17 in advance so that the insulating film 17 is not exposed to the opening 53a of the photoresist mask 53 which is widened during etching. The trench 62 can be generated before the formation of the p-side contact electrode 13, the n-side contact electrode 14, the side metal protective film 15, and the n-side metal protective film 16. Then, remove the photoresist mask 53 (Fig. 6Α). Further, as shown in Fig. 6A, all of the exposed portions on the second surface side are covered by the insulating layer 18; and the first through holes 18a and the second through holes 18b are formed in the insulating layer 18. The first uniform hole 18 8a reaches the p side metal protective film 15 . The second through hole 18b reaches the η side metal protective film 16 » The insulating layer 18 is plunged into the groove 62. As the insulating layer 18, an organic material such as, for example, photosensitive polyamidomine, benzocyclobutene or the like can be used. In this case, exposure and development of the insulating layer 18 can be directly performed without using a photoresist. Alternatively, an inorganic film such as a tantalum nitride film, a hafnium oxide film, or the like can be used as the insulating layer 18 of the -23-201234664. In the case of the inorganic film, the first through hole is obtained by etching after patterning the photoresist. 1 8a and the second through hole 1 8b. The outermost surface of the P-side metal protective film 15 and the η-side metal protective film 16 is, for example, titanium (Ti), nickel (Ni), molybdenum (Mo) or the like having good adhesion to polyamine. membrane. Then, a metal film 19 is formed on the top surface (interconnect surface 18c) of the insulating layer 18 as shown in Fig. 7A. The metal film 19 is also formed on the inner and bottom portions of the first through hole 18a, and on the inner and bottom portions of the second through hole 18b. The metal film 19 functions as a power supply layer for electroplating to be performed later. As the metal film 19, for example, a titanium (Ti) film is formed by sputtering: a copper (Cu) film is then formed on the titanium film by sputtering. Before the formation of the metal film 19, sputtering is performed on the top surface of the p-side metal protective film 15 exposed on the first through hole 18a, and the n-side metal protective film 16 is exposed on the top surface of the second through hole 18b. Or ponder. Thereby, the insulating film residues and oxides which cause an increase in contact resistance between the metal protective films 15 and 16 and the interconnect layer provided over the films are removed on the top surfaces of the metal protective films 15 and 16. By forming a titanium (Ti) film, a nickel (Ni) film, or a molybdenum (Mo) film on the outermost surface of the metal protective films 15 and 16 as, for example, 1 to 20 nm thin, the above-described sputtering etching or It is easy to honing to remove the film of the outermost surface of the metal protective films 15 and 16. The gold (Au) cleaning surface is exposed to the outermost surface of the P-side metal protective film 15 and the outermost surface of the η-side metal protective film 16 by sputtering or honing as described above. The metal film 19 is formed by forming a titanium (Ti) film having a superior adhesion to gold on a clean surface of gold (Au) and forming a copper (Cu) film on the titanium film. Thereby, the adhesion between the metal film 19 and the metal protective films 15 and 16 can be improved, and the metal film 19 is a power supply layer for electroplating. The metal film 19 is not required in the case where an interconnection layer is formed without using plating. Then, a photoresist (not shown) is selectively formed on the metal film 19; and copper plating is performed using the metal film 19 as a power source layer. Thereby, the P-side re-interconnect layer 21 and the n-side re-interconnect layer 2 2 are formed as shown in FIG. The p-side re-interconnect layer 21 and the n-side re-interconnect layer 22 are made of, for example, a copper material formed by electroplating at the same time. Alternatively, the p-side re-interconnect layer 2 1 and the η side may be formed by forming a metal film using sputtering and/or vapor deposition and then patterning unnecessary portions by etching or stripping using photoresist. Reconnect the layers 22. The back side re-interconnect layer 21 is formed in the first through hole 18a and formed on the metal film 19 around the first through hole 18a, and is transmitted through the metal film 19. Electrically connected to the P side metal protective film 1 5 » η The side re-interconnect layer 22 is formed in the second through hole 18b and formed on the metal film 19 around the second through hole 18b, and is electrically connected to the n-side metal protective film 16 through the metal film 19. Next, a photoresist 5 is selectively formed as shown in Fig. 7; and a copper shovel is implemented using the metal film 19 as a power source layer. Thereby, the p-side metal pillar 23 and the n-side metal pillar 24 are formed. The p-side metal pillar 23 is formed on the p-side re-interlayer 21; and the n-side metal pillar 24 is formed on the n-side re-interlayer 22. -25- 201234664 The P-side metal post 2 3 and the η-side metal post 24 are made of a copper material which is simultaneously formed by electroplating. Alternatively, the p-side metal pillar 23 and the n-side metal pillar 24 may be formed by forming a metal film using sputtering and/or vapor deposition and then patterning an unnecessary portion by etching or peeling using a photoresist. When the above-mentioned metal film 19 is formed, the coverage of the step is likely to be deteriorated in the portion of the insulating layer 18 which is large in the step (the portions 80 and 90 surrounded by the broken line in Fig. 7A); and the metal is likely to occur in the portions 80 and 90. The film 19 is broken. In the case where breakage occurs in the metal film 19, the plating liquid is allowed to permeate from the fracture position. In Fig. 7A, the permeation path of the plating liquid is illustrated by a thick line 100. In the embodiment, the top surface and the side surface of the side contact electrode 13 are covered by the p side metal protective film 15; and the top surface and the side surface of the n side contact electrode 14 are covered by the n side metal protective film 16. The p-side metal protective film 15 and the n-side metal protective film 16 mainly include gold (Au) which has a poor reaction such as oxidation and vulcanization. Therefore, even in the case where the permeation of the circuit liquid is allowed, the infiltrated circuit liquid is blocked by the p-side metal protective film 15 and the n-side metal protective film 16 without reaching the p-side contact electrode 13 and the n-side contact electrode 14 . Therefore, corrosion of the p-side contact electrode 13 and the n-side contact electrode 14 can be prevented. As described above, the inner wall of the first opening 17a and the inner wall of the second opening 17b which are formed in the insulating film 17 are tapered surfaces which are not perpendicular to the second surface but are inclined with respect to the second surface. Therefore, the ρ side metal protective film 15 is covered by -26-201234664, and the film is bonded to the η 保 图 连接 连接 连接 连接 及 及The covering property of the inner wall section covering the second opening 17b can be good. Therefore, the p-side contact electrode 13 can be completely protected by avoiding the breakage of the P-side metal protective film 15 and the breakage of the η-side gold protective film 16. The η side contact electrode 14 is not damaged by the plating liquid. Since the crotch side metal protective film 15 is thicker than the p side contact electrode 13, the breakage of the crotch side metal protective film 15 is less likely to occur. Similarly, the side metal protective film 16 is thicker than the n-side contact electrode 14, so that the breakage of the n-side metal film 16 is less likely to occur. The photoresist 54 used as the electro-mineral mask of the p-side metal 23 and the n-side metal pillar 24 is removed using, for example, a chemical liquid. Then, as shown in FIG. 8 , the p-side re-interconnect layer 21, the n-side re-interconnect layer 22, the side-side metal pillars 23, and the n-side metal pillars 24 are used as masks, and the metal film 19 is removed by wet etching. The exposed part. Thereby, the electrical connection between the p-side re-interlayer 21 and the n-side re-interlayer 22 through the metal film 19 is separated, even at the time of allowing the chemical liquid for the removal of the photoresist 54 and the wet-etched metal 19 to penetrate. In the case, the penetration of the chemical liquid is blocked by the p metal protective film 15 and the n side metal protective film 16 without reaching the side contact electrode 13 and the n side contact electrode 14. Therefore, the rot of the ρ side contact electrode 13 and the η side contact electrode 14 can be prevented. Then, as shown in Fig. 8B, a resin layer is formed on the insulating layer 18 as a second insulating layer. The resin layer 25 covers the surface of the p-side re-interconnect layer 21 and the side surface of the n-side re-interconnect layer 22, and is filled with the p-side 27-201234664 new interconnect layer 21 and the n-side re-interconnect layer 22 between. And the 'tree 25 covers the side surface of the ρ-side metal pillar 23 and the surface of the η-side metal pillar 24, and fills the Ρ-side metal pillar 23 and η acting as external terminals between the Ρ-side metal pillar 23 and the η-side metal pillar 24 When the side metal pillars are fixed to the fixed substrate, they are separated by a distance such that the side gold 23 and the η side metal pillars 24 are not short-circuited to each other by solder. Then, the substrate 8 is removed (Fig. 9A). It is possible to remove the substrate 8 using, for example, a sharp, chemical wet etch. Specifically, the laser light is irradiated from the surface side of the substrate 8 toward the first semiconductor layer 1. The laser light has a wave between the plate 8 and the absorption region in the absorption region of the first semiconductor layer 1 as the laser light reaches between the substrate 8 and the first semiconductor layer 1, and the first semiconductor layer 1 close to the interface is absorbed by the thunder. The energy solution of the light. For example, in the case where the first semiconductor layer 1 is GaN, the first conductor layer 1 is decomposed into gallium (Ga) and nitrogen. By this decomposition reaction, a fine space is formed between the plate 8 and the first semiconductor layer 1; the substrate 8 is separated from the first conductor layer 1. The irradiation of the laser light over the entire wafer is performed by performing multiplication for each set region; the substrate 8 is removed. Since the above-described stacked body formed on the main surface of the substrate 8 is reinforced by the p-side metal pillar 23, the n-side pillar 24, and the resin layer 25 which are thicker than the semiconductor layer 4, the sustaining phase is possible even in the absence of the substrate 8. of. After cleaning the first sheet of the semiconductor layer 4 from which the substrate 8 is removed. The gallium attached to the first surface 4a is removed using, for example, hydrochloric acid or the like (the side 〇 24 of the lipid layer is a base stripe of the base length. The surface is sometimes divided - half of the wafer S 4a is implemented on the base half of the metal Ga ) -28- 201234664 If necessary, the first surface 4a is etched using, for example, an aqueous solution of KOH (potassium hydroxide), TMAH (tetramethylammonium hydroxide) or the like. Thereby, unevenness (roughness) is formed in the first surface 4a due to the different hunting rate with the orientation of the crystal faces. Alternatively, unevenness may be formed in the first surface 4a by performing etching after patterning using a photoresist. The light extraction efficiency is increased by the unevenness formed in the first surface 4a. Then, as shown in Fig. 9B, the phosphor layer 27 and the lens 26 are formed on the first surface 4a and on the insulating layer 18 of the dicing region. The step of forming the phosphor layer 27 includes, for example, a step of supplying a liquid transparent resin having dispersed phosphor particles using a method such as printing, mounting, molding, compression molding, and the like, and a subsequent heat curing step. The transparent resin can transmit light emitted from the light-emitting layer 3 and light emitted from the phosphor; and, for example, a material such as a silicone resin, an acrylic resin, a liquid glass or the like can be used. The lens 26 is transparent to the light emitted from the light-emitting layer 3; and, for example, a silicone resin, an acrylic resin, glass, or the like can be used. Then, the resin layer 25, the insulating layer 18, the egg layer 27, and the lens 26 are cut at the position of the groove 62 to singulate into a plurality of semiconductor light-emitting devices 10. For example, a cutting knife is used to perform the cutting. Or use laser irradiation to perform the cutting. When cutting, the substrate 8 has been removed. Further, damage to the semiconductor layer 4 at the time of dicing can be avoided because the semiconductor layer 4 is not present in the trench 62 of the dicing region. -29- 201234664 The semiconductor light emitting device 10 after singulation may have a single 'wafer structure including layer 4 or a plurality of semiconductor layers. It is not necessary to implement mutual for each individual device after singulation and because the above steps until the cutting are performed on the wafer, it is possible to greatly reduce the production cost. Interconnect and package in a single stage. Therefore, productivity can be increased; and thus, according to the embodiment, the p-side metal protective film 15 and the n-side 16 protect the p-side contact electrode 13 and the n-side contact electrode 14 in the steps performed after forming these contact electrodes Use such violations. The side metal protective film 15 and the η side metal protection rim side contact electrode 1 3 and η side contact electrode 1 4 are protected from the intrusion of sulfur or the like into the insulating layer 18. Therefore, corrosion and resistance increase of the anti-cable electrode 13 and the n-side contact electrode 14 are as shown in FIG. 1A, and the inner wall of the bottom portion 17a on the side of the second semiconductor layer 2 does not need to be opened with the p-side contact electrode 13. . Similarly, the inner wall of the second opening portion I on the side of the first semiconductor layer 1 does not need to be separated from the side surface of the n-side contact electrode 14, in this case as well by forming the first opening 17a surface. A gap is formed between the inner wall of the first opening 17a and the p-side contact electric surface. The p-side contact electrode surface can be covered with the p-side metal protective film 15 by spacing the P-side metal protective film. A multi-chip junction and package of a semiconductor, the stage has been completed to reduce the price of the metal protective film from the chemical liquid; the film 16 also protects the side surface of the first opening of the t-side contact to ° in the air The bottom of the split port 17b is opened. The inner wall is the side of the tapered pole 1 3 and the side of the 1 3 is immersed in the side of the 1 3 - 201334664. Similarly, the inner wall of the second opening 17b is formed into a tapered surface within the second opening 17b. A gap is formed between the wall and the side surface of the n-side contact electrode 14. The side surface of the n-side contact electrode 14 can be covered with the η-side metal protective film 16 by immersing the η-side metal protective film 16 into the space. As shown in Fig. 1, by separating the inner wall of the bottom portion of the first opening 17a on the side of the second semiconductor layer 2 from the side surface of the p-side contact electrode 13, the entire side surface of the p-side contact electrode 13 can be completely The ground is covered by the p-side metal protective film 15 . Similarly, by separating the inner wall of the bottom of the second opening 17b on the side of the first semiconductor layer 1 from the side surface of the n-side contact electrode 14, the entire side surface of the n-side contact electrode 14 can be completely The η side metal protective film 16 is covered. Further, as shown in Fig. 11, a thin substrate 8 may remain on the first surface 4a. The substrate 8 can be honed using, for example, a honing machine for polishing the back side of the semiconductor wafer. The substrate 8 is, for example, a sapphire substrate, and can transmit light emitted from the nitride semiconductor type light-emitting layer. In this case, since the phosphor layer does not emit light having the same wavelength as that of the light emitted from the light-emitting layer, the semiconductor light-emitting device is emitted to the outside. The mechanical strength can be increased by leaving the substrate 8, and the structure can have high reliability. Further, as shown in FIG. 12, a phosphor layer 27 may be formed on the substrate 8. By leaving the substrate 8, the semiconductor layer 4 can be stably maintained without providing a P-side interconnect layer, a ?-side interconnect layer, and a resin layer. In this case, the ρ side metal protective film 15 functions as a Ρ side external terminal; and the η side metal - -31 - 201234664 film 16 functions as an η side external terminal. In other words, the p-side metal protective film 15 and the n-side metal protective film 16 are bonded to the spacer of the fixed substrate with solder or the like. The first surface 4a does not always require any of the substrate 8, the lens 26, and the phosphor layer 27. The red phosphor layer, the yellow phosphor layer, the green phosphor layer, and the blue phosphor layer described below. It can be used as the above-mentioned phosphor layer. The red phosphor layer may include, for example, a nitride-based phosphor of .CaAlSiN3:Eu or a phosphor based on Si A1 ON. In the case of using a Si ΑΙΟΝ based phosphor, (Mi.xj Rx ) aiAlSib, 〇ciNdi may be used to form the formula (1) (wherein Μ is at least one metal element other than Si and A1, and possibly It is desirable that Μ is at least one selected from the group consisting of Ca and Sr; R is a luminescent center element, and R may be expected to be Eu; X, al, bl, cl, and dl satisfy the following relationship: x is greater than 0 and less than 1, and a 1 is greater than 0.6 and less than 0.9 5, b 1 is greater than 2 and less than 3.9, cl is greater than 0.25 and less than 0.45, and dl is greater than 4 and less than 5 · 7 ). By using a SiAlON-based phosphor constituting the formula (1), the temperature characteristics of the wavelength conversion efficiency can be improved; and the efficiency in the high current dense region can be further increased. The yellow phosphor layer may comprise, for example, a (Sr, Ca, Ba) 2Si〇4: Eu citrate-based phosphor.

-32- 201234664 綠色螢光體層可包含’例如，（Ba，Ca，Mg)IQ(P〇4)6Cl2 :Eu之齒磷酸鹽基螢光體、或以siAlON爲基的螢光體 〇 在使用以SiAlON爲基的螢光體的情況中，可使用： (M,.x, Rx ) a2AlSib2〇c2Nd2 組成公式（2) (其中Μ爲除了 Si和A1之外的至少一種金屬元素，且 可能期望Μ爲選自Ca及Sr之至少一者；R爲發光中心 元素，且可期望尺爲£\1;乂、32、52、〇2、及（12滿足下 列關係：X大於〇且小於1，a2大於0.93且小於1 .3，b2 大於4.0且小於5.8，c2大於0.6且小於1，d2大於6且 小於1 1 )。 藉由使用組成公式（2)之以SiAlON爲基的螢光體 ，可改善波長轉換效率的溫度特性；並可進一步增加高電 流密集區中的效率。 藍色螢光體可包含，例如，BaMgAl1()017 : Eu之氧基 螢光體。 已說明一些實施例，僅以範例方式表達這些實施例， 而不企圖以這些實施例來限定本發明之範圍。當然，本說 明書所述之創新實施例可以其他形式實施；甚至，可在不 背離本發明之精神下做出本說明書所述之實施例形式上的 各種省略、替代、及修改。隨附之申請專利範圍及其等式 係企圖涵蓋落在本發明之範圍及發明精神內的此等形式或 -33--32- 201234664 The green phosphor layer can contain 'for example, (Ba, Ca, Mg)IQ(P〇4)6Cl2:Eu tooth phosphate-based phosphor, or siAlON-based phosphor 〇 In the case of a SiAlON-based phosphor, (M,.x, Rx) a2AlSib2〇c2Nd2 may be used to form the formula (2) (wherein Μ is at least one metal element other than Si and A1, and may be expected Μ is at least one selected from the group consisting of Ca and Sr; R is a luminescent center element, and may be expected to have a scale of £\1; 乂, 32, 52, 〇2, and (12 satisfy the following relationship: X is greater than 〇 and less than 1, A2 is greater than 0.93 and less than 1.3, b2 is greater than 4.0 and less than 5.8, c2 is greater than 0.6 and less than 1, and d2 is greater than 6 and less than 1 1 ). By using a SiAlON-based phosphor that constitutes formula (2), The temperature characteristics of the wavelength conversion efficiency can be improved; and the efficiency in the high current dense region can be further increased. The blue phosphor can include, for example, BaMgAl1() 017: Eu oxyfluoride. Some embodiments have been described, The embodiments are merely described by way of example, and are not intended to limit the scope of the invention. The invention can be implemented in other forms, and various omissions, substitutions and modifications can be made without departing from the spirit and scope of the invention. The equations are intended to cover such forms or -33- falling within the scope and spirit of the invention.

’I'I

/ I ’I / I201234664 修正。 ， 【圖式簡單說明】 圖1爲一實施例之半導體發光裝置的示意剖面圖。 圖2A至9B爲圖解該實施例之半導體發光裝置之製 造方法的示意剖面圖。 圖10爲另一實施例之半導體發光裝置的示意剖面圖 〇 圖】】爲又另一實施例之半導體發光裝置的示意剖面 圖。 圖12爲再又另一實施例之半導體發光裝置的示意剖 面圖。 圖13A及13B爲圖解該實施例之半導體發光裝置之 主要元件之平面配置的示意剖面圖。 【主要元件符號說明】 1 :第一半導體層 2 :第二半導體層 3 :發光層 4 :半導體層 4a :第一表面 5 :發光部 6 :非發光部 8 :基板 34- 201234664 10 :半導體發光裝置 1 3 : p側接觸電極 1 4 : η側接觸電極 1 5 : ρ側金屬保護膜 1 6 : η側金屬保護膜 1 7 :絕緣膜 1 7 a :第一開口 17b :第二開口 1 8 :絕緣層 18a :第一貫孔 18b :第二貫孔 18c :互連表面 19 :金屬膜 2 1 : p側重新互連層 22 : η側重新互連層 2 3 : ρ側金屬柱 2 4 : η側金屬柱 25 :樹脂層 26 :鏡片 27 :螢光體層 5 1 :光阻遮罩 5 1 a :開口 6 1 :光阻遮罩 6 1 a :開口 -35 201234664 5 2 :光阻遮罩 52a :開口 52b :開口 5 3 :光阻遮罩 53a :開口 62 :溝槽 80 :段差 90 :段差 100:電鑛液體的滲透路徑 -36-/ I ’I / I201234664 Fix. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a semiconductor light emitting device of an embodiment. 2A to 9B are schematic cross-sectional views illustrating a method of fabricating the semiconductor light emitting device of the embodiment. Figure 10 is a schematic cross-sectional view showing a semiconductor light-emitting device of another embodiment. Fig. 10 is a schematic cross-sectional view showing a semiconductor light-emitting device according to still another embodiment. Fig. 12 is a schematic cross-sectional view showing a semiconductor light emitting device according to still another embodiment. 13A and 13B are schematic cross-sectional views illustrating a planar configuration of main elements of the semiconductor light emitting device of the embodiment. [Description of main component symbols] 1 : First semiconductor layer 2 : Second semiconductor layer 3 : Light-emitting layer 4 : Semiconductor layer 4 a : First surface 5 : Light-emitting portion 6 : Non-light-emitting portion 8 : Substrate 34 - 201234664 10 : Semiconductor light-emitting Device 1 3 : p-side contact electrode 1 4 : η-side contact electrode 1 5 : ρ-side metal protective film 1 6 : η-side metal protective film 1 7 : insulating film 1 7 a : first opening 17b: second opening 1 8 : insulating layer 18a: first through hole 18b: second through hole 18c: interconnecting surface 19: metal film 2 1 : p side re-interconnecting layer 22: n-side re-interconnecting layer 2 3 : ρ side metal pillar 2 4 : η side metal pillar 25 : resin layer 26 : lens 27 : phosphor layer 5 1 : photoresist mask 5 1 a : opening 6 1 : photoresist mask 6 1 a : opening - 35 201234664 5 2 : light blocking Cover 52a: opening 52b: opening 5 3 : photoresist mask 53a: opening 62: groove 80: step 90: step 100: penetration path of the electromineral liquid - 36-

Claims (1)

201234664 七、申請專利範圍： 1. 一種半導體發光裝置，包含： 半導體層，其包括發光層、第一表面、及第二表面， 該第二表面係形成在該第一表面之相反側上，該第二表面 具有包括該發光層的發光部以及不包括該發光層的非發光 部； 絕緣膜，其設置在該第二表面上，該絕緣膜具有與該 發光部接觸的第一開口以及與該非發光部接觸的第二開口 t P側接觸電極，其設置與在該第一開口內的該發光部 接觸； η側接觸電極，其設置與在該第二開口內的該非發光 部接觸； Ρ側金屬保護膜，其覆蓋該ρ側接觸電極之頂表面及 側表面；以及 η側金屬保護膜，其覆蓋該η側接觸電極之頂表面及 側表面。 2. —種半導體發光裝置，包含： 半導體層，其包括發光層、第一表面' 及第二表面， 該第二表面係形成在該第一表面之相反側上，該第二表面 具有包括該發光層的發光部以及不包括該發光層的非發光 部； 絕緣膜’其設置在該第二表面上，該絕緣膜具有與該 發光部接觸的第一開口以及與該非發光部接觸的第二開口 -37- 201234664 P側接觸電極，其設置與在該第一開口內的該發光部 接觸； η側接觸電極，其設置與在該第二開口內的該非發光 部接觸； Ρ側金屬保護膜，其覆蓋該ρ側接觸電極之頂表面及 側表面，該Ρ側金屬保護膜之一部分係設置在該絕緣膜上 ，該Ρ側金屬保護膜之頂表面具有凹形結構，該ρ側金屬 保護膜被組態成較該Ρ側接觸電極不容易氧化或硫化；以 及 η側金屬保護膜，其覆蓋該η側接觸電極之頂表面及 側表面，該η側金屬保護膜之一部分係設置在該絕緣膜上 ，該η側金屬保護膜之頂表面具有凹形結構，該η側金屬 保護膜被組態成較該η側接觸電極不容易氧化或硫化， 該絕緣膜之該第一開口之內壁以及該絕緣膜之該第二 開口之內壁具有朝向該半導體層漸窄的錐形結構。 3. 如申請專利範圍第1或2項之半導體發光裝置，其 中該Ρ側金屬保護膜較該Ρ側接觸電極厚。 4. 如申請專利範圍第1或2項之半導體發光裝置，其 中該η側金屬保護膜較該η側接觸電極厚。 5. 如申請專利範圍第1項之半導體發光裝置，其中該 ρ側金屬保護膜較該Ρ側接觸電極不容易氧化或硫化。 6. 如申請專利範圍第1項之半導體發光裝置，其中該 η側金屬保護膜較該η側接觸電極不容易氧化或硫化。 -38- 201234664 7. 如申請專利範圍第1或2項之半導體發光裝置，其 中 該Ρ側金屬保護膜覆蓋包括該ρ側接觸電極之頂表面 及側表面之一暴露表面，以及 該η側金屬保護膜覆蓋包括該η側接觸電極之頂表面 及側表面之一暴露表面。 8. 如申請專利範圍第1或2項之半導體發光裝置，其 中 該Ρ側金屬保護膜具有之平面尺寸大於該第一開口之 平面尺寸，以及 該η側金屬保護膜具有之平面尺寸大於該第二開口之 平面尺寸。 9. 如申請專利範圍第1或2項之半導體發光裝置’其 中該第一開口之內壁係相對於該發光部之頂表面傾斜，以 造成該第一開口之開口面積從該發先部之頂表面側朝向該 絕緣膜之頂表面側增加》 1 0.如申請專利範圍第1或2項之半導體發光裝置， 其中該第二開口之內壁係相對於該非發光部之頂表面傾斜 ，以造成該第二開口之開口面積從該非發光部之頂表面側 朝向該絕緣膜之頂表面側增加。 11.如申請專利範圍第1或2項之半導體發光裝置， 其中 在該第一開口之內壁與該Ρ側接觸電極之該側表面之 間產生一間隔，以及 -39- 201234664 該P側金屬保護膜亦設置在該間隔內之該第—開□之 底面上。 12. 如申請專利範圍第1或2項之半導體發光裝置， 其中 在該第一開口之內壁與該η側接觸電極之該側表面之 間產生一間隔，以及 該η側金屬保護膜亦設置在該間隔內之該第二開口之 底面上。 13. 如申請專利範圍第1或2項之半導體發光裝置， 更包含： 第一絕緣層’其設置在該絕緣膜、該ρ側金屬保護膜 、及該η側金屬保護膜上，該第一絕緣層具有與該ρ側金 屬保護膜連接的第一貫孔以及與該η側金屬保護膜連接的 第二貫孔； ρ側互連層’其設置在該第一貫孔內以及在該ρ側金 屬保護膜之相反側上的該第一絕緣層之表面上，該Ρ側互 連層電連接至該Ρ側金屬保護膜； η側互連層，其設置在該第二貫孔內以及在該η側金 屬保護膜之相反側上的該第一絕緣層之表面上，該η側互 連層電連接至該η側金屬保護膜；以及 第二絕緣層，其至少設置在該ρ側互連層與該η側互 連層之間。 14. 如申請專利範圍第13之半導體發光裝置，其中 該Ρ側互連層包括設置在該第一絕緣層側上的ρ側重 •40- 201234664 新互連層以及設置在該P側重新互連層之頂表面上的p側 金屬柱，該p側金屬柱較該P側重新互連層厚，以及 該η側互連層包括設置在該第一絕緣層側上的η側重 新互連層以及設置在該η側重新互連層之頂表面上的η側 金屬柱，該η側金屬柱較該η側重新互連層厚。 15. 如申請專利範圍第13之半導體發光裝置，其中在 該η側金屬保護膜之相反側上的該η側互連層之表面積較 該η側接觸電極之面積大。 16. 如申請專利範圍第13之半導體發光裝置，其中該 Ρ側互連層較該Ρ側接觸電極厚。 17. 如申請專利範圍第13之半導體發光裝置，其中該 η側互連層較該η側接觸電極厚。 18. 如申請專利範圍第1或2項之半導體發光裝置， 更包含一透明體，其設置在該第一表面上，該透明體對於 發射自該發光層的光係透明的。 19. 一種半導體發光裝置之製造方法，包含： 形成絕緣膜於半導體層之第二表面上，該絕緣膜具有 第一開口及第二開口，該半導體層包括發光層、第一表面 、及該第二表面’該第二表面係形成於該第一表面之相反 側上，該第二表面具有包括該發光層之發光部以及不包括 該發光層之非發光部，該第一開口連接該發光部，該第二 開口連接該非發光部； 形成Ρ側接觸電極於該第一開口內之該發光部的頂表 面上； -41 - 201234664 形成η側接觸電極於該第二開口內之該非發光部的頂 表面上； 形成Ρ側金屬保護膜於該Ρ側接觸電極之頂表面及側 表面上；以及 形成η側金屬保護膜於該η側接觸電極之頂表面及側 表面上。 20.如申請專利範圍第19項之製造方法，其中藉由使 用光阻遮罩選擇性蝕刻該絕緣膜而產生該第一開口及該第 二開口，並且使用該相同的光阻遮罩來接續地形成該ρ側 接觸電極及該η側接觸電極。 2 1.如申請專利範圍第19或20項之製造方法，更包 含： 形成第一絕緣層於該絕緣膜、該ρ側金屬保護膜、及 該η側金屬保護膜上，該第一絕緣層具有與該ρ側金屬保 護膜連接的第一貫孔以及與該η側金屬保護膜連接的第二 貫孔； 形成Ρ側互連層於該第一貫孔內以及在該ρ側金屬保 護膜之相反側上的該第一絕緣層之表面上；以及 形成η側互連層於該第二貫孔內以及在該η側金屬保 護膜之相反側上的該第一絕緣層之表面上。 -42 -201234664 VII. Patent Application Range: 1. A semiconductor light emitting device comprising: a semiconductor layer comprising a light emitting layer, a first surface, and a second surface, the second surface being formed on an opposite side of the first surface, The second surface has a light emitting portion including the light emitting layer and a non-light emitting portion not including the light emitting layer; an insulating film disposed on the second surface, the insulating film having a first opening in contact with the light emitting portion and a second opening t P side contact electrode contacting the light emitting portion, the contact electrode being disposed in contact with the light emitting portion in the first opening; the n side contact electrode being disposed in contact with the non-light emitting portion in the second opening; a metal protective film covering a top surface and a side surface of the p-side contact electrode; and an n-side metal protective film covering a top surface and a side surface of the n-side contact electrode. 2. A semiconductor light emitting device comprising: a semiconductor layer comprising a light emitting layer, a first surface 'and a second surface, the second surface being formed on an opposite side of the first surface, the second surface having the a light emitting portion of the light emitting layer and a non-light emitting portion not including the light emitting layer; the insulating film 'on which is disposed on the second surface, the insulating film having a first opening in contact with the light emitting portion and a second contact with the non-light emitting portion Opening-37-201234664 P-side contact electrode disposed in contact with the light-emitting portion in the first opening; n-side contact electrode disposed in contact with the non-light-emitting portion in the second opening; Covering the top surface and the side surface of the p-side contact electrode, a portion of the side metal protective film is disposed on the insulating film, and a top surface of the side metal protective film has a concave structure, and the p-side metal protection The film is configured to be less susceptible to oxidation or vulcanization than the side contact electrode; and an n-side metal protective film covering the top surface and the side surface of the n-side contact electrode, the n-side metal protective film a portion is disposed on the insulating film, a top surface of the n-side metal protective film has a concave structure, and the n-side metal protective film is configured to be less susceptible to oxidation or vulcanization than the n-side contact electrode, the insulating film The inner wall of the first opening and the inner wall of the second opening of the insulating film have a tapered structure that is tapered toward the semiconductor layer. 3. The semiconductor light-emitting device of claim 1 or 2, wherein the side metal protective film is thicker than the side contact electrode. 4. The semiconductor light-emitting device of claim 1 or 2, wherein the n-side metal protective film is thicker than the n-side contact electrode. 5. The semiconductor light-emitting device of claim 1, wherein the p-side metal protective film is less susceptible to oxidation or vulcanization than the side contact electrode. 6. The semiconductor light-emitting device of claim 1, wherein the η-side metal protective film is less susceptible to oxidation or vulcanization than the η-side contact electrode. 7. The semiconductor light-emitting device of claim 1 or 2, wherein the side metal protective film covers an exposed surface including one of a top surface and a side surface of the p-side contact electrode, and the n-side metal The protective film covers an exposed surface including one of a top surface and a side surface of the n-side contact electrode. 8. The semiconductor light-emitting device of claim 1 or 2, wherein the side metal protective film has a planar size larger than a planar size of the first opening, and the n-side metal protective film has a planar size greater than the first The planar dimensions of the two openings. 9. The semiconductor light-emitting device of claim 1 or 2, wherein an inner wall of the first opening is inclined with respect to a top surface of the light-emitting portion to cause an opening area of the first opening to be from the first portion The semiconductor device according to claim 1 or 2, wherein the inner wall of the second opening is inclined with respect to a top surface of the non-light emitting portion, The opening area of the second opening is increased from the top surface side of the non-light emitting portion toward the top surface side of the insulating film. 11. The semiconductor light emitting device of claim 1 or 2, wherein a space is formed between an inner wall of the first opening and the side surface of the side contact electrode, and -39-201234664 the P side metal A protective film is also disposed on the bottom surface of the first opening in the interval. 12. The semiconductor light emitting device of claim 1 or 2, wherein a space is formed between an inner wall of the first opening and the side surface of the n-side contact electrode, and the n-side metal protective film is also disposed On the bottom surface of the second opening in the interval. 13. The semiconductor light-emitting device of claim 1 or 2, further comprising: a first insulating layer disposed on the insulating film, the p-side metal protective film, and the n-side metal protective film, the first The insulating layer has a first through hole connected to the p-side metal protective film and a second through hole connected to the n-side metal protective film; a p-side interconnect layer 'which is disposed in the first through hole and at the p On the surface of the first insulating layer on the opposite side of the side metal protective film, the top side interconnect layer is electrically connected to the side metal protective film; the n side interconnect layer is disposed in the second through hole and The n-side interconnect layer is electrically connected to the n-side metal protective film on a surface of the first insulating layer on the opposite side of the n-side metal protective film; and a second insulating layer disposed at least on the p side Between the interconnect layer and the n-side interconnect layer. 14. The semiconductor light emitting device of claim 13, wherein the side interconnect layer comprises a p-side spacer 40-201234664 new interconnect layer disposed on the first insulating layer side and is re-interconnected on the P side a p-side metal pillar on a top surface of the layer, the p-side metal pillar being thicker than the P-side re-interconnect layer, and the n-side interconnect layer including an n-side re-interconnect layer disposed on the first insulating layer side And an n-side metal pillar disposed on a top surface of the n-side re-interconnect layer, the n-side metal pillar being thicker than the n-side re-interconnect layer. 15. The semiconductor light-emitting device of claim 13, wherein a surface area of the n-side interconnect layer on an opposite side of the n-side metal protective film is larger than an area of the n-side contact electrode. 16. The semiconductor light emitting device of claim 13, wherein the side interconnect layer is thicker than the side contact electrode. 17. The semiconductor light emitting device of claim 13, wherein the n-side interconnect layer is thicker than the n-side contact electrode. 18. The semiconductor light emitting device of claim 1 or 2, further comprising a transparent body disposed on the first surface, the transparent body being transparent to a light system emitted from the light emitting layer. 19. A method of fabricating a semiconductor light emitting device, comprising: forming an insulating film on a second surface of a semiconductor layer, the insulating film having a first opening and a second opening, the semiconductor layer comprising a light emitting layer, a first surface, and the first a second surface formed on an opposite side of the first surface, the second surface having a light emitting portion including the light emitting layer and a non-light emitting portion not including the light emitting layer, the first opening connecting the light emitting portion a second opening is connected to the non-light emitting portion; a top side contact electrode is formed on a top surface of the light emitting portion in the first opening; -41 - 201234664 forming an n-side contact electrode in the non-light emitting portion in the second opening On the top surface, a top side metal protective film is formed on the top surface and the side surface of the side contact electrode; and an n side metal protective film is formed on the top surface and the side surface of the n side contact electrode. 20. The manufacturing method of claim 19, wherein the first opening and the second opening are produced by selectively etching the insulating film using a photoresist mask, and using the same photoresist mask to continue The p-side contact electrode and the n-side contact electrode are formed. 2. The manufacturing method of claim 19 or 20, further comprising: forming a first insulating layer on the insulating film, the p-side metal protective film, and the n-side metal protective film, the first insulating layer a first through hole connected to the p-side metal protective film and a second through hole connected to the n-side metal protective film; forming a meandering interconnect layer in the first through hole and the p side metal protective film On the opposite side of the surface of the first insulating layer; and forming an n-side interconnect layer in the second via hole and on a surface of the first insulating layer on the opposite side of the n-side metal protective film. -42 -
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US9029893B2 (en) 2013-02-18 2015-05-12 Kabushiki Kaisha Toshiba Semiconductor light emitting device and method for manufacturing the same
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US10164161B2 (en) * 2014-10-27 2018-12-25 Koninklijke Philips N.V. Directional light emitting arrangement and a method of producing the same
US9812611B2 (en) 2015-04-03 2017-11-07 Soko Kagaku Co., Ltd. Nitride semiconductor ultraviolet light-emitting element and nitride semiconductor ultraviolet light-emitting device
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Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3449535B2 (en) * 1999-04-22 2003-09-22 ソニー株式会社 Method for manufacturing semiconductor device
JP2004006498A (en) * 2002-05-31 2004-01-08 Toyoda Gosei Co Ltd Group III nitride compound semiconductor light emitting device
US6828596B2 (en) * 2002-06-13 2004-12-07 Lumileds Lighting U.S., Llc Contacting scheme for large and small area semiconductor light emitting flip chip devices
JP2004103975A (en) 2002-09-12 2004-04-02 Citizen Watch Co Ltd Optical semiconductor element, method for manufacturing the same, and optical semiconductor device mounting optical semiconductor element
TWI327781B (en) * 2003-02-19 2010-07-21 Nichia Corp Nitride semiconductor device
DE10350707B4 (en) * 2003-02-26 2014-02-13 Osram Opto Semiconductors Gmbh Electrical contact for optoelectronic semiconductor chip and method for its production
WO2006043422A1 (en) * 2004-10-19 2006-04-27 Nichia Corporation Semiconductor element
JP5347219B2 (en) * 2006-10-25 2013-11-20 日亜化学工業株式会社 Semiconductor light emitting device
JP5325506B2 (en) * 2008-09-03 2013-10-23 株式会社東芝 Semiconductor light emitting device and manufacturing method thereof
JP4724222B2 (en) * 2008-12-12 2011-07-13 株式会社東芝 Method for manufacturing light emitting device
JP2010166012A (en) * 2008-12-17 2010-07-29 Sumitomo Electric Ind Ltd Ohmic electrode, semiconductor device, method for manufacturing ohmic electrode, and method for manufacturing semiconductor device
US20110018013A1 (en) * 2009-07-21 2011-01-27 Koninklijke Philips Electronics N.V. Thin-film flip-chip series connected leds

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Publication number Priority date Publication date Assignee Title
US9029893B2 (en) 2013-02-18 2015-05-12 Kabushiki Kaisha Toshiba Semiconductor light emitting device and method for manufacturing the same
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TWI636597B (en) * 2015-09-01 2018-09-21 德商歐司朗光電半導體公司 Semiconductor wafer
TWI824147B (en) * 2017-12-14 2023-12-01 美商亮銳公司 Method of preventing contamination of led die
TWI714319B (en) * 2019-10-28 2020-12-21 錼創顯示科技股份有限公司 Micro light-emitting diode device
US11393959B2 (en) 2019-10-28 2022-07-19 PlayNitride Display Co., Ltd. Micro light-emitting diode device

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