201227879 六、發明說明： 【發明所屬之技術領域】 以下描述係關於一種半導體裝置及其製造方法，且更特 定言之’係關於一種具有高介電常數之金屬-絕緣體_金屬 (MIM)電容器及其製造方法。 【先前技術】 一般而言’需要一種以高速操作同時在功能態樣上具有 高儲存容量之半導體裝置。 出於此目的，已開發製造半導體裝置之技術以改良整合 度、響應速度及可靠性。為了增強半導體裝置之再新特 性’包括於半導體裝置中之組成元件（諸如電容器）之靜電 容量值應為高的。 然而，近年來，隨著半導體裝置變得高度整合，單位晶 胞面積持續減小《因此，半導體裝置之晶胞靜電電容亦減 小，從而使得難以確保用於裝置操作所需之靜電容量。 一般而言，經由增加相對電極之面積而增加電容器之靜 電電容，從而增加介電物質之相對介電常數且減小介電物 質之厚度。因此’電容器之結構得以多樣化同時減小介電 物質之厚度以獲得適合靜電容量。 :另—方面’已進行以下研究：應用具有高介電常數之材 料而非迄今已使用之氮化矽介電層，以獲得適合靜電容 量。具有高介電常數之材料包括二氧化給、氧化链及氧化 纽》 ’、’；而，當將咼介電常數（高k)材料用作MIM電容器之絕 153355.doc 201227879 緣層時，歸因於在蝕刻該MIM電容器之上部電極之後剩餘 的絕緣層，其後續製程將受影響。 此外’金屬佈線之輪廓歸因於以下而惡化：不足光阻 (PR)邊限、剩餘高介電常數之絕緣層產生金屬聚合物，及 金屬聚合物在後續導通體蝕刻製程_保留在孔内部。歸因 於此等問題，導通體電阻增加，藉此降低電容器之可靠 性。 另外，若增加後續導通體過度蝕刻目標以移除剩餘絕緣 層，則產生擊穿電壓特性惡化。 【發明内容】 通用態樣係針對一種金屬-絕緣體-金屬（MIM)電容器及 經組態以製造該麵電容器之方法，在該等態樣十增強可 靠性’最小化對後續製程之影響，且藉由將該Mm電容器 與一外部環境隔離而防止歸因於導通體過度蝕刻目標之擊 穿電壓惡化。 。。為了實現上述目標，根據本發明之一實施例的mim電容 态可包括：-下部電極及一上部電極，該下部電極及該上 部電極係形成於一基板上；一具有高介電常數之介電層， 該介電層係形成於該下部電極與該上部電極之間；一第一 保護層’該第-保護層圍繞該上部電極之_橫向表面及一 上表面；及-第二保護層’該第二保護層圍繞該介電層及 該保護層之-橫向表面，其中該介電層之寬度大於該上部 電極之寬度’且該第一保護層及該第二保護層係由具有不 同蝕刻速率之材料構成。 153355.doc 201227879 為了實現上述目標’根據本發明之一實施例的製造MIM 電谷器之方法可包括：在一基板上形成一下部電極；在該 下部電極上形成一介電層；在該介電層之區域上形成一上 電極及一硬式遮罩；及在該介電層、該上部電極及該硬 式遮罩之一橫向表面處形成一隔件。 為了貫現上述目標，根據本發明之一實施例的製造Mim 電容器之方法可包括：在一基板上形成一第一金屬層；在 該第一金屬層上依序層壓一介電層、一第二金屬層及一硬 式遮罩絕緣體；圓案化該硬式遮罩絕緣體及該第二金屬層 以形成一硬式遮罩及一上部電極；在包括該硬式遮罩、該 上部電極及該介電層之整個基板上形成一隔件絕緣層；蝕 刻該隔件絕緣層之整個表面以在該硬式遮罩、該上部電極 及該介電層之一橫向表面處形成一隔件；在該隔件、該硬 式遮罩及該第一金屬層上形成一緩衝絕緣層；及圖案化該 緩衝絕緣層及該第一金屬層以形成一下部電極。 在一通用態樣中，提供一種半導體裝置，其包括：一下 部電極，該下部電極形成於—基板上；—介電層，該介電 層包括形成於該下部電極上之一飯刻介電區域及_原生介 電區域；-上部電極，該上部電極形成於該原生介電區域 上；一硬式遮罩，該硬式遮罩形成於該上部電極上丨一隔 件’該隔件形成於該硬式遮罩及該上部電極之—側表面處 以及該蝕刻介電區域上方；及一緩衝絕緣層，該緩衝絕緣 層形成於該硬式遮罩及該隔件上。 S亥裝置可進一步提供 該介電層包括原子雷射沈積 153355.doc 201227879 (ALD)尚 kHf02/Al2〇3膜堆疊。 該裝置可進一步提供：使用—相 相u遮罩采圖案化該硬式 遮罩及該上部電㈣使該硬式料及該上㈣極一相 同形狀。 ' 裝置可it步提供：該隔件隔離該硬式遮罩及該上部 電極之該側表面。 X *亥原生介電區域將該下部電極與 該裝置可進一步提供 δ亥上部電極分離。 該下部電極之一長度大於該上部 έ亥下部電極包括TiN/Ti，及該上 該裝置可進一步提供 電極之一長度。 3玄裝置可進一步提供 部電極包括TiN。 該裝置可進-步提供：㈣刻介電區域自該原生介電區 域延伸且大致終止於該隔件之—末端處，該隔件之該末端 形成於與該隔件之接觸該硬式遮罩及該上部電極之該側表 面的-側面相對的該隔件之一側面上，且該敍刻介電區域 之一厚度小於該原生介電區域之一厚度。 «亥裝置可it步提供^隔件之該末端由該緩衝絕緣層 及該蝕刻介電區域界定。 、/裝置可進步提供:一彎曲介電區域，該彎曲介電區 域^於㈣生介電區域與該㈣介電區域之間。 -亥4置可進-步提供：該隔件形成於該彎曲介電區域上 方。 。亥裝置可進-步提供：該則介電區域自該彎曲介電區 153355.doc 201227879 域延伸且大致終止於該隔件之一末端處，該隔件之該末端 形成於與該隔件之接觸該硬式遮罩及該上部電極之該側表 面的一側面相對的該隔件之一側面上’該彎曲介電區域經 組態以連接該蝕刻介電區域及該原生介電區域，且該餘刻 介電區域之一厚度小於該原生介電區域及該彎曲介電區域 之一厚度。 該裝置可進一步提供：該緩衝絕緣層包括Si〇N。 在另一態樣中，提供一種製造一半導體裝置之方法。該 方法包括：在一基板上形成一第一金屬層；在該第一金屬 層上依序層壓一介電層、一第二金屬層及一硬式遮罩絕緣 體；選擇性地圖案化該硬式遮罩絕緣體、該第二金屬層及 該介電層，以形成一硬式遮罩、一上部電極及一具有一蝕 刻介電區域及一原生介電區域之介電層圖案；在該硬式遮 罩之上表面及側表面、該上部電極之一側表面及該介電層 圖案之該蝕刻介電區域上形成一隔件絕緣層；蝕刻該隔件 絕緣層以在該硬式遮罩之該側表面、該上部電極之該側表 面及該介電層之該蝕刻介電區域處形成一隔件；在該隔 件、該硬式遮罩及該第一金屬層上形成—緩衝絕緣層，·及 圖案化該緩衝絕緣層及該第一金屬層以形成一下部電極。 該方法可進-步提供：該選靠_案化該硬式遮罩絕 緣體及該第二金屬層包括在該第二金屬層下之該钮刻介電 區域中同時银刻一厚度之一部分。 該方法可進-步提供：該同時㈣該部分包括在該原生 介電區域與該蝕刻介電區域之間形成—彎曲介電區域。 153355.doc 201227879 ”亥方法可進-步提供：該隔件之一下表面接觸該蝕刻介 電區域’㈣件之-側表面接觸該硬式遮罩及該上部電 極，且該隔件之彎曲表面分別接觸該緩衝絕緣層及該彎曲 介電層。 忒方法可進-步提供：該隔件之一下表面接觸該蝕刻介 電區域，且該隔件之一側表面接觸該硬式遮罩及該上部電 極。 該方法可進一步提供：該蝕刻介電區域之一厚度小於該 原生介電區域之'一厚度。 該方法可進一步提供：該緩衝絕緣層包括Si〇N〇 通用態樣可提供一種MIM電容器，該mim電容器與一外 部環境隔離且受保護以防各種缺陷，藉此確保一良好漏電 流特性。 另外，通用恶樣可提供：沈積於該金屬層之一上部部分 上之SiON在蝕刻期間緩衝一蝕刻目標，藉此防止一MIM電 容器之擊穿電壓特性惡化。 結果，當使用一種根據通用態樣之製造Mim電容器之製 程時，在諸如擊穿電壓、缺陷密度及其類似者之可靠性態 樣方面可能具有一極佳特性。 其他特徵及態樣可自以下實施方式、圖式及申請專利範 圍中顯而易見。 【實施方式】 長:供以下實施方式，以便有助於讀者獲得對本文中所描 述之方法、設備及/或系統之綜合理解。因此，一般熟習 153355.doc 〇 201227879 此項技術者將想到本文中所描述之系統、設備及/或方法 之各種改變、修改及等效物。又，為了提高清晰性及簡明 性’可省略熟知功能及構造之描述。 應理解，本發明之特徵可以不同形式體現，且不應解釋 為限於本文中所闡述之實例實施例。實情為，提供實施例 以使得本發明將為詳盡且完整的，且將本發明之全部範疇 傳達給熟習此項技術者。該等圖式可能未必按比例調整， 且在一些情況下，可能已放大比例以便清楚地說明實施例 之特徵。當一第一層稱為在一第二層「上」或在一基板 上」時，其不僅可指代該第一層直接形成於該第二層或 該基板上的狀況，而且亦可指代一第三層存在於該第一層 與該第二層或該基板之間的狀況。 在下文中，參看隨附圖式詳細描述具有MIM電容器之半 導體裝置之結構的實例。 圖1A說明包括一互連區域2〇〇及一 電容器區域3〇〇之 半導體裝置之一貫例的示意性橫截面圖。在互連區域2〇〇 中，一下部互連層可由下部互連金屬層1〇31)及下部互連罩 蓋層105b形成。在下部互連層上方，上部互連層可具備安 置於其間之金屬間絕緣層13 1。上部互連層可由上部互連 金屬層139c及上部互連罩蓋層i4ic形成。上部互連層可藉 由一金屬插塞13 7c電連接至下部互連層。 參看圖1A，根據本發明之MIM電容器可包括：形成於基 板101上之下部電極105a ;形成於下部電極1〇5&上之介電 層107’其具有尚介電常數且包括第一區域及介電層突出 153355.doc -10· 201227879 部分107a ’该介電層突出部分i〇7a係自第一區域突出之第 二區域；形成於介電層1〇7之第一區域上的上部電極 l〇9a ;及形成於介電層107及上部電極1〇9a之橫向表面處 的隔件121a。 此處，介電層107可包括與上部電極1〇9a重疊之第一區 域，及自第一區域延伸且突出的介電層突出部分1〇7a。此 時，介電層之水平長度（或寬度）係經形成為長於在介電層 107上所形成之上部電極l〇9a的水平長度（或寬度卜可藉由 形成較上部電極更寬廣之介電層而將上部電極與下部電極 良好地分離，藉此幫助抑制洩漏產生。若介電層及上部電 極具有相同寬度’則上部電極與下部電極之間的長度短， 由此可能由電場沿其橫向表面產生洩漏。相反地，若介電 層之寬度如上文所述大於上部電極的寬度，則有可能防止 此問題。 下部結構係形成於基板1 0 1上。該下部結構可包括整、 插塞、導電層圖案、介電層圖案、閘極結構、電晶體及其 類似者。此外，基板101可包括半導體基板或金屬氧化物 單晶體基板。舉例而言，基板1〇1可包括矽基板、鍺基 板、SOI基板、GOI基板、氧化鋁單晶體基板、氧化鈦單 晶體基板及其類似者。 此外，將絕緣結構（未圖示）插置於基板1〇1與電容器之 間。S玄絕緣結構可具有由氧化物層製成之單層結構◊舉例 而a ’ β亥絕緣結構（未圖示）可藉由使用硼碟石夕酸鹽玻璃 (BPSG)、礙^夕酸鹽玻璃（PSG)、未摻雜之矽酸鹽玻璃 153355.doc 201227879 (USG)、旋塗玻璃（SOG)、可流動氧化物（fox)、四乙基原 矽酸酯（TEOS)、電漿增強型（PE)-TEOS、高密度電漿-化學 氣相沈積（HDP-CVD)氧化物及其類似者而形成。另一方 面’該絕緣結構（未圖示）可具有多層結構，該多層結構包 括形成於基板101上之至少一氧化物層、至少一氮化物層 及/或至少一氮氧化物層。此處，可藉由分別使用氧化 石夕、氮化矽及氮氧化矽而形成氧化物層、氮化物層及氮氧 化物層》 參看圖1A ’ ΜΙΜ電容器區域3〇〇中之ΜΙΜ電容器400之一 貫例包括金屬佈線l〇3a、金屬佈線1〇3a上之下部電極 105a、介電層1〇7及上部電極109a。金屬佈線1〇3a可由與 下《卩互連金屬層l〇3b相同之材料製成，且以與下部互連金 屬層l〇3b相同之製造步驟形成。下部電極1〇5&可由與下部 互連罩蓋層l〇5b相同之材料製成，且以與下部互連罩蓋層 105b相同之製造步驟形成。 金屬佈線H)3a可由鋁（A1)、銅（Cu)或八丨與以之組合構 成》在一通用態樣中，金屬佈線1〇3a可由A1Cu構成。下部 電極105a可藉由使用金屬、合金或導電金屬化合物形成。 舉例而言’下部電極心可為選自由以下各物組成之群組 的至少任一者：RU、Pt、TaN、、⑽、Ti趣、、201227879 VI. Description of the Invention: [Technical Field] The following description relates to a semiconductor device and a method of fabricating the same, and more particularly to a metal-insulator-metal (MIM) capacitor having a high dielectric constant and Its manufacturing method. [Prior Art] In general, there is a need for a semiconductor device that operates at a high speed while having a high storage capacity in a functional form. For this purpose, techniques for fabricating semiconductor devices have been developed to improve integration, response speed, and reliability. In order to enhance the renewed characteristics of the semiconductor device, the electrostatic capacitance value of constituent elements (such as capacitors) included in the semiconductor device should be high. However, in recent years, as semiconductor devices have become highly integrated, the unit cell area has continued to decrease. Therefore, the cell electrostatic capacitance of the semiconductor device is also reduced, making it difficult to secure the electrostatic capacitance required for device operation. In general, the electrostatic capacitance of the capacitor is increased by increasing the area of the opposing electrode, thereby increasing the relative dielectric constant of the dielectric material and reducing the thickness of the dielectric material. Therefore, the structure of the capacitor can be diversified while reducing the thickness of the dielectric material to obtain a suitable electrostatic capacity. : Another aspect has been studied by applying a material having a high dielectric constant instead of the tantalum nitride dielectric layer which has been used hitherto to obtain a suitable electrostatic capacitance. Materials with high dielectric constants include dioxide, oxidized chain, and oxidized ","; while, when 咼 dielectric constant (high-k) materials are used as the edge layer of MIM capacitors, 153355.doc 201227879 Subsequent processes will be affected due to the remaining insulating layer after etching the upper electrode of the MIM capacitor. In addition, the profile of the 'metal wiring is deteriorated due to the following: insufficient photoresist (PR) margin, residual high dielectric constant insulating layer to produce metal polymer, and metal polymer in the subsequent via etching process _ retained inside the hole . Due to these problems, the resistance of the via is increased, thereby reducing the reliability of the capacitor. In addition, if the subsequent via over-etch target is added to remove the remaining insulating layer, breakdown voltage characteristics are deteriorated. SUMMARY OF THE INVENTION A generalized aspect is directed to a metal-insulator-metal (MIM) capacitor and a method configured to fabricate the same, in which the enhanced reliability 'minimizes the impact on subsequent processes, and The breakdown voltage degradation due to the over-etch target of the via is prevented by isolating the Mm capacitor from an external environment. . . In order to achieve the above object, a mim capacitive state according to an embodiment of the present invention may include: a lower electrode and an upper electrode, the lower electrode and the upper electrode are formed on a substrate; and a dielectric having a high dielectric constant a layer, the dielectric layer is formed between the lower electrode and the upper electrode; a first protective layer 'the first protective layer surrounds the lateral surface and an upper surface of the upper electrode; and - the second protective layer' The second protective layer surrounds the dielectric layer and the lateral surface of the protective layer, wherein the width of the dielectric layer is greater than the width of the upper electrode and the first protective layer and the second protective layer are differently etched The material composition of the rate. 153355.doc 201227879 In order to achieve the above object, a method of manufacturing a MIM electric grid according to an embodiment of the present invention may include: forming a lower electrode on a substrate; forming a dielectric layer on the lower electrode; An upper electrode and a hard mask are formed on a region of the electrical layer; and a spacer is formed at a lateral surface of the dielectric layer, the upper electrode and the hard mask. In order to achieve the above object, a method of fabricating a Mim capacitor according to an embodiment of the present invention may include: forming a first metal layer on a substrate; sequentially laminating a dielectric layer on the first metal layer, a second metal layer and a hard mask insulator; rounding the hard mask insulator and the second metal layer to form a hard mask and an upper electrode; including the hard mask, the upper electrode, and the dielectric Forming a spacer insulating layer on the entire substrate; etching the entire surface of the spacer insulating layer to form a spacer at a lateral surface of the hard mask, the upper electrode and the dielectric layer; Forming a buffer insulating layer on the hard mask and the first metal layer; and patterning the buffer insulating layer and the first metal layer to form a lower electrode. In a general aspect, a semiconductor device is provided, comprising: a lower electrode formed on a substrate; a dielectric layer including a microwave dielectric formed on the lower electrode a region and a primary dielectric region; an upper electrode formed on the native dielectric region; a hard mask formed on the upper electrode and a spacer formed on the spacer a hard mask and a side surface of the upper electrode and the etched dielectric region; and a buffer insulating layer formed on the hard mask and the spacer. The S-H device can further provide the dielectric layer including atomic laser deposition 153355.doc 201227879 (ALD) still kHf02/Al2〇3 film stack. The apparatus may further provide for patterning the hard mask and the upper portion (four) using a phase-phase mask such that the hard material and the upper (four) pole have the same shape. The device can be provided by step: the spacer isolates the hard mask from the side surface of the upper electrode. The X*Heil native dielectric region further provides separation of the lower electrode from the lower electrode. One of the lower electrodes has a length greater than the upper portion of the lower electrode including TiN/Ti, and the upper device further provides one of the lengths of the electrodes. The mysterious device can further provide a portion of the electrode including TiN. The apparatus can be further provided that: (d) the dielectric region extends from the native dielectric region and terminates substantially at the end of the spacer, the end of the spacer being formed in contact with the spacer. And a side of the spacer opposite to the side surface of the side surface of the upper electrode, and a thickness of one of the dielectric regions is less than a thickness of the one of the native dielectric regions. The end portion of the spacer can be defined by the buffer insulating layer and the etched dielectric region. The / device can be progressively provided: a curved dielectric region between the (iv) dielectric region and the (iv) dielectric region. - Hai 4 can be advanced - the step is provided: the spacer is formed above the curved dielectric region. . The device can be further provided: the dielectric region extends from the curved dielectric region 153355.doc 201227879 and terminates substantially at one end of the spacer, the end of the spacer being formed with the spacer Contacting the hard mask and a side of the spacer opposite to a side of the side surface of the upper electrode, the curved dielectric region is configured to connect the etched dielectric region and the native dielectric region, and the One of the remaining dielectric regions has a thickness that is less than a thickness of the native dielectric region and the curved dielectric region. The apparatus may further provide that the buffer insulating layer comprises Si〇N. In another aspect, a method of fabricating a semiconductor device is provided. The method includes: forming a first metal layer on a substrate; sequentially laminating a dielectric layer, a second metal layer, and a hard mask insulator on the first metal layer; selectively patterning the hard Masking the insulator, the second metal layer and the dielectric layer to form a hard mask, an upper electrode, and a dielectric layer pattern having an etched dielectric region and a native dielectric region; the hard mask Forming a spacer insulating layer on the upper surface and the side surface, the side surface of the upper electrode, and the etched dielectric region of the dielectric layer pattern; etching the spacer insulating layer to the side surface of the hard mask Forming a spacer at the side surface of the upper electrode and the etched dielectric region of the dielectric layer; forming a buffer insulating layer, and a pattern on the spacer, the hard mask, and the first metal layer The buffer insulating layer and the first metal layer are formed to form a lower electrode. The method can be further provided by: locating the hard mask insulator and the second metal layer comprising a portion of the thickness of the silver inscribed in the button dielectric region under the second metal layer. The method can be provided in a step-by-step manner: the simultaneous (d) portion includes forming a curved dielectric region between the native dielectric region and the etched dielectric region. 153355.doc 201227879 "Hai method can be provided in a step-by-step manner: one of the spacers is in contact with the etched dielectric region" (four) - the side surface contacts the hard mask and the upper electrode, and the curved surface of the spacer Contacting the buffer insulating layer and the curved dielectric layer. The method may further provide: a lower surface of the spacer contacts the etched dielectric region, and a side surface of the spacer contacts the hard mask and the upper electrode The method further provides that: one of the etched dielectric regions has a thickness less than a thickness of the native dielectric region. The method further provides that the buffer insulating layer comprises a Si 〇 N 〇 general aspect to provide a MIM capacitor, The mim capacitor is isolated from an external environment and protected against various defects, thereby ensuring a good leakage current characteristic. In addition, a general-purpose sample provides that SiON deposited on an upper portion of the metal layer buffers during etching. Etching the target, thereby preventing the breakdown voltage characteristic of a MIM capacitor from deteriorating. As a result, when a process for manufacturing a Mim capacitor according to a general aspect is used, Other characteristics and aspects may be apparent from the following embodiments, drawings, and patent applications. The following embodiments are provided to assist the reader in obtaining a comprehensive understanding of the methods, devices, and/or systems described herein. Therefore, generally, 153355.doc 〇201227879, the person skilled in the art will contemplate the system described herein, Various changes, modifications, and equivalents of the device and/or method. Also, in order to improve clarity and conciseness, descriptions of well-known functions and constructions may be omitted. It should be understood that the features of the present invention may be embodied in different forms and should not be construed The present invention is intended to be limited to the embodiments described herein. It is to be understood that the invention is intended to be Proportional adjustment, and in some cases, may have been scaled to clearly illustrate the features of the embodiment. When a first layer is called When a second layer is "on" or "on a substrate", it may refer not only to the condition that the first layer is directly formed on the second layer or the substrate, but also that a third layer is present in the The condition between the first layer and the second layer or the substrate. In the following, an example of the structure of a semiconductor device having a MIM capacitor will be described in detail with reference to the accompanying drawings. Figure 1A illustrates a schematic cross-sectional view of a conventional example of a semiconductor device including an interconnect region 2A and a capacitor region 3A. In the interconnection region 2, the lower interconnection layer may be formed of the lower interconnection metal layer 1〇31) and the lower interconnection cap layer 105b. Above the lower interconnect layer, the upper interconnect layer may have an inter-metal insulating layer 13 1 interposed therebetween. The upper interconnect layer may be formed of an upper interconnect metal layer 139c and an upper interconnect cap layer i4ic. The upper interconnect layer can be electrically connected to the lower interconnect layer by a metal plug 13 7c. Referring to FIG. 1A, a MIM capacitor according to the present invention may include: a lower electrode 105a formed on a substrate 101; a dielectric layer 107' formed on the lower electrode 1'5&; having a dielectric constant and including a first region and Dielectric layer protrusion 153355.doc -10· 201227879 Part 107a 'The dielectric layer protruding portion i〇7a is a second region protruding from the first region; the upper electrode formed on the first region of the dielectric layer 1〇7 L〇9a; and a spacer 121a formed at the lateral surface of the dielectric layer 107 and the upper electrode 1〇9a. Here, the dielectric layer 107 may include a first region overlapping the upper electrode 1〇9a, and a dielectric layer protruding portion 1〇7a extending from the first region and protruding. At this time, the horizontal length (or width) of the dielectric layer is formed to be longer than the horizontal length of the upper electrode 10a9 formed on the dielectric layer 107 (or the width can be made wider by forming the upper electrode) The electric layer separates the upper electrode from the lower electrode well, thereby helping to suppress leakage. If the dielectric layer and the upper electrode have the same width, the length between the upper electrode and the lower electrode is short, thereby possibly being followed by an electric field The lateral surface creates a leak. Conversely, if the width of the dielectric layer is greater than the width of the upper electrode as described above, it is possible to prevent this problem. The lower structure is formed on the substrate 110. The lower structure may include the entire structure. a plug, a conductive layer pattern, a dielectric layer pattern, a gate structure, a transistor, and the like. Further, the substrate 101 may include a semiconductor substrate or a metal oxide single crystal substrate. For example, the substrate 1〇1 may include a germanium substrate, a germanium substrate, an SOI substrate, a GOI substrate, an alumina single crystal substrate, a titanium oxide single crystal substrate, and the like. Further, an insulating structure (not shown) is interposed on the substrate. Between 1 and 1 and the capacitor. The S-insulating structure may have a single-layer structure made of an oxide layer, for example, and the ''a-hai insulating structure (not shown) may be used by using a bauxite glass ( BPSG), sulphate glass (PSG), undoped silicate glass 153355.doc 201227879 (USG), spin-on glass (SOG), flowable oxide (fox), tetraethyl ortho-nicotinic acid Ester (TEOS), plasma enhanced (PE)-TEOS, high density plasma-chemical vapor deposition (HDP-CVD) oxide and the like. On the other hand, the insulating structure (not shown) The multilayer structure may include at least one oxide layer, at least one nitride layer, and/or at least one oxynitride layer formed on the substrate 101. Here, by using oxidized oxide, nitriding, respectively矽 and niobium oxynitride to form an oxide layer, a nitride layer, and an oxynitride layer. Referring to FIG. 1A', a conventional example of the tantalum capacitor 400 in the tantalum capacitor region 3A includes a metal wiring 10a, a metal wiring 1〇3a. Upper and lower electrode 105a, dielectric layer 1〇7 and upper electrode 109a. Metal wiring 1〇3a It is made of the same material as the lower 卩 interconnect metal layer 〇3b, and is formed in the same manufacturing step as the lower interconnect metal layer 〇3b. The lower electrode 1 〇 5 & can be interconnected with the lower interconnect cap layer 1 The crucible 5b is made of the same material and is formed in the same manufacturing steps as the lower interconnect cap layer 105b. The metal wiring H)3a may be composed of aluminum (A1), copper (Cu) or gossip and combined with it. In the general aspect, the metal wiring 1〇3a may be composed of A1Cu. The lower electrode 105a can be formed by using a metal, an alloy or a conductive metal compound. For example, the lower electrode core may be at least one selected from the group consisting of: RU, Pt, TaN, (10), Ti, and
Cu、Hf、Cu或其合金’或可以單_或混合方式使用其中 每一者。在一通用態樣中，下部電極1〇5a可由谓（頂 部VTi(底部）層構成。可能需要Ti層以改良丁⑼與An之間 的黏著力。 153355.doc •12· 201227879 可形成介電層107以用於增加mim電容器400之電容。在 一通用態樣中，介電層107可由包括氮化矽（SiN)、氧化鈕 (Ta2〇5)、一氧化姶（Hf〇2)、氧化鋁（Al2〇3)及其類似者之絕 緣材料中之任一者構成。在另一通用態樣中，介電層107 可以諸如HfCVAhO3層及Al2〇3/Hf02層之堆疊結構形成。 在又一通用態樣中，介電層1〇7可以高k Hf〇2/Al2〇3膜堆疊 之重複結構形成。此外，Hf〇2層可有效於減小漏電流。在 通用態樣中，可使用原子層沈積（ALD)高k Hf〇2/Al2〇3 膜堆疊之重複結構來展示4 fF&m2與12 fF/^m2之間的電容 密度。 上部電極109a可藉由使用金屬、合金或導電金屬化合物 而形成。舉例而言，上部電極1093可為選自由以下各物組 成之群組的至少任一者：、Pt、TaN、WN、TiN、 TiAIN、Co、Cu、Hf、Cu或其合金，或可以單一或混合方 式使用其中每一者。在一通用態樣中，上部電極1 〇9a可由 TiN層構成，下部電極1〇5a可由TiN(頂部）/Ti(底部）層構 成。因此，上部電極l〇9a可包括不同於下部電極1〇5a之材 料的材料。 如先前所提及，下部電極105&之卩層可充當黏著層以改 良下部電極與金屬佈線1033之八1(：11層之間的黏著力。然 而，因為介電層107直接在上部電極109&以下，所以上部 電極109a不需要使用在TiN層之下的丁丨層。在上部電極 109a與介電層1〇7之間不需要丁丨黏著層。Cu, Hf, Cu or alloys thereof may be used singly or in a mixed manner. In a general aspect, the lower electrode 1〇5a may be composed of a top (top VTi (bottom) layer. A Ti layer may be required to improve the adhesion between the butyl (9) and An. 153355.doc •12· 201227879 can form a dielectric Layer 107 is used to increase the capacitance of mim capacitor 400. In a generalized form, dielectric layer 107 may comprise tantalum nitride (SiN), oxide button (Ta2〇5), hafnium oxide (Hf〇2), oxidation. Any of the insulating materials of aluminum (Al2〇3) and the like. In another general aspect, the dielectric layer 107 may be formed of a stacked structure such as an HfCVAhO3 layer and an Al2〇3/Hf02 layer. In a general aspect, the dielectric layer 1〇7 can be formed by a repeating structure of a high-kHf〇2/Al2〇3 film stack. In addition, the Hf〇2 layer can effectively reduce leakage current. In a general aspect, The repeating structure of the atomic layer deposition (ALD) high-k Hf 〇 2 /Al 2 〇 3 film stack is used to demonstrate the capacitance density between 4 fF & m 2 and 12 fF / ^ m 2 . The upper electrode 109a can be used by using metal, alloy or Formed by a conductive metal compound. For example, the upper electrode 1093 may be selected from the group consisting of Any one of: Pt, TaN, WN, TiN, TiAIN, Co, Cu, Hf, Cu or alloy thereof, or each of them may be used singly or in a mixed manner. In a general aspect, the upper electrode 1 〇 9a may be composed of a TiN layer, and the lower electrode 1〇5a may be composed of a TiN (top)/Ti (bottom) layer. Therefore, the upper electrode 10a may include a material different from that of the lower electrode 1〇5a. The lower electrode 105&s layer may serve as an adhesive layer to improve the adhesion between the lower electrode and the metal wiring 1033 (11 layer). However, since the dielectric layer 107 is directly below the upper electrode 109 & The electrode 109a does not require the use of a butadiene layer under the TiN layer. A butadiene adhesion layer is not required between the upper electrode 109a and the dielectric layer 1A.
此外，可在上部電極1093之上表面上形成硬式遮罩11U J53355.doc •13· 201227879 以獲得在上部電極1 〇9a之側面處形成之侧壁隔件之足夠高 度。僅上部電極1 〇9a之高度可能太小以至於不能界定在上 部電極109a之側面處之側壁隔件。因此，可能需要硬式遮 罩111a以使得在硬式遮罩111a及上部電極i〇9a之側面處形 成側壁隔件。 另外，硬式遮罩111 a在蝕刻上部電極I 〇9a之TiN層期間 減少聚合物之產生。若將光阻圖案用作遮罩而非硬式遮 罩，則在上部電極109a之側壁及介電層1 〇7之過度蝕刻部 分之上表面上產生大量聚合物。所產生之聚合物可能如同 電極表現，因為其含有已自上部電極109a轉移之金屬成分 之緣故。介電層107之過度蝕刻部分比介電層1〇7之原生 (as-grown)部分薄。因此，自金屬聚合物至介電層1〇7之變 薄部分發生漏電流，藉此使MIM電容器之可靠性降級。然 而’使用硬式遮罩111 a之触刻製程可在上部電極1 〇9a之側 壁上禁止聚合物產生，且防止上文提及之問題發生。 硬式遮罩111 a可以由氧化物層製成之單層結構形成。舉 例而言，硬式遮罩11 la可由以下各者構成：基於氧化矽之 材料（諸如 BPSG、PSG、USG、SOG、FOX、TEOS、PE- TEOS、HDP-CVD氧化物及其類似者）’或基於氮化矽之材 料（諸如SiN及Si ON)。硬式遮罩111a可具有包括至少一氧 化物層、至少一氮化物層及/或至少一氮氧化物之多層結 構。在一通用態樣中’氧化物層、氮化物層及氮氧化物層 可藉由分別使用氧化矽、氮化矽及氮氧化矽形成。硬式遮 罩111a之厚度可在約1〇〇 A至4000 A之範圍内。 153355.doc 201227879 此外，隔件121a可藉由氧化物層所製成之單層結構形 成。舉例而言，隔件121a可由以下各者構成：基於氧化矽Further, a hard mask 11U J53355.doc • 13· 201227879 can be formed on the upper surface of the upper electrode 1093 to obtain a sufficient height of the sidewall spacer formed at the side of the upper electrode 1 〇 9a. Only the height of the upper electrode 1 〇 9a may be too small to define the sidewall spacer at the side of the upper electrode 109a. Therefore, the hard mask 111a may be required to form the side wall spacers at the sides of the hard mask 111a and the upper electrode i〇9a. In addition, the hard mask 111a reduces the generation of polymer during the etching of the TiN layer of the upper electrode I 〇 9a. If the photoresist pattern is used as a mask instead of a hard mask, a large amount of polymer is generated on the upper surface of the upper electrode 109a and the upper surface of the over-etched portion of the dielectric layer 1 〇7. The resulting polymer may behave like an electrode because it contains a metal component that has been transferred from the upper electrode 109a. The over etched portion of dielectric layer 107 is thinner than the as-grown portion of dielectric layer 〇7. Therefore, leakage current occurs from the metal polymer to the thin portion of the dielectric layer 1〇7, thereby degrading the reliability of the MIM capacitor. However, the etch process using the hard mask 111a inhibits polymer generation on the side walls of the upper electrode 1 〇 9a and prevents the above-mentioned problems from occurring. The hard mask 111a may be formed of a single layer structure made of an oxide layer. For example, the hard mask 11 la may be composed of yttria-based materials (such as BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD oxide, and the like)' or A material based on tantalum nitride (such as SiN and Si ON). The hard mask 111a may have a multilayer structure including at least one oxide layer, at least one nitride layer, and/or at least one nitrogen oxide. In a general aspect, the oxide layer, the nitride layer and the oxynitride layer can be formed by using yttrium oxide, lanthanum nitride and yttrium oxynitride, respectively. The thickness of the hard mask 111a may range from about 1 〇〇A to 4000 Å. 153355.doc 201227879 Further, the spacer 121a can be formed by a single layer structure made of an oxide layer. For example, the spacer 121a may be composed of: based on cerium oxide
之材料（諸如 BPSG、PSG、USG、SOG、FOX、TEOS、PE TEOS、HDP-CVD氧化物及其類似者），或基於氮化碎之材 料（諸如SiN及SiON)。因為氮化矽相較於氧化碎可能更可 能在上部電極109a與下部電極l〇5a之間誘發不當之邊緣電 容，所以隔件121 a之材料可為氧化矽而非氮化石夕。 緩衝絕緣層123可存在於互連區域20〇與MIM電容写區域 300兩者之間。緩衝絕緣層123可覆蓋硬式遮罩111&之上表 面、隔件121a之側表面及下部電極l〇5a之暴露表面。因為 上部電極1 09a由隔件12 1 a及硬式遮罩11丨a封閉，所以緩衝 絕緣層123不接觸上部電極1 09a。緩衝絕緣層123可由含有 氮原子之氧化矽層（亦即’氮氧化矽（Si〇N))構成。因此， 緩衝絕緣層123可執行一抗反射層之作用，該抗反射層經 組態以在後續金屬圖案化期間增加微影製程之邊限。 此外’緩衝絕緣層123可同時執行一緩衝層之作用，該 緩衝層經組態以緩衝一導通體蝕刻目標。另外，緩衝絕緣 層123亦可用作一硬式遮罩，該硬式遮罩經組態以蝕刻金 屬佈線層103及第一金屬層105 (圖2A至圖2E中所說明）。為 了钮刻金屬佈線層103及第一金屬層1〇5，將光阻（pr)用作 遮罩。然而’ PR遮罩並不足以蝕刻金屬佈線層1〇3及第一 金屬層105 ^在一通用態樣中’緩衝絕緣層123之厚度可在 100 A至500 A之範圍内。另一方面，緩衝絕緣層123可藉 由使用有機底部抗反射塗層（BARC)而非無機SiON來形 153355.doc -15· 201227879 成。 此外’金屬間絕緣層13 1可形成於緩衝絕緣層123上方。 第一墊139a及第二墊139b以及第一抗反射層141a及第二抗 反射層141b可形成於金屬間絕緣層131上方。第一墊139a 及第二墊139b可分別經由第一插塞137a及第二插塞137b而 電連接至下部電極105a及上部電極l〇9a。第一插塞137a及 第二插塞13 7b可包括鎢（W)、銅及其類似者。在一通用態 樣中，第一插塞137a及第二插塞137b可包括鎢（W)。另 外’前金屬絕緣層（未展示）可插入於基板1〇1與金屬佈線 103 a之間。 圖1B說明圖1A之介電層107之鄰區之一實例的放大示意 性橫截面圖。可將介電層1〇7劃分為三個區域。第一區域 可為蝕刻介電區域l〇7a，該蝕刻介電區域1〇7a之蝕刻厚度 小於原生介電區域l〇7b之原生厚度。蝕刻介電區域1〇以可 自原生介電區域107b延伸。彎曲（或階梯式）介電區域1〇7(5 可處於在蝕刻介電區域107 &與原生介電區域⑺几之間的鄰 近部分。 蝕刻介電區域107a之厚度可小於原生介電區域1〇7b之厚 度，藉此增加電容。亦即，由於蝕刻介電區域i〇7a之厚度 減小，故電容增加。因此，因為钱刻介電區域ι〇^之存 在，所以可獲得此效應。 因為上部電極l〇9a與硬式遮罩111&彼此不同，所以可實 施彎曲介電區域1〇7c，隔件12"可形成於mim電容器_ 中以減少上部電極109a與下部電極1〇5a之間的漏電流。隔 153355.doc 16 201227879 件121a可覆蓋硬式遮罩Ilia、上部電極1 〇9a之側表面及介 電層107之暴露表面。在一通用態樣中，介電層1〇7之暴露 表面可包括蝕刻介電區域107a及彎曲介電區域i〇7c之表 面0 下部電極105 a之水平長度（或寬度）可大於上部電極丨〇9a 之水平長度（或寬度）。藉由形成介電層107，上部電極i〇9a 可與下部電極105a良好分離，藉此幫助抑制漏電流之產 生。若下部電極l〇5a與上部電極i〇9a具有相同寬度，則可 月b由電％沿者其側表面產生漏電流。相反地，如上文所描 述，若下部電極105a之寬度大於上部電極109a之寬度，則 有可能防止此問題。 如上文所描述’可使用隔件12ia及硬式遮罩丨丨丨3將mim 電容器400與外部環境隔離且保護該MIM電容器4〇〇以防各 種缺陷，藉此獲得良好漏電流特性。 將參看圖2A至圖2R描述一種根據通用態樣之製造MIM電 谷？§之方法。 圖2A至圖2R說明製造MIM電容器之一實例的橫截面圖。 儘管未在圖式中展示，但首先可在基板1〇1上形成下部 結構（未展示），且可在下部結構上沈積前金屬介電層（未展 示）。儘管未在圖式中展示，但下部結構可包括墊、導電 圖案、佈線、閘結構、電晶體及其類似者。 接著，如圖2A中所說明，可在前金屬絕緣層（未展示）上 依序'尤積用於下部電極之金屬佈線層1〇3及第一金屬層 105。可根據佈線製程所需之以（電阻）值而改變金屬佈線 153355.doc 17 201227879 層103之厚度。金屬佈線層l〇3可包括鋁（Al)、銅及其類似 者。在一通用態樣中，金屬佈線層1〇3包括A丨Cue 第一金屬層105可包括金屬、合金或導電金屬化合物。 舉例而言，第一金屬層105可為選自由以下各者組成之群 中之至少任一者：Ti、TaN、WN、TiN、TiAm或其任何 組合。在—通用態樣中，第一金屬層105包括TiN(頂 部）/Ti(底部）層。 隨後’介電層107可沈積於第一金屬層1〇5上。介電層 107可使用以下製程形成：原子層沈積（ald)製程、賤鍵製 程、脈衝雷射沈積製程、電子束沈積製程或化學氣相沈積 製程。在一通用態樣中，使用ALD來形成高k Hf02/Al203 膜堆疊之重複結構。 儘官稍後將描述，若具有高介電常數值之絕緣材料保留 於第一金屬層105上之導通體開口區域中，則在用於形成 導通體開口之蝕刻製程期間可能出現問題。然而，關於氮 化矽（SiN) ’不可能出現問題，因為氮化矽在形成導通體 開口時容易蝕刻，甚至當其繼續保留於第一金屬層1〇5上 之側面時亦如此。 可減小SiN之厚度以增加電容器之電容。若減小SiN之厚 度，則可導致漏電流。因此，若厚度相同，則較佳使用具 有南介電常數值之材料。另一方面，在形成介電層之 後’可針對介電層107另外執行熱處理製程、臭氧處理製 程、氧處理製程、電漿退火製程及其類似者，以改良介電 層107之電特性。 153355.doc •18· 201227879 介電層107可包括第一區域及第二區域。第一區域可為 一钮刻區域，其中在後續製程期間蝕刻該區域之一部分。 第二區域可為原生區域，該原生區域用作MIM電容器之介 電物質同時為非蝕刻區域。 緊接著，用作上部電極之第二金屬層1〇9可沈積於介電 層107上《第二金屬層109可使用金屬、合金或導電金屬化 合物形成。舉例而言’第二金屬層1〇9可為選自由以下各 者組成之群中之至少任一者：W、A卜Cu、Ti、TaN、 WN、ΤιΝ、TiAIN或其任何組合。在一通用態樣中，第二 金屬層109包括TiN。 後，硬式遮罩絕緣體i η可沈積於第二金屬層i 09上以 獲得待在上部電極之側面處形成之側壁隔件之足夠高度。 仍待形成之上部電極之高度可能太小以至於不能界定在上 部電極之側面處之側壁隔件。因此，需要硬式遮罩絕緣體 111以使彳于在硬式遮罩及仍待形成之上部電極之側面處形 成側壁隔件。可以在約⑽人至4刚A之範圍中之沈積厚 度來沈積硬式遮罩絕緣體i u。 可藉由使用化學氣相沈積（CVD)製程、低壓化學氣相沈 積（LPCVD)製私、電聚增強型化學氣相力積（pEc製程 或高密度錢化學氣相沈積（HDp_CVD)製程來形成硬式遮 罩、:緣體111。硬式遮罩絕緣體⑴可具有由氧化物層製成 之單層結構。舉例而言，硬式遮罩絕緣體i!可使用以下 兩者於氧化石夕之材料（諸如bpsg、 S〇G、F〇X、TE〇S、PE_TE〇s、HDp_CVD氧化物及其類 153355.doc •19· 201227879 似者），或基於氮化矽之材料（諸如SiN及SiON)。此外，硬 式遮罩絕緣體111可具有多層結構，該多層結構包括至少 一氧化物層、至少一氮化物層及/或至少一氮氧化物層。 此處’可藉由分別使用氧化矽、氮化矽及氮氧化矽來形成 氧化物層、氮化物層及氮氧化物層。 緊接著，如圖2B及圖2C中所說明，可將光阻（pr)層113 塗佈在硬式遮罩絕緣體111上，且接著將其圖案化以形成 充當第一 PR遮罩113a的第一光阻層圖案ii3a。 隨後，如圖2D中所說明，可使用相同遮罩來蝕刻硬式遮 罩絕緣體111及第二金屬層1〇9 ’從而產生硬式遮罩111&及 上部電極109a，且硬式遮罩111 a及上部電極1 〇9a可經圖案 化以使得其具有相同形狀。可在介電層1 〇7處停止蝕刻以 至於不將第一金屬層105暴露於外部。若在蝕刻硬式遮罩 絕緣體111及第二金屬層109時暴露第一金屬層1〇5，則產 生金屬聚合物，藉此導致漏電流。 由於可執行過度蝕刻以蝕刻第二金屬層1〇9，故可蝕刻 蝕刻介電區域107a之一部分，使得蝕刻介電區域1〇7a中之 介電層107之厚度可經形成為小於原生介電區域…几中之 介電層107之至少一厚度。此處，蝕刻介電區域1〇7&中之 剩餘介電層107之層厚度可在約100入至4〇〇〇 A之範圍内。 此外，可控制蝕刻介電區域1073中之剩餘介電層1〇7之厚 度以増強製程邊限。當將第一光阻層圖案丨13a用作遮罩層 來執行蝕刻製程時，可在蝕刻硬式遮罩絕緣體U1過程中 使用CF^CHxFy/CVNVAr之氣體或其類似者，可在蝕刻 153355.doc •20- 201227879 MIM電容器之上部電極之第二金屬層1〇9過程中使用Materials such as BPSG, PSG, USG, SOG, FOX, TEOS, PE TEOS, HDP-CVD oxides and the like, or based on nitrided materials such as SiN and SiON. Since the tantalum nitride may be more likely to induce an improper edge capacitance between the upper electrode 109a and the lower electrode 10a than the oxidized rug, the material of the spacer 121a may be yttrium oxide rather than nitrite. The buffer insulating layer 123 may exist between the interconnect region 20A and the MIM capacitor write region 300. The buffer insulating layer 123 may cover the upper surface of the hard mask 111 & the upper surface of the spacer 121a and the exposed surface of the lower electrode 10a. Since the upper electrode 119a is closed by the spacer 12 1 a and the hard mask 11 丨 a, the buffer insulating layer 123 does not contact the upper electrode 119a. The buffer insulating layer 123 may be composed of a ruthenium oxide layer containing a nitrogen atom (i.e., 'Si〇N). Thus, the buffer insulating layer 123 can function as an anti-reflective layer that is configured to increase the margin of the lithography process during subsequent metal patterning. Further, the buffer insulating layer 123 can simultaneously perform the function of a buffer layer configured to buffer a via etch target. Alternatively, the buffer insulating layer 123 can also function as a hard mask configured to etch the metal wiring layer 103 and the first metal layer 105 (described in Figures 2A-2E). In order to imprint the metal wiring layer 103 and the first metal layer 1〇5, a photoresist (pr) is used as a mask. However, the 'PR mask is not sufficient to etch the metal wiring layer 1〇3 and the first metal layer 105. ^ In a general aspect, the thickness of the buffer insulating layer 123 may be in the range of 100 A to 500 Å. On the other hand, the buffer insulating layer 123 can be formed by using an organic bottom anti-reflective coating (BARC) instead of inorganic SiON to form 153355.doc -15·201227879. Further, an intermetallic insulating layer 13 1 may be formed over the buffer insulating layer 123. The first pad 139a and the second pad 139b and the first anti-reflection layer 141a and the second anti-reflection layer 141b may be formed over the inter-metal insulating layer 131. The first pad 139a and the second pad 139b are electrically connected to the lower electrode 105a and the upper electrode 10a, respectively, via the first plug 137a and the second plug 137b. The first plug 137a and the second plug 13 7b may include tungsten (W), copper, and the like. In a generalized form, the first plug 137a and the second plug 137b may comprise tungsten (W). Further, a front metal insulating layer (not shown) may be interposed between the substrate 1〇1 and the metal wiring 103a. Figure 1B illustrates an enlarged schematic cross-sectional view of one example of the neighborhood of the dielectric layer 107 of Figure 1A. The dielectric layer 1〇7 can be divided into three regions. The first region may be an etched dielectric region 10a, the etched dielectric region 1 〇 7a having an etch thickness that is less than the native thickness of the native dielectric region 〇 7b. The dielectric region 1 is etched to extend from the native dielectric region 107b. A curved (or stepped) dielectric region 1 〇 7 (5 may be in an adjacent portion between the etched dielectric region 107 & and the native dielectric region (7). The etched dielectric region 107a may be less thick than the native dielectric region The thickness of 1〇7b, thereby increasing the capacitance. That is, since the thickness of the etched dielectric region i〇7a is reduced, the capacitance is increased. Therefore, this effect can be obtained because of the existence of the dielectric region ι〇^ Since the upper electrode 10a and the hard mask 111 & are different from each other, the bent dielectric region 1〇7c can be implemented, and the spacer 12" can be formed in the mim capacitor_ to reduce the upper electrode 109a and the lower electrode 1〇5a. Leakage current between the two. 153355.doc 16 201227879 Pie 121a can cover the hard mask Ilia, the side surface of the upper electrode 1 〇 9a and the exposed surface of the dielectric layer 107. In a general aspect, the dielectric layer 1 〇 7 The exposed surface may include the etched dielectric region 107a and the surface 0 of the curved dielectric region i 〇 7c. The horizontal length (or width) of the lower electrode 105 a may be greater than the horizontal length (or width) of the upper electrode 丨〇 9a. Dielectric layer 107, upper The electrode i〇9a can be well separated from the lower electrode 105a, thereby helping to suppress the generation of leakage current. If the lower electrode 10a and the upper electrode i〇9a have the same width, the monthly b can be generated by the side surface of the electric electrode. Leakage current. Conversely, as described above, if the width of the lower electrode 105a is larger than the width of the upper electrode 109a, it is possible to prevent this problem. As described above, the spacer 12ia and the hard mask 丨丨丨3 can be used. The mim capacitor 400 is isolated from the external environment and protects the MIM capacitor 4 from various defects, thereby obtaining good leakage current characteristics. A method of fabricating a MIM device according to a general aspect will be described with reference to FIGS. 2A to 2R. 2A through 2R illustrate cross-sectional views of one example of fabricating a MIM capacitor. Although not shown in the drawings, a lower structure (not shown) may first be formed on the substrate 1〇1 and may be deposited on the lower structure. Front metal dielectric layer (not shown). Although not shown in the drawings, the lower structure may include pads, conductive patterns, wiring, gate structures, transistors, and the like. Next, as shown in FIG. 2A It can be noted that the metal wiring layer 1〇3 and the first metal layer 105 can be sequentially used on the front metal insulating layer (not shown) for the lower electrode. It can be changed according to the (resistance) value required for the wiring process. Metal wiring 153355.doc 17 201227879 Thickness of layer 103. Metal wiring layer 103 may include aluminum (Al), copper, and the like. In a general aspect, metal wiring layer 1〇3 includes A丨Cue first The metal layer 105 may include a metal, an alloy, or a conductive metal compound. For example, the first metal layer 105 may be at least any one selected from the group consisting of Ti, TaN, WN, TiN, TiAm, or Any combination. In a generalized form, the first metal layer 105 comprises a TiN (top) / Ti (bottom) layer. Subsequently, a dielectric layer 107 may be deposited on the first metal layer 1〇5. The dielectric layer 107 can be formed using an atomic layer deposition (ald) process, a 贱 bond process, a pulsed laser deposition process, an electron beam deposition process, or a chemical vapor deposition process. In a general aspect, ALD is used to form a repeating structure of the high k Hf02/Al203 film stack. As will be described later, if an insulating material having a high dielectric constant value remains in the via opening region on the first metal layer 105, a problem may occur during the etching process for forming the via opening. However, it is unlikely that there is a problem with respect to niobium nitride (SiN) because tantalum nitride is easily etched when forming a via opening, even when it continues to remain on the side of the first metal layer 1〇5. The thickness of the SiN can be reduced to increase the capacitance of the capacitor. If the thickness of SiN is reduced, leakage current can be caused. Therefore, if the thickness is the same, it is preferable to use a material having a south dielectric constant value. On the other hand, after the formation of the dielectric layer, a heat treatment process, an ozone treatment process, an oxygen treatment process, a plasma annealing process, and the like may be additionally performed for the dielectric layer 107 to improve the electrical characteristics of the dielectric layer 107. 153355.doc • 18· 201227879 The dielectric layer 107 may include a first region and a second region. The first region can be a button region where a portion of the region is etched during subsequent processing. The second region may be a native region that serves as a dielectric material for the MIM capacitor while being a non-etched region. Next, a second metal layer 1〇9 serving as an upper electrode may be deposited on the dielectric layer 107. The second metal layer 109 may be formed using a metal, an alloy or a conductive metal compound. For example, the second metal layer 1〇9 may be at least any one selected from the group consisting of W, A, Cu, Ti, TaN, WN, ΤιΝ, TiAIN, or any combination thereof. In a general aspect, the second metal layer 109 comprises TiN. Thereafter, a hard mask insulator i η may be deposited on the second metal layer i 09 to obtain a sufficient height of the sidewall spacer to be formed at the side of the upper electrode. The height of the electrode to be formed still may be too small to define the sidewall spacer at the side of the upper electrode. Therefore, it is necessary to hard-mask the insulator 111 so that the sidewall spacers are formed at the side of the hard mask and the upper electrode to be formed. The hard mask insulator i u can be deposited in a deposition thickness in the range of about (10) to 4 just A. It can be formed by chemical vapor deposition (CVD) process, low pressure chemical vapor deposition (LPCVD), and electropolymerization enhanced chemical vapor deposition (pEc process or high density chemical vapor deposition (HDp_CVD) process). Hard mask: edge 111. The hard mask insulator (1) may have a single layer structure made of an oxide layer. For example, the hard mask insulator i! may use the following two materials for the oxidized stone (such as Bpsg, S〇G, F〇X, TE〇S, PE_TE〇s, HDp_CVD oxides and their likes 153355.doc •19·201227879), or materials based on tantalum nitride (such as SiN and SiON). The hard mask insulator 111 may have a multi-layer structure including at least one oxide layer, at least one nitride layer, and/or at least one oxynitride layer. Here, 'yttrium oxide, tantalum nitride can be used respectively. And yttrium oxynitride to form an oxide layer, a nitride layer, and an oxynitride layer. Next, as illustrated in FIGS. 2B and 2C, a photoresist (pr) layer 113 may be coated on the hard mask insulator 111. And then patterning it to form the first PR mask The first photoresist layer pattern ii3a of 113a. Subsequently, as illustrated in FIG. 2D, the same mask can be used to etch the hard mask insulator 111 and the second metal layer 1〇9' to produce a hard mask 111& and an upper electrode 109a, and the hard mask 111 a and the upper electrode 1 〇 9a may be patterned such that they have the same shape. The etching may be stopped at the dielectric layer 1 〇 7 so as not to expose the first metal layer 105 to the outside. Exposing the first metal layer 1〇5 when etching the hard mask insulator 111 and the second metal layer 109 generates a metal polymer, thereby causing leakage current. Since the over-etching can be performed to etch the second metal layer 1〇9, Therefore, a portion of the etched dielectric region 107a can be etched such that the thickness of the dielectric layer 107 in the etched dielectric region 1 〇 7a can be formed to be less than at least one thickness of the dielectric layer 107 in the native dielectric region. The layer thickness of the remaining dielectric layer 107 in the etched dielectric region 1〇7& can be in the range of about 100 Å to 4 Å. In addition, the remaining dielectric layer in the etched dielectric region 1073 can be controlled. The thickness of 1〇7 is limited by the force limit. When the first photoresist layer pattern 丨13a is used as a mask layer to perform an etching process, a gas of CF^CHxFy/CVNVAr or the like can be used in etching the hard mask insulator U1, which can be etched at 153355.doc •20- 201227879 The second metal layer of the upper electrode of the MIM capacitor is used in the process of 1〇9
Ch/BCh，且將沁、Ar或其類似者用作蝕刻輪廓控制之添 加氣體。在蝕刻之後，可藉由灰化製程來剝除第一光阻層 圖案113a。 緊接著，如圖2E中所說明，可沈積隔件絕緣體121作為 絕緣膜，以使得其覆蓋硬式遮罩1Uai上表面及側表面‘、 上部電極109a之側表面及介電層1〇7之暴露表面。隔件絕 緣體121可具有在約100 A至4〇〇〇 A之範圍中的沈積厚度。 隔件絕緣體121可使用與硬式遮罩絕緣體丨丨丨之沈積材料相 同之材料，此將在隔件絕緣體121與硬式遮罩絕緣體ui之 間保留黏著力問題。 可藉由使用化學氣相沈積（CVD)製程、低壓化學氣相沈 積（LPCVD)製程、電漿增強型化學氣相沈積（pECVD)製程 或高密度電漿化學氣相沈積（HDP-CVD)製程來形成隔件絕 緣體121。隔件絕緣體121可具有由氧化物層製成之單層結 構。舉例而言，隔件絕緣體121可使用以下兩者：基於氧 化石夕之材料（諸如BPSG、PSG、USG、SOG、FOX、 TEOS、PE-TE0S、HDP_CVD氧化物及其類似者），或基於 氮化矽之材料（諸如SiN及Si0N)。此外，隔件絕緣體l2i可 具有多層結構，該多層結構包括至少一氧化物層、至少一 氮化物層及/或至少一氮氧化物層。此處，可藉由分別使 用氧化矽、氮化矽及氮氧化矽來形成氧化物層、氮化物層 及氮氧化物層。 隨後，如圖2F中所說明，可回蝕介電層1〇7及隔件絕緣 153355.doc •21· 201227879 體121之暴露部分’直至暴露第一金屬層i〇5為止。另外， 可在硬式遮罩Ilia與上部電極109a兩者之側表面上及姓刻 介電區域l〇7a及彎曲介電區域i〇7c之表面上形成隔件 121 a。藉由使用過度蝕刻製程’可完全移除保留在導通體 開口區域處之介電區域107。若不完全移除蝕刻介電區域 107a，則蝕刻介電區域1 07a之剩餘部分可能在形成導通體 開口之後續蝕刻製程中充當蝕刻阻止層，藉此阻礙導通體 開口之形成。 結果’經由形成隔件121a之製程，介電層1〇7之水平長 度（或寬度）可形成為大於在介電層107上形成之上部電極 10 9a之水平長度（或寬度）。藉由形成比上部電極1〇9a寬大 之介電層107，上部電極l〇9a可與下部電極l〇5a良好分 離，藉此幫助抑制漏電流之產生。 另一方面’硬式遮罩11 la可能在蝕刻隔件絕緣體121之 製程中稍微受損。此可能歸因於硬式遮罩llla之材料與隔 件絕緣體121之材料相同。第一金屬層1〇5之暴露上部部分 可能在蝕刻隔件絕緣體121之製程中稍微受損。此可能歸 因於第一金屬層1 05之過度蝕刻，以確保僅保留隔件絕緣 體121之側表面。 當以此方式完成形成隔件121a之製程時，ΜΙΜ電容器 400可與外部環境完全分離。結果，隔件121a可執行保護 上部電極109a連同硬式遮罩11 la之側表面的作用。蝕刻介 電區域107a可存在於隔件121a之下，且下部電極i〇5a之第 一金屬層105可存在於蝕刻介電區域l〇7a之下。在一通用 153355.doc 22· 201227879 態樣中，存在於隔件121a之下的蝕刻介電區域1〇7a之厚 度可小於原生介電區域107b之厚度。上部電極1 〇9a、彎 曲介電區域107c及硬式遮罩Ilia可與隔件121 a之側表面接 觸0 隨後，如圖2G中所說明，可沈積具有基於氮化矽之材料 (諸如SiON)之緩衝絕緣層123作為一抗反射層，使得其覆 蓋硬式遮罩111a之上表面、隔件121 a之側表面、蝕刻介電 區域107a之側表面及第一金屬層105之暴露表面。緩衝絕 緣層123具有與用於隔件絕緣體121或硬式遮罩ma中之材 料不同之蝕刻速率。緩衝絕緣層123可在形成導通體孔時 第一次在緩衝絕緣體上誘發蝕刻停止。 在一通用態樣中，可藉由使用Si〇N形成緩衝絕緣層 123。SiON可執行用於在後續金屬圖案化期間增加微影製 程之邊限之抗反射層的作用。此外，緩衝絕緣層123可同 時執行用於緩衝導通體蝕刻目標之緩衝層之作用。在一通 用態樣中，可在約5〇 A至1 000 A夕f 4 # /π 之範圍内沈積緩衝絕緣層 123之厚度。 由於緩衝絕緣層123可沈積於基板1〇1之整個表面上，故 緩衝絕緣層123可與暴露於外部之下部電㈣&第一金 屬層105直接接觸。然@，因為可分別用隔件⑵日及硬式 遮罩⑴晴閉上部電極胸之側表面及上表面，所以緩衝 ::層123不與上部電極1〇9a接觸。隔件之下表面接㈣ 幻1電區域。隔件之側表面接觸硬式遮罩及上部電極。隔 件之f曲表面分別接觸緩衝絕緣層Μ曲介電區域。 I53355.doc -23· 201227879 此外’可藉由在350 °C至420 t：之溫度.範圍内使用 SiHVNaO氣體而沈積用於緩衝絕緣層1232Si〇N。考慮到 微影製程之邊限，n(折射率）及k(消光係數）之值可分別改 變至1.8-22及0.3 0-0.45。可藉由控制SiH4/N2〇之氣體比來 改變值η及k。值„及k可隨著8出4爪2〇之氣體比的減小而增 加’藉此用來增加n2o之分率。 此外，若反射率高，則相鄰光阻（PR)層可能歸因於漫反 射而溶解，藉此導致難以控制光DI臨界尺寸（CD)。有機 B ARC可用於緩衝絕緣層123而非無機siON。 另外，當導通體過度蝕刻目標小於約5〇〇〇 A時，可以在 約50 A至400人内之範圍中之相對低的厚度來沈積Si〇N以 確保微影製程之邊限，且將Si〇N用作用於精細圖案化之抗 反射層。 然而，當導通體過度蝕刻目標大於約5〇〇〇入時，以在約 400 A至1000 A之範圍中之厚度來沈積si〇N。此外，當蝕 刻形成一導通體時，藉由使用具有高C/F比（諸如，c4f8、 CsFs、C4Fe及其類似者）之氣體化學性質來增加氧化層至 SiON之钱刻選擇性》Si〇N在執行用於緩衝導通體蝕刻目 標之緩衝層之作用的同時執行用於精細圖案化之抗反射層 之作用。 另外’緩衝絕緣層123亦可用作用於蝕刻金屬佈線層1〇3 及第一金屬層105之硬式遮罩層。然而，僅pR遮罩可能不 足以蝕刻金屬佈線層103與第一金屬層1〇5兩者。此處，緩 衝絕緣層123之厚度可在約1〇〇入至5〇〇人之範圍内。 153355.doc •24- 201227879 緊接著’如圖2H及圖21中所說明，可在緩衝絕緣層123 上塗佈第二光阻層125,且藉由光微影製程使用第二遮罩 130來進行曝光並顯影’且接著進行圖案化以形成第二Pr 遮罩125a。 隨後’如圖2J中所說明’可藉由使用第二Pr遮罩丨25a蝕 刻緩衝絕緣層123。此外，可藉由以單一或混合方式使用 CHF3、CF4,及CHj2氣體而蝕刻緩衝絕緣層123。可添加諸 如Ns、〇2、Ar及其類似者之氣體以控制蝕刻速率或橫截面 輪廓。 緊接著，可將基板101置放於金屬蝕刻設備上。接著， 使用第二PR遮罩125a及緩衝絕緣層123依序蝕刻第一金屬 層105及金屬佈線層1〇3以形成金屬佈線及下部互連金 屬層103b、下部電極1053、及下部互連罩蓋層i〇5b，藉此 完成形成M!M電容器400之製程。此外，當蝕刻第一金屬 層1 〇5及金屬料層！ 〇3時可以單-方式使㈣2或Bci3， 且可使用諸如n2、c2h4、CH4、CHF3、Ar或其類似者之氣 體來實施橫截面輪廓。隨後，如圖2K中所說明，藉由使用 氧（〇2)電漿來移除第二光阻層圖案125a。 緊接著，如圖2L中所說明，為了填充金屬佈線職與下 部互連金屬層103b之間的區’可沈積金屬間絕緣層⑶。 可執行化學機械平坦化（CMp)製程 131 » 以平坦化金屬間絕緣層 隨後，如圖2M十所說明 圖示）來對第三光阻層（未圖 ，藉由光微影製程使用遮罩（未 示）進行曝光並顯影，且接著將 I53355.doc -25- 201227879 其圖案化以形成第三光阻層圖案133。 緊接著，如圖2N中所說明，可同時形成導通體開口 135a、135b及135c以分別連接上部電極1〇9a及下部電極 1 〇5a。藉由蝕刻層間絕緣層！ 3丨及緩衝絕緣層^來形成第 開口 135a，且藉由儀刻層間絕緣層13 1、緩衝絕緣層J 23 及硬式遮罩ma來形成第二開口13几。若在形成用於形成 下。卩電極105a之導通體開口時保留具有高介電常數之触刻 "電區域107a，則飯刻介電區域1〇7a可充當餘刻障壁從 而導致開口失效》然而，因為先前完全移除蝕刻介電區域 1 〇7a(例如，在圖2F中）’所以可防止開口失效。 隨後，如圖20中所說明，將用於填充第一開口 135a及第 一開口 13 5 b之第二金屬層13 7沈積於層間絕緣層1 3 1上。此 時，可藉由使用濺鍍製程、化學氣相沈積、原子層沈積 (ALD)製程、電子束沈積製程、脈動雷射沈積（pLD)製程及 其類似者來形成第三金屬層137。此外，可藉由使用鎢 (W)、鋁（A1)、鈦、鈕、鋼、氮化鎢、氮化鋁、氮化鈦、 氮化鈦銘、氮化鈕及其類似者來形成第三金屬層137。在 此實施例中，藉由使用鎢（W)來形成第三金屬層137。 緊接著’如圖2P中所說明，經由化學機械拋光製程來平 坦化第三金屬層137，以分別在第一開口 135a及第二開口 135b内形成第一插塞137a及第二插塞137b。此時，第一插 塞137a及第二插塞137b分別連接至下部電極i〇5a及上部電 極109a 〇 隨後，如圖2Q中所說明，依序將第四金屬層I”及抗反 153355.doc •26· 201227879 射層141沈積於包括第_插塞ma及第二插塞㈣之層間 邑緣層131上’且接著將第四光阻層（未圖示）塗佈於抗反射 層141上。 緊接者’儘管未展示於圖式中，但經由光微影製程使用 遮罩（未圖示）對第四光阻層（未圖示）進行曝光並顯影，且 將其圖案化以形成第四光阻層圖案143。 (W後如圖2R中所說明，藉由使用第四光阻層圖案⑷ 依序触刻抗反射層141及第四金屬層139,以形成分別經由 第-插塞137a及第二插塞137b連接至下部電極丨心及上部 電極胸的第一塾139a及第二塾⑽以及第一抗反射層圖 案141a及第二抗反射層圖案“lb ’藉此完成佈線形成製 程。將金屬插塞137a、⑽及抓分別連接至下部電極 105a、上部電極i〇9a及下部互連罩蓋層1〇5b。在一通用態 樣中，可將鎢（W)用於金屬插塞。可分別在金屬插^ 137a、137b及137c上方形成第一墊13%及第二墊13外以及 上部互連金屬層139c，藉此完成佈線形成製程。 如上文所描述，MIM電容器可與外部環境隔離且受保護 以防各種缺陷，藉此確保良好漏電流特性。另外，沈積於 金屬層之一上部部分上之SiON可在蝕刻期間緩衝一蝕刻目 標，藉此防止MIM電容器之擊穿電壓特性惡化。 此外，下部電極之水平長度（或寬度）可大於上部電極之 水平長度（或寬度）。藉由形成比上部電極寬大之介電層之 水平長度’上部電極可與下部電極良好分離，藉此幫助抑 制漏電之產生。因為實施根據上文引用之通用態樣之製造 153355.doc •27- 201227879 MIM電容的方法，所以關於擊穿電壓、缺陷密度及其類似 者可能具有極佳可靠性。 可使用包括諸如第一、第二等之術語來描述各種元件， 但該等元件不應受該等術語限制。僅出於將一元件與另一 元件區分之目的而使用該等術語。舉例而言，在不脫離以 下申請專利範圍之範疇的情況下，可將一第一元件命名為 一第二元件，且類似地，可將一第二元件命名為一第一元 件0 應注意，本文中所使用之術語並不僅限於描述通用態 樣。順便提及，除非另外清楚地使用，否則以單數形式: 表達包括複數意思。在此應用中，術語「包含」、「包 括」或其類似者意欲表達特性、數字、步驟、操作、： 件、零件或其組合之存在，且不欲排除另一特性’、、數字、 步驟、操作、元件、零件或其組合，或對其之任何添加。 除非另有定義’否則本文中所使用的包括技術或科學術 §吾之術語具有一般熟習此項技術者通常理解之相同音田。 本文中所使用之術語不應僅基於任何辭典之定義而二 所用領域之意思來解釋。另外，除非清楚地定義，否則本 文中所使用之術語不應解釋地太理想或正式。 上文已描述許多實例。然" 改。舉例而言，若以不同次序執行IS之:進行各種修 不同方式組合所描述之…技術及/或若以 ^ 、 乐統水構、裝置或電路中之组 件，及/或若由其他李且件< I蓉 ’'· 侔m…人 成其“物替換或補充該等組 則可達成適合結果。因此’其他實施係在以下申請專 153355.doc -28- 201227879 利範圍之範疇内。 【圖式簡單說明】 圖1A說明包括一互連區域及一 mim電容器區诚之半導體 裝置之一實例的示意性橫截面圖。 圖1B說明圖1A之介電層1〇7之鄰區之一實例的放大的示 意性橫截面圖》 圖2A至圖2R說明製造MIM電容器之一實例的橫截面圖。 貝穿圖式及[貫施方式]，除非另有描述，否則相同圖式 參考數字將理解為指代相同元件、特徵及結構。出於清晰 性、說明及方便起見，可放大此等元件之相斜大小及描 繪0 【主要元件符號說明】 101 基板 103 金屬佈線層 103a 金屬佈線 103b 下部互連金屬層 105 第一金屬層 105a 下部電極 105b 下部互連罩蓋層 107 介電層 107a 蝕刻介電區域/介電層突出部分 107b 原生介電區域 107c 彎曲介電區域 109 第二金屬層 153355.doc -29· 201227879 109a 上部電極 111 硬式遮罩絕緣體 1 11a 硬式遮罩 113 光阻（PR)層 113a 第一光阻層圖案/第一 PR遮罩 121 隔件絕緣體 121a 隔件 123 緩衝絕緣層 125 第二光阻層 125a 第二PR遮罩/第二光阻層圖案 130 第二遮罩 131 金屬間絕緣層/層間絕緣層 133 第三光阻層圖案 135a 導通體開口 /第一開口 135b 導通體開口/第二開口 135c 導通體開口 137 第三金屬層 137a 金屬插塞/第一插塞 137b 金屬插塞/第二插塞 137c 金屬插塞 139 第四金屬層 139a 第一墊 139b 第二墊 139c 上部互連金屬層 153355.doc -30- 201227879 141 抗反射層 141a 第一抗反射層/第一抗反射層圖案 141b 第二抗反射層/第二抗反射層圖案 141c 上部互連罩蓋層 143 第四光阻層圖案 200 互連區域 300 金屬-絕緣體-金屬（MIM)電容器區域 400 金屬-絕緣體-金屬（MIM)電容器 153355.doc •31 ·Ch/BCh, and 沁, Ar or the like is used as an additive gas for etching profile control. After the etching, the first photoresist layer pattern 113a may be stripped by an ashing process. Next, as illustrated in FIG. 2E, the spacer insulator 121 may be deposited as an insulating film such that it covers the upper surface and side surface of the hard mask 1Uai, the side surface of the upper electrode 109a, and the exposure of the dielectric layer 1〇7. surface. The spacer insulator 121 may have a deposition thickness in the range of about 100 A to 4 Å. The spacer insulator 121 can use the same material as the deposited material of the hard mask insulator ,, which will leave adhesion problems between the spacer insulator 121 and the hard mask insulator ui. By using a chemical vapor deposition (CVD) process, a low pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (pECVD) process, or a high density plasma chemical vapor deposition (HDP-CVD) process The spacer insulator 121 is formed. The spacer insulator 121 may have a single layer structure made of an oxide layer. For example, the spacer insulator 121 may use either: an oxide based material (such as BPSG, PSG, USG, SOG, FOX, TEOS, PE-TE0S, HDP_CVD oxide, and the like), or based on nitrogen. Chemical materials such as SiN and SiON. Further, the spacer insulator 12i may have a multilayer structure including at least one oxide layer, at least one nitride layer, and/or at least one oxynitride layer. Here, the oxide layer, the nitride layer, and the oxynitride layer can be formed by using yttrium oxide, lanthanum nitride, and hafnium oxynitride, respectively. Subsequently, as illustrated in Fig. 2F, the dielectric layer 1〇7 and the spacer insulating 153355.doc • 21·201227879 exposed portion of the body 121 can be etched back until the first metal layer i〇5 is exposed. Further, spacers 121a may be formed on the side surfaces of both the hard mask Ilia and the upper electrode 109a and on the surfaces of the first dielectric region 10a and the curved dielectric region i7c. The dielectric region 107 remaining at the open region of the via can be completely removed by using an overetch process. If the etch dielectric region 107a is not completely removed, the remaining portion of the etched dielectric region 107a may act as an etch stop layer in a subsequent etch process that forms the via opening, thereby preventing the formation of the via opening. As a result, the horizontal length (or width) of the dielectric layer 1〇7 can be formed to be larger than the horizontal length (or width) of the upper electrode 10 9a formed on the dielectric layer 107 via the process of forming the spacer 121a. By forming the dielectric layer 107 wider than the upper electrode 1 〇 9a, the upper electrode 10a can be well separated from the lower electrode 10a, thereby helping to suppress the generation of leakage current. On the other hand, the 'hard mask 11 la' may be slightly damaged in the process of etching the spacer insulator 121. This may be due to the fact that the material of the hard mask llla is the same as the material of the spacer insulator 121. The exposed upper portion of the first metal layer 1〇5 may be slightly damaged during the process of etching the spacer insulator 121. This may be due to over-etching of the first metal layer 105 to ensure that only the side surfaces of the spacer insulator 121 are retained. When the process of forming the spacer 121a is completed in this manner, the tantalum capacitor 400 can be completely separated from the external environment. As a result, the spacer 121a can function to protect the upper electrode 109a together with the side surface of the hard mask 11 la. The etched dielectric region 107a may be present under the spacer 121a, and the first metal layer 105 of the lower electrode i〇5a may exist under the etched dielectric region 107a. In a general 153355.doc 22 201227879 aspect, the thickness of the etched dielectric region 1 〇 7a present under the spacer 121a may be less than the thickness of the native dielectric region 107b. The upper electrode 1 〇 9a, the curved dielectric region 107c, and the hard mask Ilia may be in contact with the side surface of the spacer 121 a. Subsequently, as illustrated in FIG. 2G, a material based on tantalum nitride (such as SiON) may be deposited. The buffer insulating layer 123 serves as an anti-reflection layer such that it covers the upper surface of the hard mask 111a, the side surface of the spacer 121a, the side surface of the etched dielectric region 107a, and the exposed surface of the first metal layer 105. The buffer insulating layer 123 has an etching rate different from that used for the spacer insulator 121 or the hard mask ma. The buffer insulating layer 123 may induce an etch stop on the buffer insulator for the first time when forming the via hole. In a general aspect, the buffer insulating layer 123 can be formed by using Si〇N. SiON can perform the role of an anti-reflective layer for increasing the margin of the lithography process during subsequent metal patterning. Further, the buffer insulating layer 123 can simultaneously perform the function of buffering the buffer layer for etching the target of the via. In a general aspect, the thickness of the buffer insulating layer 123 may be deposited in the range of about 5 Å A to 1 000 Å f 4 # / π. Since the buffer insulating layer 123 can be deposited on the entire surface of the substrate 1〇1, the buffer insulating layer 123 can be in direct contact with the first metal layer 105 exposed to the lower portion of the external (4) & However, since the spacer (2) day and the hard mask (1) can be used to close the side surface and the upper surface of the upper electrode chest, the buffer :: layer 123 is not in contact with the upper electrode 1 〇 9a. The surface under the spacer is connected to the (4) illusion 1 electric area. The side surface of the spacer contacts the hard mask and the upper electrode. The curved surfaces of the spacers respectively contact the buffer insulating layer to distort the dielectric regions. I53355.doc -23· 201227879 Further, the insulating layer 1232Si〇N can be deposited by using SiHVNaO gas in a temperature range of 350 ° C to 420 t:. Considering the margin of the lithography process, the values of n (refractive index) and k (extinction coefficient) can be changed to 1.8-22 and 0.30-0.45, respectively. The values η and k can be changed by controlling the gas ratio of SiH4/N2〇. The values „ and k may increase as the gas ratio of 8 out of 4 claws 2〇 decreases', thereby increasing the fraction of n2o. Furthermore, if the reflectance is high, the adjacent photoresist (PR) layer may be returned. Dissolved by diffuse reflection, thereby making it difficult to control the critical dimension (CD) of the light DI. Organic B ARC can be used to buffer the insulating layer 123 instead of the inorganic siON. In addition, when the via over-etch target is less than about 5 〇〇〇A Si〇N may be deposited at a relatively low thickness in the range of about 50 A to 400 to ensure the margin of the lithography process, and Si〇N is used as an anti-reflection layer for fine patterning. When the via over-etch target is greater than about 5 in, the Si〇N is deposited in a thickness in the range of about 400 A to 1000 A. Further, when etching forms a via, by using a high C The gas chemistry of the /F ratio (such as c4f8, CsFs, C4Fe, and the like) to increase the oxide selectivity of the oxide layer to SiON"Si〇N performs the role of buffer layer for buffering the etch target of the via Simultaneously performing the function of the anti-reflection layer for fine patterning. The edge layer 123 can also serve as a hard mask layer for etching the metal wiring layer 1〇3 and the first metal layer 105. However, only the pR mask may not be sufficient to etch both the metal wiring layer 103 and the first metal layer 1〇5. Here, the thickness of the buffer insulating layer 123 can be in the range of about 1 to 5 。. 153355.doc •24- 201227879 Immediately following the description of FIG. 2H and FIG. 21, the buffer insulation can be used. A second photoresist layer 125 is coated on the layer 123, and exposed and developed using the second mask 130 by a photolithography process and then patterned to form a second Pr mask 125a. Subsequently, as shown in FIG. 2J It is explained that the buffer insulating layer 123 can be etched by using the second Pr mask 丨 25a. Further, the buffer insulating layer 123 can be etched by using the CHF3, CF4, and CHj2 gases in a single or mixed manner. For example, Ns can be added. , 〇2, Ar, and the like gas to control the etch rate or cross-sectional profile. Next, the substrate 101 can be placed on the metal etching apparatus. Next, the second PR mask 125a and the buffer insulating layer 123 are used. Etching the first metal layer 105 and the metal wiring layer 1〇3 to form The metal wiring and the lower interconnect metal layer 103b, the lower electrode 1053, and the lower interconnect cap layer i〇5b, thereby completing the process of forming the M!M capacitor 400. Further, when etching the first metal layer 1 〇 5 and metal Material layer! 〇3 can be made in a single-mode (4) 2 or Bci3, and the cross-sectional profile can be implemented using a gas such as n2, c2h4, CH4, CHF3, Ar or the like. Subsequently, as illustrated in Figure 2K, The second photoresist layer pattern 125a is removed by using an oxygen (〇2) plasma. Next, as illustrated in Fig. 2L, an inter-metal insulating layer (3) may be deposited in order to fill the region between the metal wiring and the lower interconnect metal layer 103b. A chemical mechanical planarization (CMp) process 131 can be performed to planarize the intermetallic insulating layer and then as illustrated in FIG. 2M to illustrate the third photoresist layer (not shown, using a mask by photolithography) (not shown) exposure and development, and then I53355.doc -25 - 201227879 is patterned to form a third photoresist layer pattern 133. Next, as illustrated in FIG. 2N, the via opening 135a may be simultaneously formed, 135b and 135c are respectively connected to the upper electrode 1〇9a and the lower electrode 1〇5a. The first opening 135a is formed by etching the interlayer insulating layer 3丨 and the buffer insulating layer, and is etched by the interlayer insulating layer 13 1 The insulating layer J 23 and the hard mask ma are formed to form the second opening 13. If the conductive region 107a having a high dielectric constant is retained while forming the via opening for forming the lower electrode 105a, the rice is served. The engraved dielectric region 1〇7a can act as a residual barrier to cause the opening to fail. However, since the etched dielectric region 1 〇7a (for example, in FIG. 2F) is completely removed previously, the opening failure can be prevented. As explained in 20, will be used A second metal layer 13 7 filling the first opening 135a and the first opening 13 5 b is deposited on the interlayer insulating layer 113. At this time, by using a sputtering process, chemical vapor deposition, atomic layer deposition (ALD) a process, an electron beam deposition process, a pulsed laser deposition (pLD) process, and the like to form a third metal layer 137. Further, by using tungsten (W), aluminum (A1), titanium, button, steel, A third metal layer 137 is formed by using tungsten nitride, aluminum nitride, titanium nitride, titanium nitride, a nitride button, and the like. In this embodiment, the third metal is formed by using tungsten (W). Layer 137. Next, as illustrated in FIG. 2P, the third metal layer 137 is planarized by a chemical mechanical polishing process to form a first plug 137a and a second plug in the first opening 135a and the second opening 135b, respectively. Plug 137b. At this time, the first plug 137a and the second plug 137b are respectively connected to the lower electrode i〇5a and the upper electrode 109a. Subsequently, as illustrated in FIG. 2Q, the fourth metal layer I" and the anti- Anti-153355.doc •26· 201227879 The shot layer 141 is deposited between the layers including the first plug and the second plug (four). On the edge layer 131' and then a fourth photoresist layer (not shown) is applied to the anti-reflective layer 141. The immediate image, although not shown in the drawings, uses a mask through the photolithography process (not The fourth photoresist layer (not shown) is exposed and developed, and patterned to form a fourth photoresist layer pattern 143. (W, as illustrated in FIG. 2R, by using the fourth light The resist layer pattern (4) sequentially etches the anti-reflection layer 141 and the fourth metal layer 139 to form a first germanium 139a connected to the lower electrode core and the upper electrode chest via the first plug 137a and the second plug 137b, respectively. The second turn (10) and the first anti-reflection layer pattern 141a and the second anti-reflection layer pattern "lb' thereby complete the wiring formation process. Metal plugs 137a, (10) and grips are respectively connected to the lower electrode 105a, the upper electrode i〇9a, and the lower interconnect cap layer 1〇5b. In a general case, tungsten (W) can be used for metal plugs. The first pad 13% and the second pad 13 and the upper interconnect metal layer 139c may be formed over the metal pins 137a, 137b, and 137c, respectively, thereby completing the wiring forming process. As described above, the MIM capacitor can be isolated from the external environment and protected against various defects, thereby ensuring good leakage current characteristics. In addition, SiON deposited on an upper portion of the metal layer can buffer an etch target during etching, thereby preventing deterioration of breakdown voltage characteristics of the MIM capacitor. Further, the horizontal length (or width) of the lower electrode may be greater than the horizontal length (or width) of the upper electrode. The upper electrode can be well separated from the lower electrode by forming a horizontal length of the dielectric layer wider than the upper electrode, thereby helping to suppress the occurrence of leakage. Since the method of manufacturing the 153355.doc • 27-201227879 MIM capacitor according to the general aspect cited above is implemented, it is possible to have excellent reliability with respect to breakdown voltage, defect density, and the like. The various elements may be described using terms such as first, second, etc., but such elements are not limited by the terms. These terms are used only for the purpose of distinguishing one element from another. For example, a first component may be named as a second component without departing from the scope of the following claims, and similarly, a second component may be named as a first component. The terms used herein are not limited to describing the general aspects. Incidentally, in the singular form, the expression includes the plural meaning unless otherwise clearly used. In this application, the terms "including", "including", or the like, are intended to mean the presence of the features, numbers, steps, operations, parts, parts or combinations thereof, and do not exclude another feature ', number, step , operations, components, parts or combinations thereof, or any additions thereto. Unless otherwise defined, the use of the term "technical or scientific" as used herein has the same meaning as commonly understood by those skilled in the art. Terms used herein should not be construed solely on the basis of the definition of any dictionary and the meaning of the fields used. In addition, terms used herein are not to be interpreted as ideal or formal unless clearly defined. Many examples have been described above. "Change". For example, if the IS is performed in a different order: the various techniques described are combined in various ways and/or if the components in the system, device, or circuit, and/or Pieces <I Rong''· 侔m... people become "substituting or supplementing these groups to achieve a suitable result. Therefore, other implementations are within the scope of the following application 153355.doc -28-201227879. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a schematic cross-sectional view showing an example of a semiconductor device including an interconnection region and a mim capacitor region. Fig. 1B illustrates one of the adjacent regions of the dielectric layer 1〇7 of Fig. 1A. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2A to FIG. 2R illustrate cross-sectional views of one example of fabricating a MIM capacitor. The bezel pattern and the [through mode], unless otherwise stated, the same figure reference numerals will be used. It is understood that the same elements, features, and structures are referred to. For the sake of clarity, description, and convenience, the skew size and depiction of such elements can be enlarged. [Main element symbol description] 101 Substrate 103 Metal wiring layer 103a Metal wiring 103b under Interconnect metal layer 105 first metal layer 105a lower electrode 105b lower interconnect cap layer 107 dielectric layer 107a etch dielectric region/dielectric layer protruding portion 107b native dielectric region 107c curved dielectric region 109 second metal layer 153355 .doc -29· 201227879 109a Upper electrode 111 Hard mask insulator 1 11a Hard mask 113 Photoresist (PR) layer 113a First photoresist layer pattern / First PR mask 121 Spacer insulator 121a Spacer 123 Buffer insulation layer 125 second photoresist layer 125a second PR mask / second photoresist layer pattern 130 second mask 131 inter-metal insulating layer / interlayer insulating layer 133 third photoresist layer pattern 135a via opening / first opening 135b Body opening/second opening 135c via opening 137 third metal layer 137a metal plug/first plug 137b metal plug/second plug 137c metal plug 139 fourth metal layer 139a first pad 139b second pad 139c upper interconnect metal layer 153355.doc -30- 201227879 141 anti-reflection layer 141a first anti-reflection layer / first anti-reflection layer pattern 141b second anti-reflection layer / second anti-reflection layer pattern 141c Upper interconnect cap layer 143 Fourth photoresist layer pattern 200 Interconnect region 300 Metal-insulator-metal (MIM) capacitor region 400 Metal-insulator-metal (MIM) capacitor 153355.doc •31 ·