TW201223106A - Digital linear voltage modulator - Google Patents

Abstract

The present invention relates to a digital linear voltage modulator which can output a modulated voltage, having high current efficiency and can be integrated into a variety of chip, which includes: at least a digital error detection circuit module, a first control logic circuit module, a second control logic circuit module, a mode indication module, a voltage divider circuit module, at least a push-up element circuit module and a pull-down device circuit module. Wherein at least a digital error detection circuit module outputs a logic signal according to the voltage difference value between a compared voltage and a reference voltage, while a first control logic circuit module and the second control logic circuit module separately control at least a push-up element circuit module and a pull-down device circuit module to output the aforementioned modulated voltage.

Description

201223106 VI. Description of the invention: [Technical field to which the invention pertains] It is possible to give: a digital linear voltage modulator, especially a modulation that is within or beyond the critical voltage range. Voltage, high current efficiency, and digital linear voltage modulators that can be integrated into a variety of wafers. [Prior Art] As a factory, voltage modulators can be roughly classified into two types, one is an exchange voltage regulator and the other is a linear voltage modulator. Among them, voltage regulators are often used in digital control systems. However, since the switching voltage regulator needs to convert the signal by the analog digital converter, there are a lot of traces in the circuit that are more than _ Φ # /, the inductor, and the switching voltage modulator is easy to integrate into one. Inside the wafer. Another benefit is that although the crossover of the switching voltage regulator is linear (4), it only needs to occupy a small wafer area, and it has a small capacitance. However, since the conventional linear voltage modulators are implemented in the form of analog circuits, when the linear voltage modulator operates in a high-speed environment, the magnitude of the quiescent current generated is smaller than the magnitude of the signal current. In fact, it is very significant 'the current efficiency of the conventional linear voltage modulator (C_ent Efficiency) is very limited. As shown in Fig. 1, it is a schematic diagram showing the circuit architecture of a conventional analog linear modulator. The analog analog linear modulator 1 is composed of an error amplifier (ΕΐΤ〇Γ Amplifier) 1 1 , an analog buffer 1 2 and a 201223106 output device 13 , and an analog buffer 丨The 2 series is coupled to the difference amplifier 1 1 and the output unit 13. When the analog analog modulator operates, the error amplifier n is used to compare the voltage difference between the reference voltage (~F) and the output voltage (ν〇υΐ) and the voltage difference is The value is transferred to the output element 丨3 via the analog buffer 丨2. Thereafter, the capacitive element 14 of the output element 13 is thus subjected to a charge and discharge operation such that the voltage of the output voltage CVour) is in the vicinity of the voltage of a target output voltage. Finally, the voltage (νουι) is supplied to the load 丨5. However, since the aforementioned error amplifier I丨 and analog buffer 丨2 are both composed of analog circuits, the performance of the error amplifier 丨丨 and analog buffer 丨2 is very sensitive to environmental changes, and the analogy is analogous to the linear modulation. The performance of the transformer (such as the voltage value of the output voltage) is also very sensitive to changes in the environment. Therefore, conventional analog linear modulators are often unable to operate at the operating point of the original design. As mentioned above, subject to the basic characteristics of analog circuits, the current efficiency of conventional linear voltage modulators (C_m) Efficiency) is quite limited and not easy to integrate into various types of wafers, which is known in the industry: Analog linear modulators are used in green energy-related applications (such as low voltage 'high current efficiency and smaller chips) The application of the area is not a small problem. So the industry has to be able to output - a modulation voltage that is within or beyond the threshold voltage range, a high current efficiency, and a digital linear voltage modulator that can be integrated into various wafers. SUMMARY OF THE INVENTION 201223106 The primary object of the present invention is to provide a digital linear voltage modulator that integrates a linear voltage modulator into a variety of wafers. . . SUMMARY OF THE INVENTION The object of the present invention is to provide a digital linear voltage modulator capable of outputting a modulation voltage in a range exceeding a threshold voltage or in a range close to a threshold voltage, and having high current efficiency. In order to achieve the above-mentioned goal, the digital linear voltage modulation crying is used to output a modulation voltage, including: at least - digital error sampling; the routing group is based on a comparison voltage and a reference voltage. Between the voltage difference output-logic signal; a first control logic circuit module, which is connected to the 乂6-bit difference detection circuit module to receive the logic signal; 7 second control logic circuit module , _ this at least - digital error detection, (four) receive this logic signal, a mode indicating module, is a light control circuit module, to set the voltage transformer circuit module of the modulation voltage, system, sub-job At this point, the mode indicating module and the h-digit error sensing circuit module; at least - pushing up the component circuit mode circuit:: connecting the first control logic circuit module; and - pulling down the component Wu, and the system is connected to this The second control logic circuit module. Wherein: the:::the logic circuit module and the second control logic circuit module are based on the state of the avoidance signal, and the operation mode of the at least one push-up component circuit module to read the circuit module is output The modulation voltage, phase =:f push component circuit module and the pull-down component circuit module; I cross voltage output terminal 'outputs the modulated electric energy A · A % output group from the modulated voltage output terminal, To adjust this to the second = output and _ the divider circuit circuit package soil is transferred to the voltage divider circuit module, the voltage divider 201223106 circuit mode, and then according to the mode set module The level of the modulation voltage is corresponding to the output voltage 至 to the at least “digital error detection circuit wedge group”, so that the at least one digital error detection circuit module outputs another logic signal. Therefore, in the digital linear voltage modulator of the present invention, the components included in the digital error detecting circuit module (ie, the first voltage control delay unit, the second voltage control delay unit, and the first inversion) , a first inverter, a third inverter, a fourth inverter, a fifth inverter 'sixth inversion, a seventh inversion 11, an eighth inverter, a first-reactor and The second positive second device and the like are all digital components, so the digital linear voltage modulator of the present invention not only greatly improves the current efficiency (up to 99 9%) compared with the conventional linear voltage modulator having an analog error amplifier. Level), which can be integrated into various wafers. In addition, the j-position linear voltage modulator of the present invention can maintain its number by properly designing the number of push-up element circuit modules and the number of types of voltages output by the voltage divider circuit modules thereof. Under the condition that the wafer area is less than a special value, continuously provide a modulation voltage in the range of exceeding the threshold voltage or close to the threshold voltage (such as a modulation voltage between 〇5 volts to γ volts) And can quickly switch the voltage of the modulated voltage it outputs to another voltage value (such as rapidly switching from 05 volts to 〇7 volts). On the other hand, the digital linear voltage modulator of the present invention has a digital error detection circuit module (such as three digital error detection circuit modules) and this; a digital error detection circuit module In order to operate, that is, it 201223106 is sequentially triggered to output a logic signal according to a voltage difference between a comparison voltage (Vmp) and a reference voltage (vREF). Therefore, in the digital linear voltage modulator of the present invention, the time period during which the logic signal is generated can be further shortened', so that the reaction time interval of the digital linear voltage modulator of the present invention is further shortened and can be the same The modulation voltage is modulated more times. Thus, the digital linear voltage modulation of the present invention can quickly switch the voltage of the modulated voltage outputted by it to another voltage value (for example, rapidly switching from 0.5 volt to 〇7 volt), and its output The stability of the modulation voltage can be greatly improved. [Embodiment] Please refer to Fig. 2' for a schematic diagram showing the circuit architecture of a digital linear voltage modulator according to an embodiment of the present invention. As shown in FIG. 2, the digital linear voltage modulator 2 of the embodiment of the present invention includes: at least one digital error detecting circuit module 21, a first control logic circuit module 22, and a second control logic circuit. The group 23, a mode indicating module 24', a voltage divider circuit module 25, a: /, a push-up component circuit module 26, and a pull-down component circuit module 27. The at least one digital error detecting circuit module 2 outputs a logical k number (not shown) according to a voltage difference between a comparison voltage (vCMP) and a reference voltage (Vref). H means that although 圊2 only shows the first-order digital error detection circuit module 2, in fact, the digital linear voltage regulator of the present invention can have different numbers of bit errors in different application environments. Detection circuit module 2!. 201223106 "In addition, the first control logic circuit module 22 and the second control logic circuit module 23 are respectively respectively connected to at least the digital error detection circuit module 2 to receive the aforementioned logic signal. In the embodiment, the digital linear voltage modulation «中 & type 曰T; ^ group 24 series to 帛 - control logic circuit module 22' voltage divider circuit module 25 are respectively connected to the mode Instructing the module 24 and the digital error detecting circuit module 21. In addition, at least one push-up device circuit group 26 is connected to the first control logic circuit module 22, and the pull-down device circuit module 27 is coupled. To the second control logic circuit module 23, it should be noted that in the embodiment, the foregoing logic signal includes a first-order logic signal and a second-order logic signal. However, in other application environments. The foregoing logic signal may include a different number of secondary logic signals. On the other hand, although in the digital linear voltage modulation of an embodiment of the present invention shown in FIG. 2, 丨, __ u & Π 乂 T T Up) a few pieces of circuit module 26 only contains a group The component circuit module is pushed. However, in other application environments, the at least one push-up component circuit module 26 may also include different sets of push-up component circuit modules, for example, including six sets of push-up component circuit modules. As shown in FIG. 2, the at least the upper-substance circuit module 26 and the pull-down device circuit module 27 are coupled to a modulation voltage output terminal "a" to output a modulation voltage (Vreg). The modulated voltage output 28a is recoupled to a load 29. On the other hand, the modulation voltage output terminal 28a is further coupled to the voltage divider circuit group 2: > to transfer (return) the modulation voltage (Vrkg) output from the modulation voltage output terminal 28a to the voltage division. Circuit module 25. 201223106, when the digital linear voltage modulator of an embodiment of the present invention operates, the first control logic circuit module 22 and the second control logic circuit module 23 are both based on the aforementioned logic signal (the first time included therein) The state of the logic signal and the second logic signal respectively controls at least one push-up component circuit module 26 (coupled with the first control logic circuit module 22) and the pull-down component circuit module 27 (with the second control logic circuit) The module 23 is coupled to operate in such a manner that at least one of the push-up component circuit module 26 and the pull-down component circuit module 27 cooperate with each other to output the aforementioned modulation voltage (Vrkg), and the output modulated voltage (Vr^) The level of the system is controlled by the mode indicating module 24. Subsequently, as previously described, this modulation voltage (Vrkg) is also transferred (returned) to the voltage divider circuit module 25 in addition to being output from the modulation voltage output terminal 28a. Then, the voltage divider circuit module 25 correspondingly outputs a further comparison voltage (VcMp·) to at least one digital error detection circuit module according to the level of the modulation voltage set by the mode indication module. So that at least one digit error extracting circuit module 21 can output a further logic signal (not shown) according to the voltage difference between the other comparison voltage 〜, and the aforementioned reference voltage ～γ). The logic circuit module 22 and the second control logic circuit module 23 of the digital linear panel modulator of the present invention are again based on the state of the logic signal (not shown). Controlling at least one of the upper component circuit module 26 and the pull-down component circuit module 27 to operate at least one of the push-up component circuit module 26 and the pull-down component circuit module 27 to output another modulation voltage (Vreg ). The level of the modulated voltage is also controlled by the mode indicating module 24. 201223106 Hereinafter, the digital error detecting circuit of the digital linear voltage modulator according to an embodiment of the present invention will be described in detail with reference to the drawings. Module circuit frame And a flow outputting a logic signal (including a first logic signal Q丨 and a second logic signal Q2). As shown in FIG. 3, it shows a digital linear voltage modulation according to an embodiment of the present invention. The schematic diagram of the circuit structure of the digital error detection circuit module includes a first delay line unit 31, a first flip-flop 32, and a second delay line. The unit 33, a second flip-flop 34, and a NAND gate 35. In addition, the first delay line unit 31 further includes a first voltage control delay single SD, a first inverter 311, and a The second inverter 312 and a third inverter 313, and the first voltage control delay unit 〇 is controlled by a comparison voltage (VcMp). On the other hand, the first delay line unit 33 further includes a first Two voltage control delay units 〇2, a fourth inverter 331, a fifth inverter 332, a sixth inverter 333 and a seventh inverter 334, and the second voltage control delay unit D2 is Controlled by a reference voltage (Vref). In the present embodiment, the first flip-flop 32 is The negative edge triggers the flip-flop, and has a first input terminal I, a first clock input terminal CLK|& a first output terminal 〇, wherein the first input terminal is coupled to the third The output terminal 'the first output terminal 反向 of the inverter 3丨3 outputs a first logic signal (Q丨). On the other hand, the second flip-flop 34 is also a negative edge triggering flip-flop, and Having a second input terminal 丨2, a second clock input terminal CLK2, and a second output terminal 〇2°, wherein the second input terminal h is coupled to the output end of the third inverter 313, the second output The second logic signal (Q2) is outputted by the terminal 〇 2. In addition, the first clock input terminal clk of the first 201223106 flip-flop 32 is coupled to the output terminal of the fifth inverter 332, and the second positive The second clock input of the inverter 34 is coupled to the output of the seventh inverter 334. Finally, in this embodiment, the anti-gate 35 includes an input terminal, a uniform energy terminal (EN) and an output terminal, and the input terminal of the opposite gate 35 is coupled to the output terminal of the fourth inverter 33 1 . The output of the anti-gate 35 is coupled to the eighth inverter 36. Subsequently, the eighth inverter 36 is recoupled to the first voltage control delay unit D| of the first delay line unit 3i and the second voltage control delay unit D2 of the second delay line unit 33. When the digital error detecting circuit module 2 is operated, the signal at the end point of the output side of the third inverter 313 is derived from a first voltage controlled delay unit, and is sent out through three inversions. The signal obtained after the delay of the first inverter 3U, the second inverter 3丨2 and the third inverter 3 1 3 is delayed. The signal 'between the Ci terminals located between the fifth inverter 332 and the sixth inverter 333 is derived from a second voltage controlled delay unit D2, and passes through two inverters (ie, the fourth inverter). The signal obtained after the delay of 331 and the fifth inverter 332). On the other hand, the signal at the C2 end point on the output side of the seventh inverter 334 is φτ' from the second voltage control delay unit A, and is passed through four inverters (ie, the fourth inversion|§33b The signals obtained after the delay of the fifth inverter 332, the sixth inverter 333, and the seventh inverter 334) are delayed. Therefore, based on the circuit characteristics of the D〇 endpoint, the C1 endpoint, and the C2 endpoint in the digital error detection circuit module 2, the voltage difference is different (ie, between Comparing the voltage difference between the voltage (ν [Μρ) and the reference voltage (VREF - 0.5 volts)), the digital error 201223106 of the present embodiment detects the first logic signal (Qi) and the output of the circuit module 21 The logical values of the secondary logic signal (Q2) respectively are as shown in the following list 1: Q1 logic value Q2 logic value V CMP < 0.495 volts 1 1 0.495 volts < Vcmp < 0.505 volts; special 0 ] 1 0.505 Volt <VCMP 0 0 Table 1

The second control logic circuit module 22 and the second control logic circuit module 23 of the digital linear voltage modulator of the embodiment of the present invention receive the first-order logic signal (Q1) and the second Secondary logic signal ((8) to control at least one push-up component circuit module % (coupled with the first control logic circuit module 22) and pull-down component circuit module 27 (with the second control logic circuit module, and -3 The operation mode is such that at least the push-up component circuit module % and the pull-down component circuit module 27 cooperate with each other to output the aforementioned modulation voltage (Vre(;).

... In addition, as mentioned above, the level of the modulation voltage (V(4)) is controlled by the mode right group 24 and the mode indicator module 24 controls the voltage divider circuit module 2 to accept the modulated voltage. (Vreg) is converted into - another - comparative thin (Vcmp), for example, a voltage close to a voltage of 0.7 volts (Vreg is converted to a voltage close to: - another voltage of comparison (VCMP). Finally, in this embodiment The digital error reading circuit module 21 shown in FIG. 3 includes the first reverse thief 311, the second inverter 3|2, the third reverse phase § 313, the fourth reverse cry, and the second time J31. The fifth inverter 332, the sixth inverter 12 201223106 333, the seventh inverter 334 and the eighth inverter 36 are all digital inverters, and the first flip-flop 32, the second positive and negative The device 34 and the anti-gate 35 are also digital components, so the digital error detection circuit module 2 1 is a digital circuit module, rather than an analog circuit module that constitutes a conventional analog error amplifier. Please refer to FIG. 4 again. , which is a schematic diagram showing the circuit architecture of the first voltage controlled delay unit shown in FIG. 3. The first voltage control delay The unit D has a first PMOS transistor 41, a second PMOS transistor 42, a third PMOS transistor 43, a fourth PMOS transistor 44, a first NMOS transistor 45, and an output inverter 46. In addition, the source of the first PMOS transistor 4 1 is coupled to a bias power supply (VDD), and the gate terminal of the first PMOS transistor 41 is coupled to a comparison voltage (VCMP). The source of the second PMOS transistor 42 is coupled to the drain of the first PMOS transistor 41, and the gate of the second PMOS transistor 42 is grounded. In addition, the source of the third PMOS transistor 43 The gate of the third PMOS transistor 43 is also grounded. As shown in FIG. 4, the source of the fourth PMOS transistor 44 is coupled to the third PMOS. The drain of the fourth PMOS transistor 44 is coupled to the drain of the first NMOS transistor 45, and is coupled to the output inverter 46. In addition, the gate of the first NMOS transistor 45 The gates of the fourth PMOS transistor 44 are coupled to each other and coupled to an input voltage (IN), and the output inverter 46 is coupled to an output voltage (OUT). The gate of the second PMOS transistor 42 and the gate of the third PMOS transistor 43 are grounded, and the second PMOS transistor 42 and the third PMOS transistor 43 are both turned on, 201223106 and can suppress the fourth PMOS. The coupling between the transistor 44 and the first NMOS transistor 45 is switched. When the first voltage control delay unit D! operates, the voltage input to the gate of the first PMOS transistor 41 is a comparison voltage (VcMp). And when the comparison voltage (VCMP) increases, the drain source voltage (Vds) of the first pm〇s transistor 41 becomes smaller, and the current flowing through the first PMOS transistor 41 is thus reduced. The power source (VDD) is reduced in charge rate to the circuit under the first PMOS transistor 41 via the first pmS transistor 41. Thus, as the comparison voltage (VCMP) increases, the delay time at which the input voltage (IN) of the first voltage-controlled delay unit D| is transmitted to the output voltage (?τ) is prolonged. Conversely, when the comparison voltage (VCMP) is decreased, the drain source voltage (VDS) of the first PMOS transistor 41 becomes large, and the current flowing through the first pmos transistor 41 is thereby increased, so that the bias power source ( Vdd) improves the charging rate of the circuit under the first PMOS transistor 41 via the first PM〇s transistor 4丨. Thus, when the comparison voltage (vCMP) is decreased, the delay time of the first voltage control delay unit D, the input voltage (in) is transmitted to the output voltage (?τ) is shortened. It should be noted that, in the foregoing digital error detecting circuit module 2, the second voltage control delay unit 〇2 has the same circuit architecture as the first voltage control delay unit, and the difference between the two Only the gate terminal of the first Ρ μ 〇 S transistor of the second voltage controlled delay unit D is coupled to the reference voltage (vR1ZF) instead of a comparison voltage (VcMp). Therefore, a detailed description of the circuit architecture and operation of the second voltage control delay unit D2 will not be repeated here.

201223106: The structure of the voltage control delay unit of 4 is not only the specific aspect of the implementation of the present invention, that is, the circuit structure of the voltage control delay unit is not limited to the circuit structure shown in Fig. 4, any available voltage To control | ^ state (four) way can be applied to the voltage-controlled delay unit of the digital error detecting circuit module of the digital linear voltage modulator of the present invention - Fig. 5 shows an embodiment of the present invention Digital linear electric dust modulator: Schematic diagram of the circuit structure of the voltage divider circuit board. In the middle, the partial pressure circuit module 5 is a resistive voltage divider circuit module, and in this embodiment The 'divider circuit module 5 includes six resistive elements 5Π, 512 513, 514, 515, 516 and six switching elements 52ι, (2) (2), similar, still, 526. In addition, 'each different switching element corresponds to The circuits respectively have different bifurcation ratios to convert the voltage division voltage of the modulation voltage to the vicinity of the voltage of the reference voltage (VREF) for the number (four) difference (four) circuit module to be as shown in FIG. 5, each switching element 52 522, 523, 524, 525, 52 The corresponding circuit has a voltage division ratio of 丨, 5/6 5/7, 5/8 '5/9 and 1/2 from top to bottom. Thus, the digital linearity of the present invention_embodiment The voltage divider circuit module of the voltage modulator can set a voltage (Vre (;) voltage (ie, the modulation voltage) within a range of a threshold voltage (four) r threshold that exceeds the threshold voltage ^uper thresh0(4). The voltage is between 〇.5 volts and 1 volt. The partial voltage is converted to the vicinity of the voltage of the reference voltage (Vri:f). Moreover, in the present embodiment, the reference voltage d丨) is W volt. 201223106 Although in FIG. 5, the voltage divider circuit module has one resistive element and six switching elements, the number is used to match the wheel-out voltage level of the digital linear voltage modulator of the present embodiment. The number (the output voltage level of the digital linear voltage modulator according to an embodiment of the present invention can be designed to be 0.5 volts, 0-6 volts, 0.7 volts, 〇8 volts, "volts, volts, 6 types) Therefore, in fact, the voltage divider circuit and the number of resistor elements and switching elements included There are no restrictions, they can be designed according to the number of voltage levels to be output, and the voltage divider circuit module is designed to have other numbers of resistance elements and switching elements. ' ' ''

The operation mode of the digital linear voltage modulator according to an embodiment of the present invention will be described in detail as follows: 2 First, please refer to the voltage divider circuit module 5 of FIG. 5, if an implementation of the present invention is to be implemented. For example, the digital linear voltage modulator outputs a voltage of 〇7 volts (VREG), and the mode indicator 24 controls the voltage divider circuit module 5 so that the voltage divider circuit module 5 has a voltage divider. The circuit of ratio 5/7 is turned on, that is, the switching element 523 is turned off.

Then, since the reference voltage (Vref) is set to 〇5 volts, the above-mentioned 〇7 volt modulation voltage (Vreg) is passed through the (5/7) voltage division ratio circuit to divide the 〇7 volt modulation voltage. Near to 5 volts. Subsequently, the voltage after the partial voltage conversion (referred to as another comparison voltage) is again transmitted to the digital error detector. At this time, the digital error detecting circuit module 2} compares the other comparison voltage (vCMP) with the reference voltage. Subsequently, the first logic control signal (Q1) and the second logic signal (Q2) are transmitted to the first control logic circuit module 22 and the second control logic circuit module 16 201223106 group 23, the first control logic circuit mode The group 22 and the second control logic circuit module 23 respectively control at least one push-up component circuit mode according to the logic values respectively received by the first logic control signal (Q丨) and the second logic signal (Q2) received. The group 26 and the pull-down component circuit module 27 operate in such a manner that at least one of the push-up component circuit module 26 and the pull-down component circuit module 27 cooperate with each other to output a modulation voltage (VREG). w When another comparison voltage (vCMP) is higher than the reference voltage (VRd (due to another

A comparison voltage (VCMP) is higher than 0.505 volts, and 〇5〇5 volts is higher than 0.5 (four) of the reference voltage.) The second control logic circuit module 23 controls the pull-down component circuit module 27 to adjust The voltage at the variable voltage output terminal "a is pulled down. Conversely, the m comparison voltage (VeMp.) is lower than the reference voltage (v-cho) (because another comparison voltage (VcMP) is lower than 0 495 volts, and 〇495 volts is low At 0.5 volts of the reference voltage, the first control logic circuit module 22 controls at least one push-up component circuit module 26 to push up the voltage of the modulated voltage output terminal 28a. "After this, the modulation voltage (Vr) [:g; K £ is transmitted (returned) to the voltage divider circuit, 25 to repeat the operation described above. This mode of operation is continuously cycled until the modulation voltage output from the modulation voltage output terminal 28a is The voltage is modulated to 〇7 volts. Please refer to Fig. 6, which is a schematic diagram showing the circuit architecture of a digital linear voltage modulator according to another embodiment of the present invention. As shown in Fig. 6, another aspect of the present invention: The digital linear voltage modulator 6 of the embodiment includes: "digital error detection" The switch group 6丨, the first control logic circuit module 'a second control logic. The circuit is changed 63 & type refers to the module 64, the voltage divider circuit module μ ' 201223106 6 push-up component circuit mode Group 66〗 662, 663, 665, 666 and - pull-down component circuit module 67. In the middle, the & bit error detection circuit module is based on a comparison voltage (VcMp) and a reference voltage (v_) The voltage difference between the two outputs a logic signal (not shown). In addition, the first control logic circuit module M62 and the second control logic circuit module 63 are respectively connected to the digital error detection circuit module 61. In order to receive the aforementioned logic signal, in another embodiment of the digital linear voltage modulator of the present invention, the mode indicating module 64 is coupled to the first control logic circuit module 62, and the voltage divider circuit module The group 65 is respectively coupled to the mode indicating module μ and the digital error detecting circuit module W. In addition, the above six push-up element circuit sets 661, 662, 663, 664, 665, 666 are coupled. Connected to the first control logic circuit module 62 and the mode finger * module 64, and indicated by the mode mode The group M control operates in an accumulation manner. On the other hand, the 'pull-down element circuit module is consumed to the second control logic circuit module 63. As shown in Fig. 6, the above-mentioned six push-up element circuit modules 66丨662, 663, 664, 665 '666 are respectively coupled to the modulating voltage output terminal 68a and the modulating voltage output terminal 68a to output a modulation voltage (V^G), and the modulation voltage output terminal 68a is Re-coupling to a load 69. On the other hand, the modulation voltage output terminal 68a is coupled to the voltage divider circuit module 65 to transmit the modulation voltage (Vreg) outputted by the modulation voltage output terminal 68a. Granted to the voltage divider circuit module 65. In this embodiment, the six push-up component circuit modules 661, 662, 663 '664, 665, 066 and the pull-down component circuit module 67 cooperate with each other to output a load having a maximum value of 100 m A. Current. 201223106 _ In addition, the circuit structures of the six push-up component circuit modules are respectively included in a circuit module and a transistor. For example, the push-up TL device circuit module 66 1 includes a driving circuit module 66 丨丨 and a PMOS transistor 66 丨 2, and the driving circuit module is “coupled to the first control logic circuit module 62 , The PMOS transistor 66丨2 outputs the load current required for any modulation voltage (VREG), such as any voltage between 55 volts and volts.

In the present embodiment, the pM〇s electro-crystalline systems respectively of the six push-up element circuit modules 661, 663 664 665, and 666 respectively cooperate with each other, and share the responsibility of providing load current. Thus, the digital linear voltage modulator of the other embodiment of the present invention can provide a load current of (10)_ at a different output voltage (VREG). Moreover, since each of the six push-up component circuit modules has a burden on the load-carrying component circuit module (the load current is supplied) is not large, so that each of the six push-up component circuit modules described above - The area of the chip required to push up the component circuit module can be further reduced, which effectively reduces the cost of the digital linear voltage modulator of another embodiment of the present invention. Figure 7 is a diagram showing the circuit architecture of a digital linear voltage modulator according to still another embodiment of the present invention. As shown in FIG. 7, the digital linear voltage modulator of the present invention is further referred to as a digital linear voltage modulator, and includes three digital error detecting circuit modules 7 1 1 , 7丨2, and 7 1 3 . , a first 松 丨 w 处 & ' ' ^ k system logic circuit module 72, a second control logic circuit module 73, - mode indicating module 74, a voltage divider device:: Group 7 5, A push-up element circuit module and 7 6 β _ , 悮, and 76 and a pull-down element circuit module. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The voltage difference of the voltage (Vr丨丨) outputs a logic signal (not shown). In the digital linear voltage modulator of another embodiment of the present invention, the three digital error_circuit modules The Sichuan and Sichuan '713 series materials operate, and the latter two digital error detection circuit modules 7丨2, 7丨3 are operated by the first digital error detection circuit module. And these 3 The time points at which the digital error detection circuit modules 711 '7丨2, 713 operate respectively (also referred to as the time points m to be triggered are respectively separated by a preset delay time (de|av time).

. . In this embodiment, the delay time is set to be equal to the detection time of the early-digital error detection circuit module (detecti〇n “coffee” is divided by the at least-digit error detection circuit module) For example, since the digital linear voltage modulator of the present embodiment has three digital error detecting circuit core groups, m, 713, the aforementioned delay time (7) e (four) time is one can be Single digital error detection circuit module detection time 3 equal time"

Thus, when the digital linear voltage modulator of another embodiment of the present invention operates, there is a digital error detecting circuit module every 1/3 of the single-digit error detecting circuit module detecting time. Because it is triggered, a logic signal (not shown) is output according to a voltage difference between the comparison voltage (vCMP) and a reference voltage (Vref), that is, if the digital linear voltage of the present invention is 5 weeks. The transformer has a greater number of digital error detection circuit modules, and the time period for generating logic signals (not shown) can be further shortened. 20 201223106 ...the logic circuit module 72 and the second control logic circuit &73; system is connected to three digits to detect the circuit module Chuan, 712, H to receive three digital error measurement circuit module The logic signals output by 711, 712, and 713 in sequence. η ... in this 33 and again "" examples of the digital ^ linear voltage adjustment

The second display module 74_ is connected to the first control logic circuit module ‘the voltage dividing circuit module 75 is connected to the mode indicating module Μ and the number (four) difference detecting circuit module 7丨. In addition, at least one push-up component circuit group 76 is switched to the first control logic circuit module 72, and the pull-down component circuit group 77 is coupled to the second control logic circuit module. Figure 7 is no, month; at least one of the push-up component circuit modules % should be: pull-element circuit module 77 mutual _ a variable voltage output terminal %, to: a modulation voltage (Vreg), The modulated voltage output 78a is recoupled to: load 79. On the other hand, the modulation voltage output terminal 78a is further coupled to the voltage divider: to transfer (return) the modulation voltage (vreg) outputted by the voltage output terminal 78a to the voltage divider circuit module for 5 weeks. When the digital line-type voltage (four) device of another embodiment of the present invention operates, the first control logic circuit module 72 and the second control logic circuit module 73 are both based on three digital error reading circuit modules. , 7] 2, 7丨3 sequentially output the state of the logic signal, respectively controlling at least the push-up component circuit module 7 6 (coupled with the first control logic circuit module 7 2) and the pull-down component circuit module 7 7 (coupled with the second control logic circuit module 733), such that at least the push/L device circuit block 76 and the pull-down device circuit block 77 cooperate with each other and the 201223106 outputs the aforementioned modulation voltage (vRPX) ·), and the level of the output modulated voltage (Vki ( ) is controlled by the mode indicating module 74. Subsequently, as described above, the modulated voltage (VkF 〇) K is output from the modulated voltage. In addition to the output of terminal 78a, it is also transmitted (returned) to voltage divider circuit module 75. Then, voltage divider circuit module 75 is based on the mode indicating module to set the level of the modulation voltage. Corresponding output one another comparison voltage to three digital error detection circuit modules 7n, 7丨2 7Π, so that the three bit error detecting circuit modules 71丨, 7丨2, 7丨3 can be based on the other comparison voltage (V(, N.n>) and the aforementioned reference voltage (Vrkf) The voltage difference between the two sequentially outputs another logic signal (not shown). The first control logic circuit module 72 of the digital linear voltage modulator according to another embodiment of the present invention The second control logic circuit module 73 again controls the operation mode of the at least one push-up component circuit module 76 and the pull-down component circuit module 77 according to the state of the other logic signal (not shown), so that at least one is The push component circuit module 76 and the pull-down component circuit module 77 cooperate with each other to output another modulation voltage (Vreg), and the level of the output modulation voltage is also controlled by the mode indication module 74. Therefore, Digital error detecting circuit module 7 1 1 , 7丨2, 71 3 'The time interval (reaction time interval) of the output voltage of the digital linear voltage modulator according to another embodiment of the present invention can be further Shortened. For example, the digital line of another embodiment of the present invention The reaction time interval of the voltage modulator can be greatly shortened from the reaction time interval (about 600 ps) of the digital linear voltage modulator of the embodiment of the present invention having only a single digital error detecting circuit module. /3 (about 200 ps). Therefore, since the modulation voltage can be modulated more and more times in the same 22 201223106, the output voltage modulation of the digital linear voltage modulator of another embodiment of the present invention is stable. The degree of stability is much higher than that of the digital linear voltage modulator output modulation voltage according to an embodiment of the present invention, and the technique for greatly improving the stability of the output modulation voltage is generally called time interleaved digital control. technology. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing the circuit architecture of an analog linear modulator of π. FIG. 2 is a schematic diagram showing the circuit architecture of a digital linear voltage modulator according to an embodiment of the present invention. 3 is a schematic diagram showing the circuit architecture of a digital error detecting circuit module of a digital linear voltage modulator according to an embodiment of the present invention. Figure 4 is a diagram showing the circuit architecture of the first voltage controlled delay unit shown in Figure 3. Fig. 5 is a view showing the circuit architecture of a voltage divider circuit module of a digital linear voltage modulator according to an embodiment of the present invention. Figure 6 is a diagram showing the circuit architecture of a digital linear voltage modulator according to another embodiment of the present invention. Fig. 7 is a schematic view showing the circuit architecture of a digital linear voltage modulator according to still another embodiment of the present invention. [Main component symbol description] I-class ratio linear variant 2,6,7 digital linear voltage modulator 5 voltage divider circuit module 丨丨 error amplifier 201223106 丨2 analog buffer 13 output component 14 electric grid component丨5, 29, 69, 79 load 21, 61, 7 丨丨, 7 丨 2, 7 丨 3 digital error detection circuit module 22 '62 '72 first control logic circuit module 23 '63 '73 second Control logic circuit module 24, 64, 74 mode indicating module 25, 65, 75 voltage divider circuit module 26, 66 662 '663, 664, (6), _, % push-up component circuit mode

27, 67 '77 pull-down component circuit module 28a, 68a, 78a modulation voltage output terminal 32 first flip-flop 34 second flip-flop 36 eighth inverter 42 second PMOS transistor 44 fourth PMOS transistor 46 output inverter 3 1 1 first inverter 3 1 3 third inverter 331 fourth inverter 333 sixth inverter I, first input 0, first output CLK2 second clock Input DO, Cl, C2 endpoints

31 first delay line unit 33 second delay line unit 35 reverse gate 41 first PMOS transistor 43 third PMOS transistor 45 first NMOS transistor D, first voltage controlled delay unit 3 1 2 second inverter

Ds second voltage control delay unit 332 fifth inverter 334 seventh inverter CLK, first clock input terminal 12 second input terminal 〇2 second output terminal 24 201223106 6611 drive circuit module 6612 PMOS transistor 511 , 512, 513, 514, 515, 516 resistive elements 521, 522, 523, 524, 525, 526 switching elements

Claims (1)

201223106 VII. Patent application scope: 1. A digital linear voltage modulator for output-modulation voltage, including: at least one digit error detection circuit module, based on a comparison voltage and a reference The voltage difference between the voltages outputs a logic signal; the first control logic circuit module is coupled to the at least two digit error detection circuit module to receive the logic signal; a second control logic circuit module coupled to the at least one digital error detection circuit module for receiving the logic signal; a mode indication module consuming the first control logic circuit module to set a voltage-dividing voltage level; a voltage divider circuit module is connected to the mode indicating module and the at least one digital error detecting circuit module; at least one push-up component circuit module is lightly connected To the first control logic circuit module; and the pull-down component circuit module, the shaft is connected to the second control module; Wherein the first control logic circuit module and the second control logic circuit group respectively control the operation mode of the at least 70 circuit modules and the pull-down component circuit module according to the state of the logic signal to perform The modulation voltage, and the at least -t ... push-up device circuit module and the pull-down circuit module are connected to a modulation voltage output terminal to output (four) variable voltage from the (four) output terminal; The variable voltage output terminal is connected to the voltage divider circuit module to transmit the modulation voltage to the voltage divider circuit; 26 201223106 group 'the voltage divider circuit module is further set according to the mode indicating module The sinusoidal power-changing level is 'corresponding to the output one another-comparing the voltage to the at least one-digit error detecting circuit module, so that the at least one digital error detecting circuit module outputs 'another logic signal. 2. The digital linear voltage modulator according to claim 1, wherein the logic signal comprises a first logic signal and a second person logic [number] and the first one is less digital error detection. The circuit module includes: a first delay line unit including a first voltage control delay unit, a first inverter, a second inverter, and a third inverter, and the first voltage control delay unit Controlled by the comparison voltage; a first positive and negative 11' system-negative edge triggering positive and negative feedback and including a -first input terminal, a first clock wheel input terminal and a first output terminal, and the first The input end is coupled to the third anti-South crying output, and the first output end outputs a far first logic signal; the first-second delay line unit includes a second voltage control delay unit, : a quadruple inverter 'a fifth inverter, a sixth inverter and a seventh reverse-and-first voltage control delay unit are controlled by the reference voltage: - a second flip-flop, a negative edge triggering flip-flop and including a first Γ clock input and a second output, The second heart is "wide" and the second output is outputted by the second output, and the second output is outputted by the second logical signal: and the 0:1 inverse gate ίτ' includes a round end, the _ enable end and a Output port; X port: the first clock-inverter of the first flip-flop is coupled to the output of the fifth inverter, - τ 弟 - the second clock input of the flip-flop 27 201223106 is connected to the output end of the seventh inverter; the input end of the anti-gate is coupled to the output end of the fourth inverter, and the output end of the anti-gate is coupled to the eighth reverse And the eighth inverter is recoupled to the first voltage control delay unit of the first delay line unit and the second voltage control delay unit of the second delay line unit. 3. The digital linear voltage modulator of claim 2, wherein the first inverter, the second inverter, the third inverter, the fourth inverter, The fifth inverter, the sixth inverter, the seventh inverter, and the eighth inverter are digital inverters. 4. The digital linear voltage regulator of claim 2, wherein the first voltage controlled delay unit comprises: a first PMOS transistor, a source coupling of the first PMOS transistor Connected to a bias power supply, the gate of the first PMOS transistor is coupled to the comparison voltage; a second PMOS transistor, the source of the second PMOS transistor is coupled to the first PMOS transistor The drain of the second PMOS transistor is grounded; a third PMOS transistor, the source of the third PMOS transistor is coupled to the drain of the second PMOS transistor, the third PMOS The gate of the transistor is grounded; a fourth PMOS transistor, the source of the fourth PMOS transistor is coupled to the drain of the third PMOS transistor; a first NMOS transistor, the first NMOS The drain of the crystal is coupled to the drain of the fourth PMOS transistor, and the gate of the first NMOS transistor 201223106 is mutually coupled with the gate of the fourth PMOS transistor, and then drained to the input voltage; And an output inverter connected to the wave of the first NM〇s transistor and the fourth PMOS The drain electrode body, and then connected to an output voltage consumption. 5. The digital linear voltage modulator of claim 1, wherein the amplitude of the modulation voltage is within a range of a threshold voltage or a threshold voltage. . . 6. The digital linear voltage modulation as described in claim 1 of the patent application, wherein the 6 Xuan transformer circuit is a resistor-type voltage divider circuit module, and the 戎 voltage divider circuit module includes 6 Resistive element and 6 switching elements. 7. The digital linear voltage modulation as described in claim 6 of the patent application, wherein the digital linear voltage modulator can divide and convert the voltage of the modulated voltage The system is between 0.5 volts and volts. π 8 · The digital linear voltage modulation state described in claim 6 wherein the number of the at least one push-up element circuit module is 6. 9. The digital linear voltage modulator of claim 8 wherein the six sets of push-up component circuit modules are operated in an accumulated manner and coupled to the first control logic circuit module, respectively. The digital linear regulator according to claim 1, wherein the at least one push-up component circuit module comprises a driving circuit group and a PMOS transistor, and a driving circuit module coupled to the first control logic The circuit module, the PM 〇 Sfaa 提供 body provides a load current required to output the modulating voltage. 201223106 11. The digital linear voltage modulator of claim 1, wherein the at least one digit The number of error detection circuit modules is 3. Eight, the pattern (see next page): 30