TW201220691A - Clockless return to state domino logic gate and integrated circuit and logic function evaluation method corresponding thereto - Google Patents

Abstract

A clockless return to state domino logic gate is disclosed responsive to multiple input nodes including at least one return to state node. A domino circuit presets a preset node to a first state. The domino circuit switches to a latch state and switches an output node when the preset node is pulled to a second state, and resets back to the preset state and switches the output node back to its default state when a reset node is pulled to the first state. An evaluation circuit pulls the preset node to the second state when the input nodes are in an evaluation state. An enable circuit enables a reset condition when the domino circuit is in its latch state. A reset circuit pulls the reset node to the first state after an evaluation event when the input nodes are no longer in the evaluation state and when the reset condition is established.

Description

201220691 VI. Description of the Invention: [Technical Field] The present invention relates to a logic circuit, and more particularly to a self-resetting return to state (RTS) domino logic gate, The operation does not have to rely on the clock signal and is used to respond to state transition (RTS) signals. [Prior Art] The setting of the logic circuit on the integrated circuit (1C) is usually for the purpose of performing logic operations quickly, and therefore, there are many possible layouts. In many instances, directing a clock signal to a circuit that provides logic operations is difficult and difficult to implement. Including static as well as dynamic logic gates and circuits, most logic circuits need to operate on an input clock. The static complementary MOS logic gate operates at a relatively low energy, but has a considerable input capacitance, and the signal is complementary. The P-type device and the N-type device are in a mutual force. Therefore, the static complementary MOS logic is half-logic. The operation of the gate is quite slow. Dominos are faster than the opposite static devices, but are almost always controlled by an input clock signal. This field of technology requires a logic circuit or logic gate that can perform logic operations in a faster and more efficient manner without the need for a clock signal. SUMMARY OF THE INVENTION A clockless state-return domino logic gate formed according to an embodiment of the present invention has a plurality of nodes, a domino circuit, an estimation circuit, a uniformity circuit, and a reset circuit. Each of the above nodes is designed to switch between a first state and a second state. Each of the input nodes is set to the first state, and then returns to the second state according to the state regression operation. The CNTR2460I00-TW/0608-A42737-TW/Final 4 201220691 state. The domino circuit has a preset state and a latched state. When the domino circuit is in the preset state, the domino circuit sets a preset node and a consistent node to the first state, and sets the output node and a first reset node to the second state. When the preset node transitions to the second state, the domino circuit switches to the latched state to transition the output node to the first state and to transition the enable node to the second state. When the first reset node transitions to the first state, the domino circuit resets to the preset state. When the input node is in any one of the at least one estimated state, the estimating circuit shifts the preset node to the second state; otherwise, the estimating circuit does not affect the level of the preset node. When the enabling node is in the second state, the enabling circuit switches the second reset node to the first state; otherwise, the enabling circuit does not affect the level of the second reset node. The reset circuit couples the first and second reset nodes together when the input node is not any of the at least one estimated state. The reset circuit isolates the first and second reset nodes from each other when the input node is any of the at least one estimated state. The estimation circuit and the reset circuit can be of a dual configuration with each other. The state regression technique can be implemented by a regression logic '〇' design for responding to the regression logic '〇' input signal, or can be implemented by the regression logic T to respond to the regression logic T input signal. An integrated circuit implemented in accordance with an embodiment of the present invention includes a first logic and a clockless state return domino logic gate. The first logic supplies a plurality of state regression signals. The state regression signals are each switched to a first state and a second state. Regarding each state regression signal, after being set to the first state, the first logic will return to the second state according to the state regression operation CNTR2460I00-TW/0608-A42737-TW/Final 5 201220691 card logic. The no-vehicle state returns to the bone - flute-1 preset node uniform energy node, the round-out node, and the helmet-time jrm first reset node, each switching to the first and second states. : The return of the pulse state back to the domino logic gate includes - domino circuit, an estimation circuit, a uniform circuit and a reset circuit. A logical operation estimation method implemented in accordance with an embodiment of the present invention. The method includes receiving a plurality of state regression signals. Regarding each shape: the second tiger t is operated according to the state after the setting to the -th state, the fth state. The method further includes supplying a -preset state and a ''fourth' - domino circuit. When the domino circuit is in the preset state, the preset node and the consistent energy node are in a first state, and the ::output node and a reset node are in a second state. When the preset node 1 reaches the first state, the domino circuit switches to the latched state. The field S reset node transitions to the first state 'the domino circuit transitions back to the pre-state' to transition the output node to the first state and transitions the enable: point to the second state. The method further includes estimating the state return input ° ° /, in the ° Hai, when the return rounding signal is in at least one of the estimated states, "turning the preset node to the second state, so that the The card circuit is switched to its flash lock state. The method is further included when the enabling node is in the second state and the state regression signal is no longer any of the at least one estimated state, and the reset node is the first state to reset the LY card The circuit is in this preset state. The no-clock state regression formed by the embodiment of the present invention has a plurality of nodes, a domino circuit, an estimation circuit, an enable circuit, and a reset circuit. Each node switches to a first state with CNTR2460l00-TW/0608-A42737-TW/Final ή 201220691 and a second state. At least one input node is a state regression node, and after being set to the first state, the second state is returned according to the state regression operation. The domino circuit has a preset state and a latched state. When the card circuit is in the preset state, the domino circuit sets a preset node and a consistent energy node to the first state, and sets an output node and a first reset node to the second state. When the preset node is pulled to the second state, the domino circuit switches to the latched state to pull the output node to the first state and pull the enable node to the second state. When the first reset node is pulled to the first state, the domino circuit is reset back to the preset state. When the input node is in any of the at least one estimated state, the estimating circuit pulls the preset node to the second state; otherwise, the estimating circuit does not interfere with the level of the preset node. The enabling circuit pulls the second reset node to the first state when the enabling node is in the second state. The reset circuit couples the first and second reset nodes together when the input node is not in any of the at least one estimated state; otherwise, the reset circuit converts the first and second weights The nodes are isolated from each other. The above state regression technique can be implemented as a regression logic '〇' architecture to respond to the return logic '〇' input signal. Alternatively, the state regression technique described above can be implemented as a regression regression logic 'Γ' to respond to the regression logic '1' input signal. The estimation circuit and the reset circuit can be used to collectively perform any required logic operations or functions, and need not be limited to each other's dual configuration design. In one embodiment, the estimation circuit corresponds to the aggregate state of the input node, and the reset circuit engages an input node that is less than the total number of input nodes. Regarding the input nodes provided to the reset circuit, each is a state regression section CNTR2460!00-TW/0608-A42737-TW/Final 7 201220691 in the spoon ^ invention - the integrated circuit produced by the embodiment, including The first-logic and one-no-nothing state return to the domino logic gate' logic provides at least one state regression signal, switching to the -first state = and a second state. Regarding each state regression signal, the first logic === is a state of the first state and then returns to the second state according to the state. The no-synchronization state returns to the domino logic idle-preset node, the consistent energy node, an output node, and - and a second reset node; each of the nodes is capable of switching between the first and the first. The description of the no-clock state return to the domino logic gate further includes a domino; a road, an estimation circuit, a uniform circuit, and a reset circuit. Short Army = an estimate formed according to an embodiment of the present invention - the logic includes the following steps. First, a plurality of inputs μ ′ are received, and the access signals are each switched between a first state and a second state. In addition, 'providing a domino circuit, operating in a preset state and a lock-like preset state, the domino circuit setting - preset node and consistent point to a first state, and setting a round out node and a weight Set the node to the second state. When the preset node is pulled to the second state, the domino circuit switches to the challenge state, transitions the output node to the first state and pulls the enable node to the second state. When the reset node is pulled to the first state, the domino circuit is reset back to the preset state. The method further includes a #·^ upper-side cancer regression input signal, and when the state regression input U is in any one of - the estimated state, the preset node is pulled to the second state 'to Domino circuit to the flash lock state. The method further includes: when the enabled node is in the second state and the state regression input b is not any one of the at least one estimated state, CNTR2460l00-TW/0608-A42737-TW/Final 8 201220691 The reset node pulls the first-to-be-dissociated signal to include at least one state back to the domino circuit. The above input state regression operation returns to the first: 2nd after setting the first state to the root, κ, - ‘step-state. According to the present invention, a solid domino logic gate includes a bone = a state of no-return state regression achieved by the state of the domino logic for == into the circuit. The clockless input logic signal is designed to be a logic signal, wherein the card circuit includes three inverters and a 2-state state switch. A device of the bone and - the second device, and in the form of a 〃帛-conducting - 1 ^ ^ /, - second conduction. The first inverting is coupled to the input and the output: the first connection node is coupled to the first output node between the output node and the enable node.筮一推士 An inversion to input Yes - Control the above output section: with the above preset node. The first device of the second conduction state has a second power supply potential connected to the second logic state, the m: the energy node, and a second current end face connected to the first weight = the first power supply potential node The control terminal is lightly connected to the input of the third inverter, and a first current terminal is connected to the preset node. When the input logic is in the - estimated state, the input circuit pulls the preset node to the first - logical state. When the input money transitions to the estimated state, the incoming circuit temporarily pulls the first reset node to the first logic state. In an embodiment, the input circuit includes an estimation circuit, an energy circuit, and a reset circuit. When the above input logic signal is an estimate cNTR2460I00-TW/0608-A42737-TW/Final 9 201220691 preset savings to the second logic state. Reset the node to the first :: 2: enable the circuit will - the second estimate state, the weight ^,. § The input logic signal is not in the two:: Γ, the first power potential node has - the first money 々 the second power supply (four) point has a reference potential, the conduction form is a semiconductor Ρ type design, the conductor Nf丨 design. ^ ^ The first material form is a half point right: in the two modes of implementation, 'the first power supply potential node potential, ΐ the second power supply potential node has a positive power supply open form for the semiconductor Ν type design, and the first Two conduction ^ conductor type 3 meter. The above input signal may include at least one regression signal, and according to different designs, the input signal will return to logic, r or regression logic, 〇,. The integrator f path implemented in accordance with an embodiment of the present invention includes at least one clockless state return domino logic gate and a first circuit. The second power supply is supplied with at least one state_signal, and is set to the second state according to the state return operation after the state return signal is set to the first state. The no-clock state return to the domino logic gate can be designed in a similar manner as described above. . A method of estimating multiple input logic signals. The input logic signals include at least one state regression input signal. The method includes setting a preset node to a first logic state, the first logic state being an inversion of a second logic state. The method further includes inverting the preset node to determine a logic state of an output node 'inverting the output node to determine a logic state of the consistent energy node, and shifting the state when the enabled node is the first logic state Setting a node to the second logic state, inverting the reset node to determine a logic state of an inverse CNTR2460I-TW/〇608-A42737-TW/FinaI 10 201220691 phase reset node, in which the reverse reset When the node is in the second logic state, the preset node is switched to the first logic state, and when the input signal forms an estimated state, the preset node is forced to the second logic state, and the transition state is the first logic. Reversing the state back to the at least one state regression signal of the second logic state, and forcing the reset node to be the first time when the enable node is the second logic state and the input signal trips the estimated state according to the state regression operation A logical state. In addition, when the reset node is forced to the first logic state, the inverting reset node returns to the second logic state, and then, the preset node is in the first logic state, and then, the transition state is Returning the node to the second logic state, and then transitioning the enable node back to the first logic state, then transitioning the reset node back to the second logic state, and then transitioning the inverted logic state The node returns to the first logical state. [Embodiment] The following description will help those skilled in the art to make and use the invention disclosed in the present specification for specific applications and conditions. Various modifications may be made by those skilled in the art in light of the embodiments disclosed herein, and the teachings disclosed herein may be practiced in other embodiments. Therefore, the scope of the invention is not intended to be limited to the particular embodiments shown and described herein The inventors have discovered a need in the industry for high speed, efficient, and logical operations that do not rely on clock signals. Therefore, the inventors developed a state in which the clock signal is not required to be returned to the domino logic gate, which is discussed below in Figures 1-17. 1 is a simplified block diagram illustrating a wafer (or an integrated body CNTR2460I00-TW/0608-A42737-TW/Final 11 201220691 way, IC) 101 including one implemented in accordance with an embodiment of the present invention. A clockless return to state domino circuit 105. The integrated circuit 1 can be of any type and can include any number of electronic circuits that have been developed in the art. In one embodiment, the wafer 101 is a processor, such as a microcontroller or microprocessor, and the like, and any type of integrated circuit or wafer may be used for it. A clock signal CLK is disposed on the integrated circuit ιοί and is received by a state regression logic 103. The state regression logic 1〇3 outputs one or more state regression rounding signals IN(RTS) to couple a plurality of input Lang points corresponding to the inputs of the clockless state return domino circuit. The clock signal CLK is also tied to the non-state return logic (NON-RTS l〇gic) i〇4. The non-state regression logic 104 outputs one or more non-state regression signals in (NON-RTS) to a plurality of inputs coupled to the corresponding inputs of the clockless state regression domino circuit 105. This is described in more detail below. The design of the input signal IN (the combination of IN (RTS) and IN (NON-RTS)) differs depending on the design of the input signal IN (without the clockless state returning to the domino circuit 1〇5). In some applications (for example, dual configuration/dual. configurations), each input signal IN is a state regression signal RTS (exemplified by a logic or gate design). In addition, in other applications (for example, non-dual configuration), at least one of the input signals in is a state regression signal RTS'. The remaining signals in the input signal in are state regression signals RTS or non- The state returns to the ΝΟΝ-RTS signal. Usually, it is necessary to develop and provide the above state regression signal under the following conditions. The above-mentioned clockless state return domino circuit 105 rotates one or more state regression output signals OUT(RTS) to another logic circuit 1〇7 related CNTR2460IOO-TW/0608-A42737-Ding W/Final 12 201220691 input terminal' And the clock signal CLK is also connected to the clock input of the logic circuit 107. The state return logic 1〇3 includes any combination of static or dynamic circuits' and further includes any latch or combination of register circuits. A turn-in signal IN (RTS) is provided in accordance with a state regression operation. Logic 1〇7 includes any combination of static or domino circuits (with pinned or unpinned) and/or any combination of latches or registers to receive, or latch, or The output signal OUT (RTS;) is temporarily stored. The state return input and output signals IN and out represent that the signal will return to a predetermined state or - first state after switching to a second state. In the binary logic, the state regression is not back to logic, 〇, (RT〇, its default logic state is logic, 〇,), is back to logic, 〗, ten T1, its default logic state is logic '1 ,). The clockless state regression domino circuit 1〇5 includes one or more clockless state return domino logic gates. The clockless state return domino logic gates are cascaded to each other or coupled together in any series or parallel manner. A variety of non-synchronous state regression domino logics have the opportunity to be cascaded or concatenated, limited only by time conditions, which are defined by whether the corresponding output signal is valid or not. Each (four) = state return domino logic gate can receive any number of state regression rounding signals and output at least one state return output signal to other circuits - including other no clock state return domino logic gates, or logic circuits 1〇7 'or other similar circuits. FIG. 2 is a block diagram illustrating a clockless state return domino logic gate 2〇〇 implemented in accordance with an embodiment of the present invention for implementing one or more of the no-pulse state regression in the domino circuit 1G5. No clock-like domino logic gate. The input signal IN or signals are supplied to the input node corresponding to CNTR2460I〇〇-TW/0608-A42737-TW/Final 13 201220691 to be input to the corresponding input end of a state regression estimation circuit 201, and at least one of the above The input signal IN is supplied to a state regression reset circuit 203. Although the same input signal IN is supplied to both circuits 201 and 203, it may be only one of the above-described input signals IN that is supplied to the state regression reset circuit 203 in some embodiments. A collection of ones. Additionally, the input signal IN can be a state regression signal (RTS) or can include one or more non-state regression signals (non-RTS). The clockless state return domino logic gate 200 further includes a state return domino circuit 205; the state return domino circuit 205 is coupled to a pair of power supply potentials VSRC1 and VSRC2. The power supply potentials VSRC1 and VSRC2 are each provided by a power supply circuit (not shown in the figure), and the power supply potential is uniformly supplied to a plurality of electronic circuits on the integrated circuit 101 at an appropriate potential, and the adopted technology can be a common technology in the technical field. . The potential supplied by each of the power supply potentials and the potential interval corresponding to the power supply potentials VSRC1 and VSRC2 are related to the circuit type and the particular technique or process, for example, 5 volts, 3.3 volts, or 2.1 volts. Typically, one of the power supply potentials VSRC1 and VSRC2 is a reference potential (e.g., VSS) and the other is a supply potential VDD, which can be implemented by techniques common in the art. The state regression estimation circuit 2 (Π, the state regression reset circuit 203 and the state regression enable circuit 207 can together form an input circuit, corresponding to the input signal IN. The state regression estimation circuit 201 is coupled to the power supply potential VSRC2, and is further coupled to The preset node 202 is coupled to the state to return to a preset input/output terminal PSET of the domino circuit 205. The state return domino circuit 205 has an output that supplies a state regression output signal OUT (RTS) to an output node 208, and Having a reset input and output terminal RST generates a reset signal (also CNTR2460I00-TW/0608-A42737-TW/Final 14 201220691 - labeled RST) at a reset node 206, and also has a state regression enable signal output The RTSE supplies a state regression enable signal (also labeled RTSE) to the corresponding one state regression enable node 204. The no-cycle state return domino logic gate 200 includes a state regression enable circuit 207 coupled to the power supply potential VSRC1. The state regression enabling circuit 207 has an input coupled to the node 204 to receive the state regression enable signal RTSE and has another endpoint coupled to a second reset node 210. The state regression reset circuit 203 is coupled between the reset nodes 210 and 206. Each signal node (eg, IN, OUT, PSET, RST, RTSE, etc.) has a first logic state and a second logic state; The first logic state is related to the power supply potential VSRC2, and the second logic state is related to the power supply potential VSRC1. The state regression estimation circuit 201 has an initial preset state, at which time each input signal IN is the first logic state, and its regression state. The return state is the same. When the input signal IN is in the same state as the transition state, forming one of the one or more estimated states, the state regression estimating circuit 201 enters an estimated state to generate an estimated event. The input signals IN The one or more estimated states - the generating of the estimated event - are related to the respective logic design of the state regression estimating circuit 201. For example, if the state regression estimating circuit 201 is designed as a logic or gate, then an estimated event is such Occurs when any one or more of the input signals IN occurs in a transition state from the first state to the second state. In another embodiment, if the state The regression estimation circuit 201 is implemented as a logic and gate, and an estimation event occurs only when each input signal IN transitions from the first logic state to the second logic state. The state regression domino circuit 205 typically has two The state includes a preset state ("preset" state) and a latch state ("latch" state). CNTR2460100-TW/0608-A42737-TW/Final 15 201220691 The preset state is usually the state returning the domino circuit The initial, or preset, value of 205. In the preset state, the state return domino circuit 205 presets its preset input/output terminal PSET, so the node 202 is in the second logic state. In addition, in the preset state, the state return domino circuit 205 initially sets the reset signal RST to the first logic state and sets the state regression enable signal RTSE to the second logic state. The state regression reset circuit 203 has an isolation state and a reset state determined by the state of the input signals IN applied thereto. When the input signals IN applied to the state regression reset circuit 203 are each at or return to the first logic state, the state regression reset circuit 203 is in its reset state. Otherwise, the state regression reset circuit 203 is in its isolated state. It must be specifically stated that the state regression reset circuit 203 is in its isolated state whenever the collective state of the input signals IN conforms to any one of the one or more estimated states. When the state regression enable signal RTSE is in the second logic state, the state regression enabling circuit 207 is in its initial preset state; when the state regression enabling signal RSTE is in the first logic state, the state returns to The power circuit 207 is transitioned to a consistent state. The operation of the clockless state return to the domino logic gate 200 is discussed below. An estimated event occurs when the input signal IN transitions to any one of the one or more estimated states; at this time, the state regression estimation circuit 201 enters its estimated state, and the state regression reset circuit 203 enters its isolation. status. In the above estimated state, the state regression estimating circuit 201 changes the signal of the node 202, and therefore, the preset input/output terminal PSET of the state return domino circuit 205 transitions to the first logic state, causing the state to return to the domino circuit 205 from The preset state is switched to the latched state. The state returning domino circuit CNTR2460I00-TW/0608-A42737-TW/Final 16 201220691-205 switches the output signal OUT to the second logic state when switching to its latched state, and switches the state regression enable signal RTSE to the first The logic state, and the reset signal RST is no longer affected. The state regression enable circuit 207 enters its enable state, coupling node 210 to the power supply potential VSRC1 in response to the state return enable signal RTSE of the first logic state. Since the state regression reset circuit 203 is in response to the input signal IN being in its isolated state, even if the state regression enabling circuit 207 is enabled, the reset signal RST is not affected. For the above reasons, the reset signal RST remains in the first logic state. When the state regression input signal IN supplied to the state regression reset circuit 203 returns to its preset state according to the state regression operation, the state regression reset circuit 203 enters its reset state, coupling the reset nodes 210 and 206 together. The reset signal RST is pulled to the second logic state by circuits 203 and 207. The transition of the reset signal RST to the second logic state causes a reset event to cause the state return domino circuit 205 to return to its preset state. As explained below, the state return domino circuit 205 changes the potential of its preset input and output terminal PSET, causing the node 202 to return to the second logic state. In addition, state returning card circuit 205 switches output signal OUT back to the first logic state and switches state return enable signal RTSE back to the second logic state. The state return enable circuit 207 is effectively turned off corresponding to the state transition enable signal RTSE to the transition state of the second logic state, and the state return domino circuit 205 pulls the reset signal RST back to the first logic state. In summary, when the input signal IN is in the same state as any one of the one or more estimated states, the state regression estimation circuit 201 transitions to an estimated state, generating an estimated event, and the state regression reset circuit 203 enters An isolated state. In response to the above estimated event, the state regression domino circuit 205 transitions from the CNTR2460I00-TW/0608-A42737-Ding W/Final 17 201220691 its preset state to the question lock state, switches the output signal OUT, and switches the state regression enable signal RTSE. This state regression enable circuit 207 is enabled. The state regression estimation circuit 201 returns to its preset state when the respective state regression input signals IN, or at least the state regression input signals IN supplied to the state regression reset circuit 203 return to the first logic state according to the state regression operation. And the state regression reset circuit 203 enters its reset state to pull the reset signal RST to the second logic state to generate a reset event. The reset event should be returned, the state returning to the domino circuit 205 back to its pre-set state, causing the state return enable signal RSTE to return to the second logic state to disable the state regression enable circuit 207. Once the state regression enable circuit 207 is disabled, the state of the state regression reset circuit 2〇3 no longer affects operation until another estimated event occurs. The state return to the domino circuit 2〇5 then pulls the reset signal RST back to the first logic state, causing the timeless pulse, the % return domino logic gate 200 to be ready for the next estimated event. As a result, the clockless state returns to the domino logic gate 2 as a self-reset circuit. A logic condition estimation is achieved without the clock signal. The following is a discussion of a regression-free logic 'O' (RTO) logic gate design with no clock state returning to the domino logic gate 2 and a regression 叩 叩 逻辑 logic gate design. The regression logic, 〇, logic gate design is the limb response regression logic, input signal. The regression logic, Γ logic gate design is used to respond to the return logic T input signal. In some embodiments, the state regression estimation circuit plus, and the state regression reset circuit 2G3 is a dual configuration (4) (10) design to respond to the same state regression input signal IN. In the mode of application (for example, the first 〇盥17p 七 4, the spoon tongue ...\ a non-implementation mode), the state regression reset circuit 203 is simplified, wherein the temple is supplied to the state back to the estimated The state regression input signal IN of CNTR2460IOO-TW/0608-A42737-TW/Final, 0 Kaisaki I Ο 201220691 201 is also supplied to the state regression reset circuit 203, and the state regression estimation circuit 2〇1 The same logical transfer will be performed by the state regression reset circuit 2G3 on the selected subset of the state regression input #1>^. In other embodiments, the circuits 201 and 203 are not dual configuration designs and are supplied to the circuit 2〇 Only one subset of the input signals IN of 1 is supplied to the state regression reset circuit 2〇3. The input signals IN supplied to the state regression reset circuit 203 are state regression signals, regardless of the remaining input fingers IN being state regression (RT phantom or non-state regression (non-RTS) signals. In any of the implementations described In the mode, when the estimation state is true, the reset state is not established. When the state regression estimation circuit shows that the estimation state is not met, the estimation state is not established. When the estimation state is not established, but the reset condition of the state regression reset circuit is established, The reset state is established. Fig. 3 is a block diagram 'illustrating a clockless regression logic', a domino logic gate 300, a regression logic '0' implementation for returning the domino logic gate 200 without the clock state. The output signal OUT and the at least one input signal IN are designed to be a return logic '0' signal, with logic, 〇, being a preset logic state. Based on the prior art in the prior art, the power supply potential VSRC1 is used as a supply potential VDD, and the power supply potential is VSRC2 serves as a reference potential VSS. The state regression estimation circuit 201, the state regression domino circuit 205, and the state regression reset circuit 203 are implemented as The regression logic '0' estimation circuit 3〇1, a regression logic '〇' domino circuit 305, and a regression logic reset circuit 303 are designed according to the regression logic operation. It must be noted that although circuits 301 and 303 are used One may isolate other circuits as a regression logic '1, the circuit (with its output view), but still rely on its input and return logic, 〇, domino logic gate 300 as a whole function of the return logic, 〇 , CNTR2460I00-TW/0608-A42737-TW/Final 19 201220691 technology. The preset input and output terminal PSET is implemented as a pre-charge input wheel output terminal PCHG. The pre-charge input and output terminal pCHG is coupled to a pre-charge node 302; The pre-charge node 302 implements the aforementioned preset node 2〇2. The clockless regression logic '〇' domino logic gate 300 sets a regression logic, 〇_, the output signal is applied to an output node 308, and the reset signal RST Then generated at the reset node 306. The foregoing state regression enable node 2〇4 is implemented as a regression logic, and the enable node 304' is coupled to the gate of the P channel device-1. The p-channel device P1 implements the foregoing State regression The circuit 207 has a source coupled to the power supply VDD and is coupled to the return logic '〇' reset circuit 303 via a second reset node 31. Regression logic, 〇, reset Circuit 3〇3 is further coupled to reset node 306. Figure 4 illustrates a regression logic '〇' domino circuit 4〇〇, which is an embodiment of regression logic, 〇, domino circuit 305. Pre-charge node 3〇2 is coupled The input terminal of the inverter 401 is coupled to the drains of the p-channel devices p2 and p3. The output of the inverter 401 is coupled to the output node 308 to provide the regression logic, 〇, the output signal OUT(RTO)' It is supplied to the gate of the p-channel device p3 and the input terminal of the other inverter 403. The output of inverter 403 is coupled to node 304 to supply the return logic, 〇, enable signal RT0E to the gate of N-channel device N1. The source of the N-channel device N1 is coupled to the reference potential VSS, and its drain is coupled to the reset node 306 to supply the reset signal RST. The reset signal RST is supplied to the input of an inverter 405. An inverting reset signal RSTB is supplied to the output of the inverter 405. The inverting reset signal RSTB is supplied to the gate of the P channel device P2, and its source is coupled to the power supply potential VDD. The inverter 401 and the P-channel device P3 form a half-keeper circuit 402 to maintain the level of the pre-charge input and output terminal PChG until the return logic '〇' CNTR2460I0〇-TW/0608-A42737-TW/ Final 20 201220691

The estimation circuit 301 pulls it low. The precharge input/output terminal pcHG is initially precharged to a high level, so the 'inverter 4〇1 causes the output signal OUT to be at a low level to turn on the P channel device P3. The p-channel device P3 pulls the precharge input/output terminal PCHG to the supply potential VDD to maintain the high level logic state of the precharge input/output terminal PCHG. Since the output signal OUT is initially at a low level, the inverter 403 causes the return logic, 〇, enable signal rT〇e to turn on the N-channel device N1' to pull down the level of the reset signal RST. Inverter 405 thus provides a high level inverted reset signal RSTB that disables p-channel device P2. Referring to Figures 3 and 4, in response to an estimated event generated when one or more of the input signals IN transitions to one or more of the estimated states, the regression logic '〇' estimates the circuit 3〇1 to precharge the input. The output pCHG level is pulled low, causing the return logic '〇' domino circuit 4 to transition to its latched state. Therefore, the inverter 401 pulls up the level of the turn-out signal out, so that the p-channel device P3 is not turned on. The inverter 4〇3 will pull down the return logic, 〇, enable the level of the RT0E signal to make the P channel device? 1 Turn on and make ^^ channel ιΝ1 non-conducting. The P channel device P1 # is turned on to connect the node 31 to the supply potential VDD. The ON of the N-channel device N1 causes the reset signal RST to no longer be limited to a low level. The input signal IN (four) calculation state causes the regression logic, 〇, reset circuit 303 to transition to its isolated state, causing the node to isolate node 310. In this way, the reset node 3〇6 will be temporarily isolated, so the reset signal will not be made into the (four) state. Since there is no other device: the 'reset signal RST is still _ at the low level. In another implementation, 有 1 has an N-channel device, which is indicated by a dotted line, and is supplied in the circuit of FIG. 4, and the reverse pirate 405 constitutes another semi-sustain circuit, with the low-level state of the number RST. The channel device device 2 has a reset signal of the CNTR2460I00-TW/0608-A42737-TW/FinaI, a reception counter 201220691 phase reset signal RSTB, a drain connection node 306, and a source connection reference potential VSS. Since the inverted reset signal RSTB is initially at a high level, the N-channel device N2 causes the node 306 to remain at a low level in a state where the N-channel device N1 is not conducting. The N-channel device N2 is used to ensure or ensure that the reset signal RST is still at a low level in the aforementioned state. When the input signal IN is in the estimated state, the return logic '0' reset circuit 303 maintains its isolated state. When the return logic '〇' input signal IN supplied to the regression logic '〇' reset circuit 303 returns to its preset state, the return logic '0' resets the circuit 303 to its reset state, generating A reset event in which the P channel device P1 and the return logic '〇' reset circuit 303 pull the reset signal RST to a high level. Note that if the circuit has an N-channel device N2, the return logic '0' reset circuit 303 is designed to oppose the N-channel device N2 to pull up the level of the reset signal RST. The inverter 405 thus pulls down the level of the inverted reset signal RSTB to turn on the P-channel device P2. The turned-on P-channel device P2 pulls the potential of the precharge input and output terminal PCHG to its preset state. Please note that when each of the return logic '0' input signals IN supplied to the regression logic reset circuit 303 returns to the preset state, the input signal IN is no longer in an estimated state, so the return logic '0' estimation circuit 301 The level of the preset input and output terminal PCHG is no longer pulled low. In this way, the P-channel device P2 pulls the level of the pre-charge input and output terminal PCHG back to its pre-charge state. When the level of the precharge input and output terminal PCHG is at a high level, the inverter 401 causes the output signal OUT to be at a low level again to turn on the P channel device P3, and maintain the precharge input and output terminal PCHG at a high level. The inverter 403 pulls the return logic '0' enable signal RT0E to a high level to turn on the N channel device N1 and disable the P channel device P1. Since the P-channel device P1 is not turned on, the return logic '0' reset circuit is isolated from the supply potential VDD, and the reset signal RST is no longer pulled up. In addition, the turned-on N-channel device N1 pulls the reset signal RST to a low level, and the inverter 405 pulls the inverted reset signal RSTB to a high level to make the P-channel device P2 non-conductive (and In the example of supplying the N-channel device N2, the N-channel device N2 is further turned on). Although the P-channel device P2 is not turned on, the semi-sustain circuit 402 maintains the precharge input and output terminal PCHG at a high level. As a result, the regression logic '0' domino circuit 400 is reset back to its preset state, ready for the next estimated event. Figure 5 illustrates the operation of the clockless regression logic '0' domino logic gate 300 in a timing diagram in which the regression logic '0' domino circuit 400 is used to implement the regression logic '0' domino circuit 305 in accordance with one embodiment. The first state signal EVAL displays an estimated state of the regression logic '0' estimation circuit 301, the establishment of which represents the generation of an estimated event. The first state signal EVAL is a high level when the estimated state is established, and is a low level when the estimated state is not established. The number of estimated states of the input signal IN is determined by the logic function design of the return logic '〇' domino circuit 305. For example, if the regression logic '〇' domino circuit 305 is designed to be a logic or function, then any one or more of the input signals IN are at a high level corresponding to an estimated state. If the regression logic '0' domino circuit 305 is designed to implement a logic and function, the input signal IN has only one estimated state; in this estimated state, each input signal IN is at a high level. The second state signal RESET displays a reset state of the reset logic '0' reset circuit 303; when the reset state is established, the second state signal RESET is a high level; when the reset state is not established, the second state The signal RESET is at a low level. The reset state is determined by the CNTR2460!00-TW/0608-A42737-TW/Final 201220691 design of the reset logic '0' reset circuit 303 and the input signals supplied to the return logic '0' reset circuit 303. The state of IN. Each time the input signal IN is any one of one or more of the estimated states, the reset state is not established and the return logic '0' reset circuit 303 is in its isolated state. The return logic '0' reset circuit 303 is in its reset state whenever each of the return logic '0' input signal IN supplied to the return logic '0' reset circuit 303 returns to logic '0'. The reset event occurs only when the return logic '〇' enable signal RT0E is the low level that turns P channel device P1 on, and the return logic '〇' resets circuit 303 to its reset state. A few applications rely on the design of the evaluation and reset circuits. Regardless of the dual configuration, or non-dual configuration design, when all input signals IN return to logic '0', the reset state is established and the estimated state is not true. In the dual configuration and non-dual configuration design, when the estimation state is established, the reset state is not established. In the non-dual configuration design, only a subset of the input signal IN is supplied to the regression logic '〇' reset circuit 303, and the reset state may not be true when the estimated state is not established, and may still be after the estimated state transitions to not established. Maintenance is not established. Figure 5 contains timing diagrams for the signals EVAL, RESET, PCHG, OUT, RT0E, RST, and RSTB. The transition delay of the signal shown is for illustrative purposes only and is not intended to limit the delay time for a particular design. At the initial time T0, the first state signal EVAL is at a low level, indicating that the input signal IN is not in an estimated state. The second state signal RESET is a meaningless signal at timing T0. Note that, according to the regression logic operation, the input signal IN (at least the signals of the regression logic '〇') is returned to logic '0' after an estimation interval and before the next estimation interval. However, individual input signals may have different time delays. When the input signal IN is all set to the preset state CNTR2460I00-TW/0608-A42737-TW/Final 24 201220691

- state, the first state signal EVAL is at a low level and the second state signal RESET is at a high level. If one or more of the input signals are converted to a high level but still do not meet the conditions of the estimated state (before the next estimation interval), the second state signal RESET may be toggled one or more times between the two states and simultaneously The status signal EVAL maintains a low level. Therefore, the second state signal RESET is not in a specific state as shown, and further, since the state regression enabling circuit 207 (implemented by the P channel device P1 in the regression logic example) does not function, the any state earlier than the estimated event The two-state change is not important. The signals PCHG, OUT, RT0E, RST, and RSTB are initially set to logic 'Γ, '0', 1', '0', and 'Γ, respectively, at time T0. At the subsequent time point T1, the input signal IN is entered into an estimated state, so that the first state signal EVAL is pulled high and the second state signal RESET is pulled low. In response to the high level first state signal EVAL, the return logic '0' estimation circuit 301 pulls down the precharge input and output PCHG potential by a continuation time point T2 after a short delay to cause an estimation event. Since the second state signal RESET is at a low level, the return logic '0' reset circuit 303 is in its isolated state. In response to the precharge input and output signal PCHG being pulled to the low level, the inverter 401 pulls up the level of the output signal OUT at the continuation time point T3 after the short delay. As the output signal OUT rises, the inverter 403 pulls down the level of the return logic '0' enable signal RT0E at the subsequent time T4 after the short delay to turn on the P channel device P1 and not turn on the N channel device. N1. Since the return logic '0' reset circuit 303 is non-conducting, the reset signal RST is not affected by any device and is maintained at a low level (or maintained at a low level by the N-channel device N2). The state of the clockless return logic '0' domino logic gate 300 remains unchanged and the first state signal EVAL is at a high level. At the time of CNTR2460I00-TW/0608-A42737-TW/Final 25 201220691 time point Τ5, one or more signals in the input signal IN change its state, causing the estimation state to be unsatisfiable, and accordingly, the first state signal EVAL transitions to low. Level. If the input signals supplied to the return logic '〇' reset circuit 303 are each returned to logic '0', the second state signal RESET is pulled up at time T5 as indicated by the broken line 501. In the case of a non-dual configuration design, there is a delay between the transition of the first state signal EVAL to the low level and the transition of the second state signal RESET to the high level. It must be noted that since the first state signal EVAL is at a low level, the estimation state is not established, and the return logic '0' estimation circuit 301 does not pull down the precharge input/output signal PCHG after the time point T5. The precharge input and output signal PCHG is maintained at a low level until it is subsequently pulled up to a high level by the P channel device P2. Note that the other half-sustainer circuit (not shown) can be used to maintain the precharge input and output signal PCHG at a low level in the above conditions. At the time point T5 or the subsequent time point T6, the input signal IN supplied to the return logic '0' reset circuit 303 is turned to zero to start the reset state of the return logic '0' reset circuit 303, so that The two-state signal RESET is at a high level. The return logic '0' reset potential 303 is combined with the P channel device P1 to raise the potential of the reset signal RST at a time point T7 after a short delay to start a reset event. The inverter 405 pulls the inverted reset signal RSTB low in response to the short delay T8. The inverted reset signal RSTB is turned to the low level to turn on the P channel device P2, and the precharge input/output signal PCGH is pulled back to the preset state at a time point T9 after a short delay. When the precharge input and output signal PCHG is at the high level, the inverter 401 sets the output signal OUT to the low level again at the time point T10 after the short delay. The output signal OUT, which is transitioned to a low level, turns on the P channel device P3, so that the half CNTR2460iOO-TW/O6O8-A42737-TW/Final 26 201220691 maintain circuit 402 maintains the precharge input and output signal PCHG at a high level until the next The estimated range will be pulled down. The inverter 403 pulls the return logic '0' enable signal RT0E to the high level at a time point T11 after a short delay. The high-level state of the return logic '〇' enable signal RT0E causes N-channel to be turned on and the P-channel device P1 to be non-conducting. Since the P channel device P1 is not turned on, the return logic '0' reset circuit 303 no longer pulls up the reset signal RST. The conduction of the N-channel device N1 causes the reset signal RST to be pulled back to the low level at a time point T12 after a short delay. The inverter 405 pulls up the inverted reset signal RSTB to the high level at a time point T13 after a short delay, and therefore, the P channel device P2 no longer pulls up the precharge input/output signal PCHG. At this time, the precharge input/output PCHG is maintained at a high level by the half sustain circuit 402. At a later time point T14 at time point T13, the signal returns to its preset state, and the return logic '〇' estimation circuit 301 and P channel device P1 are in their preset states, and the return logic '0' domino circuit 305 returns to its pre-reduction. The state is set. Further, assuming that each signal in the input signal IN is at a low level, the return logic '0' reset circuit 303 is in its reset state. In summary, an estimated state of the input signal IN causes an estimation event that causes the output signal OUT to be at a high level and enables a subsequent reset event. The reset state of the input signal IN causes the return logic '0' reset circuit 303 to initiate a reset event, and the clockless return logic '0' domino logic gate 300 returns to its initial state, ready for the next estimated interval. As shown, the second state signal RESET is at a high level until time T11. At time T11, the return logic '0' enable signal RT0E transitions to a high level to determine that the clockless return logic '0' domino logic gate returns to its initial state, and thereafter, the second state signal RESET is Meaningless. Please note that when the reset signal RST is pulled to the high level at the time point T7, even if the CNTR2460100-TW/0608-A42737-TW/Final 27 201220691 state is not established and the second state signal RESET is pulled low, the reset signal RST is still The high level is maintained because the N-channel device N1 is still non-conducting and cannot affect the reset signal RST. Therefore, although the reset state should be maintained until the return logic '0' enable signal RT0E transitions to the high level, the input signal can pull the level of the second state signal RESET after the time point T7 and before the time point T11. Without impact, therefore, proper circuit operation can be maintained. Once the return logic '0' enable signal RT0E is at a high level, the P channel device P1 is non-conducting, and any meaningless transition of the input signal IN has no effect after time point T11. A situation other than the above meaningless transition may additionally trigger an estimated state. Note that the state regression signal RTS may not have a meaningless transition. However, some input signals may be non-state regression signals and may have meaningless transitions. The input signal IN supplied to the regression logic '〇' estimation circuit 301 is selected to avoid potential estimation states from occurring. Figure 6 is a schematic block diagram illustrating a clockless regression logic '0' domino logic gate 600 for implementing a logic or gate, for the input signal of the return logic '0' Ι1·.· Or operation, where Μ is a positive integer greater than one. In such an embodiment, the input signals Ι1···ΙΜ are all regression logic signals. The clockless regression logic '〇' domino logic gate 600 includes a regression logic '0' domino circuit 305. The regression logic '0' domino circuit 305 is coupled to a regression logic '0' estimation circuit 601 (to implement the regression logic '0' estimation circuit 301), and coupled to a regression logic '0' reset circuit 603 (for A regression logic '〇' reset circuit 303) is implemented. The regression logic '0' estimation circuit 601 includes a plurality of channel devices ΝΜ, ΝΜ, each of which is coupled to the node 302 by a drain, and each of which is coupled to the reference potential VSS with a source. The channel devices ΝΑ...ΝΜ each have a gate corresponding to the received input signal 11...ΙΜ as shown. Similarly, the return CNTR2460I00-TW/0608-A42737-TW/Final 28 201220691 logical '〇 reset circuit 603 includes one P-channel device PA...PM, connected in series between the second reset node 310 and the reset node 306 . As shown, the first P-channel device PA and the P-channel device P1 are coupled to the drain node of the P-channel device PA, and the drain of the P-channel device PA is coupled to the source of the next P-channel device. In accordance with this concatenation rule, the last P-channel device PM is coupled to node 306 with its drain. The P channel devices PA...PM each receive one of the input signals Ι1··· as a gate as shown in the figure. Although only two of the plurality of Ν channel devices ΝΜ...ΝΜ, 两个, a plurality of Ρ channel devices ΡΑ···ΡΜ, two devices ΡΑ and ΡΜ, a plurality of input signals II··· For the two signals II and ΙΜ in the ΙΜ, it must be understood that any number of the devices and signals may be their implementation (eg, input signals to the gates of the Ν channel device Ρ and the Ρ channel device 12) …Wait). The clockless regression logic '0' domino logic gate 600 is an embodiment of a dual configuration design in which the return logic reset circuit 603 is a dual configuration design of the regression logic '0 estimation circuit 601. In the dual configuration design, the signals supplied to the return logic '〇' estimation circuit 601 and the return logic '0' reset circuit 603 are both input signals Ι1···ΙΜ. The operation of the clockless regression logic '0' domino logic gate 600 generally conforms to the timing diagram shown in FIG. In such a state, when the input signal Ι1··· is operated as logic '0' according to the return logic '0', the first state signal EVAL is at a low level and the second state signal RESET is at a high level. When any one of the input signals Ι1···ΙΜ is a high level, the estimation state is established, and the reset state is not established; therefore, the first state signal EVAL is in the high level state, and the second state signal RESET is in the low level. status. Because the circuits 601 and 603 are of a dual configuration design, as the input signal IN is switched, CNTR2460100-TW/0608-A42737-TW/Final 29 201220691 is changed, and the first state signal EVAL and the second state signal RESET are switched and maintained. Inverted for each other. As any of the input signals IN transitions to logic '1', the precharge input and output signal PCHG transitions to a low level, and the output signal OUT transitions to a high level after a short delay, and the return logic·, The enable signal RT0E transitions to a low level after another short delay to enable a reset event. When the input signals η...iM are each according to the regression logic, 〇, when the operation returns to the logic '〇', the regression logic, 0, the reset circuit 603 raises the reset event, causing the reset # RST to transition to Micro Motion. Bit, the inverted reset signal RSTB transitions to the low level, the precharged input loses the money PCHG to the high level, and the output signal OUT returns to the low level as previously described. In some designs, the number of p-channel devices cascaded within the 0' reset circuit 603 is limited to a specific number to ensure proper operation. For example, in a certain mode, it is allowed to be serially connected to the power supply potential VDD and reset, and the maximum number of P channel formations between the points is 4, and the number of input signals is limited to 3 as 3). In order to log a large number of input signals. Alternatively, multiple clockless regression logics can be used: or cascaded together, with a large number of logic pairs for any number of inputs; the number is logically ORed, as detailed below. Ghost diagram, illustrating two clockless state regression dominoes Logic gates 701, 703盥7ΓΚ, m, - a 05 composed of a joint logic gate design 700 for the implementation of a logic operation. Teng people state regression pattern, and the design is shown as ^ m applied to any regression logic, 0, or regression logic, 1, application. In one embodiment, the eight input signals II...16 in the Di n fly are logically transported to produce a state regression round-out or up to the whole church... UT. The input signal n...13 is the state return letter CNTR246010〇-TW/0608-A42737-TW/Final ^ Input 4 port 狁16 nai 30 201220691 - Medium to one) One or all up to all states Regression signal. The joint logic gate design 700 includes two three-input no-cycle state return domino logic gates and 703, and another dual input state return domino logic gate 705. State = Bones Card Logic Gate 701 receives the round-in signal η.·.Ι3 and supplies a state return output 彳§唬〇1 (RTS) as an input signal for the state return domino logic gate 7〇5. Similarly, the state return domino logic gate 7〇3 receives the input signals 14...16 and supplies a state regression output signal 02 (RTS) as another input signal to the state return month card logic gate 705. The state return domino logic gate 705 supplies a state return signal 〇UT (RTS) at its output. As a result, multiple non-clock state return domino logic gates can be combined or cascaded to cope with a large number of input signals to perform a specific logic operation. In addition, there are other designs that do the same. For example, the first stage structure 'receives two of the six input signals' each with three dual input logic gates and each produces an output signal to combine as an input signal to a three input logic gate. Alternatively, the techniques can be applied to implement logical operations of other numbers of input signals, and the six input signals described above are for illustrative purposes only. Logic gates 701, 703, and 705 within the joint logic gate design 700 can each be based on different logic operation requirements - for example, logical AND (OR), logical OR (OR), logical NOT (NAND), and logical non-4 ( N〇R), logically exclusive OR (XOR)... or any other set of logical operations - implemented with appropriate or available input signals. For example, regarding a logical XOR of signal X or X of signal A and X 〇R(A ' B), state regression turns into signals A and B and their inverted signals a, and b, ( The label "," is represented as an inverted signal) to be supplied. Logic gates 701, 703 in the joint logic gate design 700 CNTR2460I00-TW/0608-A4273 7-TW/Final 31 201220691 and 705 can perform different operations. Although the figure shows only three, any number of logics can be connected in series, in parallel, or otherwise based on techniques well known to those skilled in the art. The two logic gates 701, 703, and 705 can each be implemented as a -_ or gate according to the clockless return logic logic circuit. The implementation of the money sample; the card logic 701 701 is designed as a logic or gate, logically or differently for the input signal η...Ι3 to supply the output signal 01; the logic between 7 and 3 words is a logic gate. Perform a logical OR operation on the input signal Ι4··.Ι6 to supply #02; and the logic gate 705 巧 呌 & ^ ^ dead port is counted as a logic or gate, and the signal is logically ORed to Produce output money 〇υτ. In this way, big, ~ no clock return logic, oh, domino logic gates can be combined or cascaded to cope with a large number of logical operations of the input signal 'for example, to achieve __ logic or operation two picture 8 A block diagram illustrates a clockless sequence, in which a series operation is implemented in accordance with another embodiment of the present invention. Without the clock return logic, hey, the domino logic $_ includes the above logic '〇, the domino circuit 305. The regression logic (four), the domino circuit 3G5 light connection - regression logic, 0, estimation circuit 80] (to achieve the regression logic, 〇, estimation circuit 301) and - regression logic, 〇, reset circuit Xie (to achieve this Return logic '〇' reset circuit 3G3). Regression logic, 估算, the estimation circuit 8()1 includes three n-channel devices 则, then with the NC, each of which consumes the node 3〇2, and each source sinks the - relay node, point 802. Regression logic, 〇, the estimation circuit further includes two N-channel devices ND and then, each of which is connected to the node 802 with no poles, and each of the source is coupled to the reference potential vss. The N channel devices NA...NE receive five input signals n_i5 with gates, respectively. In this embodiment, the regression logic '〇' estimation circuit 8〇1 performs a logic operation to make CNTR2460I00-TW/0608-A42737-TW/Final 32 201220691 0UT=(I1|I2|I3)&(I4|I5 ), where the symbol "|" represents a logical OR operation, and the symbol "&" represents a logical AND operation. An estimated state occurs when either of the input signals II...13 is at a high level and at least one of the input signals 14 and 15 is at a high level. The return logic '0' reset circuit 803 includes two channel devices ΡΑ and ΡΒ connected in series between the drain of the channel device Ρ1 and the reset node 306, and is connected to the node of the channel device Ρ1. 310. Specifically, the channel device is coupled to the source of the channel device ΡΑ1 by a source, and is coupled to the source of the channel device by a drain, and the channel device is coupled to the reset node with a drain. 306. The input signal 14 is supplied to the gate of the channel device, and the input signal 15 is supplied to the gate of the channel device. In this embodiment, the reset state occurs only when input signals 14 and 15 are both low. Input signals 14 and 15 are regression logic '0' signals; input signals II...13 may be regression logic '〇' signals but need not necessarily be regression logic '〇' signals. Although the state regression signal is the expected setting, in some designs, combining non-state regression signals with state regression signals can be a quite useful design. The non-state regression signal may need to meet certain time conditions relative to the state regression signals. For example, in one embodiment, the non-state regression signal may be set or maintained in response to a state regression signal. The operation of the clockless return logic '0' domino logic gate 800 generally conforms to the timing diagram shown in FIG. In such an embodiment, the estimated state is established when at least one of the input signals II...13 is at a high level and at least one of the input signals 14 and 15 is at a high level, the estimated state triggering an estimated event at time Τ1 . Referring to the foregoing description, in response to the estimated event, the precharge input and output signal PCHG transitions to a low level, and then the output signal OUT transitions to a high CNTR2460100-TW/0608-A42737-TW/Final 33 201220691 level, and then The return logic '0' enables the signal RT0E to transition to a low level; the transitions are separated by a short delay. The first state signal EVAL maintains a high level within the interval in which the estimated state is established. The reset state is established only when the input signals 14 and 15 are both set to a low level. The second state signal RESET is maintained at a low level because any of the input signals 14 and 15 is at a high level. Therefore, the second state signal RESET is maintained low when the first state signal EVAL is at a high level. Level. When the first state signal EVAL transitions to the low level at the time point T5, if the input signals 14 and 15 are simultaneously at the low level, the second state signal RESET will transition to the high level. At the time point T5, if the input signals 14 and 15 both transition to the low level, the second state signal RESET can be turned to the high level, but the second state signal RESET is also likely to remain at the low level for a longer time. . For example, if the input signals II...13 are all turned to the low level and any of the input signals 14 and 15 are maintained at the high level, the second state signal RESET remains when the first state signal EVAL transitions to the low level. Do not turn to high level. The input signals 14 and 15 are all low level according to the return logic '0' operation (for example, refer to the time point T6 of FIG. 5), then the second state signal RESET transitions to the high level and the return logic '0' resets the circuit. 803 enters its reset state to cause a reset event. As described above, in response to the reset event, the reset signal RST transitions to a high level, the inverted reset signal RSTB transitions to a low level, and the precharge input and output signal PCHG transitions back to a high level. And the output signal OUT is turned back to the low level, and the above transition states are each delayed by a short delay. The clockless return logic '0' domino logic gate 800 is a non-dual configuration implementation in which the return logic '〇' reset circuit 803 is not a dual configuration design of the return logic '0' estimation circuit 801. In this embodiment, the input signal II... CNTR2460100-TW/0608-A42737-TW/Final 34 201220691 - 15 only one subset of an input signal 14 and 15 - is supplied to the regression logic '〇' reset circuit 803. However, since the estimation state is only established when at least one of the input signals 14 and 15 is at a high level, therefore, when the regression logic '0M ancient' arithmetic circuit 801 is in its estimated state, the return logic '0' reset circuit 803 is inevitably Its isolation ensures proper operation. In particular, at the beginning of the estimated event, the return logic '〇' reset circuit 803 is in its isolated state, and the return logic '0' domino circuit 305 transitions to its latched state to turn on the P-channel device P1. The reset signal RST is not subjected to any device-determined potential under the estimated conditions. When the input signals 14 and 15 are all converted to a low level according to the return logic '0' operation, the return logic '〇' estimation circuit 801 is out of its estimated state, and the return logic '0' circuit 803 enters its reset state, causing a heavy Set the event. The reset event causes the regression logic '0' domino circuit 305 to transition back to its preset state, causing the P channel device P1 to be non-conducting, and then lowering the level of the reset signal RST to prepare for the next estimated event. . The logic operation of the clockless regression logic '0' domino logic gate 800 can be used for a joint logic gate structure similar to the joint logic gate design 700. For example, logic gate 701 can be implemented by a three-input logic or gate that receives input signal IL···13 to supply an output signal 01. Logic gate 703 can be implemented by a dual input logic or gate to receive two input signals 14 and 15 to supply an output signal 02. Logic gate 705 can be implemented by a dual input logic and gate to logically AND signals signals 01 and 02. As a result, the joint structure will implement logical operations (I1|I2|I3)&(I4|I5). In another architecture, a third P-channel device (not shown) may be provided in series between nodes 310 and 306. The three P-channel devices connected in series are used to receive the input signals II, 12 and 13, respectively. The resulting operation is equivalent, even with respect to the state of the two input letters CNTR246OIOO-TW/O608-A42737-TW/FinaI 35 201220691 (14 and 15), the state of the three input signals (Π, 12 and 13) It may take a little longer for the return logic, oh, the domino circuit 305 to transition from the latched state back to the preset state. Figure 9 is a schematic block diagram illustrating a clockless regression logic, 骨, domino logic gate 900, in which a logic and gate are implemented, and a regression logic, 〇, input signal II ... ΙΜ is logically operated . In such logic and embodiments, the input signals η...ΐΜ are each a return logic '〇' signal. The clockless regression logic '0' domino logic gate 900 includes the regression logic, 骨, domino circuit 305, coupled to the regression logic '〇' estimation circuit 9〇1 (implementing the regression logic, 〇, estimation circuit 301) And a regression logic, 〇, reset circuit 〇3 (implementing the regression logic '0' estimation circuit 303). Regression logic, 估算, the estimation circuit 〇1 includes Ν Ν ΝΑ ΝΑ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , As shown, the drain of the channel device 面 is connected to node 302, and its source is coupled to the drain of the next ν channel device in the series, and follows this rule until the last stage Ν channel device ΝΜ, and Ν The source of the channel device 耦 is coupled to the reference potential vss. As shown, the ν channel device ΝΑ...匪* receives the input signal η...ΐΜ from the gate. Correspondingly, the regression logic reset circuit includes a plurality of ρ channel devices pa...m connected in parallel between the node 310 and the reset node 3〇6. In particular, the source of the ρ channel device PA...PM is coupled to the point 310, and the drain is coupled to the reset node 306. CNTR2460I00-TW/0608-A42737-TW/Final No clock return logic, 0, domino logic _ is another embodiment of the dual configuration. Without the clock return logic, hey, domino logic is generally consistent with the timing diagram disclosed in Figure 5. In such an embodiment, the estimated state is established when all the input signals η· are high level, and the current channel is 导...NM is fully turned on, and the pre-charge input and output terminals PCHG are simultaneously turned on. Pull to the reference potential VSS. When any of the input signals Ι1···ΙΜ is at a low level, the reset state is established. In this embodiment, the regression logic '0' estimation and reset circuits 901 and 903 are of a dual configuration design with each other. Depending on the application, the logic gate can be designed to receive a variety of input signals. However, as previously discussed with respect to the clockless regression logic '〇' domino logic gate 600, in order to ensure operational accuracy, the number of channel devices cascaded in the regression logic '〇' estimation circuit 901 is limited to a certain number. . As with the joint logic gate design 700 discussed previously, the clockless regression logic '〇' domino logic gate 900 can employ a cascade technique to achieve the logical AND of any number of input signals with multiple logics and gates. Each of the logic gates 701, 703, and 705 can be implemented as a logic and gate with reference to the clockless return logic '0' domino logic gate 900. In one embodiment, the logic gate 701 is designed as a logic and gate for logically ANDing the input signals II...13 to generate the signal 01; the logic gate 703 is designed as a logic and gate, and the input signals 14...16 The logic AND operation is performed to generate the signal 02; the logic gate 705 is designed as a logic and gate, and the signals 01 and 02 are logically ANDed to generate the output signal OUT. As such, a plurality of clockless regression logic '0' domino logic gates can be combined or stacked to achieve a particular logic operation - for example, a logical AND operation of a pair of large input signals. Figure 10 is a block diagram illustrating another clockless regression logic '0' domino logic gate 1000 for implementing a logic and gate, for a return logic '0' input signal Ι1··· The operation includes a simplified reset circuit 1003. The clockless regression logic '0' domino logic gate 1000 is roughly similar to the clockless regression logic '〇' domino logic gate 900, where the same element CNTR2460100-TW/0608-A42737-TW/Final 37 201220691 uses the same Numbering. Comparing the two circuits, the return logic, 0, the reset circuit 903 is implemented by a return logic, 〇, reset circuit 1003. Without the clock return logic, the operation of the domino logic gate 1000 generally conforms to the timing diagram disclosed in Figure 5. The return logic '0' reset circuit 1003 includes only a p-channel device PA, the source is coupled to the drain of the P-channel device p to the node 31, and the drain is coupled to the reset node 306. Any one of the input signals η..·ΙΜ, indicated as signal IX in the figure, is supplied to the gate of the channel device. Compared with the clockless logic, 〇, domino logic gates, no clocks return to logic '〇' domino logic gates 〇〇〇 〇〇〇 the same operation, is designed as a non-double configuration structure. Without clock return logic, 0, domino logic = 1000 operation is basically similar to clockless regression logic, 骨, domino logic gate 900, the difference is that its reset state is only established when the input signal 低 is low. When the input signal Ι1..·ΙΜ—including the signal Ιχ—has transitioned to a high level, the reset state does not hold and the estimated event occurs. When the signal transition state is logic '0', the estimated state is not established and the reset state is established, the second reset event is triggered, so that the no-clock return logic, 〇, the domino circuit 3〇5 returns to its pre- Set the status. Without clock return logic, hey, the domino logic gate 1〇〇〇 has the advantage of simplified regression logic, 〇, reset circuit, which is implemented with only one ρ channel device; however, if signal IX is slower than other input signals When the mode returns to the zero level, there will be a certain speed loss. Without clock return logic, hey, the advantage of Domino Logic Gate 900 is likely to increase the speed of response, because after the event is estimated, the reset event will be at the speed of the input signal. Occurs; however, more complex regression logic is needed, hesitating, resetting the circuit design. If the input signal is taken as the "fastest return logic '〇' signal', it can be selected as signal ΙΧ ' to solve the clockless regression logic CNTR2460I00-TW/0608-A42737^TW/Final 38 201220691 - The problem of the reaction speed of the '0' domino logic gate 1000. Referring to the timing diagram of Figure 5, a regression-free logic '0' domino logic gate 300 using regression logic '0' domino circuit 400 is reviewed, wherein multiple or all of the selected input signals are selected (depending on their specific design) When the return logic '〇' operation is (or transition to) logic '〇', the clockless regression logic '〇' domino logic gate 300 is its initial preset state. When the input signal asserts the estimated state, the reset state is not established and an estimated event occurs. In the state where the estimation state is established, the reset state is maintained as not established. When the return logic input signal supplied to the reset circuit returns to its predetermined logic '0' state, the estimated state transition is not true, and thereafter the reset state is established. The reset is ultimately based on the regression logic '〇' operation. Regarding the clockless regression logic '〇' domino logic gate 600, the reset event occurs when the input signals Ι1···ΙΜ are all transitioned to logic. Regarding the clockless regression logic '0' domino logic gate 800, the reset event occurs when a subset of input signals II...15, i.e., input signals 14 and 15 - transitions to logic '0'. Regarding the clockless regression logic '0' domino logic gate 900, the reset event occurs when either of the input signals II"/ΙΜ transitions to logic '〇'. Regarding the clockless regression logic '〇' domino logic gate 1000, the reset event occurs when the selected one of the input signals, signal IX, transitions to logic '0'. Figure 11 is a schematic block diagram illustrating a clockless regression logic 'Γ domino logic gate 1100, implemented in accordance with a regression logic 'Γ implementation of returning to the domino logic gate 200 without the clock state. The one or more input signals and the resulting output signal are designed as a return logic '1' signal having a predetermined logic state of logic 'Γ. The power supply potential VSRC1 is designed as the reference potential VSS, and the power supply potential VSRC2 is designed as the power supply potential VDD, which is opposite to the design of the clockless return CNQ2460100-TW/0608-A42737-TW/Final 39 201220691 k. The state regression estimation circuit 乂 '', the 知 月 月 circuit 205 and the state regression reset circuit 203 are respectively estimated by the -regressive logic τ circuit 1! - - regression logic, 1, domino circuit ^ 05 and a regression logic,丨, the reset circuit 11〇3 is implemented according to the one-to-four regression 'Γ operation. Please note that although the circuits 1101 and n〇3 can each be regarded as the return logic due to the operation of the output signal, 〇, the circuit According to its turn-in signal and regression logic, the overall role of the domino logic is regarded as the return logic, !, the circuit. The aforementioned preset input and output chat T is changed from the face to the pre-clear node. A pre-clear input/output terminal PCLR of 1102 takes no clock return logic, i, the output of the domino logic gate sets a regression logic at an output node 1108, outputs a signal 〇υτ, and generates a reset node 1106. Reset the signal abdomen. The state regression enable node 2〇4 is implemented by a regression logic M' enablement node, point 1104, and is connected to the gate of the N-channel device N1 to realize the state regression enabling circuit 2〇7 <>;^ The channel device connects the reference reset potential VSSJ___ to the second reset node (10), and the return logic, 1, the reset circuit 11〇3 is subtracted from the reset node ui. Figure 12 is a schematic block diagram illustrating an embodiment of a regression logic, a domino circuit 1200, a regression logic, and a domino circuit 11〇5. Regression logic T (four) circuit · For regression logic, 〇, the inverse design of domino circuit 3 (8), in which the reference potential vss replaces the supply potential VDD in the circuit 3〇〇, and the supply potential VDD replaces the reference potential vss in the circuit 30〇 to The P-channel device replaces the N-channel device in the circuit 300, and the N-channel device replaces the P-channel device in the circuit 300, and the operational state of each node is the inverted state of the corresponding node in the circuit 300 (logic, 〇, state) Replace CNTR2460I00-T W/0608-A42 73 7-TW/Final 4〇201220691 with logic 'Γ state, and replace logic τ state with logic, 〇, state). In addition, the 'P-channel and N-channel devices in each inverter and the power supply potential setting ten are the reverse design of the circuit 300; because the same is performed for the opposite temple, the same symbol is used. Said. The pre-clear node 1102 is configured to input the input of the inverter 1201 and is coupled to the N-channel devices N2 and N3. The output of the inverter] 201 is coupled to the output node 1108 to supply a logic return signal, and is further coupled to the gate of the N-channel device N3 and the turn-in end of the inverter 1203. The output of the inverter 1203 is coupled to the node 11〇4 to supply the return logic, 丨, the enable signal rT1]E for application to the gate of the p-channel reset P1. The P-channel device P1 is coupled to the supply potential VDD by the source and is coupled to the reset node 11〇6 to supply the reset signal RST. The reset signal RST is supplied to the input terminal of the inverter 1205, and the output terminal of the inverter 1205 supplies an inverted reset signal RSTB. The inverted output signal RSTB is supplied to the gate of the channel device N2, and the source of the N-channel device N2 is coupled to the reference potential VSS. The inverter 1201 and the N-channel device N3 form a half-dimensional conversion circuit 1202, and maintain the pre-clear input and output terminal PCLR potential to a low level until the return logic, 1. The estimation circuit 1101 pulls the potential of the pre-clear input wheel output terminal pcLR. Rise. The P-channel device P2 is shown as a dotted line (corresponding to the N-channel device N 2 in the regression logic and card circuit 300) with its gate receiving inversion resetting the second RSTB' and coupling the node 11G6 with the drain, and The source is CM. The pre-clear input and output terminal PCLR is initially pre-cleared to a low level, so the phaser 1201 sets the output signal OUT to a high level, so that the ν channel device m is turned on. The Ν channel device is thus guilty of maintaining the pre-clearing rounds of the input and exit paR to a low level. Since the initial state of the output signal OUT is a high level, the inverter 1203 sets the regression logic, and the enable signal RT1E is at a low level, so that the p-pass CNTR2460I00-TW/0608-A42737-TW/Final 41 201220691 channel device Pi conduction, conduction P channel device? 1 will be RST. The inverter (10) thus pulls the inverted reset signal rstBm = the starting state of the device N2 is non-conducting. Referring to Figures 12 and 12, in response to one or more inputs (four) - or the occurrence of any of the estimated states - the estimated event, the regression logic '1' estimation circuit 11 () 1 pulls the pre-clear wheel output Duanhong (four) level, resulting in regression, series,], domino circuit 1200 transition to its flash lock state. In particular, inverter 1201 pulls down the output signal 〇υτ to disable the N-channel device. Inverted H 1203 pulls up the return logic! , enable the level of the signal RT1E to make the N channel device! ^ Conducted, and the p-channel device ρι is not turned on. The turned-on N-channel device N1 is coupled to the node 11 〇 to the reference potential vss. The non-conducting p-channel device P1 will no longer limit the reset signal RST to a high level. Entering the estimated state of 彳§IN will cause the regression logic, and the reset circuit 1103 will be in its isolated state, so that nodes 11〇6 and 111〇 are isolated from each other. As a result, the reset node 11 〇 6 is temporarily isolated, and the reset signal RST is no longer limited to a specific state. However, since no other device attempts to change the state of the reset signal RST, the reset signal RST is maintained at a high level. When the input signal IN is in an estimated state, the return logic '1' reset circuit]1 〇3 maintains its isolation state.

When supplied to the regression logic, 1, the input signal IN of the reset circuit 1103 is each returned to its preset state, and the return logic, 1, the reset circuit n〇3 transitions to its reset state, triggering a reset event, Among them, the N-channel device N1 and the return logic '1' reset circuit 1丨〇3 jointly pull the reset signal RST to the low level. The inverter 205 will then pull the inverted reset signal RSTB to the high level to turn on the N-channel device N2. The turned-on N-channel device N2 pulls the potential of the pre-CNTR2460I00-TW/0608-A42737-TW/Final άΐ 201220691 clear input/output terminal PCLR to a preset value. Please note that the return logic should be given, and each input signal m = of the reset circuit (10) is reset to a preset state, and the input signals IN will no longer be in an estimated state, so the listening regression logic τ estimation circuit 1101 does not Then, the pre-clear input and output terminal Pclr is pulled to the south level. As a result, the N-channel device milk can be input to the output again, and the PCLR is pulled down to the pre-clear state. If the pre-clear output terminal is busy to the high level, the inverter 12Q1 will set the output signal 〇υτ to the high level again, so that the channel device milk is turned on, and the pre-clear input and output terminal Pclr is kept at the low level. The inverter 1103 will lower the return logic, 丨, enable the signal 丨 丨 ^ to turn on the P channel device? 1. The N-channel device is not turned on. Since the N-channel device N1 is not turned on, the logic is returned. 1. The reset circuit (10) is isolated from the reference potential VSS, and S does not lower the level of the reset signal RST. In addition, the conduction of the 'P channel device Pi will pull the reset signal RST to a high level, and the inverter 1105 will pull the inverted reset signal RSTB to the low level, so that the N channel is not turned on. Although the N-channel device N2 is not turned on, the half-hold circuit 1202 maintains the pre-clear input and output terminal pcLR potential at a low level. As a result, the regression logic, 1, the domino circuit 12 〇〇 resets back to its preset bear j to prepare for the next estimated event. Figure 13 depicts a clockless regression logic in a time series diagram, 丨, the operation of the domino gate 1100, where the regression logic, 1, the domino circuit 11〇5 is a regression logic 一种 an implementation of the Γ 牌 circuit 1200 the way. The third 苎3, timing diagram is basically similar to the timing diagram of Figure 5, except for a few signals, and the level adjustment of the circuit signal (inverting it). In particular, compared with Figure 5, Figure 13 replaces the precharge input and output signal PCHG with the pre-clear wheel input output signal pcLR, to return logic, 1, the output is f CNTR2460100-TW/0608-A42737-TW/ Final 43 201220691 (RT1) replaces the regression logic '〇, output signal OUT (RTO)' and replaces the return logic '〇' enable signal RT0E with the return logic '1'. The signals PCLR, OUT(RT1), RT1E, RST, and RSTB in Figure 13 are the inverse of the signals PCHR, OUT(RTO), RT0E, RST, and RSTB of Figure 5, respectively. In addition, the transition time basically has the same short delay. Compared with Fig. 5, Fig. 13 also includes the waveforms of the first state signal EVAL and the second state signal RESET, and the reaction is similar. In this embodiment, the first state signal EVAL is used to indicate the estimation state of the regression logic '1' estimation circuit 1101, which is a high level when the estimation state is established, and a low level when the estimation state is not established. The second state signal RESET is used to indicate the reset state of the return logic '1' reset circuit Π03, which is high level when the reset state is established and low level when the reset state is not established. The reset state causes a reset event to occur only when the regression logic '1' enable signal RT1E is at a high level after an estimated event. Figure 13 presents the signals EVAL, RESET, PCRL, OUT(RT1), RT1E, RST, and RSTB in a timing diagram. The transition delays that exist between the individual signals are for illustrative purposes only and do not accurately show the actual conditions. Referring to the initial time point T0 'the first state signal EVA; the initial state of L is the low level, indicating that the input signal IN is not in the estimated state. Further, based on the discussion in Fig. 5, the second state signal RESET is meaningless at the time point T0. At time point TO, signals PCLR, 〇UT(RT1), RT1E, RST, and RSTB are initially set to logic, 〇, ,, ι,, 〇, ,, ι, and 0, respectively. At the connection time point T1 'the input signal in enters the estimation state together, causing the first state signal EVAL to transition to the high level, and the second state signal CNTR2460I00-TW/0608-A42737-TW/FinaI 44 201220691 RESET transition state is Low level. In response to the high level state of the first state signal EVAL, the return logic 'Γ estimation circuit 1101 pulls up the preamplifier input and output terminal PCLR potential at a time point T2 after a short delay, causing an estimation. Since the second state signal RESET is at a low level, the return logic '1' reset circuit 1103 is in its isolated state. In response to the pre-clearing of the signal transition of the input and output terminals PCLR to the high level, the inverter 1201 pulls the level of the output signal OUT low at the continuation time point T3 after a short delay. In response to the output signal OUT of the low level, the inverter 1203 raises the level of the return logic '1' enable signal RT1E at a subsequent time T4 after a short delay to turn on the N channel device N1 and make the P channel Device P1 is not conducting. Since the return logic 'Γ reset circuit 1103 does not function, the reset signal RST is not affected by any device and is maintained at a high level (or, in the embodiment with the designed P channel device P2, maintained by the P channel device P2 at a high level) Level). The state of the no-clock return logic '1' domino circuit 1200 is unchanged when the first state signal EVAL is at the high level. At the subsequent time point T5, one or more of the input signals IN change state, causing the estimated state to be unsuccessful, and the first state signal EVAL is correspondingly transitioned to a low level. If the input signals IN supplied to the return logic 'Γ reset circuit 1103 each return to logic '1', the second state signal RESET transitions to a high level at time T5 as indicated by the broken line 501. However, with regard to the non-dual configuration design, there is a delay between the transition of the first state signal EVAL to the low level and the transition of the second state signal RESET to the high level. Please note that since the first state signal EVAL is at a low level, the estimation state is not established, so the return logic 'Γ estimation circuit 1101 does not pull up the potential of the pre-clear input/output terminal PCLR after the time point T5. The potential of the pre-clear input terminal PCLR will remain at a high level until the N-channel device N2 CNTR2460100-TW/0608-A42737-TW/Final 45 201220691 acts 'lows its level. At time, point T5 or consecutive time point T6, supplied to the regression logic, the input signal of the reset circuit 1103 is turned to a high level to start the reset logic Τ reset circuit 1103 reset state, so that the second The status signal RESE is turned to a high level. Back to the first, the reset circuit 1103 is combined with the channel device Ν1 at the -time delay Τ7, the reset signal is pulled low at the level of D to start-reset event. Inverter • In response to the above operation, at the time-to-time point T8 after the short delay, the level of the inverting reset signal ruler (10) is raised. The inverted reset signal rstb, which is transitioned to a high level, turns on the N-channel device N 2, and the timing of the pre-clear input and output terminal PCLR is low at the time point τ 9 after the short delay. When the level of the output terminal of the pre-turn wheel is lowered, the inverter 1201 sets the output signal out to a high-precision output signal qut at a time point after the short-delay delay, so that the channel device Ν3 Turning on, causing the semi-sustaining circuit UG2 to maintain the potential of the pre-clear input and output terminal PCLR at a low level until a later estimation interval pulls its level. The reverse phase benefit 1203 will return to the logical T-energy message at the time point τη after the short delay! The level of the tiger RT1E is lowered. The low-level state of the return logic 'factory enable signal RT1E makes the P channel device? 1 is turned on, and the N-channel device N1 + is turned on. Since the N-channel device N1 is not turned on, the return logic, 1, the reset circuit 1103 no longer pulls down the level of the reset signal rSt. Conducted p

The channel device P1 pulls the reset signal RST back to the high level at a time point T12 after a brief delay. The inverter 1205 pulls down the level of the inverted reset signal RSTB at a time point T13 after a short delay, so that the channel device Ν2 no longer pulls down the level of the pre-clear input and output terminal PCLR. At this time, the semi-sustaining circuit 12〇2 is responsible for maintaining the level of the pre-clear input/output terminal PCLR at the low level. Following CNTR246OF00-TW/O608-A42737-TW/Final 46 201220691 - at time point T14 after time point T13, the signal is returned to the initial preset state. Therefore, the regression logic '1' estimation circuit 1101 and the N channel device N1 are in their preset states, and the regression logic '1' domino circuit 1105 returns to its preset state. In addition, it is assumed that the input signals IN are each high level, and the regression logic ' 1 ' Reset circuit 1103 is in its reset state. In summary, the estimated state of the input signal IN triggers an estimation event that causes the output signal OUT to transition to a low level and enables a subsequent reset event. The reset state of the input signal IN causes the return logic 'Γreset circuit 1103 to initiate a reset event and causes the clockless regression logic's domino logic gate 1100 to return to its initial state to meet the next estimation interval. As discussed in Figure 5, the second state signal RESET is at a high level until time T11 - the return logic 'Γ enable signal RTE1 transitions to a low level one to ensure that there is no clock return logic T logic gate. Return to it The initial state, after which the second state signal RESET is meaningless as shown. Please note that when the reset signal RST is pulled to the low level at the time point T7, if the reset state is not established, the second state signal RESET is pulled low to the low level, and the reset signal RST is still maintained at the low level, because P The channel device P1 is still non-conducting and has no effect on the reset signal RST. Therefore, although the reset state should be maintained until the return logic '1' enable signal RT1E transitions to the low level, if the input signal is after the time point T7 and before the time point T11, the second state signal RESET is pulled down. Still does not affect the correct circuit operation. Once the return logic 'Γ enable signal RT1E is low, the P channel device P1 is turned on, and any meaningless transition of the input signal IN does not affect the overall circuit state after the time point T11. Figure 14 is a schematic block diagram illustrating a clockless regression logic 'Γ CNTR2460100-TW/0608-A42737-TW/Final 47 201220691 Month Logic Gate 14〇〇, used to implement a logical OR operation, for μ Input signal II ". 逻辑 logical OR operation. No clock return logic, 1, domino logic gate 1400 includes regression logic domino circuit〗 】 〇 5. Circuit] 〇 5 coupled with a regression logic Ί 'estimation circuit 14 〇 1 (used to implement the aforementioned regression logic, ], the estimation circuit 1101) and a regression logic, ;!, the reset circuit 14〇3 (used to implement the aforementioned regression logic 1 reset circuit 1103). The regression logic '1' estimation circuit Οι Μ Μ P · · · · · · 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自Receive one of the input signals η..·ΙΜ. In a similar manner, the return logic, 1, the reset circuit 14〇3 includes a plurality of channel devices ΝΑ···ΝΜ, connected in series between the node π10 and the reset node]1〇6. As shown in the figure, the first stage of the channel device ΝΑ is coupled to the node on the drain of the channel device Ν1 by the source, and is coupled to the source of the next stage channel device by the drain; Up to the last stage of the channel device νμ. The last stage Ν channel device ΝΜ's 耦 pole coupling node 11〇6c> N channel devices NA...NM each provide a gate to receive one of the wheeled signals II..IM as shown. Although only two of the N-channel devices (NA'NM), two of the P-channel devices (pA, PM), and only the input signals n and IM are shown, in fact, according to the disclosed The rule that the omitted portion may include any number of the devices with a 2 correlation signal (e.g., an input signal 12 that is supplied to the N-channel and p-channel devices 1^3 and 1^ gates). There is no clock return logic, 1. The domino logic gate 14 is a dual configuration design, wherein the regression logic '丨' reset circuit 14〇3 is the regression logic, 1. The dual configuration design of the estimation circuit 14G1.射, in the dual configuration design towel, supply CNTR2460I00-TW/0608-A42737-TW/Final 48 201220691 - Regression logic '1' estimation circuit 1401 and regression logic 'Γ reset circuit 1403 are the same input signal II ” · ΙΜ. The operation of the clockless regression logic '1' domino logic gate 1400 generally conforms to the timing shown in Figure 13. In this embodiment, when the input signal Π···ΙΜ is in accordance with the regression logic When the logic is '1', the first state signal EVAL is at a low level, and the second state signal RESET is at a high level. When any of the input signals II "·ΙΜ transitions to a low level, the estimation state is established. And the reset state is not established, so the first state signal EVAL is at a high level and the second state signal RESET is at a low level. Since the circuits 1401 and 1403 are of a dual configuration design, the first state is switched with the input signal IN, the first The state signal EVAL and the state of the second state signal RESET are switched, and are maintained as the inversion of the other party. The estimated event caused by the low level transition of any one of the input signals IN is pre-cleared to the input and output terminals PCLR. High level And the output signal OUT transitions to a low level after a short delay, and the return logic 'Γ enable signal RT1E shifts to a high level after another short delay to enable a reset event. When the input signal Ι1·.· ΙΜ All numbers are converted back to logic '1' according to the return logic '1' operation. The return logic 'Γ reset circuit 1403 triggers a reset event, causing the reset signal RST to transition to a low level, and the inverted reset signal RSTB to The state is high level, the pre-clear input and output terminal PCLR level is pulled back to the low level, and the output signal OUT is pulled back to the high level as described above. In some designs, the serial connection is reset in the logic Γ The number of N-channel devices within circuit 1403 may need to be limited to a certain amount to ensure proper operation of the circuit. For example, in one embodiment, the number of N-channel devices connected in series between reference potential VSS and reset node 1106 is limited. 4, therefore, the number of input signals will be limited to 3 (ie, Μ is 3). Refer to Figure 7, Logic CNTR2460100-TW/0608-A42 73 7-TW/Final 49 201220691 Gates 701, 703 and 705 respectively Can be implemented by a regression logic,], logic or idle Each logic gate uses no clock return logic, 丨, domino logic between the 1400 technology. In this embodiment, the logic gate 7〇1 is designed as a logic or gate, logic for the regression logic '1, input letter (four) heart Or operation to supply the regression logic 'Γ signal οι. The logic gate 7〇3 is designed as a regression logic, work, logic or gate, and the logic of the return logic, 1, the input signal 14...16, is supplied to the return logic, and the signal is 〇2. Logic gate 7G5 is designed as: - return to logic logic or idle, take a logical OR operation on signals 01 and 02 to supply the output signal 〇UTe of the return logic '1' signal, such as multiple clockless regression logic, 1 The domino logic gates can be combined or cascaded to perform a specific logical operation, such as a sequence or operation, on a large number of regression logic '1' inputs. Figure 15 is a schematic block diagram illustrating a clockless regression logic,], a domino logic gate test in which diverse logic operations are implemented in accordance with another embodiment. Without the clock return logic, hey, the domino logic (four) test includes the return logic, the domino circuit 1105. The circuit (10) is connected to the return logic Μ, the estimation circuit 15G1 (for implementing the regression logic q, the estimation circuit] 1G1) and a regression logic 'Γ reset circuit 15〇3 (for implementing the regression logic, ], reset circuit H03) . Without the clock return logic, hey, the design of the domino logic gate 15〇〇 is basically the same as the clockless regression logic, 〇, the domino logic gate 8〇〇, the reverse design of the return logic, Γ operation. Illustrated, instead of the logic gate 8000, the logic gate 1500 replaces the reference potential with the power supply potential VDD, replacing the power supply potential VDD with the reference potential VSS, replacing the p-channel device with the N-channel device, and replacing the channel device with the P-channel device. Let the input reed use the regression logic '', the operation mode instead of the return logic, 操作, the operator CNTR2460I00-TW/0608-A42737-TW/Final 50 '201220691, the signal state is inverted, and the input is made Signals II...13 are regression logic or non-regressive logic, 1, signals. The aforementioned nodes 302, 304, 306, 308, and 310 are replaced with similar nodes 1102, 1] 04, 1106, 11 〇 8, and π ι ο, respectively, to perform similar operations in a manner similar to the nth through 14th. The operation of the clockless regression logic T-dollar logic gate 1500 generally conforms to the timing diagram disclosed in FIG. No clock return logic, 1, domino logic gate 1500 戸, line logic transport 〇 UT = ~ ((~II Bu 12 Bu 13) & (~14丨~15)), where, pay sign ~" represents Is a logical inversion. Similar to the clockless regression logic, 〇, domino logic gate 8〇〇, no clock return logic '1' domino logic gate 1500 is another implementation of non-dual configuration j 'where, regression logic, 1, reset circuit 15〇3 is not a dual configuration design of the regression logic T estimation circuit 1501. Only one subset of the input signals n~I5 - input signals 14 and 15 - are supplied to the return logic, 1, reset circuit 1503. Since one of the input signals μ and b must be at a low level when the estimated state is established, the return logic, 丨, reset circuit 15〇3 is the isolated state. As long as the regression logic, i, the estimation circuit is deleted as the estimated state /, the regression logic '1' reset circuit 1503 must be in its isolation state to ensure that the same as the clockless regression logic, 0' domino logic gate 8〇〇 The way is normal operation. In addition, without clock return logic, 1, the domino logic gate 15 can be implemented as a technique similar to the joint logic gate design 700 - a cascade logic gate. In the _, the mode, the third N channel device (not shown in the figure) adds = mo and (d) (4) in the tandem device 'to make three cascades of n-channels to receive the input signal η, and 13. The above correction implements the ^ logic operation. However, regarding the regression logic, 丨, the domino circuit η〇5 lock state transition state returns to the preset state, _ ^ 4 J binary input is missing CNTR2460IOO^TW /0608-A42737-TW/Final 5 ] 201220691 (II··· 13) The situation is time consuming compared to the condition of the two input signals (14 and 15). Figure 16 is a block diagram, illustrating a clockless regression logic, 1, domino logic gate ποο 'for a logic and gate, for M regression logic, 丨, input signal η...IM it row logic and operation . No clock return logic,], bone: Logic gate 1600 includes a regression logic,], domino circuit 11〇5. Circuit (10) face-to-regression logic, 1, estimation circuit 16_ to achieve the aforementioned regression logic, Γ estimation circuit (10)) and a regression logic, i, reset circuit coffee (use = before ^ return logic, !, reset Circuit 11G3). No-Cycle Regression Logic 1 The design of the domino 闸 闸 1600 is basically similar to the no-reverse regression 〇 〇, domino logic gate _, the difference is in the logic of the time logic is based on regression logic! , the deformation made by the operation. Explain that, compared with the domino logic idle, the domino logic gate 16〇〇 replaces the bit VSS with the power supply potential vdd, and replaces the power supply potential with the reference potential vss, replaces the channel device with the channel device, and replaces the channel device with the p channel device. n channel device, two input II.15 return to logic 1, design and return logic to output signal 〇UT for regression, design and (4) logic, 〇, sigh. Ten' and let the jg number state be an inverted design. Node tear, smoke, pass, 308, and 310 are replaced by similar nodes _, _, _, _, and (1) ,, respectively, to achieve the equivalent operation discussed in Figure η. In addition to Si Regression Logic, the Skeletal Logic Gate 1600 is designed for dual configuration. No clock return logic '1, domino logic gate 16 〇〇 has stayed in the same way as the timing diagram shown in Figure 3. In this embodiment, the estimation of the first parameter and the setting of the first parameter are established.

The quasi-she will be pre-cleared by the full number of PMs. The output terminal PCLR CN 1 and the electric potential VDD. The reset status is established when you enter ^卢n...IM CNTR2460,0〇.TW/0608.A42737-TW/Final 52 ^ ^ 201220691/South. In such an embodiment, the regression logic is estimated and the reset circuit and 16〇3 are designed in a dual configuration. The circuit is designed to accept an input number of the number f according to various needs. McCaw has no time to return to logic! The Domino Logic Gate has just been discussed in the past: Similarly, the serial connection in the regression logic, 丨, the number of estimated circuit _ p channels can be limited to a certain number to ensure that the circuit is normal. Refer to Figure 7 'Logic Gate 7 (H, 7〇3 and 7〇5 each can be used: clock back ^ logic, Γ 逻辑 logic gate deletion technology - regression logic, i, logic and gate implementation. So - come, A plurality of clockless regression logics can be combined or cascaded to perform a specific logical operation on a large number of input signals, such as a logical AND operation. Figure 17 is a schematic block diagram, illustrating a No clock return logic, 1, domino logic gate 1700, for - logic and gate, logical and different for the M input signal heart's use of simplified reset circuit 1703. No clock return logic '1' The domino logic gate 17〇〇 is basically similar to the clockless regression logic '1, the domino logic _ touch, where the same components use the same number, and the regression logic '1, the reset circuit 1603 is changed by the regression logic, 丨, heavy The circuit Π03 is replaced. Without the clock return logic, i, the domino logic gate 17〇〇 _ generally conforms to the timing diagram shown in Figure 13. The regression logic, 丨, reset circuit 17〇3 has only one N-channel device NA, The source is coupled to the N-channel device Νι to the node 1110, and The drain is coupled to the reset node 1106. Any one of the input signals IM - usually labeled ι - will be supplied to the pole between the 1^ channel devices. No clock return logic, 1, domino logic gate n〇〇 operation 盥i Return to logic (four), domino logic is equivalent, different bone = CNTR2460100-TW/0608-A42737-TW/Fina) 53 201220691 $ gate 17GG is a non-dual configuration design implementation. No clock return logic τ month card, the gate] 7〇〇 operation is basically similar to the clockless regression logic, 1, bone, logic gate 1600, the difference is that the reset state is only the input signal ιχ is the same level Established. When the input signal includes the input signal - each transitions to a low level, the reset state does not hold and the estimated event occurs. When the input signal IX transitions to logic, 〇, the estimated state is not established, and the reset state is established, causing a reset event to cause no clock return logic, and the domino circuit 1105 returns to its preset state. No clock (four) logic, 1, domino logic gate 1700 has the advantage of its return logic, i, the reset circuit is more simplified, only one _ channel device is included in it, however, if the input signal Ιχ turn back to logic, ^ The speed is slower than other input signals, and there is a problem with the speed of response. No clock ^ 卞 卞 卞 逻辑 逻辑 逻辑 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 The price is regression logic, i, the design of the reset circuit will be more complicated. (4) The speed problem of the logic gate 00 can be avoided by making the input signal IN t, the input signal that can be most quickly converted to logic T, the input signal Ιχ. Recall that there is no clock return logic, r domino logic gate m〇, so that it adopts the regression logic of the operation of the timing diagram of Fig. 13, 1, domino circuit 1200, benefit logic, skeletal logic gate (10) in the input signal according to logic 1 is inserted (or transitioned to) logic, 1, is in (or transitioned to) the initial preset state. When the input signal makes the estimated makeup point, & υ initial pre-pipe weight 1 to feel the reset state does not hold and ::! burst. When the estimated state is established, the reset state remains unsynchronized & money, pure should be given back to its default logic, and the state turns to sorrow ' CNTR2460l00-TW/0608-A42737-TW/Final ^ heart reset based on Back to 201220691, the logic τ operates the bamboo shoots. For example, resetting things; occurs in each 8^ regression logic Τ 牌 逻辑 逻辑 Γ Γ Γ Γ 。. In the absence of the clock to return to the logic mu1·, all of the transitions are logical. The event occurs in the round-robin read logic ^ _ as an example, and the 15-transition is logical and subset. - Round the signal 14 with an example, reset the second return logic, and the domino logic turns back to logic, 1, hour. Take ^, ^5, ^... to take any of the examples, the reset event occurs in Yu's, and the logic T-dollar logic 1700 is the input signal 1X1 state for the selected signal - it is called There are other embodiments or variants of the invention in detail. For example, upper =:, still possible = other suitable implementations such as circuits. :== Any number of circuits in the circuit is π, i V ; 丨, , 之 logic of the circuit; including the technique of body signal inversion. The disclosed techniques are well known for use with respect to any bit or character, and are well-known, digital, or binary circuits in the art. It is well known that H:7,5 may be based on the concepts and embodiments disclosed above to 'design or adapt the rest of the structure, in front of the material _ God's:: with the scope defined by the following request, DETAILED DESCRIPTION OF THE INVENTION [Brief Description of the Drawings] The following description will be helpful in understanding the advantages, features, and modifications of the present invention. The accompanying drawings include: " CNTR2460100-TW/0608-A42737-TW/Final 201220691 1 A simplified block diagram includes a cardioid or an integrated circuit returning domino circuit according to an embodiment of the present invention; a clockless state implemented by the equation; FIG. 2 is a block diagram, and the implementation is implemented - no time The pulse state returns to the domino logic: the embodiment has no clock state return to the domino circuit ^ can be broken to achieve the first cascading logic gate; one or more no clock state back to Fig. 3 is a schematic block diagram, Graph regression domino logic gate - kind of regression logic, 〇 ^ 2 graph no clock state clock return logic, 〇, domino logic; @ 式本的无无第4图 is a regression logic, 〇, 立图回Logical domino circuit The figure of the implementation diagram ‘illustrated the third card logic two gates: the time: the diagram ’ diagram 3 shows the clockless regression logic. 'Bone I:::; which uses the regression logic of Figure 4. The domino circuit diagram is a schematic block diagram 'illustrating a clockless regression logic domino logic gate' for implementing a logic or gate, and (4) solid input (four) n...iM for logical OR operation; Fig. 7 is a simplified block diagram , illustrating a cascade of logic gate designs, wherein there are two clockless state return logic gates coupled together to implement a logic operation; 'Fig. 8 is a schematic block diagram illustrating another implementation in accordance with the present invention The mode-free state of the clockless state is returned to the domino logic gate to implement a variety of logic operations; Figure 9 is a schematic block diagram illustrating a clockless regression logic, 〇, bone CNTR246〇I〇〇-TW/ 〇608-A42737-TW/Final 56 201220691 card logic gate, used to implement an input signal η.···ΙΜ...; and operation 'for M regression logic, 〇, enter logic .. Figure 10 is -咅方秘, 辑, 0, domino logic gate, use; diagram another - no clock return logic, 〇, input signal η··.ΤλΛ only one logic and gate, for M regression reset circuit f A is a logical AND operation, which includes a simplified * Π diagram for a schematic The block diagram, the domino logic gate, is based on _ ', , , (4) ~ logic 1, according to the non-clock state of the 2nd diagram, returning to a kind of regression logic of the domino logic gate's implementation method. Figure back to the figure (four) logicΤ Domino circuit - schematic diagram, diagram 11 of the back-bone circuit - implementation; change, 1, private 13, picture - timing diagram, to illustrate the operation of the 11th picture without clock synchronization logic * month logic, Among them, the regression logic of Fig. 12 is used, 1, the implementation method of the domino circuit; the A / i4 picture is - unintentional block diagram, the ® solution - no clock return logic τ month ^ series gate 'where a logic or gate is realized, For μ regression logic, the plant input signal II...IM is logically ORed; a 15th graph is a clockless regression logic, i, a domino block test of the domino logic gate, according to another species The embodiment is implemented to perform a variety of logical operations; Figure 16 is a clockless regression logic, 丨, a schematic block diagram of the domino logic gate 'to achieve - logic and gate, for a regression Logic, i, input signal Ι1··· 逻辑 logical AND operation; and the second picture is another No clock return logic, 丨, a schematic block diagram of the domino logic gate, used to implement a logic and gate, for a regression logic, Γ CNTR246010〇-TW/0608-A42737-TW/Fina] 57 201220691 Signal II "·ΙΜ performs logical AND operations, including a simplified reset circuit. '[Main component symbol description] 101~ Integral circuit; 103~ state regression logic; 104~ non-state regression logic; 105~ no clock state return domino circuit; 107~ logic circuit; 200~ no clock state return domino logic Gate; 201~state regression estimation circuit; 202~preset node; 203~state regression reset circuit; 204~state regression enable node; 205~state return domino circuit; 206~reset node; 207~state regression enable Circuit; 208~output node; 210~second reset node; 300~ no clock return logic '0' domino logic gate; 301~regression logic '0' estimation circuit; 302~ precharge node; 303~regressive logic weight Set circuit; 304~regression logic '0' enable node; 305~regression logic '0' domino circuit; 306~reset node; 308~output node; 310~second reset node; 400~regression logic '0' Domino circuit; 401~inverter; 402~half-maintainer circuit; 403, 405~inverter; 501~reaction of second state signal RESET indicating double configuration design; 600~no-return logic '0' bone Logic gate; 601~regression logic '0' estimation circuit; CNTR2460100-TW/0608-A42737-TW/Final 58 201220691 603~regression logic '0' reset circuit; 700~ joint logic gate design; 701, 703, 705~ No clock state return to domino logic gate; 800~ no clock return logic '〇' bone·brand logic gate; 801~regression logic '0' estimation circuit; 802~relay node; 803~regression logic '0' reset Circuit; 900~ no clock return logic '0' domino logic gate; 901~regression logic '0' estimation circuit; 903~regression logic '0' reset circuit; 1000~ no clock return logic '0' domino logic gate ; 1003 ~ regression logic '0' reset circuit; 1100 ~ no clock return logic T domino logic gate; 1101 ~ regression logic 'Γ estimation circuit; 1102 ~ pre-clear node; 1103 ~ regression logic 'Γ reset circuit; 1104 ~ Regression logic 'Γ enable node; 1105 ~ regression logic 'Γ骨牌 circuit; 1106 ~ reset node; 1108 ~ output node; 1110 ~ second reset node; 1200 ~ regression logic T domino circuit; 1201 ~ inverter 1202~half maintenance Circuit; 1203, 1205 ~ inverter; 1400 ~ no clock return logic '1' domino logic gate; 1401 ~ regression logic '1' estimation circuit; 1403 ~ regression logic 'Γ reset circuit; 1500 ~ no clock return Logic 'Γ骨牌闸闸; 1501~regression logic'Γ estimation circuit; 1502~relay node; 1503~regression logic '1' reset circuit; CNTR2460100-TW/0608-A42737-TW/Final 59 201220691 1600~ Pulse regression logic 'Γ骨牌逻辑闸; 1601~regression logic '1' estimation circuit; 1603~regression logic '1' reset circuit; 1700~ no clock return logic '1' domino logic gate; 1703~regression logic '1 'Reset circuit; CLK~clock signal; EVAL~first status signal; II ".16~ input signal; I1(RT0)...IM(RT0), IX(RTO)~regressive logic '0' input Signal; I1(RT1)".IM(RT1), IX(RTl)~regression logic,Γ input signal; IN~ input signal; IN(NON-RTS)~non-state regression input signal; IN(RTS)~state Return to the input signal;

Nl, N2, NA.-.NM~N channel devices;

Ol (RST), 02 (RST) ~ output signal; OUT ~ output; OUT (RTO) ~ regression logic '0' output signal; OUT (RTl) ~ regression logic 'Γ output signal; OUT (RTS) ~ state regression Output signal; PI, P2, P3, PA...PM~P channel device; PCHG~ precharge input/output/signal; PCLR~pre-clear input/output/signal; PSET~preset input/output; RESET~ Two-state signal; RST~reset signal; RSTB~inverting reset signal; CNTR2460I00-TW/0608-A42737-TW/Final 60 201220691 RT0E~regression logic '0' enable signal; RT1E~regression logic '1' Energy signal; RTSE~state return enable signal; T0...T14~time point; VDD~power supply potential, VSRC1, VSRC2~power supply potential; VSS~reference potential. CNTR2460100-TW/0608-A42737-TW/Final 61

Claims (1)

201220691 VII. Patent application scope: 1: - Return to the dominoes without the clock state _, including: 稷 H are each designed to be in H: change: its: including a plurality of round-in nodes, - preset nodes, :&quot a second point and a first and a second reset node, wherein the upper nodes each include a state transition node, which is set to be the first secret, and returns to the second state according to the state; The private card lightning 4# has a preset state and a flash lock state. When the month card circuit is in the preset state, the domino circuit sets the pre-threshold state, and sets the output node and the f reset Lang points to the second state, when the preset node is turned to the first state (four), the domino circuit switches to the locked state, causing the round node to transfer to the first state and the state is enabled The node to the above state 'when the first-reset node is switched to the first circuit to reset back to the preset state; the monthly card-estimating circuit is at least - the estimated shape = one at the input node 'Transfer the preset node to the second state above' and in the section Not accumulating the state of the preset node when the state is not estimated; discriminating the consistency circuit, shifting the second reset node to the first state when the enabling node is in the second state, otherwise, not Interfering with the level of the second = node; and - setting a reset potential, coupling the first reset node and the two points when the input signals are not any of the at least one estimated state, And the first reset node is isolated from the second reset node if the input signal is any of the at least one estimated state. CNTR2460100-TW/0608-Α4273 7-TW/Final 62 201220691 The logic gate is back to the domino count as described in item 1 of the If patent scope. /, the estimation circuit and the reset circuit are mutually configured with a clockless state return domino operation for the dual configuration logic. The logical logic clock state is back to the dominoes and operations on the plurality of input nodes. /, 5"""J + The above-mentioned number of input nodes perform the logic-free range in the no-clock state regression dominoes described in item 1, ί=solid: the ingress node includes a plurality of regression logics. , nodes, and, a plurality of input nodes are each designed to be in the month, - logic, I, state switching, and the upper, the 0 state and the logic,], after the transition state back to logic, 0 obtains several input signals respectively Setting to the preset node includes a pre-charging node, returning logic, 0, a domino circuit; the monthly card circuit includes a back when the domino circuit is the preset material charging node and the enabling node to logic, Bu: :: way to set the first reset node to (four), the output node and the domino circuit state the output node is a pin lock state point is logic, 0', when the first reset section ^ 1 The state circuit is reset to the preset state, and when the logic '1' is set, the dominoes: when the plurality of input nodes are the above-mentioned, the estimation circuit shifts the state of the pre-charge node CNTR2460I〇〇-TW/0608-A42737-TW/Final, 〇,, when the above 6j 201220691 ^ number of input nodes are not at least the above estimated state, the estimation circuit does not affect the preset node; Test the enable node as logic, 〇_ The enabling circuit is transited to the second point that is opposite to the Wei weight can not affect the second reset circuit point i. 1 Wang ι is logic; as its application; the non-synchronous state of the fine range mentioned in item 1 returns to the dominoes. The above plurality of input nodes comprise a plurality of regression logics, the points are self-logical, state and logic state, wherein Each input node is set to logic, G, and then return logic,! The preset node includes a pre-clear node, and the domino circuit includes a logical '1' domino circuit; when the domino circuit is in the preset state, the bone :: two points = enable node to logic. , and set the heart = the first - reset point to the logic Τ ' when the card circuit is in the lock state 'the domino circuit shifts the value of the point to the logic, ^ turn can node the node to logic, oh, When the first reset node transitions to logic, 0, the domino circuit is reset back to the preset state; when the plurality of input nodes form any of the at least one estimated state, the estimating circuit transition state The pre-clearing node to logic, i, and when the plurality of input nodes do not form any of the at least one estimated state, the estimating circuit does not affect the preset node; and when the enabling node is logic, When the enable circuit switches the second reset node to logic, 〇, otherwise, the enable circuit does not affect the second reset section CNTR2460I00^TW/0608-A42737.TW/Final 64 201220691 logic :=The patent-free range is not returned to the domino point; the upper phase number of input nodes includes a plurality of regression logics, and the input node includes a pre-charge node; the pre-=r connection= And corresponding to the plurality of input nodes a turn-in node; the closed-axis connected to the enabling circuit includes a -p-th electric potential, the axis is connected to the second-weight two: set and: the energizing node; and the point is set, and the gate is connected The reset circuit includes a plurality of second-to-second reset nodes that are connected in series with the corresponding one of the input nodes. Passing the above-mentioned plurality of input logic gates with the idle pole, the no-clock state described in item 1 of the patent patent circumference returns to the above-mentioned plural input sections of the dominoes to 4 k >points; ,, and has several regressions Logic, 0, input section, the preset node includes - pre-charging; the point is «set, serially connected to the corresponding wheel node in the pre-charging node. M gate is lightly connected to the plurality of inputs to enable the circuit Including a first _, the source potential, the 趣 趣 接 该 该 该 该 该 该 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以-TW/Final 201220691 The reset circuit includes a plurality of _ the second reset node, the channel is set, and each of the source gates is lightly connected to the first reset node of the transfer side, and is replaced by 9 (4) The input node that should be cut. Logic gate, wherein: the item of the clock state returns the domino number of the input node period; ", including a plurality of regression logics, 0, the input section of the preset node includes a pre-charge node; the estimation circuit includes a plurality of pass points and the reference potential are connected to the corresponding one of the wheeled nodes connected to the precharged point, and the plurality of input nodes are coupled to the plurality of input nodes, wherein the enable node comprises a first ρ electric potential, The bungee switches the second reset; the device is lightly connected to the power supply node by the source; and the defect is coupled to the gate, and the reset circuit includes a second ρ 罟铕ϋ 曹罟铕ϋ The channel device is coupled to the second terminal to the first reset node by a source, and is substantially purely one of the input nodes of the plurality of input nodes. The manuscript is 10. The patented first card logic gate, wherein: And the clock state returns to the bone point; the upper cut number of input nodes includes a plurality of regression logics, and the r input node edge preset node includes a pre-clear node; the estimation circuit includes a plurality of p channels _ Pre-clear the node, take the source axis卩 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 TW TW TW TW TW CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN The first Nit channel device is connected to the source, the second reset node is connected to the source, and the second Nit channel device is connected to the corresponding node in the first node. The wheel people node since the gate (four) the above multiple losses u. Such as the scope of the patent scope] card logic gate, where: <Heart',,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The estimating circuit includes a plurality of p-points and an H device between the power supply potentials, and is connected in series with the corresponding one of the pre-clearing nodes; the 'axis is connected to the plurality of inputs, and the enabling circuit includes a first-Nth pass The test potential is coupled to the second heavy 'M source to the parametric node with the drain electrode; and '' and the closed end is coupled to the second to the second; the pass is set, and the respective (4) gates are transferred to the above plural Input section resets the node, Λ 12. For example, the application of the patent scope; = the gate of the group, wherein: the meaning of the no-clock state returns to the plurality of input node points; the similarity logic, 1, the input of the preset node includes a pre-clear node; CNTR2460I00 -TW/0608-A42737-TW/Fina! ^ ' 67 201220691 The estimation circuit includes a plurality of p-channel points and the supply potentials, each of which is directly connected in series between the input nodes corresponding to the pre-clear section I (four) Extremely transfer the above multiple inputs.  The enable circuit includes a first N-channel device test potential, the drain is coupled to the second reset node, and the energy node; and the source is switched to the gate and the gate is connected to the reset. The potential includes a second N g two reset node, "the wire consumes the first -: set: 其 the input of the plurality of input nodes is set and "closed_13."  - an integrated circuit comprising: - a - logic, supplying a plurality of states of the regression signal is designed in a first state and two of the plurality of state regression signals are each set to be operated according to the first phase - The logic is set to the above-mentioned second shape energy; the clock-like card logic gate, purely on the number: state Hu 1 the no-clock state domain domino logic gate includes: - a preset node, an enable node, an output node, and a first/first reset node, each designed to switch between the first and second states; - a domino circuit having a pre-recorded state and a locked state, and two: when the domino circuit is in the preset state The domino circuit Γ = the preset node and the enable node to the first state, and the output node and the first reset node to the second state ', when the preset node is switched to In the second state, the domino circuit switches to the flash lock state, causing the output node to transition to the first -CNTR2460. 00-TW/〇6〇8-A42737-TW/Final 68 201220691 state, and the state of the enable node to the second state, when the first reset node transitions to the first state, the domino circuit Resetting back to the preset state; - the material circuit, when the plurality of state regression signals are at least one of the estimated state, transitioning the preset node to the first state - and returning in the plurality of states When the signal is not any of the at least one estimated state, the preset node is not affected; and the enabling circuit is configured to: when the enabling node is in the second state, turn t, the second reset node to the foregoing a second reset node; and ^ otherwise, does not affect: the reset circuit 'couples to the first reset section when the plurality of state regression signals are not any of the estimated states ^Resetting the node' and isolating the first reset point to the second reset node when the plurality of state regression signals are described to any one of the estimated states. Chu applies for the integrated circuit described in item 13 of the patent scope, and the 竽 j-logic supply in the basin supplies a plurality of regression logics;:: The second state is logic. , and the timeless two: the record of the armor - no clock return logic, G, domino logic gate. 15. If the product === regression state τ signal according to item 13 of the patent application scope, the above-mentioned first state = fset fIM W is logic T, and the clockless S-shaped domino escaping gate includes - no clock Return to logic, skeletal logic gate. The second circuit of the twenty-two patents, the product circuit described in the thirteenth item, the "no k-like resentment return to the domino τ ^ 咖 嶋 fresh tw marriage 37_TW / ^ series idle ^ including the string design of the complex _ 201220691 state Return to the domino logic gate. A method for estimating nasal-logical operations, including: Receiving a plurality of state regression input signals, each of which is designed to be returned to the second state according to the state return operation after being set to a first state; supplying a domino having a preset state and a question lock state Circuit, when the month card circuit is in the preset state, the domino circuit sets a preset - the ί energy node is in the first state, and the set-output node is set to the second state, in the preset When the node is turned to the upper=second state, the domino circuit switches to the lock state transition state, and the output points to the first state and transitions the enable node to the second state, when the reset node transitions When the first state is reached, the preset state is set, u estimates the plurality of state regression input signals, wherein the plurality of cancers: the input signal is at least one of the estimated states Pointing to the second state 'to switch the domino circuit to the flash lock state, and the == signal is the second state and the plurality of state regression inputs are the plurality of estimation states g In the middle-position, the node is set to the first-state to reset the card circuit to the pre-recorded power. The method of claim 17, wherein: ^ the preset node is switched to the second state to switch the domino circuit to the lock, and 4 to the enable node to the first The two-state steps include: '·, enabling a reset condition of the domino circuit. 19. The method of claim 17, wherein CNTR246OI00-TW/0608-A42737-TW/Final 7〇201220691 calculates a plurality of state regression input signal steps for the packet operation in the plurality of state regression input signals to The second or second logic or the above-mentioned first state transitions the preset node to the second transition state to the bone: the circuit includes the enabling node two = turn _=;:? signals are the second State; 20. The step of calculating the plurality of state regression input signals according to the method described in claim 17 includes: performing an estimation operation to convert the preset node to the above-mentioned plurality of states to return the signal to the full-state a second state, and wherein: the upper middle=the step of placing the domino circuit comprises: the enabling node is at least one of the plurality of state regression input signals, and the second state is transitioning to the reset node to the The first...regression 21·-there is no clock state return logic gate, including: a = each node 'each switched to a first state and a bad' including a plurality of input nodes, a preset node, and One and a second reset node, two: at least one of the incoming points includes a bear-like state, and then transitions back to the second according to the state return operation; = becomes the above-mentioned domino; the it has a preset state and, State, when the preset state, the domino circuit sets the preset node and the ^^^ point is the first state, and the output node is set and the second point is the second state, when the preset node is in a state For the above The circuit is switched to the f-side large state, and the output state is increased by the transition state (4) when the first state 201220691 returns to the first state, the domino state, when the first weight 3 is reset back to the preset state; Estimating the circuit, when the plurality of round-in nodes are at least one of the estimated state, the transition state is as follows: ^ The plurality of input nodes are not the above-mentioned at least one estimate (four) Exactly, the preset node is not affected; the enabling circuit 'the second state point is the first state in the enabling node, and the second node does not affect the second state when the enabling node does not And resetting the node; and the plurality of input ports are connected to the first reset node to the second reset node when the plurality of input nodes are not at least one of the above: the wide state The node isolates the first reset node from the second reset node by the at least one estimated state. Card logic: (4) ^^^ = between the two items mentioned in item 21 of the range of interest, wherein the estimation circuit and the reset circuit are non-double: For example, the 21st card logic gate of the patent application scope, wherein the reset lightning technology is not (4) state returning to the bone-sub-personal person--the set of plural input nodes: the sub-set includes at least one but not all: The input nodes of the sub-set each include a state transition section. Each of the sub-states only occurs when the domino circuit of the plurality of round-in nodes only changes from the first-state transition state, and the 堇 is in the above-mentioned number of turns The sub-sets of the input nodes are all reset to the preset state when they are in the first state. ”, ^ _421·==^Γ Γ咐 (4) state regression bone 201220691 card logic gate, where: the above multiple input nodes include at least one regression t said at least one regression logic, g, the nodes are each in-logic , the state of the state switch 'and at least one of the above-mentioned regression logic, 0, that is, d is set to logic, i turn back to logic, 0,; the preset node includes - pre-charge node, and the domino circuit Logic '〇' domino circuit; when back to the preset state, the domino circuit sets the accommodating point and the neon node to logic, Γ, and sets the output node and, the -reset node to logic '〇', when The domino circuit is in the form of a flash lock: the state of the output node to the logic state and the state of the transition state. And taking the first reset node back to the logic, the domino circuit is reset back to the preset state; when the plurality of input nodes are any of the at least one estimated state, The estimating circuit shifts the pre-charging node to logic, 〇, when the above complex number, the input node is not the above-mentioned at least one estimated state, when -:, the estimating circuit does not affect the preset node; and when the enabling The node is logic, 〇, when the enabling circuit transitions the second reset, that is, to the logic, 1'' and when the (four) point is not logical, 〇, the causative circuit does not affect the second weight Set the node. ^. 25. The clockless state return logic gate as described in claim 24, wherein the reset circuit is lightly connected to a subset of the plurality of input nodes, the subset comprising at least one but not all of the input nodes, the plurality of Each of the input nodes in the subset of input nodes includes a regression logic node, and each of the at least one estimated state occurs only in the above cNTR2460I. TW/〇6〇8-A42737-TW/Final 73 201220691 Multiple input nodes The sub-person, 〇, switch to logic, 丨, sleep. σ, at least one input node is used by the child of the logical node and the financial card circuit inputs the preset state only for the plurality of the above. . There are input nodes are all logic, G' is reset back to the open 26 · / in the scope of the patent application, the no-synchronization state mentioned in item 21 returns to the logarithm of the number of inferior surnames At=, , if 5 / h 占 至 to 〉, a regression logic T node, Shi Shu to " regression logic,], node and logic, 〇, state switching, Shangcheng τ驿 logic 1 shape forgiveness, a regression logic , the Γ node is 0 and then 回归 0 is returned to the logic, 1,; the preset node includes a box, the main #科,,, and the domino circuit includes a -regressive logic '1' domino circuit; When the domino circuit is in the preset state, the domino circuit setting = point = enable node is logic. And setting the output node and using the first point as the logic, when the domino circuit is in the flash lock state, the domino circuit shifts the output node to logic logic", when the first reset section _ : 2, _ Lang points in the point to return to the logic, 0, when the domino circuit is reset back to the preset state; when the above plurality of input nodes are any of the at least one estimated state A, the estimation Circuit transition state, the pre-clear node is logic, 1, and ♦ the plurality of input nodes are not in the above-mentioned at least one estimation state, the estimation circuit does not affect the preset node; and when the enable node For logic, 1, the enable circuit switches the second reset node to logic and when the enable node is not logic, I, the enable circuit does not affect the second reset node. CN丁R2460I00-TW/0608-A42737-TW/Final 74 201220691 The card logic is in the no-synchronous state of the bones as described in item 26 of the scope of patent 4 == brakes, where the reset circuit is difficult for the above multiple input Node's - point:, :,: [This: the set includes at least one but not All of the above input sections include - return to the input nodes in the subset of the input nodes, each package H series '!' node', and the at least one estimated state is at least one of the subset of the plurality of input nodes = When the node tit is input, and the domino circuit is only in the above plural. The input nodes of all the numbers in k sub-wood 5 are logical, 〇, when Cao w returns to the preset state. Ke U knows to reset Hanru's patent application scope 21st card logic, where: ..., the pulse state returns to the bone at least one of the input nodes; including a regression logic, 0, the preset node Included as a pre-clear node; and the domino circuit includes: the first phase of the pirate' has a round-in-one pro-technology box dead A/_ has a round-out end • the output node is connected to the pre-charge node and a first P Channel device, and the ancient point 'has-source_connected_power supply=5=round-out node, the pre-charge node, and has a drain coupled to a second inverter, has an input and has an output-side light connection The enabling node, a non-exit node, a first N-channel device having a 'gate coupled to the enable node, and: a connection to the test node; and 'and a pole coupled to the reset CNTR2460I 〇〇-TW/〇6〇s. A42737 Tw/F. Na ( ^ 201220691 and financial = device: with - input, the reset node and bit, and; the gate device ' has - the source is connected to the power supply has the output of the third inverter,] ί Xiu / And the pole is coupled to the pre-charging node, and has a card logic: the timeless state as described in the item returns to the bone and the reset circuit includes: r second ν flux: two second channel devices. For example, the 21st card logic gate of the patent application scope, wherein the description of the innocent pulse state returns to at least the input node of the plurality of input nodes; including a regression logic, I, the preset node includes a pre-clear node And the domino circuit comprises: a fifth inverted state, having an input terminal main ~ and having an output terminal to transfer the round out node; a monthly point, a first channel mounting, a point of sight, having a source = connected to the output node, the pre-clear node, · /, has a drain coupled to the first inverter, has a λ WJ · and the ancient mountain 9 into the j ^ transfer the round-out node, and has an output The end is coupled to the enabling node, and the first P-channel device has a right one--gate coupled to the enabling node, and two: a power supply node; and a pole coupled to the reset-first a three-inverter having a CNTR2460100-TW/0608-A42737-TW/Fina] 76 coupled to the reset node, 201220691 • and having an output; and a second N-channel device having a source The reference potential is coupled to have a gate coupled to the output of the third inverter, and There is a pole to lightly connect the pre-clear node. 31.  The clockless state returning to the domino logic gate as described in claim 30, wherein the estimating circuit comprises a plurality of second P channel devices, and the reset circuit comprises at least one third N channel device. 32.  An integrated circuit, comprising: a first logic to supply at least one state regression signal, wherein the at least one state regression signal is designed to switch in a first state and a second state, and the first logic operates according to a state regression After the at least one state regression signal is set to the first state and then set back to the first shape sorrow, and a clockless state is returned to the domino logic gate, the plurality of input nodes receive the at least one state regression signal, and the The clock state returning to the domino logic gate includes: a preset node, a uniform energy node, an output node, and a first and second reset node, each designed to switch between the first and second states; a domino circuit having a preset state and a latched state, wherein when the domino circuit is in the preset state, the domino circuit sets the preset node and the enabling node to be in the first state, and set the output node and the first a reset node is in the second state, and when the preset node transitions to the second state, the domino circuit Switching to the latched state to transition the output node to the first shape CNTR2460I00-TW/0608-A42737-TW/FinaI 77 201220691 state and transitioning the enable node to the second state, when the first Resetting the node to return to the first - makeup capable of setting the state; 丨 the domino circuit is reset back to the pre-estimation circuit 'when the plurality of input nodes are at least one of the estimated sorrows The preset node to the second state 'and does not affect the preset node when the plurality of input nodes are not any of the at least one of the estimated states; ^ - enabling circuit, the enabling The node is the second second reset node to the fourth (four), and does not affect the second reset node when the first node is in the first state; and a reset circuit is used in the plurality of input When the node is not any of the at least one estimated state, the first reset node to the second reset node, and the plurality of input nodes are any one of the at least one estimated state The second reset node is isolated/third when the second reset node is reset. For example, the integrated circuit described in item 32, wherein the estimation circuit and the reset circuit are designed in a non-dual configuration. 34. The integrated circuit of claim 32, wherein the reset circuit is coupled to a subset of the plurality of input nodes, the subset comprising at least one but not all of the input nodes, Each of the input nodes in the subset of the plurality of inputs, ie, points, is a state regression node, and the plurality of estimation states each occur only in at least one input node of the subset of the plurality of wheel people nodes from the second state In the transition state, the domino circuit is reset back to the preset state when all of the input nodes in the subset of the plurality of input nodes are in the second state. CNTR246O100-TW/0608-A42737-TW/Final 7S 201220691 The integrated circuit described in item 34 of the patent application scope provides at least one regression logic, 〇, signal, the above first form = , series, Γ And the second state is logic (four), and the no-time clock 4 = 遴 闸 includes a clockless regression logic, 〇, domino logic idle, and the sub-set of the last input node (four) input node each , 0, node. Resignation 36.  For example, in the frequency circuit described in the range of $34, the first logic supplies at least one regression logic signal, wherein the upper state is logic, 0, and the second state is logic, and the timeless _ the bones logic The gate includes - no clock return logic, the rf card logic gate ^ the rounding nodes in the subset of the plurality of input nodes are logical, 1, nodes. Dry back 37.  A method for estimating a logical operation, comprising: receiving a plurality of input signals, each designed to switch between a -state and a second state, wherein the subtracting the input signal includes a return to the f-number, the at least A state regression signal will be reset back to the second bear according to the state regression operation after being set to the above-mentioned first sorrow.   a bone two circuit having a preset state and a latch state, when the domino circuit is in the preset state, the card circuit sets the preset point and the enable node to a first state, and sets An output node and two reset g卩 points to a second state, when the preset node transitions to the second state, the domino circuit switches to the question lock state to shift the output node to, the first a state and a transition state of the enabling node to the second state, when the reset node is in the first state, the domino circuit is reset back to the preset state; CNTR246OI00-TW/0608-A42737-TW/ Final 79 201220691 Estimating the above plurality of input signals, the i signal is at least one estimated wing strength, and the input signal is switched to the flash when the input node is switched to the flash circuit. a lock state; and the second state of the above = two - ί and the plurality of input signals are not; when the first state = the target estimator state, the state is changed to the reset state to the first shape, to Place the domino circuit to the preset position. 38.  The method of claim 37, wherein the resetting step comprises: the enabling node transmitting the reset node to the m-th at least one state regression signal when switching to the first state First state. 11th - 39.  The method of claim 37, wherein: the estimating step comprises: transitioning the preset node to the second state when there is at least one transition state in the at least one state regression signal to the first state; And the resetting step includes: changing the reset node to the first state when the enabling node is in the second state and the at least one state return signal is all returned to the second state. 40. The method of claim 37, wherein: the estimating step comprises: shifting the preset node to the second state when the at least one state regression signal is fully converted back to the first state, and the weight is The step of setting includes transitioning the reset node to the first state when the enabling node is in the second state and the at least one state regression signal is fully transitioned back to the second state. 41.  A clockless state is returned to the domino logic gate, and responds to a plurality of input logic signals. The above input logic signals are respectively switched to a first and a first CNTR2460100 'TW/0608-A42737, TW/Fina 丨80 201220691 € No clock state returns to the logic.   A domino circuit, including: ]i.   And a plurality of nodes, switching to the foregoing - the foregoing node includes a preset node, a round-out two-to-state, and a --threshold node; a round-out point, an enable node, and a phaser having an input The terminal _ is connected to the preset metric ton and the octave-output terminal is coupled to the output node; p point, a first f of the one-to-one conduction form is connected to the output node, and the JL has a __f ” Related - the: power supply 冤 / original, 即 position is point, and the right 笙 _ k end is coupled to the preset node; eight brothers one electric and -; t =, with a round end • connect the wheel An output node, the eight-wheeled end is coupled to the enabling node; a first conduction form of the second conduction, the terminal is connected to the second logic, and the first current is: first current [, with - The control end is coupled to the enabling node, the '^ terminal is coupled to the first-reset node; the first electrical:::the inverter has a round-in terminal that consumes the first-reset section, and has an output And a second device of the form of a lighter transmission: a second current device having a -first current supply potential node having a control terminal switching the first The output terminal has a second current terminal that is pre-coupled to the preset node, and the reset is added to the circuit, and the number of the door is also converted into a single input. Ten X responds to the above multiple input logic CNTR2460. 〇〇-Tw/〇6〇8. A42737. Tw/Fina] ^ 科丨口 is in the middle, when 201220691 the above multiple rounds of logic, although A 砗n · Tiger is at least one of the estimated state of the "when the input circuit transitions the preset node to the A plurality of round-robin logic_numbers are separated from (four) X-th-status states 'when taking office', at least one (fourth) state of the estimated state. Temporarily turning to the first-reset node to the first 42. For example, the patented range first card logic gate, wherein the input circuit includes: returning to the bone by the hot clock state, when: ϊΐιΓί to respond to the plurality of input logic signals, "any one == solid logic signal is The at least one estimated state: the state of the first circuit is that the preset node is the second logic state, and the second energy state is the second logic state, and the transition state reset point is a first logic state; And a reset circuit designed to respond to at least one of the input logic signals, 1 and 2. The internal signal is not at least one of the above-mentioned estimates: two, a plurality of input logics, each of which is external The reset circuit is lightly connected to the first reset node to the second reset node. The cardless logic is as described in item 42 and the non-synchronous state is returned to the bone wide (four), wherein at least one of the lighter money is at least - Resent the return signal, which is supplied to the estimated electrical regression signal. "The circuit and a state of the reset circuit. For example, the n-card logic gate described in claim 41 of the patent application further includes the output terminal of the second conduction=none-time==bone=end_three-inverter, the first reset node' and has-second The current terminal is coupled to the first R246 〇, 〇〇-TW/〇6〇8-A42737-TW/Finai 82 弟一电201220691 source potential node. 45. For example, in the patent application scope 4] card logic, wherein the first; kg J4 (four) pulse state return to the bone position 'the second power potential node inflammation-positive power supply type includes the semiconductor P form, and the second pass A form of conduction. The seek open/type includes a semiconductor N-shaped 46. For example, the application of the 3rd patent range 4] card logic, wherein the:: the no-clock state returning to the second power potential node has one: two: there:: test potential 'this includes the semiconductor N form, and the The second conduction: the electric card logic (four), riding the return material to return to the bone positive value power supply two or two f source potential nodes respectively have - at least - including the above several input logic signals 匕栝 regression ,, 0, signal , i · the preset node includes a pre-charge node; eight of the first-conducting form of the first set, has a gate button 匕 苐 P P - P channel installed power potential, and ί::: node, with a source receiving the positive polarity and having a drain coupled to the precharge node; the _ device package in the form of a conduction, the pole is coupled to the reset node; and the second device in the first conductive form Including, the source has the positive value - the original potential of the channel-mounted third inverter has a pole coupled to the gate and has a non-axis to the pre-charge node. CNT^460l00^W/0608-A42737-TW/Fil 4 1 item without clock state return bone 83 C 201220691 == bit = = and the second power potential node respectively includes at least one of the series signal including bit ' Wherein the plurality of input logics, ^" includes a regression logic τ signal, wherein the preset point includes - a pre-clear node; the first device includes - the -n channel loading potential and has The first clearing mode of the first device includes: a first receiving the positive power supply potential, having a -gate core,,. 〆, having a drain coupled to the reset node; and::-the second device in the form of conduction includes a second phase; = receiving the reference potential, having a -axis junction having - a pole coupled to the pre-clear node . 49.  An integrated circuit comprising: a f-th path, supplying at least one state regression signal, wherein the upper=one state regression signal is switched to the -first state and the second, and the first circuit is set to the above state in the state regression signal After the shape L, it will be set back to the second state according to the state regression operation; : Number: the node 'switches to the above first and second logic: state, upper:: solid: the point includes a preset node, an output node a uniform energy node, a heavy f卽 point, and a plurality of input nodes, wherein the plurality of input nodes are up to >, and the factory receives one of the at least one of the recorded state return signals; the first reversed phase has an input terminal Connected to the preset node, and an output terminal is connected to the output node;" 201220691 output node, having, capable of receiving a first power supply potential associated with the first logic state, and a second terminal is coupled to the preset node-wheel: ==: a node at the wheel end and having a first transmission of the second transmission state - the second power source in the second logic state = ::Stream-terminated-third inverter with one/in:, connected to the reset node; having an output; w, lightly connecting the reset node, and having the first conduction form The first power supply potential, ^ the first current terminal of the Bayi is connected to the output end, and is provided with - the second: the control terminal is lightly connected to the third input of the third inverter: the current terminal is connected to the preset node, And the rebel circuit, coupled to the preset node, the node, and the plurality of input nodes, the ^^ point, the enabling node is at least one of the estimated states, and the plurality of rounded preset nodes to the first: _ Road transition state is not in the above-mentioned at least one estimated state: death = number = ingress node transition state, the reset node to the first logic state wins the 'round-in circuit temporarily the 50th profit range The integrated circuit of item 49, further comprising a second device in a 4-conducting form, further comprising the wheel end of the inverter, having a first: fork control (four) connected to the third j-th current terminal receiving the The second power supply potential, which is the point, the integrated circuit described in Item 49 of the patent application scope, Longzhong The power supply potential of the younger brother includes a positive electric power tower, wherein the CNT~tw/_8_ gives a -:; potential, the second power supply potential includes 201220691, the first conductive position includes the semiconductor p-type technology, and The first conductive form includes a semiconductor N-type technology. The integrated circuit described in claim 49, and the reference potential, the second power supply potential includes -: the first conductive conduction type includes a semiconductor n-type technology The intermediate-conducting circuit includes a semiconductor P-type technology. The integrated circuit of claim 49, wherein the upper reference potential, the source potentials in the material respectively comprise a positive power supply potential and a preset node Including - pre-charging node; set, = 1 ^ form of the first device includes - the -p channel is equipped with eight poles coupled to the output section, a power supply potential, and has - no polarity called the pre-charge point The positive value is set, and the first device of the H-conductor form includes: -N-channel loading:: pole: the reference potential 'has a pole turn point and has a pole that consumes the reset node, and , the second device in the form of 1 包括 includes - the second p channel The output terminal of the third inverter, 曰J has a gate coupled to the 54 such as Shenyi straight p, and a immersive transfer of the precharge node.苐- and = _ 49 items of the integrated circuit, 1 and the second power supply potential respectively package the power supply potential, and wherein: the smart switch and a positive value of the preset node include - pre-clear node; The first device in the form of conduction includes a first set, having -f (four) the input (four) point, , and CNTR2460IOO-TW/〇6〇8-A42737-TW/Final ^ source receiving the reference 201220691 * potential, And having a drain electrode coupled to the pre-clear node; the first device of the second conductive form includes a first p-channel device having a source receiving the positive power supply potential, and having a gate lightly connected to the enabler a second node of the first conductive form, the second device includes a source receiving the reference potential, and having a gate coupled to the node The output of the third inverter has a drain coupled to the pre-clear node. 55.  A method for estimating a plurality of logic signals, wherein the plurality of logic signals includes at least one state regression input signal, comprising: setting a preset node to a first logic state, the first logic being a second logic state Inverting; presetting the preset node to define a logic state of an output node; inverting the output node to define a logic state of the consistent energy node; and transitioning the reset node when the enable node is the first logic state Up to the second logic state; inverting the reset node to determine a logic state of an inverting reset node; and when the inverting reset node is in the second logic state, transitioning the preset node to the first a logic state; forcing the preset node to be the second logic state only when the plurality of input signals are at least one of the estimated states, the plurality of input signals including at least one state regression input signal, the state regression logic The signal returns to the second logic state after the transition state is the first logic state; the enable node is the second logic state and the plurality of inputs are When the state regression operation is separated from an estimated state, the reset node is forced to the first logic state; and CNTR2460!00-TW/0608-A42737-TW/Final 87 201220691~ the reset node is forced to be the first- In the logic state, the inversion reset=point turn g is the second logic state. Then, the preset node returns to the logic state. Then, the output node returns to the second logic state, and then turns The enable node returns to the first logic state, and then the reset node returns to the second logic state, and then the inverted state resets to occupy the first logic state. 56.  The method of claim 55, wherein the step of forcing the preset node to the second logic state comprises transitioning at least one of the at least one state regression input signal to the first logic centroid And the step of forcing the reset node to the first logic state comprises transitioning at least one of the at least one state regression input signal back to the first logic state. 57.  The method of claim 55, further comprising maintaining the reset node to the first logic state using a half of the sustain circuit. 58.  The method of claim 55, further comprising maintaining the reset node to the second logic state using a half of the sustain circuit. 59.  The method of claim 55, wherein the step of setting the preset node to the first logic state comprises pre-charging a pre-charge point to a logic '〗, the resetting the reset node The step of the second logic state includes transitioning the reset node to logic, and the step of transitioning the preset point to the first logic state includes transitioning the precharge node to logic '1', the step of forcing the preset node to the second logic state comprises forcing the pre-charge node to fall to logic, 0, and the step of forcing the reset node to the first logic state comprises forcing the weight Set the node up to logic '],. CNTR2460I〇〇-TW/〇6〇8-A42737-TW/Final 88 201220691 6〇. The method of claim 55, wherein the step of setting the preset node to the first logic state comprises setting the second setting to a logic, 〇, the transition state to the first pre-node The step of shifting the reset node to the logic, 1, the step of the above-mentioned transition state, the step of the f-series state includes shifting the pre-clearing section = 〇 'the above forcing the preset node to the second logic State = Force the pre-clear node up to logic, 丨,, 匕 - - Logic state steps include forcing the ^1 node to force the reset node to fall to logic, 0,. CNTR2460I00-TW/0608-A42737-TW/Final 89