TW201218592A - Switching power converters and switching control circuits therefor - Google Patents

Abstract

A switching control circuit for a switching power converter is provided. The switching control circuit is coupled to a switching device and an auxiliary winding of a transformer. The switching control circuit includes a valley detecting circuit, a valley lock circuit, and a PWM circuit. The valley detecting circuit is coupled to receive a reflected voltage signal from the auxiliary winding of the transformer for outputting a control signal in response to the reflected voltage signal. The valley lock circuit is coupled to receive the control signal for outputting a judging signal in response to the control signal during a first period and a second period following the first period. The PWM circuit outputs a switching signal in response to the judging signal.

Description

201218592 VI. Description of the Invention: [Technical Field] The present invention relates to a switching control circuit, and more particularly to a switching control circuit for switching a power converter. [Prior Art] A power converter is used to unregulated an overvoltage or current source. Power converters typically include a transformer or magnetic element having a primary side coil disk and two underside coils to provide isolation. A switch that is connected to the primary side coil is used to control the transfer of energy from the primary side coil to the secondary side coil. The power converter operates at high frequencies so that size and weight can be reduced. However, the switching operation of the switch will result in switching loss and electromagnetic interference (Electro_magnetic_interference' EMI). Figure j shows the flyback converter (fly_backp〇werc_erter) and the waveform of the associated signal is shown in Figure 2. The switch Q丨 is used to switch the dust collector τ, and the control power is transmitted from the primary side winding Np of the transformer D to the transformer Ο1, :::: coil NS. Switching letter! Tiger ¥〇 is generated to drive the switch 1 Tian 'passage period 1 D (10) switch Q|# switch signal, there is a change. #_„ When Qi is turned off, the energy is transmitted through the rectification to the reverse power transfer and at the same time 'according to the electrical cross-over ratio of the output capacitor Co to the MIIT1 - the secondary coil core To produce ^EVr (not shown in Figure 1). Therefore, once mrr is switched, the power across the switch _仏 "equal to the input power parasitic power Μ r HD is stored in the virtual ... 'where 'virtual parasitic capacitor cQ It is equivalent to switching off the parasitic capacitor of 201218592 and Q. In - the energy is completely discharged, and the 〇 / / 史 俊 俊 俊 俊 〇 〇 〇 〇 〇.能量 The energy stored in the parasitic capacitance CQ is transmissive. . The σ 1 human side coil Νρ is reversed to the wheeling voltage vw. Parasitic capacitance Co盥 transformer pressure crying T — L 丨N Wang Wanggu

, / τ 丨 - the secondary side coil inductor forms a resonant tank. A, , and the groove frequency fR can be expressed by the formula (1): f〇r-__ 2./Γ-y^Lp X cj The second j system represents the capacitance value of the parasitic capacitor Cq, and the Lp system represents the change of the stolen 1 The inductance of the primary side coil inductor. π is transferred back and forth to the energy of the parasitic electric cell Cq at the I-period d to the under-torque inductor that is transformed into T1. The power conversion H has a delay time Tq ' ^ which corresponds to the time it takes for the parasitic capacitor Cq to discharge until the voltage % to ^ reaches a minimum value. The delay time % is the period of the quasi-symmetry (quasi), and it can be expressed by the equation (2): τ 1 . , as indicated above, if the switch Q 丨 is turned on during the valley voltage across the switch Q1 A flexible switching is achieved to minimize switching loss and electromagnetic interference (EMI) of the power converter. SUMMARY OF THE INVENTION The present invention provides a switching control circuit suitable for switching a power switching DO switching control circuit, a lightly switched switch, and an auxiliary coil of a transformer. The switching control circuit includes a valley detecting circuit, a valley locking circuit, and a pulse width modulation (PWM) circuit. The valley detecting circuit receives the reflected voltage signal from the auxiliary coil of the transformer to output according to the reflected voltage signal. The control signal. The valley lock circuit receives the control signal 201218592 to continue the first period according to the = number 'where the second period is in the first period and the second period. The pulse width circuit outputs the switching signal according to the determination signal. Providing a switching power converter including a switch, a change, and a switching control circuit The switch is controlled by the switching signal. The coffee has a secondary side coil and an auxiliary line 圏. The switching control circuit switches the switching switch and the auxiliary coil of the transformer. The switching control circuit includes a hole detecting circuit, a valley locking circuit, and a pulse width adjustment. Changing (ρ_ _ modulatlon ' PWM) circuit. The valley detecting circuit receives the reflected voltage signal 'from the dancer: the auxiliary coil to control the signal according to the reflected voltage signal. The reflected voltage signal is generated when the switch is turned off' and The resistor is connected to the auxiliary coil of the transformer. The valley lock circuit receives the control signal to output the determination signal according to the control signal in the first period and the second period, wherein the second period is continued in the first period. The valley locking circuit is configured to receive the determination signal, and output a switching signal according to the determination signal to turn on the switching switch. [Embodiment] The above objects, features and advantages of the present invention are made more obvious, and the following is a preferred embodiment. The example 'with the closed type is described in detail below. Fig. 3 shows the switching work according to the present invention. The switching control circuit 30 includes a feedback terminal FB, a current sensing terminal cs, a voltage detection terminal DET, an output terminal OUT, a power supply terminal vcc, and a reference terminal gnd. 'The voltage τ 丨 includes the primary side coil Np The secondary side coil Ns and the auxiliary 201218592 two underside coils (4) switch the secondary side coil of the switch to the second 4 Ds and the output capacitor c. To couple the switching power converter: switch:!: The coil is transmitted through the second rectifier ~ and the capacitor cst, the power supply terminal VCC of the circuit 30 to supply the power supply vcc to the switching control circuit 30. cc^ people read the third picture 'switching control circuit μ voltage detecting end det The auxiliary coil na is coupled to the auxiliary coil na, wherein the switching switch switching control circuit 3Q receives the reflected voltage from the resistor R2. The output terminal ο τ of the switching control circuit 30 generates a switching signal switching switch Q1. The current sensing resistor Rs is connected to the switch 1 < When the switch Y1 is turned on, the switching current signal vcs is generated. The current sensing terminal CSM of the I 々 control circuit 3G is connected to the current sensing s, and receives the switching m number Vcs. Furthermore, the switching control circuit ^ feedback terminal FB consumes the optical combiner 35 to receive-receive the signal Vfb. The facer 35 switches the power conversion through the resistor 31 and the susceptor 32 to the output terminal ′ to receive across the output capacitor c. The output signal ν. And converting the output signal v0 into a feedback signal VfB. Referring to Fig. 3, when the changeover switch Qi is turned off, the switching control circuit 3 receives the reflected voltage HvA from the auxiliary coil of the transformer 透过 through the resistor ^. Then, the switching control circuit 3G detects whether the % switching is open to the valley voltage of the reflected voltage signal vA in a spectral period, and detects the previous oscillation period. Whether it has the same or more troughs than it does. When the same or a large number of troughs is detected, the switching control circuit 30 turns on the switching switch Qi. This increases the efficiency of switching power converters and avoids noise. 201218592 Figure 4 shows a switching control circuit in accordance with an embodiment of the present invention. The switching control circuit 30 includes a valley detecting circuit 丨〇, a valley locking circuit 2, a minimum off time circuit 70, an unlocking circuit 4A, and a pulse width modulation (PWM) circuit 50. The valley reading circuit 1 includes a first current mirror composed of transistors 100 and 102, a sample resistor rm, and a comparator 103. The first current mirror is coupled to the auxiliary winding Να of the transformer through the switch ι〇ι and the resistors Ri and r2 (shown in Fig. 3). When the switch Q1 is turned off, the switch 1〇1 receives the reflected voltage (4) vA from the resistance κ, where the reflected voltage signal Va is proportional to the voltage VD across the switching switch Q!. The reflected voltage signal ¥8 alternately oscillates between the positive voltage and the negative voltage during the resonance period. When the reflected voltage signal vA is at a negative voltage, the switch 1〇1 is turned on, and the first current 1丨 flows through the switch UH. At this time, the first-current mirror is mirrored to the second current L according to the first current L. Then, the sampling resistor RM coupled to the first current mirror receives the first current I and generates a peak voltage signal Vm. The magnitude of the peak voltage signal vM is also proportional to the voltage across the switch. The valley detecting circuit 10 further includes a peak comparator 1〇3 that receives the peak voltage (4) VM to generate a control signal Sc (comparison result) based on the peak voltage signal ^ and the first threshold voltage vT1. The chopping valley lock circuit 20 includes a counter 200, a register 2 (M, a subtraction benefit 202, and an arbiter 2〇3. The counter 2 receives the control signal & to count the reflected voltage signal VA in each cycle. The number of troughs is generated according to the counting result (for example, c〇~. Among them, the counter 2 number of leaves is in the trough number of the reflected voltage signal generated by the current period. The temporary storage 201 storage data r〇 ~R3, wherein the data R〇~心8 201218592 is related to the number of troughs generated in the previous cycle and reflected from the counter 200, VA. The subtractors 2〇2 are respectively coupled to the output of the counter 2〇〇 and The output of the register 201 receives the data C〇~C3 and R〇~R3, and performs subtraction operations on the materials CG~C3 and Rq~R3 to generate subtraction results D〇~D3. The arbiter 203 receives The data D〇~D3 are used for arbitration, and the sub-rounding-judgment signal SL to the PWM circuit 500. Once the subtraction result data DG 〇3 is not less than zero (positive value), the judgment signal & is enabled (enabiecj), which indicates Compared with the 4 vibration cycles, The same or more troughs are detected. On the other hand, when the subtraction result data D0~D3 is less than zero (negative value), the judgment signal SL is disabled (disabled), which means that when compared with the previous s white vibration period The valley lock circuit 20 locks when less number of troughs is detected. Referring again to Fig. 4, the minimum off time circuit 70 receives the feedback signal VFB to generate a minimum off time signal based on the feedback signal Vfb. The minimum off time signal Srt and the control signal sc are detected to detect the time between the two wave valleys after the minimum off time of the minimum off time signal Srt. Once the minimum off time of the minimum off time signal SRT is detected When the time is longer than the time between the two waves, the unlocking of the Sunlock k is enabled. The PWM circuit 50 includes either the gate 5 and the gate 52, and the flip-flop 53. The gate 51 receives the lock 彳§ sUNCL〇CK and the determination signal And one of the gates a is coupled to the output of the gate 51. The other input of the gate 52 receives the dare to close the time signal SRT. The gate 52 generates the rounding signal s52. The front and back boundaries 53 have The pulse terminal Ck, the data terminal D, the reset terminal R, and the output terminal q. The clock terminal ck receives the control signal sc to enable the switching signal vG. The data terminal 〇201218592 according to the output signal of the gate or the minimum off time signal The reset terminal R is coupled to the output of the comparator 60. The comparator 60 is coupled to the feedback terminal FB and the current sensing terminal CS to receive the feedback signal Vfb and the switching current signal Vcs to reset respectively. The flip-flop 53 and the switching signal are turned off. Fig. 5 shows the minimum off-time circuit 7A according to an embodiment of the present invention. The minimum off time circuit 7A includes a first comparison stomach 〇1, an inverter 702, a current source iREF, a capacitor 〇7〇, a second comparator 7〇6, and or a gate and the 'minimum off time circuit 70 further includes three Switches 7〇3, 7〇4, and 705. The first comparator 701 receives the feedback signal VFB and the second threshold voltage Vn for comparison operation. The inverter 7〇2 is coupled to the output of the first comparator 7(1). The switch 703 receives the feedback signal Vfb2 which is controlled by the output of the first comparator. Switch 704 receives the second threshold voltage ν τ 2 and is controlled by the output of the comparator: through the inverter 7 〇 2 . Turn on M 7G5 _ switch 7〇3 5 2 and feel that the switching signal % is controlled by the current source 1REF and capacitor 70 as between the power supply VCC and ground. The second comparator 7〇6 draws current: upper: and a node ’ between the capacitor C7 and receives the reference voltage to operate. Or gate 7Q7 minus the output of the second comparator and the tool ^Vg. Or gate 707 produces a minimum off time signal SRT. The wrong mine indicates that the circuit 4g is based on this wealth. In the solution ^ positive and negative 80, switch 8 current source 82, capacitor 83, during the period * holding circuit 84 together - the detection circuit 'to detect at each S7> system on ί 1 and compare S 89 is used to form a limiting circuit for limiting the phase of the smallest _. - Referring to Figure 7, after the switch Ql 201218592 is turned on, the reflected voltage signal vA has alternating positive and negative voltages. When the magnitude of the peak voltage k number VM is greater than the first threshold voltage ντι (see Fig. 4), the control signal sc is enabled. The output from the flip-flop 80. The signal s8〇 is disabled according to the rising edge of the control signal sc (as shown in Fig. 6), at which time the switch 81 is turned off and the charging consists of the current source 82 and the capacitor 83. The circuit generates a ramp signal s81. Next, the maximum voltage signal Vm# is generated at the output of the maximum sustain circuit 84 (e.g., a sampling circuit) and is passed to the negative input of the comparator 89. In addition, another ramp signal S88 is generated at the positive input of comparator 89 based on the pulse width of the minimum on-time signal. Once the ramp signal Sss is greater than the maximum voltage signal, the unlock signal SUNL0CK is enabled through the other flip-flop 890 and is disabled by the delay circuit 891 after a delay time. Figure 8 is a diagram showing the state 200 of the valley lock circuit 2 in accordance with an embodiment of the present invention. Counter 200 is a four-bit counter that includes four positive and negative | § 204 to generate data c〇 ~ C: 3 based on the rising edge of control signal Sc. Each flip-flop 2〇4 further has a reset terminal R to be reset according to the rising edge of the switching signal VG. This counter is a conventional counter and has been widely used' so the description is omitted here. Fig. 9 is a view showing the temporary storage 201 of the valley lock circuit 2 according to the embodiment of the present invention. The register 201 has input terminals ΪΝ〇~ΪΝ3 for receiving the data c〇~C3 outputted by the counter 2〇〇 according to the rising edge of the switching signal vG. The temporary storage benefit 201 also has an output port 〇〇~〇3 to output data ~ R3. Figure 10 shows a subtractor 202 in accordance with an embodiment of the present invention. The subtraction state 202 is composed of a complex adder (fuii adder) for receiving the data of 201218592, respectively, C〇~C3 and r〇~r, the result data 〇0~〇3 and the coffee ^^ then 'rounding minus The result data NEG was enabled; and when #, ,. When the value is positive, the subtraction data NEG is disabled. /,,·. If the result is a negative value, the result of the subtraction is shown in Fig. 11. The result is _ packet according to the present invention; the result is - and m is the result of NECJ. The judgment signal St is output after the operation. / In the field 軏 Refer to Figure 12A, 筮 冈 4, a_u μ electric (four) electric final wave peak: = r has alternating positive VV Λ / w long, electric 邕彳 5 唬 VM size and the first voltage - ΐ : Ray r V4 is inversely proportional. When the magnitude of the peak voltage signal Vm is greater than the second =: = represents the generation of the valley, the control signal is enabled. The number of births. 4 In the first = shouting ~ the number of energized represents the trough production in the first cycle of the first cycle, the number of troughs of P2 is greater than the number of troughs of the high logic ^ cycle) P1 'judgment signal Sl is = can). At this time, the switching signal Vg is broken due to the opening of the control signal due to the minimum off time signal. The radio V2B diagram and the fourth diagram' have a positive positive voltage and a negative voltage after the switch Q1 is turned off. Once at the minimum off - period / 11 time is longer than the time between the two waves, the first _lock signal SUNLOCK will be enabled. In the second period p, the number of Γ/ΓΓ is less than the first period. The number of ι之波谷, because.琨, still disabled (low logic level). At this time, if the minimum 12 201218592 off time signal sRT is a high logic level, the switching signal Vg is turned to a high logic level (on state) according to the rising edge of the control signal ssc. According to the above, the switching control circuit of the embodiment of the present invention can detect whether the voltage VD across the switching switch Q is close to the valley voltage according to the reflected voltage signal when the switching switch Q! is turned off. In addition, once the number of troughs per cycle is less than the number of troughs corresponding to the previous cycle, the switching signal vG is enabled after the detection, the ϊ to the lower trough to avoid noise from valley switching. Therefore, the switching control circuit of the embodiment of the present invention can provide higher efficiency to the switching power converter when operating under different loads. The present invention is disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art will be able to make a few changes without departing from the spirit and scope of the invention. Run ΐ 'Therefore, the scope of protection of the present invention is subject to the scope defined by the patent application. 1 [Simple description of the drawing] Fig. 1 shows a flyback power converter; Fig. 2 shows a signal waveform of a flyback power converter in Fig. 3; Fig. 3 shows a switching power converter according to the present invention; 4 diagram is not according to the embodiment of the present invention, the switching control circuit of the third converter; am force rate conversion, invention 4, (10) control power according to an embodiment of the present invention, and the switching control electric brother 7 diagram 3, the signal waveform of the switching power converter is switched; 13 201218592 FIG. 8 shows a counter of the valley locking circuit of the switching control circuit in FIG. 4 according to an embodiment of the present invention; FIG. 9 shows a fourth diagram according to an embodiment of the present invention. a register of a valley lock circuit of a medium switching control circuit; FIG. 10 shows a subtractor of a valley lock circuit of the switching control circuit of FIG. 4 according to an embodiment of the present invention; and FIG. 11 is a diagram showing an embodiment of the present invention 4 is an arbiter for switching the valley locking circuit of the control circuit; and 12A and 12B are diagrams showing the signal wave of the switching power converter in FIG. 3 [Major component symbol description] 'Figure 1: C〇~transmission Out capacitor; CQ~virtual parasitic capacitor;

Ds~rectifier;

Ns ~ secondary side coil Tl ~ transformer; VG ~ switching signal; V 〇 ~ output signal; NP ~ primary side coil; Q1 ~ switch; VD ~ voltage; VIN ~ input voltage; Figure 2: fR ~ resonant tank frequency T0N~ conduction period; VD~ voltage; T d~ discharge time; Tq~ delay time; VG~ switching signal;

VlN~ input voltage; VR~reflected voltage signal; Fig. 3: 14 201218592 30~ / switching control circuit; 31~ resistor; 32~ regulator; 35~ optocoupler; C〇~ output capacitor; Cq~ virtual parasitic Capacitor Cst^-capacitor; CS~• current sensing terminal; 'DA~second rectifier; Ds~rectifier; DET~voltage detection terminal; FB~•feedback terminal; GNE >~reference terminal; Na~ auxiliary coil; Np~ primary side coil; Ns~ secondary side coil; OUT ~ output terminal; ~ switcher; Ri ' R2 ~ resistor; Rs ~ current sense resistor; Ding Guang transformer; VA ~ • reflected voltage signal; Vcc"; Vcs " ~ switch current signal; Vfb " - feedback signal; VD ~ • voltage; vG ~ / switching signal; VIN - - input voltage; V 〇 ~ - output signal; vcc ~ power supply; 4: 10~ Valley detection circuit; 20~ valley lock circuit; 40~ unlock circuit; 50~ pulse width modulation (PWM) 51~ or gate; 52~ and gate; 53~ flip-flop; 60~ comparator; Small off time circuit; 101--switch; 100, 102~ transistor; 103~ comparator; 200, - counter; 201~ register; 202-~ subtractor; 203--arbiter; 15 201218592 ck~ Pulse terminal; CS ~ current sensing terminal; D ~ data terminal; DET ~ voltage detection terminal; FB ~ feedback terminal; 11 ~ first current; 2 / ~ 1 brother two current, R ~ reset terminal; Rm ~ Sampling resistor; Q~output; s52~output signal; Sc~ control signal; sL~judgment signal; SRT~minimum off time signal SuNLOCK~unlock signal, VA~reflected voltage signal; Vcc~power supply; VFB~ feedback signal; VG~switching signal; Vti~first threshold voltage; vM~peak voltage signal; Figure 5: 70~minimum off time circuit; 701~first comparator; 702~inverter; 703, 704, 705~ switch; 706~ second comparator; 707~ or gate;

Iref~ current source, C70~capacitor,

Srt ~ minimum off time signal; Vcc ~ power supply; vFB ~ feedback signal; VG ~ switching signal; Vref ~ reference voltage, vT2 ~ second threshold voltage; Figure 6: 40 ~ unlock circuit; 80 ~ forward and reverse; 81~switch; 82~current source; 83~capacitor; 84~maximum sustain circuit; 16 201218592 85~inverter; 86~switch; 87~current source; 88~capacitor; 89~ comparator; 890~ forward and reverse ; 891 ~ delay circuit; S80 ~ output signal; $81, ~ ramp signal; Sc ~ control signal; sRT ~ minimum off time signal; SuNLOCK ~ unlock signal; Vcc ~ power, VMAx ~ maximum voltage signal; vG ~ switching signal; 7: Q, the output of the general-reverse device 80. Sc~ control signal; sRT~minimum off time signal Ssi, S88~ramp signal; T〇ff, min~minimum off time; Va~reflected voltage signal; Vmax~ Maximum voltage signal; VG~switching signal; Figure 8: 200~ counter; 204~ forward and reverse; C〇...C3~ data; Sc~ control signal; Vd~ voltage; VG~ switching signal; Figure: 201~ register; Co~c3~ data; IN0...IN3~ input; 0〇~03~output; R〇~R3~ output data; VG~switch signal; 201218592 ίο图: 202 ~ subtractor; C〇~C3~ data; D〇...D3~subtraction result data; R〇~Κ·3~ output data; NEG~subtraction result data; Figure 11: 90~ or gate; 91~反Or gate; 203~arbiter; D〇... D3~ subtraction result data; NEG~subtraction result data; SL~judgment signal; 12A diagram: P1~first period (previous period); P2~second period (current cycle);

Sc~ control signal; ~ judgment signal; SRT ~ minimum off time signal;; vG ~ switching signal; vM ~ peak voltage signal;

Toff, min~minimum off time; VT1~first threshold voltage; VVl/^V2^V3^V4'^"第电压,第12B图: P1~1st cycle (previous cycle); P2~2 Cycle (current cycle); sc~ control signal; sL~judgment signal; 18 201218592 sRT~minimum off time signal;

SuNLOCK~unlock signal; VA~reflected voltage signal; VG~switching signal; VM~peak voltage signal;

Toff, min~minimum off time; VT1~first threshold voltage; Vvi, Vv2, Vv3, Vv4~first voltage;

Tvalley^ wave. 19

Claims (1)

201218592 VII. Shenqing patent scope: The π control circuit is applicable to a switching power converter, which is connected to a switch and a transformer-auxiliary coil. The switching control circuit comprises: a circle 1; 5 μΪ: a detection circuit Receiving the number of the auxiliary line from the transformer to output a control signal according to the reflected voltage signal - the circuit 'receiving the control signal' in a first period" - period according to the control a signal to output a determination signal, wherein the second period is continued in the first period; and a pulse width modulation (PWM) circuit outputs a switching signal according to the determination signal. Declaring a switching control circuit according to item 1 of the patent scope, further comprising: a minimum off time circuit 'receiving a feedback signal to generate a minimum off time signal; and taking a J solution '贞 circuit receiving the minimum off time signal and the control a 唬 to generate an unlock signal; D 以 in which 'the minimum off time signal is associated with the feedback signal, and the lock 仏 and the minimum The closed time and the control signal are associated. _ Shi Shen. In the switching control circuit of the second aspect of the patent scope, the 'distance unlocking circuit includes: /, τ number to output a maximum voltage signal-detecting circuit, receiving the control signal; and the limiting circuit 'receiving the minimum off time signal And the maximum power 20 201218592 pressure signal to generate the unlock signal. The most described switching control circuit, wherein the row ratio comparator receives the feedback signal and the -threshold voltage for inversion, and switches the rounding of the first comparator; the output switch 'receives the feedback signal And receiving the second::wheel:= boundary voltage of the first comparator, after the one receiving, switching the first switch and the second switch, and receiving the; - current source and - capacitor, in series Connected to a power supply and a grounded second comparator 'supplied with a common point between the current source and the capacitor' and receives a reference voltage for comparison operation; and - or gate: consumes the second comparator The output 'and receives the switching signal to generate the minimum off time signal. 5. The switching control circuit of claim 1, wherein the valley detecting circuit comprises: a factory switch 'transmitting-resistive coupling the auxiliary line of the transformer to connect when the switch is closed & the reflected voltage 来自 from the resistor; a first current mirror coupled to the switch to convert a first current flowing through the switch to a second current; 21 201218592 to receive the second a current-sampling resistor coupled to the first current mirror and generating a peak voltage signal; and a comparator coupled to the sampling resistor to compare the peak voltage signal with a threshold voltage and outputting the control signal. 6. The switching control circuit of claim 1, wherein the valley locking circuit comprises: eight degrees ten, receiving the control signal for each of the first period and the first period Counting the number of troughs of the reflected voltage signal and generating a data according to the counting result; ▲ a register coupled to the counter to store the data on the number of troughs of the reflected voltage signal in the first period a subtractor coupled to the counter and the register to receive the data of the number of troughs of the reflected voltage signal during the first period (fourth) and the number of troughs of the reflected voltage signal during the first period The data, and a subtraction operation on the data about the number of troughs of the reflected voltage signal in the second period and the trough number 1 of the reflected voltage signal in the first period to generate a Subtracting result data; and an arbitrator 'receiving the subtraction result data to perform arbitration to generate the judgment signal. a switching power converter comprising: a switching switch controlled by a switching signal; a transformer 'having a primary side coil and an auxiliary coil; and a switching control circuit coupled to the switching switch and the transformer The auxiliary coil, wherein the switching control circuit comprises: 22 201218592 - a trough circuit that receives a reflected electric bunker signal from the auxiliary coil of the M device to output a control signal according to the reflected voltage signal. The reflected electric git number is generated by the switching switch being turned off, and the resistor is coupled to the auxiliary coil of the transformer; ^, a valley locking circuit, receiving the control signal to be in a first period and a second The period outputs a determination signal according to the control signal, wherein the second period is continued in the first period; a pulse width modulation (pulm width) circuit coupled to the valley lock circuit to receive the determination signal, and outputting the switching signal to turn on the switch according to the determination signal. Medium 8. Shi Shen. The switching power converter of the invention of claim 7 further includes: a /, - minimum off time circuit 'receiving a feedback signal to generate a shutdown time signal; and 〃 ^ - unlocking circuit' receiving The minimum off time signal and the control to generate an unlock signal; wherein 'the minimum off time signal is associated with the feedback signal, and the unlock signal is associated with the minimum time and the control signal. The power converter of item 8, wherein the unlocking circuit comprises: a detecting circuit that receives the control signal to output a maximum voltage signal; and the limiting circuit 'receives the minimum off time signal and the maximum number to generate The power converter of claim 8, wherein the minimum off-time circuit comprises: a first comparison state, receiving the feedback signal and a threshold voltage for performing Comparing operation; an inverter coupled to the output of the first comparator; - the first switch 'receiving the feedback signal, and receiving the Controlled by the output of a comparator; the first open receiving the threshold voltage and controlled by the output of the first comparator through the inverter; a second switch coupled to the first switch and the second a switch, and controlled by the switching signal; - the current source and the - capacitor 'connected in series between the power source and a ground; - the second comparator has a common point between the current source and the capacitor, and receives a reference voltage And performing a comparison operation; and/or a gate coupled to the output of the second comparator, and receiving the switching signal to generate the minimum off time signal. 11. The power converter according to claim 7 of the patent scope Wherein, the valley detecting circuit comprises: - a switch, the auxiliary coil of the transformer is connected through the electrical switch, and the switching current _ receives the reflected voltage from the resistor and the first current mirror is coupled Connecting the current to a second current; a sampling resistor 'couples to the first switch' to flow through a current mirror of the switch to receive the second current 24 201218592 and generate a peak voltage signal And a comparator coupled to the sampling resistor with a threshold voltage to compare the peak voltage and output the control signal. 13 " 12. As claimed in claim 7 of the power conversion crying, the valley lock circuit comprises: , time T ------ ------ —— Receive the control signal to be in the first cycle with Counting the number of troughs of the reflected voltage signal in each of the second periods to generate a data; a register coupled to the counter to store a valley of the reflected voltage signal in the first period a quantity of data; a subtractor coupled to the counter and the register to receive data about the number of troughs of the reflected voltage signal during the second period and a valley with respect to the reflected voltage signal during the first period a quantity of data and a subtraction operation on the data on the number of troughs of the reflected voltage signal in the second period and the number of troughs of the reflected voltage signal in the first period to generate a subtraction result data; And an arbitrator' receives the subtraction result data to perform arbitration to generate the determination signal. 25