201216334 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種空乏型(depletion type)金屬氧化物半導 體元件之製造方法，特別是指一種具有崩潰防護之空乏型金屬 氧化物半導體元件之製造方法。 【先前技術】 第1圖顯示先前技術之空乏型雙擴散汲極金屬氧化物半 • 導體元件(double diffused drain metal oxide semieonduetor; DDDMOS)剖視圖，如第1圖所示，於p型石夕基板i中形成p 型井區11，以及絕緣結構12以定義元件區，絕緣結構 12例如為區域氧化(i〇cai 〇xidati〇n 〇f仙_，L〇c〇s)結構。 於元件區loo中’形成閘極13、漂移區14、源極15a、沒極 15、P型濃摻雜區16、臨界電壓調整區17。其中，p型井區 11 T為基板1本身，而漂移區14、源極i5a、汲極15、臨界 電壓調整區17係由微f彡技術定義各區域，並分別以離子植入 技術，將N型雜質，以加速離子的形式，植入定義的區域内； P型漠摻雜區16亦由郷技術定義輯，並峰子植入技 術，將P型雜質，以加速離子的形式，植人料的區域内。 其t，源極15a與汲極15分別位於閘極13兩侧下方，漂移 區14位於沒極側且部分位於開極13下方，臨界賴調整區 17部分位於間極13下方，以調整此空乏型金屬氧化物半導 體兀件之臨界電壓，而源極15a與p型濃摻雜區Μ之間，以 絕緣結構12隔開。由於臨界電屢調整區17所推雜之雜 與漂移區14相同，皆為]yj刑 m ” Μ鐾L 為型纽空乏型金屬氧化 物+導體几件知作時，相較於加強型金屬氧化物半導體元 201216334 件，更容易發生崩潰，尤其是在第1圖中’圓形虛線所標示 之範圍，也就是在靠近汲極之閘極邊緣下方，較容易發生能 帶-能帶(band-to-band)崩潰，而降低了崩潰電壓，限制元件的 應用範圍。 第2圖顯示先别技術之空乏型橫向擴散元件(iaterai diffused metal oxide semiconductor，LDMOS)剖視圖，與第 1 圖之先前技術相較，第2圖所顯示之LDMOS另具有本體極 18 ’且其閘極13有一部分位於絕緣結構12上。同樣地，本 圖所顯示之LDMOS於圖中圓形虛線所標示之範圍，亦有與 前述DDDMOS相同的問題，也就是較容易發生能帶_能帶 (band-to-band)崩潰’而降低了崩潰電壓，限制元件的應用範 圍。 第3圖顯示另一種先前技術之空乏型雙擴散汲極金屬氧 化物半導體元件剖視圖，在此稱之為DM〇s，與第丨圖相同， 14種DMOS亦於圖中圓形虛線所標示之範圍，較容易發生能 帶-能帶(band-to-band)崩潰，而降低了崩潰電壓，限制元件的 應用範圍。 以往解決以上問題的方法，是著眼於調整漂移區14、源 極15a、;及才亟15、或臨界電壓調整㊣17的植入濃度或擴散範 圍，但並不能有效解決問題。此因，電路中並不會單獨只有 空乏型金屬氧化物半導體元件，而通常包含加強型金屬氧化 物半導體元件1程上，是先以相_植人參數製作加強型 和二乏型元件的漂移區14、源極15a、與汲極Μ，之後再植 入空乏型元件的臨界電壓調整區17，以將該元件由加強型元 件轉變為空乏型元件。換言之，電路中的加強型和^乏型元 201216334 件，其漂移區14、源極15a、與汲極15之參數是共用的，如 ，調整空乏型元件的參數，將影響加強型元件的效能。所以， 就製作空乏型元件而言，唯—能夠調整的是臨界電壓調整區 17的植人參數’但臨界電壓調整區17的濃度勢必不能太低， 否則無法將加強型元件轉變為空乏型元件。因此，在以上限 制下，先刚技術無法前述解決能帶_能帶崩潰的問題。 有鑑於此，本發明即針對上述先前技術之不足，提出一種 空乏型金屬氧化物半賴元件之製造方法，可麟元件操作之 崩潰電壓，增加元件的應用範圍。 〃 【發明内容】 本發明目的在提供一種空乏型金屬氧化物半導體元件之 製造方法。 ^為達上述之目的，本發明提供了一種空乏型金屬氧化物 半導體元件之製造方法，包含··提供一基板，並於該基板中 形成第一導電型井區以及一絕緣結構以定義元件區；於該元 件區中分別定義漂移區、源極、沒極、與臨界電壓調整區，並 分別植入第二導電型雜質，以形成該漂移區、源極、汲極、與 臨界電壓調整區；於該元件區中汲極與臨界電壓調整區之間定 義崩潰防護區，並植入第一導電型雜質，以形成該崩潰防護 區；以及於該元件區中形成一閘極；其中，該崩潰防護區部 分位於閘極下方，且其範圍包含臨界電壓調整區靠近汲極側 之邊緣。 在其中一種實施型態中，該第一導電型為p型，且第二 導電型為N型。而在另一種實施型癌中，該第一導電型為n 型，且第二導電型為P型。 201216334 在其中一種實施型態中，該絕緣結構可為一區域氧化結 構或一淺溝槽絕緣(shallow trench isolation，STI)結構。 上述空乏型金屬氧化物半導體元件之製造方法中，該崩 潰防護區之定義，可由一專屬之光罩定義。 在其中一種實施型態中，該崩潰防護區之定義，亦可由 一第一導電型輕摻雜汲極光罩定義，該第一導電型輕摻雜汲 極光罩同時定義位於同一基板上之另一相反傳導型態金屬氧 化物半導體元件之第一導電型輕摻雜汲極區域。 在另一種實施型態中，該崩潰防護區之定義，亦可由一 第一導電型反穿隧效應光罩定義，該第一導電型反穿隧效應 光罩同時定義位於同一基板上之另一相反傳導型態金屬氧化 物半導體元件之第一導電型反穿隧效應區域。 在另一種實施型態中’該空乏型金屬氧化物半導體元件 為一雙擴散汲極金屬氧化物半導體元件(d〇uble diffilsed drain metal oxide semieGnductor，DDDM0S)或一橫向擴散元件 (lateral diffused metal oxide semiconductor, LDMOS) ° 底下藉由具體實施例詳加說明，當更容易瞭解本發明之 目的、技術内容、特點及其所達成之功效。 【實施方式】 本發明中_式觸示意，主要意絲示製程步驟以及各 層之間之上下次賴係，至於形狀、厚度與寬制並未依照比 例繪製。 請，閱第4A-4D之剖面流麵，顯示本發明的—個實施 例’本實施觸示—種空乏型雙擴散汲極金屬氧化物半導體 兀件1〇之製造方法。如第4A圖所示，首先提供—基板卜 201216334 例如但不限於為P型或NS矽基板，接著於基板丨中形成第 一導電型井區11與絕緣結構12，以定義元件區1〇〇，如本 圖所示，元件區100定義於絕緣結構12之間，絕緣結構12 可以為區域氧化（LOCOS)或淺溝槽絕緣（STI)製程技術 所形成’在本實施例中，絕緣結構12例如為L0C0S結構。 另外’第一導電型井區11可為但不限於基板1本身，亦可 由微影技術所定義，並由離子植入技術將第一導電型雜質摻 雜至所定義之區域形成。接下來，如第4B圖所示，於元件 區100中形成漂移區14、源極15a、汲極15、第一導電型濃 摻雜區16、臨界電壓調整區π。其中，漂移區14、源極15a、 汲極15、臨界電壓調整區17係由微影技術定義各區域，並 以離子植入技術，將第二導電型雜質，例如但不限於為N型 雜質，以加速離子的形式，如圖中虛線箭號所示意，分別植 入定義的區域内；第一導電型濃摻雜區16亦由微影技術定義 區域’並以離子植入技術，將第一導電型雜質，例如但不限 於為P型雜質，以加速離子的形式，植入定義的區域内。其 中，源極15a與汲極15分別位於閘極13兩侧，漂移區14 位於汲極側且部分位於閘極13下方，臨界電壓調整區17部 分位於閘極13下方’以調整此空乏型金屬氧化物半導體元件 之臨界電壓，而源極15a與第一導電型濃摻雜區16之間，以 絕緣結構12隔開。 接下來，如第4C圖所示，與先前技術不同的是，本實 施例增加形成崩潰防護區19，其方式如第4C圖中虛線箭號 所示意，以離子植入技術，將第一導電型雜質，例如但不限 於為P型雜質，以加速離子的形式，植入定義的區域内；崩 潰防護區19的範圍宜包含臨界電壓調整區π靠近沒極15側 201216334 之邊緣。由於崩潰防護區19所植人的雜f與漂移區i4、沒 極15、和臨界電壓調整區17的傳導型態相反，因此可提 崩潰電壓。減_是，雖然在驗防龍^巾植入第二 2型雜質，、但整體it件仍為空乏型树，亦即崩潰防護區 疋呈現較淡的第二導電型態。崩潰防護區D的範圍可利 用專屬光罩定義，不過錄方式是共用基板丨上其他元 2之光罩，搭配該其他元件之製程步驟來一併完成，以節 錢程步驟減罩成本；適合利絲作為崩餘護區19之 共用光罩與製程步驟將於後詳述。 再，下來，如第4D圖所示，於元件區1〇〇中形成問極 ，即元成了空乏型雙擴散汲極金魏化物轉體元件1〇; 其中’閘極13的形成方式與材質有各種作法，為本技術者 所熟知，因非本案重點，故不予贅述。 第5 _示本發_第二實施例，本實施例顯示本發明 應用於空乏型橫向擴散金屬氧化物半導體元件之剖面圖，其 =造方式與第-實施例類似，於本實施例中，崩潰防護區 19|巳圍職包含臨界碰罐區π靠近汲極15側之邊緣， 但其位於閘極13下方，與絕緣結構12交界處。 第6 _示本發明的第三實施例，本實施例顯示本發明 …用於空乏型DM0S元件之剖面圖，其製造方式與第一實 ，例類似，於本實施例t，崩潰防護區19範圍同樣包含臨 界電壓調整區17靠近汲極15側之邊緣。 第7圖顯示本發韻第四實補，本實施繼示在同一 基板1上除製作空乏型雙擴散沒極金屬氧化物半導體元件ι〇 =外’也在另—元件區· t製作另—相反傳導型態的金屬 b物半導體元件20，此元件例如但不限於為圖示的加強型 201216334 南壓兀件’亦可為低壓元件或空乏型元件。由於其為相反傳導 型態的金屬氧化物半導體元件2〇,因此會形成相反傳導变態 =源極25a與沒極25,且通常需要形成輕摻雜區阶。因此， 空乏型疋件10的崩潰防護區I9，便可利用該相反傳導型態 的元件20形成輕摻雜區19a時所使用的第一導電型輕推雜汲 極光罩，來作為共用光罩，打開崩潰防護區19之定義範圍， 並f形成輕摻雜區19a的同一步驟中，將第一導電型雜質植 =崩凊防漢區19,以達成本發明的目的。除使職反傳導型 ,。7〇件的轉雜極光罩外，類似地’亦刊用在同一基板 之金屬氧化物半導體元件之第—導電型反穿隧效應 别g你^為形成崩潰防護區19的共用光罩，該第一導電 光罩同時定義空乏型元件1G關潰防護區 的第、位於同—基板上之另-金屬氧化物半導體元件 的第一導電型反穿隧效應區域。 以上已針對較佳實施例來 =熟悉本技術者易於了解本發明二== 技:可發明之權利㈣。在本發明之相同精神下，熟米本 特性下，可加人其他製程步 要的 微影技術並不限於光罩技術，亦可 明的制雜蓋上歧杨_效=桃磁術。本發 【圖式簡單說明】 =«㈣____峨⑽彻元件剖 第2圖顯錢前技術之橫⑽散元件剖視圖。 201216334 第3圖顯示另一種先前技術之雙擴散汲極金屬氧化物半導體 元件剖視圖。 第4A-4D之剖面流程圖，顯示本發明的第一實施例。 第5圖顯示本發明的第二實施例。 第6圖顯示本發明的第三實施例。 第7圖顯示本發明的第四實施例。 【主要元件符號說明】 1基板 10空乏型金屬氧化物半導體 元件 11第一導電型井區 12絕緣結構 13閘極 14漂移區 15汲極 15a源極 16第一導電型雜質濃摻雜區 17臨界電壓調整區 19崩潰防護區 19a輕摻雜區 20另一金屬氧化物半導體元 件 25汲極 25a源極 100, 200元件區201216334 VI. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing a depletion type metal oxide semiconductor device, and more particularly to the manufacture of a depleted metal oxide semiconductor device having collapse protection method. [Prior Art] Fig. 1 is a cross-sectional view showing a double diffused drain metal oxide semi-dane (DDDMOS) of the prior art, as shown in Fig. 1, on a p-type slab substrate i A p-type well region 11 is formed, and an insulating structure 12 is defined to define an element region, and the insulating structure 12 is, for example, a region oxide (i〇cai 〇xidati〇n 〇f仙_, L〇c〇s) structure. In the element region loo', a gate 13, a drift region 14, a source 15a, a gate 15, a P-type heavily doped region 16, and a threshold voltage adjustment region 17 are formed. Wherein, the p-type well region 11 T is the substrate 1 itself, and the drift region 14, the source electrode i5a, the drain electrode 15, and the threshold voltage adjustment region 17 are defined by micro-f彡 technology, and respectively, by ion implantation technology, N-type impurities, in the form of accelerated ions, are implanted in defined regions; P-type desert-doped regions 16 are also defined by 郷 technology, and peak-implantation techniques are used to implant P-type impurities in the form of accelerated ions. Within the area of the material. The source 15a and the drain 15 are respectively located below the two sides of the gate 13. The drift region 14 is located on the non-polar side and partially below the open electrode 13. The critical adjustment region 17 is located below the interpole 13 to adjust the deficiency. The threshold voltage of the metal-oxide-semiconductor element is separated from the source-type 15a and the p-type heavily doped region by an insulating structure 12. Since the hybrid of the critical electric-adjustment zone 17 is the same as the drift zone 14, the yj is m Μ鐾 L is a type of vacant metal oxide + conductor, compared to the reinforced metal. The oxide semiconductor element 201216334 is more prone to collapse, especially in the range indicated by the circular dashed line in Fig. 1, that is, below the gate edge near the drain, the band-band (band) is more likely to occur. -to-band) crashes, reducing the breakdown voltage and limiting the application range of the component. Figure 2 shows a cross-sectional view of the iaterai diffused metal oxide semiconductor (LDMOS) of the prior art, and the prior art of Figure 1. In contrast, the LDMOS shown in FIG. 2 has a body pole 18' and a portion of the gate 13 is located on the insulating structure 12. Similarly, the LDMOS shown in the figure is in the range indicated by the circular dotted line in the figure. There is the same problem as the aforementioned DDDMOS, that is, the band-to-band collapse is more likely to occur, and the breakdown voltage is lowered to limit the application range of the component. Fig. 3 shows another prior art depletion type. double A cross-sectional view of a diffused drain metal oxide semiconductor device, referred to herein as DM〇s, is the same as in the first diagram, and 14 DMOSs are also within the range indicated by a circular dashed line in the figure, and the band-energy band is more likely to occur. -to-band) crashes, lowering the breakdown voltage and limiting the application range of the component. In the past, the method to solve the above problem was to adjust the drift region 14, the source 15a, and the threshold 15, or the threshold voltage adjustment. Implant concentration or diffusion range, but it can not effectively solve the problem. The reason is that the circuit does not have only the depleted metal oxide semiconductor component alone, but usually contains the reinforced metal oxide semiconductor device. Phase _ implant parameters make the drift region 14, the source 15a, and the drain Μ of the reinforced and the two-depleted components, and then implant the threshold voltage adjustment region 17 of the depletion element to transform the component from the reinforced component It is a depleted component. In other words, the enhanced type and the missing element 201216334 in the circuit have the parameters of the drift region 14, the source 15a, and the drain 15 being shared, for example, adjusting the parameters of the depleted component, The efficiency of the reinforced component. Therefore, in terms of making the vacant component, only the implant parameter of the threshold voltage adjustment region 17 can be adjusted 'but the concentration of the threshold voltage adjustment region 17 must not be too low, otherwise the enhanced type cannot be used. The component is transformed into a depleted component. Therefore, under the above limitation, the prior art cannot solve the problem that the band-capacity collapses. In view of this, the present invention is directed to the above-mentioned deficiencies of the prior art, and proposes a depleted metal oxide. The manufacturing method of the semi-relay element can reduce the breakdown voltage of the operation of the component, and increase the application range of the component. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a depleted metal oxide semiconductor device. In order to achieve the above object, the present invention provides a method for fabricating a depleted metal oxide semiconductor device, comprising: providing a substrate, and forming a first conductive type well region and an insulating structure in the substrate to define an element region The drift region, the source, the immersion, and the threshold voltage adjustment region are respectively defined in the device region, and the second conductivity type impurity is implanted respectively to form the drift region, the source, the drain, and the threshold voltage adjustment region. Defining a collapse protection zone between the drain and the threshold voltage adjustment region in the component region, and implanting a first conductivity type impurity to form the breakdown protection region; and forming a gate in the device region; wherein The crash protection zone is partially below the gate and its range contains the edge of the threshold voltage adjustment zone near the drain side. In one embodiment, the first conductivity type is p-type and the second conductivity type is N-type. In another embodiment of the invention, the first conductivity type is an n-type and the second conductivity type is a P-type. 201216334 In one embodiment, the insulating structure can be a regional oxide structure or a shallow trench isolation (STI) structure. In the above method for manufacturing a depleted metal oxide semiconductor device, the definition of the collapse protection region can be defined by a dedicated photomask. In one embodiment, the definition of the crash protection zone may also be defined by a first conductivity type lightly doped yttrium reticle, which simultaneously defines another one on the same substrate. The first conductivity type lightly doped drain region of the opposite conduction type metal oxide semiconductor device. In another embodiment, the definition of the crash protection zone may also be defined by a first conductivity type anti-through tunneling mask, which simultaneously defines another one on the same substrate. The first conductivity type reverse tunneling effect region of the opposite conduction type metal oxide semiconductor device. In another embodiment, the depleted metal oxide semiconductor device is a double diffused metal oxide semiconductor device (DDDM0S) or a lateral diffused metal oxide semiconductor. , LDMOS) ° The details of the present invention, the technical contents, the features and the effects achieved by the present invention are more readily understood by the specific embodiments. [Embodiment] In the present invention, the singularity of the touch is mainly indicated by the process steps and the next step between the layers, and the shape, thickness and width are not drawn according to the ratio. Referring to the cross-sectional flow planes of Figs. 4A-4D, an embodiment of the present invention is shown, which is a method of manufacturing a depleted double-diffused-dip metal oxide semiconductor device. As shown in FIG. 4A, first, the substrate 10216334 is provided, for example, but not limited to, a P-type or NS-based substrate, and then the first conductive type well region 11 and the insulating structure 12 are formed in the substrate , to define the element region 1〇〇. As shown in the figure, the element region 100 is defined between the insulating structures 12, and the insulating structure 12 may be formed by a region oxidation (LOCOS) or shallow trench isolation (STI) process technology. In this embodiment, the insulating structure 12 For example, it is a L0C0S structure. Further, the first conductive type well region 11 may be, but not limited to, the substrate 1 itself, or may be defined by lithography, and may be doped by ion implantation techniques to dope the first conductivity type impurity to a defined region. Next, as shown in Fig. 4B, a drift region 14, a source 15a, a drain 15, a first conductive type heavily doped region 16, and a threshold voltage adjustment region π are formed in the element region 100. The drift region 14, the source 15a, the drain 15 and the threshold voltage adjustment region 17 are defined by lithography techniques, and the second conductivity type impurity, such as but not limited to an N-type impurity, is ion-implanted. In the form of accelerating ions, as indicated by the dotted arrows in the figure, they are respectively implanted into the defined regions; the first conductive type heavily doped region 16 is also defined by the lithography technique and is implanted by ion implantation technology. A conductive impurity, such as, but not limited to, a P-type impurity, is implanted in a defined region in the form of an accelerated ion. Wherein, the source 15a and the drain 15 are respectively located on both sides of the gate 13, the drift region 14 is located on the drain side and partially under the gate 13, and the threshold voltage adjustment region 17 is partially located below the gate 13 to adjust the depleted metal. The threshold voltage of the oxide semiconductor device is separated from the first conductive type heavily doped region 16 by the insulating structure 12. Next, as shown in FIG. 4C, unlike the prior art, the present embodiment increases the formation of the collapse protection zone 19 in the manner indicated by the dashed arrow in FIG. 4C, and the first conductivity is performed by ion implantation technology. Type impurities, such as, but not limited to, P-type impurities, are implanted in defined regions in the form of accelerated ions; the extent of the collapse protection zone 19 preferably includes a threshold voltage adjustment region π near the edge of the no-pole 15 side 201216334. Since the impurity f implanted in the collapse protection zone 19 is opposite to the conduction pattern of the drift zone i4, the gate 15, and the threshold voltage adjustment zone 17, the breakdown voltage can be raised. Less _ Yes, although the second type 2 impurity is implanted in the tamper-proof towel, the overall piece is still a deficient tree, that is, the collapse protection zone 疋 exhibits a lighter second conductivity type. The scope of the crash protection zone D can be defined by a dedicated mask, but the recording mode is the mask of the other element 2 on the common substrate, and the process steps of the other components are completed together, and the cost is reduced by the step of saving the money; The common reticle and process steps of the wire as the containment zone 19 will be detailed later. Then, as shown in Fig. 4D, a question pole is formed in the element region 1〇〇, that is, the element becomes a depletion type double-diffused bismuth gold-Wide-transfer element 1〇; wherein the formation of the gate 13 is There are various methods of material, which are well known to the skilled person. Because it is not the focus of this case, it will not be repeated. The present invention shows a cross-sectional view of the present invention applied to a depleted laterally diffused metal oxide semiconductor device, which is similar to the first embodiment in the present embodiment. The collapse protection zone 19|巳 includes the edge of the critical bumper zone π near the side of the drain 15 but is located below the gate 13 at the interface with the insulating structure 12. 6 shows a third embodiment of the present invention, and this embodiment shows a cross-sectional view of the present invention for a depletion type DMOS element, which is manufactured in a manner similar to that of the first embodiment, in the present embodiment t, the crash protection zone 19 The range also includes the edge of the threshold voltage adjustment region 17 near the side of the drain 15 . Fig. 7 shows the fourth real complement of the present rhyme, and the present embodiment is shown on the same substrate 1 except that the depletion type double-diffused metal-oxide-semiconductor element ι〇= is also used in the other-component area. The oppositely conductive metal element semiconductor element 20, such as, but not limited to, the reinforced type 201216334, which is illustrated as a low voltage element or a depleted element. Since it is an oppositely-conducting metal oxide semiconductor device 2, an opposite conduction metamorphosis = source 25a and no-pole 25 is formed, and it is usually necessary to form a lightly doped region. Therefore, the collapse protection zone I9 of the depletion element 10 can be used as the common mask by using the opposite conductivity type element 20 to form the light-doped region 19a. In the same step of opening the definition of the collapse protection zone 19 and f forming the lightly doped region 19a, the first conductivity type impurity is implanted = the collapse prevention zone 19 to achieve the object of the present invention. In addition to the occupational anti-conduction type. In addition to the 7-piece turned-on-pole mask, the same type of conductive-type tunneling effect of the metal-oxide-semiconductor element used in the same substrate is also known as the common mask for forming the collapse protection zone 19. The first conductive mask simultaneously defines a first conductivity type anti- tunneling effect region of the other metal-oxide-semiconductor element on the same substrate as the first protection region of the depletion element 1G. The above has been directed to the preferred embodiment = those skilled in the art will readily appreciate that the present invention is two == technology: the inventable right (four). Under the same spirit of the present invention, under the characteristics of cooked rice, the lithography technique that can be added to other processes is not limited to the reticle technology, and it is also possible to make a miscellaneous _ effect = peach magnetism.本发 [Simple description of the diagram] = «(4) ____ 峨 (10) section cross-section of the component Figure 2 shows a cross-sectional view of the horizontal (10) component of the pre-money technique. 201216334 Figure 3 shows a cross-sectional view of another prior art double diffused drain metal oxide semiconductor device. A cross-sectional flow chart of Figures 4A-4D shows a first embodiment of the present invention. Fig. 5 shows a second embodiment of the present invention. Fig. 6 shows a third embodiment of the present invention. Fig. 7 shows a fourth embodiment of the present invention. [Major component symbol description] 1 substrate 10 depletion metal oxide semiconductor device 11 first conductivity type well region 12 insulation structure 13 gate 14 drift region 15 drain 15a source 16 first conductivity type impurity concentrated doping region 17 critical Voltage adjustment region 19 collapse protection region 19a lightly doped region 20 another metal oxide semiconductor device 25 drain 25a source 100, 200 element region