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TW201212200A - Semiconductor component and method of manufacture - Google Patents

Semiconductor component and method of manufacture Download PDF

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Publication number
TW201212200A
TW201212200A TW100121480A TW100121480A TW201212200A TW 201212200 A TW201212200 A TW 201212200A TW 100121480 A TW100121480 A TW 100121480A TW 100121480 A TW100121480 A TW 100121480A TW 201212200 A TW201212200 A TW 201212200A
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
electrical connector
bonding
pad
semiconductor
Prior art date
Application number
TW100121480A
Other languages
Chinese (zh)
Other versions
TWI532143B (en
Inventor
Shutesh Krishnan
Soon Wei Wang
Original Assignee
Semiconductor Components Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Components Ind filed Critical Semiconductor Components Ind
Publication of TW201212200A publication Critical patent/TW201212200A/en
Application granted granted Critical
Publication of TWI532143B publication Critical patent/TWI532143B/en

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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes stacked semiconductor die. In accordance with embodiments, the semiconductor component includes a substrate having a component receiving area and a plurality of bond pads. A semiconductor chip is attached to the component receiving area. An electrical connector is coupled to the semiconductor chip and the substrate. A second semiconductor chip is mounted or attached to one of the ends of the electrical connector such that this end is positioned between the semiconductor chips. A second electrical connector is coupled between the second semiconductor chip and the substrate. A third semiconductor chip is mounted over or attached to the second electrical connector such that a portion is between the second and third semiconductor chips.

Description

201212200 六、發明說明： 【發明所屬之技術領域】 本發明大體上係關於電子器件，且更特定言之係關於半 導體晶粒封裝及用於封裝半導體晶粒之方法。 【先前技術】 在過去，半導體工業使用各種封裝組態以增加一系統中 的半導體晶粒之封裝密度。對於電子裝置之所增加需求增 加了更小、更輕且又更多功能的半導體裝置之需求且導致 具有增加的半導體封裝密度與更小的輪廓及安裝覆蓋區之 半導體封裝之一需求。在一些實施例中，半導體晶粒以附 接至該半導體晶粒之黏著劑之一插入層垂直堆疊於彼此之 頂部上以將邊半導體晶粒搞合在一起^晶粒附接至一玻璃 環氧類型印刷電路板基板或其他類似基板。接著該半導體 晶粒線接合至該基板以在該基板與該半導體晶粒之間形成 電互連》此一封裝組態之一實例係揭示於在2003年丨丨月i 8 日頒予Thomas B. Glenn等人之美國專利第6,650,019號 中。具有經堆疊積體電路晶粒之一電子總成之另一實例係 揭示於在2006年4月18日頒予Todd P. 〇man之美國專利第 7,〇30,317號中。 因此’具有一半導體組件及堆疊半導體晶粒以製造該半 導體組件而沒有增加該半導體組件之覆蓋區之方法係有利 的。其將進一步有利於具有成本效益及時間效應而實施該 半導體組件及方法。 【發明内容】 156577.doc 201212200 在-實施例中，-半導體組件包括具有—組件承接區域 及複數個接合塾之-基板；具有第一表面及第二表面之一 第一半導體晶片，該第—半導體晶片之該第一表面輕合至 該組件承接區域；具有第—端及第n第-電連接 器’該第一端鄰近於該第-半導體晶片之該第二表面；且 有第一表面及第二表面之一第二半導體晶片，該第二半導 體晶片之該第一表面輕合至該第—電連接器之該第—端， 其中該第-導電體之該第一端係定位於該第一半導體晶片 與該第二半導體晶片之間；具有第-端及第二端之一第二 電連接器’該第二電連接器之該第一端鄰近於該第二半導 體晶片之該第二表面；及具有第一表面及第二表面之一第 三半導體晶片’該第三半導體晶片之該第一表面輕合至該 第二電連接器之該第一端，纟中該第二電連接器之該第一 端係在該第二半導體晶片與該第三半導體晶片之間。 、在另-實施例中，一半導體組件包括具有一晶片承接區 域及複數個接合塾之-基板；輕合至該晶片承接區域之一 第-半導體晶片，該第一半導體晶片具有第一表面及第二 表面’其中該第二表面包含一閘極接點及一源極接點；一 第一電連接器’其糕合於該第一半導體晶片之該第二表面 與該複數個接合墊之一第一接合墊之間；耦合至該第一電 連接器之一第二半導體晶片，該第二半導體晶片具有第一 表面及第二表面，其中該第二半導體晶片之該第二表面包 含一閘極接點及一源極接點；及一第二電連接器，其耦合 於該第一半導體晶片之該閘極接點與該複數個接合墊之一 156577.doc201212200 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to electronic devices, and more particularly to semiconductor die packages and methods for packaging semiconductor dies. [Prior Art] In the past, the semiconductor industry used various package configurations to increase the packing density of semiconductor dies in a system. The increased demand for electronic devices has increased the need for smaller, lighter, and more functional semiconductor devices and has led to a need for semiconductor packages with increased semiconductor package density and smaller profile and mounting footprint. In some embodiments, the semiconductor die is vertically stacked on top of each other with one of the adhesives attached to the semiconductor die to bond the edge semiconductor die together ^ die attach to a glass ring An oxygen type printed circuit board substrate or other similar substrate. The semiconductor die is then bonded to the substrate to form an electrical interconnection between the substrate and the semiconductor die. An example of such a package configuration is disclosed in Thomas B on May 8th, 2003. U.S. Patent No. 6,650,019 to Glenn et al. Another example of an electron assembly having a stacked integrated circuit die is disclosed in U.S. Patent No. 7, 30,317, issued to Todd. Therefore, a method of having a semiconductor component and stacking semiconductor dies to fabricate the semiconductor component without increasing the footprint of the semiconductor component is advantageous. It will further facilitate the implementation of the semiconductor component and method with cost effectiveness and time effects. [Invention] 156577.doc 201212200 In an embodiment, the semiconductor component includes a substrate having a component receiving region and a plurality of bonding pads, and a first semiconductor wafer having a first surface and a second surface, the first The first surface of the semiconductor wafer is lightly coupled to the component receiving region; having a first end and an nth first electrical connector 'the first end adjacent to the second surface of the first semiconductor wafer; and having a first surface And a second semiconductor wafer of the second surface, the first surface of the second semiconductor wafer is lightly coupled to the first end of the first electrical connector, wherein the first end of the first electrical conductor is positioned at Between the first semiconductor wafer and the second semiconductor wafer; having a first end and a second end, the second electrical connector, the first end of the second electrical connector being adjacent to the second semiconductor wafer a second surface; and a third semiconductor wafer having a first surface and a second surface; the first surface of the third semiconductor wafer is lightly coupled to the first end of the second electrical connector, the second The first end of the electrical connector Between the second semiconductor wafer and the third semiconductor wafer. In another embodiment, a semiconductor component includes a substrate having a wafer receiving region and a plurality of bonding pads, and a first semiconductor wafer that is lightly coupled to the wafer receiving region, the first semiconductor wafer having a first surface and a second surface ′, wherein the second surface comprises a gate contact and a source contact; a first electrical connector lands on the second surface of the first semiconductor wafer and the plurality of bonding pads Between a first bonding pad; a second semiconductor wafer coupled to the first electrical connector, the second semiconductor wafer having a first surface and a second surface, wherein the second surface of the second semiconductor wafer comprises a a gate contact and a source contact; and a second electrical connector coupled to the gate contact of the first semiconductor wafer and one of the plurality of bond pads 156577.doc

201212200 第-接合塾之間’及—第三電連接器’其麵合於該源極接 點及該第一電連接器之間。 在另-實施例中…種用於製造—半導體組件之方法包 括提供具有一組件承接區域及複數個接合墊之一支撐結 構；將-第-半導體晶合至該支#結構之該組件承接 區域，該第一半導體晶片具有第一接合墊及第二接合墊； 將該第#導體晶片之該第一接合塾電麵合至該複數個接 合墊之一第一接合墊且將該第一半導體晶片之該第二接合 墊電耦合至該複數個接合墊之至少一第二接合墊；以一第 一電連接器將該第一半導體晶片耦合至該複數個接合墊之 一第三接合墊·’將一第二半導體晶片耦合至該第一電連接 益，該第二半導體晶片具有一第一接合墊及一第二接合 墊，及將該第二半導體晶片之該第一接合墊電耦合至該複 數個接合墊之一第四接合墊，將該第二半導體晶片之該第 二接合墊電耦合至該複數個接合墊之至少一第五接合墊， 及以一第二電連接器將該第二半導體晶片耦合至該複數個 接合墊之一第六接合墊。 【實施方式】 將從結合附圖閱讀以下詳細描述而更好地理解本發明， 其中相同參考符號指明相同元件。 一般而言’本發明提供一種半導體組件及一種用於製造 該半導體組件.之方法。根據本發明之實施例，一半導體組 件包括具有一組件承接區域及複數個接合墊之一基板。_ 半導體晶片48係附接至該組件承接區域丨8。具有若干端或 156577.doc 201212200 接觸區帶64及68之一電連接器62係耦合至半導體晶片48及 基板12。一半導體晶片78係安裝或附接至電連接器62之端 64使得端64係定位於半導體晶片48與半導體晶片78之間。 具有若干端或接觸區帶94及98之一電連接器92係耦合至半 導體晶片78與基板12。一半導體晶片118係安裝於端94之 上或附接至端94使得端94係在半導體晶片78與半導體晶片 118之間。 圖1係根據本發明之實施例之在製造之一早期階段之一 半導體組件10之一部分之一俯視圖。圖1中展示一支撐結 構12，例如’諸如一印刷電路板，其具有一表面14、一組 件承接區域18、形成於組件承接區域18的一部分之一組件 接觸結構19、若干接合墊組2〇、22、24及26、若干接合墊 組28、30、32及34及接合墊36、38、40及42。接合墊組20 包括接合墊20g&接合墊2〇s ;接合墊組22包括接合墊22g 及接合墊22s ;接合墊組24包括接合墊24g&接合墊24s ;且 接合墊組26包括接合墊26(5及接合墊26s。同樣地，接合墊 組28包括接合墊28g及接合墊28§ ;接合墊組儿包括接合墊 3〇g及接合墊30s ;接合墊組32包括接合墊32g及接合墊 32s ;且接合墊組34包括接合墊34〇及接合墊34s。此外，在 接合墊組20與28之間形成接合墊36，在接合墊組22與3〇之 間形成接合墊38，在接合墊組24與32之間形成接合墊⑽， 且在接合墊組26與34之間形成接合墊42。舉 極電極之接合墊且可稱為閉極接合墊或閘極墊；接合墊 156577.doc 201212200 20s、22s、24s、26s、28s、30s、328及345充當用於源極電 極之接合墊且可稱為源極接合墊或源極墊；且接合塾％、 38、40及42充當用於汲極電極之接合墊且可稱為汲極接合 墊或汲極墊。應注意，基板12具有相對主表面14及16，其 中表面16展示於圖3中。 組件接觸結構19、接合墊組20、22、24、26、28、30、 32及34及接合墊36、38、40及42可由包含一層或多層之一 導電材料之金屬化系統組成。用於組件接觸結構丨9、接合 墊組20至34及接合墊％至π之金屬化系統之合適金屬包含 銅、銘、铭合金、其等之組合或類似物。或者，支擇結構 12可為一引線框、一陶瓷基板、包括一樹脂（諸如環氧、 聚醯亞胺、三嗪，或酚醛樹脂、·環氧玻璃複合物）之一結 構或類似物。支撐基板12上的接合墊之佈局或定位不為本 發明之實施例之一限制。 一組件（例如，諸如具有相對表面49及5 1(展示於圖3中） 之一半導體晶片48)安裝至組件承接區域18中的組件接觸 結構19。半導體晶片48可使用焊料、一導電膏、傳導膜或 類似物而附接至組件接觸結構19。表面49及51係在半導體 晶片48之相對側上。當耦合至组件接觸結構19之該組件為 一半導體晶片時，組件承接區域18可稱為一半導體晶片承 接區域或一晶片承接區域。半導體晶片48具有充當一閘極 接點之閘極接合墊50及充當一源極接點之一源極接合墊 52 °閑極接合墊5〇係藉由一接合線54連接至閘極接合塾 2〇G且源極接合墊52係藉由對應的接合線56連接至源極接 156577.doc 201212200 合墊2〇s。儘管展示複數個接合線％及展示三個源極接合 墊20S ’但是接合線56之數量及源極接合墊2〇s之數量不為 本發明之限制。可有一個、兩個或更多個接合線％及一 個、兩個、三個或更多個接合墊2〇s。應注意，如整個應 用所使用之術語接合線亦可稱為線接合或接合線。 圖2係圖1中所示之但在製造之一稍後階段之一半導體組 件10之一等角視圖。圖3係沿著圖2之剖面線3至3截取之半 導體組件1〇之一截面圖》為了簡潔起見，將—起描述圖2 及圖3。如參考圖1所討論，閘極接點5〇係藉由一接合線η 連接至接合墊20G且源極接點52係藉由接合線56連接至接 合墊20s。具有端64及68及一中心區帶66之一電連接器62 將源極電極52耦合至支撐結構12之接合墊4〇。端以可稱為 插入物區帶’此係因為其可定位於至少兩個半導體日片 之間’亦即，一半導體晶片可定位於插入物區帶64之下且 另一半導體晶片可定位於插入物區帶64之上。電連接号& 可為一夾子、一線、一帶（例如，諸如一鋁帶）或類似物。 端68係透過（例如）一焊料層71接合至接合墊4〇且插入物區 帶64可藉由一電絕緣材料之一層63連接至半導體晶片48。 介電質材料63之合適實例包含一陶瓷材料、熱界面材料、 導熱膜、氧化層、氮化矽層、氧化鋁或類似物。端68可稱 為一接觸區帶，此係因為其使得與接合墊40電接觸。舉例 而s ’插入物區帶64為一矩形形狀區帶。用於電連接器a 之合適材料包含銅、铭、金屬及塗覆有一貴金屬之金屬人 金連接器、錫、鋼、銅合金、鈹、金、銀' 鋁合金、黃 156577.doc -10- 201212200 銅、黃銅合金或類似物。 圖3繪不半導體晶片48係透過一導電且導熱晶粒附接材 料60連接至組件接觸結構19。合適晶粒附接材料包含焊 料傳導膏 傳導膜或類似物。表面51接觸晶粒附接 材料60。舉例而言’半導體晶片佩括—絶緣閘極半導體 裝置，其中表面51充當—汲極接點。因此，該汲極接點接 觸晶粒附接材料6G 1極接合墊50及源極接合塾52係形成 於表面49上或由表面49形成。 圖3進一步繪示支撐結構12，其具有形成於表面14上或 由表面14形成之源極接合墊2〇s、24广28s及32s及汲極接 合墊36及40及連接至導熱體21之組件接觸結構19，該導熱 體自組件接觸結構19延伸至表面16。導熱體21適於移除來 自女裝於組件接觸結構19上或安裝高於組件接觸結構〗9之 組件之熱。 圖4係在製造之一稍後階段之圖2及圖3之半導體組件ι〇 之一等角視圖。圖5係沿著圖4之剖面線5至5截取之半導體 組件10之一截面圖及圖6係沿著圖4之剖面線6至6截取之半 導體組件10之一截面圖。為了簡潔起見，將一起描述圖4 至圖6。圖4中展示安裝至電連接器62之具有相對表面乃及 81之一半導體晶片78。半導體晶片78係透過一導電晶粒附 接材料83連接至插入物區帶64。合適晶粒附接材料包含焊 料、一傳導膏、一傳導膜或類似物。晶粒附接材料83可與 晶粒附接材料60相同。半導體晶片78具有充當一閘極接點 之一閘極接合墊80及充當一源極接點之一源極接合墊82。 156577.doc -11 - 201212200 閘極接點80係藉由一接合線84連接至閘極接合墊22g且源 極接點82係藉由對應接合線86連接至源極接合墊22s。儘 管展示複數個接合線86及展示三個源極接合墊22s，但是 接合線86之數量及源極接合墊223之數量不為本發明之限 制。可有一個、兩個或更多個接合線86及一個、兩個、三 個或更多個接合塑· 22s。 具有端94及98及一中心區帶96之一電連接器92將源極電 極82連接至支撐結構12之接合墊36。端94可稱為一插入物 區帶，此係因為其可定位於至少兩個半導體晶片之間，亦 即’ 一半導體晶片可定位於插入物區帶94之下且另一半導 體晶片可定位於插入物區帶94之上。電連接器％可為一爽 子、一線、一帶（例如，諸如一鋁帶）或類似物。端98係透 過（例如）一焊料層71接合至接合墊36且插入物區帶94可藉 由一層介電質材料104連接至半導體晶片78。介電質材料 104之合適實例包含一陶瓷材料、熱界面材料、導熱膜、 氧化層、氮化矽層、氧化鋁或類似物。介電質層i 〇4可由 與介電質層63相同之材料組成。端98可稱為一接觸區帶， 此係因為其使得與接合塾3 6電接觸。舉例而言，插入區帶 94為一矩形形狀區帶。用於電連接器92之合適材料包含 銅、銘、金屬及塗覆有一貴金屬之金屬合金連接器、錫、 鋼、銅合金、破、金、銀、鋁合金、黃銅、黃鋼合金戋類 似物。 圖7係在製造之一稍後階段之半導體組件1〇之—等角視 圖。圖7中展示安裝至電連接器92之具有相對表面119及 156577.doc -12- 201212200 121之一半導體晶片118。應注意，半導體晶片118可透過 一介電質材料（例如，諸如介電質層63及104之材料）附接至 電連接器92之插入物區帶94。半導體晶片118具有充當一 閘極接點之-閘極接合塾i2G及充當—源極接點之一源極 接合墊122。閘極接合墊120係藉由一接合線124連接至閘 極接合墊26G且源極接合墊122係藉由對應接合線126連接 至源極接合墊26s。儘管展示複數個接合線126及展示三個 源極接合墊26s，但是接合線126之數量及源極接合墊26s 之數量不為本發明之限制。可有—個、兩個或更多個接合 線126及一個、兩個、三個或更多個接合墊26s。 圖8係根據本發明之另一實施例之在製造之一早期階段 之半導體組件15〇之一部分之一俯視圖。圖8中展示一支 撐結構12A，例如，諸如具有一表面14、一組件承接區域 18、 形成於組件承接區域18之—部分中的—組件接觸結構 19、 _20gi、20si、22gi、22si、24gi、24si 26gi、 26S1、28G1、28S1、30G1、30S1、32gi、32μ及 I、34“及 接合塾36、38、40及42之一印刷電路板。應注意，除了接 合墊組…、〜、^、…、…、^、瓜及仏分別已被 接合墊 20S1、22S1、24S1、26S1、28“、3〇s]、％ 及 & 代 替外，基板〗2A類似於基板12。為了一致起見，圖丨中展示 之參考符號20G、22G、24G、26g、28g、馬、％及&分 別已被參考符號2〇G1、22⑺、24gi、26gi、28gi、3〇g〗、 32〇ι及34〇ι代替。 一組件（例 類似於圖1至圖3中所示之半導體組件 156577.doc •13- 201212200 如，諸如具有相對表面49及51(展示於圖3中）之一半導體晶 片48)係安裝至組件承接區域18中的組建接觸結構19。當 連接至組件接觸結構19之該組件為一半導體晶片時，組件 承接區域18可稱為一半導體晶片承接區域或一晶片承接區 域。半導體晶片48具有一閘極接點50及一源極接點52。閘 極接點50係藉由一接合線54連接至閘極接合墊且源極 接點52係藉由一電連接器152連接至源極接合墊20S1。舉例 而言’電連接器152具有接觸端154及158及一中心部分 156。電連接器152可由與電連接器62及92相同之材料製 成。接觸端154可透過一導電材料（例如，諸如焊料）連接至 源極接點52。接觸端158可透過一導電材料（例如，諸如焊 料）連接至接合墊20S1。 圖9係圖8中所示之但在製造之一稍後階段之半導體組件 150之一等角視圖。除了接合線52已被具有接觸端154及 158之電連接器152代替外’圖9類似於圖2。如上文所述， 接觸端1 5 4係經由一導電材料（例如，諸如焊料）電連接至源 極接點52且接觸端158係透過一導電材料（例如，諸如焊料） 電連接至接合墊20S1。接合線及電連接器可稱為互連或電 互連。 圖10係圖9中所示之但在製造之一稍後階段之半導體組 件150之一等角視圖。除了接合線56及86分別已被電連接 器152及162代替外，圖1〇類似於圖4。參考圖8已描述電連 接器152。舉例而言，電連接器162具有接觸端164及168及 一中心部分166。接觸端164可透過一導電材料（例如，諸 • 14· 156577.docThe 201212200 first-junction and the third electrical connector are disposed between the source contact and the first electrical connector. In another embodiment, a method for fabricating a semiconductor component includes providing a support structure having a component receiving region and a plurality of bonding pads; and bonding the -th semiconductor to the component receiving region of the branch structure The first semiconductor wafer has a first bonding pad and a second bonding pad; electrically bonding the first bonding surface of the first conductor chip to one of the plurality of bonding pads, and bonding the first semiconductor The second bonding pad of the wafer is electrically coupled to the at least one second bonding pad of the plurality of bonding pads; the first semiconductor wafer is coupled to the third bonding pad of the plurality of bonding pads by a first electrical connector. ' coupling a second semiconductor wafer to the first electrical connection, the second semiconductor wafer having a first bond pad and a second bond pad, and electrically coupling the first bond pad of the second semiconductor die to a fourth bonding pad of the plurality of bonding pads, electrically coupling the second bonding pad of the second semiconductor wafer to at least one fifth bonding pad of the plurality of bonding pads, and using a second electrical connector second Semiconductor wafer is coupled to the plurality of bonding pads engages one sixth pads. The present invention will be better understood from the following detailed description of the appended claims. In general, the present invention provides a semiconductor component and a method for fabricating the same. In accordance with an embodiment of the present invention, a semiconductor component includes a substrate having a component receiving region and a plurality of bonding pads. A semiconductor wafer 48 is attached to the component receiving area 丨8. One of the electrical connectors 62 having a plurality of terminals or 156577.doc 201212200 contact zones 64 and 68 is coupled to the semiconductor wafer 48 and the substrate 12. A semiconductor wafer 78 is mounted or attached to the end 64 of the electrical connector 62 such that the end 64 is positioned between the semiconductor wafer 48 and the semiconductor wafer 78. An electrical connector 92 having a plurality of end or contact zones 94 and 98 is coupled to the semiconductor wafer 78 and the substrate 12. A semiconductor wafer 118 is mounted over end 94 or attached to end 94 such that end 94 is between semiconductor wafer 78 and semiconductor wafer 118. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a top plan view of one portion of a semiconductor component 10 in one of the early stages of fabrication in accordance with an embodiment of the present invention. A support structure 12 is shown in FIG. 1, such as, for example, a printed circuit board having a surface 14, a component receiving area 18, a component contact structure 19 formed in a portion of the component receiving area 18, and a plurality of bonding pad sets 2 22, 24 and 26, a plurality of bond pad sets 28, 30, 32 and 34 and bond pads 36, 38, 40 and 42. The bond pad set 20 includes bond pads 20g & bond pads 2〇s; bond pad sets 22 include bond pads 22g and bond pads 22s; bond pad sets 24 include bond pads 24g & bond pads 24s; and bond pad sets 26 include bond pads 26 (5 and bonding pad 26s. Similarly, bonding pad set 28 includes bonding pads 28g and bonding pads 28; bonding pad sets include bonding pads 3〇g and bonding pads 30s; bonding pad sets 32 include bonding pads 32g and bonding pads 32s; and the bonding pad set 34 includes a bonding pad 34 and a bonding pad 34s. Further, a bonding pad 36 is formed between the bonding pad groups 20 and 28, and a bonding pad 38 is formed between the bonding pad groups 22 and 3, at the bonding A bonding pad (10) is formed between the pad sets 24 and 32, and a bonding pad 42 is formed between the bonding pad groups 26 and 34. The bonding pads of the electrode electrodes may be referred to as a closed pad or a pad pad; the bonding pad 156577. Doc 201212200 20s, 22s, 24s, 26s, 28s, 30s, 328, and 345 serve as bond pads for the source electrodes and may be referred to as source bond pads or source pads; and junctions 塾%, 38, 40, and 42 act as A bonding pad for a drain electrode and may be referred to as a gate pad or a pad. It should be noted that the substrate 12 has For major surfaces 14 and 16, wherein surface 16 is shown in Figure 3. Component contact structure 19, bond pads 20, 22, 24, 26, 28, 30, 32 and 34 and bond pads 36, 38, 40 and 42 may be a metallization system comprising one or more layers of electrically conductive material. Suitable metals for the metallization system of the component contact structure 丨9, the bonding pad groups 20 to 34 and the bonding pads % to π comprise copper, inscriptions, alloys, Or a combination or the like. Alternatively, the support structure 12 can be a lead frame, a ceramic substrate, including a resin (such as epoxy, polyimine, triazine, or phenolic resin, epoxy glass composite). One structure or the like. The placement or positioning of the bond pads on the support substrate 12 is not a limitation of one embodiment of the invention. An assembly (eg, such as having opposing surfaces 49 and 51 (shown in Figure 3)) A semiconductor wafer 48) is mounted to the component contact structure 19 in the component receiving region 18. The semiconductor wafer 48 can be attached to the component contact structure 19 using solder, a conductive paste, a conductive film or the like. The surfaces 49 and 51 are attached to the semiconductor. On the opposite side of the wafer 48 When the component coupled to the component contact structure 19 is a semiconductor wafer, the component receiving region 18 can be referred to as a semiconductor wafer receiving region or a wafer receiving region. The semiconductor wafer 48 has a gate bond pad 50 that acts as a gate contact. And as a source contact, a source bond pad 52 ° idle bond pad 5 is connected to the gate bond 〇 2 〇 G by a bond wire 54 and the source bond pad 52 is connected by a corresponding bond wire 56 connected to the source to connect 156577.doc 201212200 pad 2 〇 s. Although a plurality of bond wires % are shown and three source bond pads 20S' are shown, the number of bond wires 56 and the number of source bond pads 2〇s are not limited by the present invention. There may be one, two or more bonding wires % and one, two, three or more bonding pads 2 〇 s. It should be noted that the term bonding wire as used throughout the application may also be referred to as wire bonding or bonding wires. Figure 2 is an isometric view of one of the semiconductor components 10 shown in Figure 1 but at a later stage of fabrication. Figure 3 is a cross-sectional view of a semiconductor component 1 taken along section lines 3 through 3 of Figure 2. For the sake of brevity, Figures 2 and 3 will be described. As discussed with reference to Figure 1, the gate contact 5 is connected to the bond pad 20G by a bond wire n and the source contact 52 is connected to the bond pad 20s by a bond wire 56. An electrical connector 62 having ends 64 and 68 and a central zone 66 couples the source electrode 52 to the bond pads 4 of the support structure 12. The end may be referred to as an intervening zone 'this is because it can be positioned between at least two semiconductor wafers', ie, a semiconductor wafer can be positioned below the interposer zone 64 and another semiconductor wafer can be positioned Above the insert zone 64. The electrical connection number & can be a clip, a wire, a tape (for example, such as an aluminum tape) or the like. End 68 is bonded to bond pad 4 via, for example, a solder layer 71 and interposer strip 64 may be attached to semiconductor wafer 48 by a layer 63 of electrically insulating material. Suitable examples of the dielectric material 63 include a ceramic material, a thermal interface material, a thermally conductive film, an oxide layer, a tantalum nitride layer, aluminum oxide or the like. End 68 can be referred to as a contact strip because it causes electrical contact with bond pads 40. For example, the s' insert zone 64 is a rectangular shaped zone. Suitable materials for the electrical connector a include copper, metal, metal and gold metal coated with a noble metal, tin, steel, copper alloy, tantalum, gold, silver 'aluminum alloy, yellow 156577.doc -10- 201212200 Copper, brass alloy or similar. 3 depicts that the non-semiconductor wafer 48 is coupled to the component contact structure 19 via a conductive and thermally conductive die attach material 60. Suitable die attach materials include solder conductive paste conductive films or the like. Surface 51 contacts die attach material 60. For example, a semiconductor wafer includes an insulating gate semiconductor device in which the surface 51 acts as a drain contact. Therefore, the drain contact contact die attach material 6G 1st bond pad 50 and the source bond pad 52 are formed on or formed by the surface 49. 3 further illustrates a support structure 12 having source bond pads 2 〇 s, 24 s 28 s and 32 s formed on surface 14 and drain pads 28 and 40 and connected to heat conductor 21 The assembly contacts the structure 19 that extends from the component contact structure 19 to the surface 16. The heat conductor 21 is adapted to remove heat from a component of the component contact structure 19 or a component that is higher than the component contact structure. Figure 4 is an isometric view of the semiconductor component ι of Figures 2 and 3 at a later stage of fabrication. Figure 5 is a cross-sectional view of the semiconductor component 10 taken along section lines 5 through 5 of Figure 4 and Figure 6 is a cross-sectional view of the semiconductor component 10 taken along section lines 6 through 6 of Figure 4. For the sake of brevity, Figures 4 through 6 will be described together. A semiconductor wafer 78 having an opposing surface and 81 mounted to electrical connector 62 is shown in FIG. Semiconductor wafer 78 is coupled to interposer zone 64 via a conductive die attach material 83. Suitable die attach materials include solder, a conductive paste, a conductive film or the like. The die attach material 83 can be the same as the die attach material 60. The semiconductor wafer 78 has a gate bond pad 80 that acts as a gate contact and a source bond pad 82 that acts as a source contact. 156577.doc -11 - 201212200 The gate contact 80 is connected to the gate bond pad 22g by a bond wire 84 and the source contact 82 is connected to the source bond pad 22s by a corresponding bond wire 86. Although a plurality of bond wires 86 and three source bond pads 22s are shown, the number of bond wires 86 and the number of source bond pads 223 are not limited by the present invention. There may be one, two or more bonding wires 86 and one, two, three or more bonding plastics 22s. An electrical connector 92 having terminals 94 and 98 and a central zone 96 connects the source electrode 82 to the bond pad 36 of the support structure 12. End 94 can be referred to as an intervening zone because it can be positioned between at least two semiconductor wafers, i.e., a semiconductor wafer can be positioned below interposer zone 94 and another semiconductor wafer can be positioned Above the insert zone 94. The electrical connector % can be a sink, a wire, a tape (e.g., such as an aluminum tape) or the like. End 98 is bonded to bond pad 36 via, for example, a solder layer 71 and interposer strip 94 may be coupled to semiconductor wafer 78 by a layer of dielectric material 104. Suitable examples of dielectric material 104 include a ceramic material, a thermal interface material, a thermally conductive film, an oxide layer, a tantalum nitride layer, aluminum oxide, or the like. The dielectric layer i 〇 4 may be composed of the same material as the dielectric layer 63. End 98 can be referred to as a contact strip because it causes electrical contact with the engaging jaws 63. For example, the insertion zone 94 is a rectangular shaped zone. Suitable materials for the electrical connector 92 include copper, metal, metal alloy and metal alloy connectors coated with a noble metal, tin, steel, copper alloy, broken, gold, silver, aluminum alloy, brass, yellow steel alloy, etc. Things. Figure 7 is an isometric view of a semiconductor component in a later stage of fabrication. A semiconductor wafer 118 having an opposing surface 119 and 156577.doc -12-201212200 121 mounted to electrical connector 92 is shown in FIG. It should be noted that the semiconductor wafer 118 can be attached to the interposer zone 94 of the electrical connector 92 through a dielectric material (e.g., materials such as dielectric layers 63 and 104). The semiconductor wafer 118 has a gate junction 塾i2G that serves as a gate contact and a source bond pad 122 that serves as a source contact. The gate bond pads 120 are connected to the gate bond pads 26G by a bond wire 124 and the source bond pads 122 are connected to the source bond pads 26s by corresponding bond wires 126. Although a plurality of bond wires 126 and three source bond pads 26s are shown, the number of bond wires 126 and the number of source bond pads 26s are not limited by the present invention. There may be one, two or more bond wires 126 and one, two, three or more bond pads 26s. Figure 8 is a top plan view of one portion of a semiconductor component 15 in an early stage of fabrication in accordance with another embodiment of the present invention. A support structure 12A is shown in FIG. 8, for example, having a surface 14, a component receiving area 18, formed in a portion of the component receiving area 18, a component contact structure 19, _20gi, 20si, 22gi, 22si, 24gi, 24si 26gi, 26S1, 28G1, 28S1, 30G1, 30S1, 32gi, 32μ and I, 34" and one of the bonding pads 36, 38, 40 and 42 printed circuit boards. It should be noted that in addition to the bonding pad set ..., ~, ^, The substrate 2A is similar to the substrate 12 except that the bonding pads 20S1, 22S1, 24S1, 26S1, 28", 3〇s, %, and & For the sake of consistency, reference numerals 20G, 22G, 24G, 26g, 28g, horses, %, and & shown in the drawings have been referred to by reference symbols 2〇G1, 22(7), 24gi, 26gi, 28gi, 3〇g, respectively. 32〇ι and 34〇ι instead. A component (example similar to the semiconductor component 156577.doc • 13-201212200 shown in Figures 1-3), such as a semiconductor wafer 48 having opposing surfaces 49 and 51 (shown in Figure 3) is mounted to the component The contact structure 19 is formed in the receiving area 18. When the component connected to the component contact structure 19 is a semiconductor wafer, the component receiving region 18 can be referred to as a semiconductor wafer receiving region or a wafer receiving region. The semiconductor wafer 48 has a gate contact 50 and a source contact 52. The gate contact 50 is connected to the gate bond pad by a bond wire 54 and the source contact 52 is connected to the source bond pad 20S1 by an electrical connector 152. For example, the electrical connector 152 has contact ends 154 and 158 and a central portion 156. Electrical connector 152 can be made of the same material as electrical connectors 62 and 92. Contact end 154 can be coupled to source contact 52 via a conductive material (e.g., such as solder). Contact end 158 can be coupled to bond pad 20S1 via a conductive material (e.g., such as a solder). Figure 9 is an isometric view of one of the semiconductor components 150 shown in Figure 8 but at a later stage of fabrication. Except that the bond wires 52 have been replaced by electrical connectors 152 having contact ends 154 and 158, FIG. 9 is similar to FIG. As described above, the contact end 154 is electrically connected to the source contact 52 via a conductive material (eg, such as solder) and the contact end 158 is electrically coupled to the bond pad 20S1 through a conductive material (eg, such as solder). . Bond wires and electrical connectors can be referred to as interconnects or electrical interconnects. Figure 10 is an isometric view of one of the semiconductor components 150 shown in Figure 9 but at a later stage of fabrication. Figure 1 is similar to Figure 4 except that bond wires 56 and 86 have been replaced by electrical connectors 152 and 162, respectively. Electrical connector 152 has been described with reference to FIG. For example, electrical connector 162 has contact ends 164 and 168 and a central portion 166. The contact end 164 is permeable to a conductive material (eg, • 14·156577.doc)

S 201212200 如焊料）連接至源極接點82(展示於圖5中）^接觸端ι68可透 過一導電材料（例如，諸如焊料）連接至接合墊22si。接合 線及電連接器可稱為互連或電互連。 圖11係圖10中所示之但在製造之一稍後階段之半導體組 件150之一等角視圖。除了接合線126已被電連接器172代 替外，圖11類似於圖7，該電連接器172具有接觸端174及 178及在接觸端174與178之間的一中心區帶176。接觸端 178係電連接至接合墊2631且接觸端丨74係連接至源極接點 122。接合線及電連接器可稱為互連或電互連。 圖12係根據本發明之另一實施例之一半導體組件2〇〇之 一等角視圖。圖12之描述連續自圖7之描述。應注意，圖i 至圖7之半導體組件已藉由參考符號1〇而識別。為了簡潔 起見，圖12之半導體組件之描述之參考數字已變成參考符 號200。圖12中展示將源極接點122連接至接合墊38之一電 連接器202。電連接器2〇2具有端2〇4及2〇8及一中心區帶 206。端204可稱為一插入物區帶，此係因為其可定位於至 少兩個半導體晶片之間，亦、gp，一 |導體晶片可定位於插 入物區帶204之下且另一半導體晶片可定位於插入物區帶 204之上電連接器202可為一夹子、一線、一帶（例如， 諸如一鋁帶）或類似物。端2〇8係透過（例如）一焊料層接合 至接合墊38且插入物區帶2〇4可藉由一層介電質材料（例 如，諸如介電質層63或介電質層1〇4(展示於圖6中）)連接至 半導體晶>| 118。舉例而言’插人物區帶2()4為_矩形形狀 區帶用於電連接器2〇2之合適材料包含銅、鋁、金屬及 156577.doc -15· 201212200 塗覆有一責金屬之金屬合金連接器、錫、鋼、銅合金、 鈹、金、銀、鋁合金、黃銅、黃銅合金或類似物。 圖η係圖12之但在製造之一賴後階段之半導體組件細 之一等角視圖。圖13中展示安裝至電連接器2〇2之具有相 對表面219及221之-半導體晶片川。半導體晶片μ具有 充當-閘極接點之一閘極接合塾22〇及充當一源極接點之 一源極接合墊222。閘極接合墊22〇係藉由一接合線224連 接至閘極接合墊30G且源極接合墊222係藉由對應接合線 226連接至源極接合墊3〇^接合線可稱為線接合或接合 線。儘管展示複數個接合線226及展示三個源極接合墊 3〇s，但是接合線226之數量及源極接合墊3〇s之數量不為 本發明之限制。可有一個、兩個或更多個接合線226及一 個、兩個、三個或更多個接合墊3〇s。 圖14係圖13之但在製造之一稍後階段之半導體組件 之一等角視圓。圖4中展示將源極接點222連接至接合墊42 之電連接器242。電連接器242具有端244及248及一中心 區帶246。端244可稱為一插入物區帶，此係因為其可定位 於至/兩個半導體晶片之間，亦即，一半導體晶片可定位 於插入物區帶244之下且另一半導體晶片可定位於插入物 區帶244之上。電連接器242可為一夾子、一線、一帶（例 如’諸如一鋁帶）或類似物。端248係透過（例如）一焊料層 接合至接合墊42且插入物區帶244係透過一層介電質材料 (例如’諸如介電質層63或介電質層1〇4(展示於圖6中））連 接至半導體晶片218。舉例而言，插入物區帶244為一矩形 156577.doc 201212200 形狀區帶。用於電連接器242之合適材料包含銅、銘、金 屬及塗覆有-責金屬之金屬合金連接器、錫、鋼、銅合 金、皱、金、銀、is合金、黃銅、黃鋼合金或類似物。 圖15係圖14之但在製造之一稍後階段之半導體組件200 之-等角視圖。圖15中展示安裝至電連接器加之具有表 面259及261之一半導體晶片258。半導體晶片258具有充當 -閘極接點之-間極接合塾26()及充當—源極接點之一源 極接合墊262。閘極接合塾26〇係藉由_接合線⑽連接至 閘極接合墊28G且源極接合墊262係藉由對應接合線2“連 接至源極接合墊28s。接合線可稱為線接合或接合線。儘 管展示複數個接合線266及展示三個源極接合墊28s，但是 接合線266之數量及源極接合墊28s之數量不為本發明之限 制。可有一個、兩個或更多個接合線266及一個、兩個、 三個或更多個接合墊28s。 通常，在半導體晶片48、78、118、218及258、電連接 器 62、92、202 及 242 及接合線 54、56、84、86、124、 126、224、226、264及266周圍形成一保護結構（未展示）„ 舉例而σ ’該保護結構為一模製化合物。應注意，保護結 構之類型不為本發明之一限制。例如，該保護結構可為一 蓋或帽，或類似物。或者，可能不存在該保護結構。 圖16係根據本發明之另一實施例之一半導體組件3〇〇之 一等角視圖。除了接合線226係連接至導電體2〇2而非連接 至接合墊38外，半導體組件300類似於半導體組件2〇〇。 圖17係根據本發明之另一實施例之一半導體組件32〇之 156577.doc •17· 201212200 一等角視圖。除了源極區帶加係透過—導電體或夾子M2 而非接合線連接至導電體2〇2外，半導體組件320類似於半 導體組件300。 現應瞭解，已接供—括aim " 種半導體組件及一種用於製造該半 、、件之方法。根據本發明之實施例，以一堆疊組態形 成具有（例如）功率金氧半場效電晶體（勘卿τ)之半導體晶 粒。因此’複數個堆疊半導體晶粒係封裝於—保護材料 (例如，諸如一模製化合物)中。根據本發明之實施例之製 造半導體組件之-優點在於其容許堆疊三個或更多個半導 體晶粒’其減小經封裝之半導體晶粒之覆蓋區。此外，該 半導體晶粒可用作個別裝置或可協作以形成（例如）如圖16 及圖17中料之互補組件。此外，根據本發明之實施例使 用具有一較小覆蓋區之一封裝增強半導體組件之功率能 力β 儘管已在本文令揭示特定實施例，但是其不意欲將本發 明限於所揭示之實施例《熟習此項技術者將認知，在不脫 離本發明之精神之情況下，可作修改及變更。本發明意欲 包含如落入隨附申請專利範圍之範疇内之所有此等修改及 變更。 【圖式簡單說明】 圖1係根據本發明之實施例之一半導體組件之一部分之 一平面圖； 圖2係根據本發明之實施例之一半導體組件之一部分之 一等角視圖； 156577.doc -18-S 201212200 is soldered to source contact 82 (shown in Figure 5). Contact terminal ι68 is connectable to bond pad 22si via a conductive material (e.g., such as solder). Bond wires and electrical connectors can be referred to as interconnects or electrical interconnects. Figure 11 is an isometric view of one of the semiconductor components 150 shown in Figure 10 but at a later stage of fabrication. 11 is similar to FIG. 7, except that the bond wire 126 has been replaced by an electrical connector 172 having contact ends 174 and 178 and a center zone 176 between the contact ends 174 and 178. Contact end 178 is electrically coupled to bond pad 2631 and contact end 74 is coupled to source contact 122. Bond wires and electrical connectors may be referred to as interconnects or electrical interconnects. Figure 12 is an isometric view of a semiconductor component 2 in accordance with another embodiment of the present invention. The description of Figure 12 is continuous from the description of Figure 7. It should be noted that the semiconductor components of Figures i through 7 have been identified by reference numeral 1A. For the sake of brevity, the reference numerals of the description of the semiconductor component of Fig. 12 have become reference symbol 200. An electrical connector 202 that connects the source contact 122 to the bond pad 38 is shown in FIG. The electrical connector 2〇2 has ends 2〇4 and 2〇8 and a central zone 206. Terminal 204 can be referred to as an intervening zone because it can be positioned between at least two semiconductor wafers, and also, a gp, a |conductor wafer can be positioned below the interposer zone 204 and another semiconductor wafer can be The electrical connector 202 positioned within the insert zone 204 can be a clip, a wire, a tape (eg, such as an aluminum tape) or the like. The end 2〇8 is bonded to the bond pad 38 by, for example, a solder layer and the interposer strip 2〇4 can be formed by a layer of dielectric material (eg, such as dielectric layer 63 or dielectric layer 1〇4). (shown in Figure 6)) connected to the semiconductor crystal > | 118. For example, 'Picture zone zone 2 () 4 is _ rectangular shape zone. Suitable materials for electrical connector 2〇2 include copper, aluminum, metal and 156577.doc -15· 201212200 coated with metal Alloy connectors, tin, steel, copper alloys, tantalum, gold, silver, aluminum alloys, brass, brass alloys or the like. Figure η is an isometric view of the semiconductor component of Figure 12 but at a later stage of fabrication. A semiconductor wafer having opposite surfaces 219 and 221 mounted to electrical connector 2〇2 is shown in FIG. The semiconductor wafer μ has a source bond pad 222 that acts as a gate junction 22' of the gate junction and serves as a source contact. The gate pad 22 is connected to the gate pad 30G by a bonding wire 224 and the source pad 222 is connected to the source pad by a corresponding bonding wire 226. The bonding wire may be referred to as wire bonding or Bonding wire. Although a plurality of bond wires 226 are shown and three source bond pads 3 〇 s are shown, the number of bond wires 226 and the number of source bond pads 3 〇s are not limited by the present invention. There may be one, two or more bond wires 226 and one, two, three or more bond pads 3〇s. Figure 14 is an isometric view of the semiconductor component of Figure 13 but at a later stage of fabrication. Electrical connector 242 that connects source contact 222 to bond pad 42 is shown in FIG. Electrical connector 242 has ends 244 and 248 and a central zone 246. End 244 may be referred to as an intervening zone because it can be positioned between two semiconductor wafers, that is, one semiconductor wafer can be positioned below interposer zone 244 and another semiconductor wafer can be positioned Above the insert zone 244. The electrical connector 242 can be a clip, a wire, a tape (e.g., such as an aluminum tape) or the like. The end 248 is bonded to the bond pad 42 by, for example, a solder layer and the interposer zone 244 is permeable to a layer of dielectric material (eg, 'such as dielectric layer 63 or dielectric layer 1 〇 4 (shown in Figure 6). Medium)) is connected to the semiconductor wafer 218. For example, the insert zone 244 is a rectangular 156577.doc 201212200 shaped zone. Suitable materials for the electrical connector 242 include copper, metal, metal-coated metal alloy connectors, tin, steel, copper alloy, wrinkle, gold, silver, is alloy, brass, yellow steel alloy Or similar. Figure 15 is an isometric view of the semiconductor component 200 of Figure 14 at a later stage of fabrication. Mounted to the electrical connector plus one of the semiconductor wafers 258 having surfaces 259 and 261 is shown in FIG. The semiconductor wafer 258 has a - - junction junction 26 () that acts as a --gate junction and a source bond pad 262 that acts as a source junction. The gate junction 26 is connected to the gate bond pad 28G by a bonding wire (10) and the source bond pad 262 is "connected to the source bond pad 28s by a corresponding bond wire 2. The bond wire may be referred to as wire bond or Bonding wire. Although a plurality of bonding wires 266 and three source bonding pads 28s are shown, the number of bonding wires 266 and the number of source bonding pads 28s are not limited by the present invention. There may be one, two or more. Bonding wires 266 and one, two, three or more bonding pads 28s. Typically, semiconductor wafers 48, 78, 118, 218 and 258, electrical connectors 62, 92, 202 and 242 and bonding wires 54, A protective structure (not shown) is formed around 56, 84, 86, 124, 126, 224, 226, 264, and 266. For example, σ' is a molding compound. It should be noted that the type of protection structure is not a limitation of the present invention. For example, the protective structure can be a lid or cap, or the like. Or, the protection structure may not exist. Figure 16 is an isometric view of a semiconductor component 3 in accordance with another embodiment of the present invention. The semiconductor component 300 is similar to the semiconductor component 2 except that the bonding wires 226 are connected to the conductors 2〇2 instead of to the bonding pads 38. Figure 17 is an isometric view of a semiconductor component 32 156577.doc • 17· 201212200 in accordance with another embodiment of the present invention. The semiconductor component 320 is similar to the semiconductor component 300 except that the source region is via a conductor or clip M2 rather than a bond wire to the conductor 2〇2. It should be understood that a semiconductor package and a method for manufacturing the same are provided. In accordance with an embodiment of the present invention, a semiconductor wafer having, for example, a power MOS field effect transistor (Kyosei τ) is formed in a stacked configuration. Thus, a plurality of stacked semiconductor dies are encapsulated in a protective material (e.g., such as a molding compound). An advantage of fabricating a semiconductor component in accordance with an embodiment of the present invention is that it allows for the stacking of three or more semiconductor dies [which reduces the footprint of the encapsulated semiconductor die. In addition, the semiconductor dies can be used as individual devices or can cooperate to form complementary components such as those in Figures 16 and 17. In addition, the power capability of encapsulating the reinforced semiconductor component with one of the smaller footprints is used in accordance with an embodiment of the present invention. Although specific embodiments have been disclosed herein, it is not intended to limit the invention to the disclosed embodiments. It will be appreciated by those skilled in the art that modifications and variations can be made without departing from the spirit of the invention. It is intended that the present invention include all such modifications and modifications as fall within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a portion of a semiconductor component in accordance with an embodiment of the present invention; FIG. 2 is an isometric view of a portion of a semiconductor component in accordance with an embodiment of the present invention; 156577.doc - 18-

S 201212200 圖3係沿著刮面線3至3截取之圖2之半導體組件之一截面 圖； 圖4係在製造之一稍後階段之圖2及圖3之半導體組件之 一等角視圖； 圖5係沿著剖面線5至5載取之圖4之半導體組件之一截面 圖； 圖6係沿著剖面線6至6截取之圖4之半導體組件之一截面 fg!l · 圖， 圖7係在製造之一稍後階段之圖4至圖6之半導體組件之 一等角視圖； 圖8係根據本發明之實施例之一半導體組件之一部分之 一平面圖； 圖9係在製造之一稍後階段之圖8之半導體組件之一等角 視圖； 圖10係在製造之一稍後階段之圖9之半導體組件之一等 角視圖； 圖11係在製造之一稍後階段之圖1〇之半導體組件之一等 角視圖； 圖12係在製造之一稍後階段之圖η之半導體組件之一等 角視圖； 圖13係在製造之一稍後階段之圖12之半導體組件之—等 角視圖； 圖14係在製造之一稍後階段之圖13之半導體組件之一等 角視圖； 156577.doc 201212200 組件之一等 之一等角視 之一等角視 圖15係在製造之一稍後階段之圖14之半導體 角視圖； 圖1 6係根據本發明之實施例之一半導體組件 圖；及 圖1 7係根據本發明之實施例之一半導體組件 圖。 【主要組件符號說明】 10 半導體組件 12 支撐結構 12A 支撐結構 14 表面 16 表面 18 組件承接區域 19 組件接觸結構 20 接合塾組 20〇 接合墊 20s 接合墊 2〇gi 接合墊 2〇si 接合墊 21 導熱體 22 接合墊組 22g 接合墊 22s 接合墊 22〇ι 接合墊 156577.doc 201212200 22Si 接合墊 24 接合墊組 24g 接合墊 24s 接合墊 24G1 接合墊 24s, 接合墊 26 接合墊組 26g 接合墊 26s 接合墊 26G1 接合墊 26Si 接合墊 28 接合墊組 28〇 接合墊 28s 接合墊 2B〇i 接合墊 28si 接合墊 30 接合墊組 30〇 接合墊 30s 接合墊 3〇gi 接合墊 3〇si 接合墊 32 接合墊組 32g 接合墊 32s 接合墊 156577.doc •21 201212200 32G1 接合墊 32s, 接合墊 34 接合墊組 34g 接合墊 34s 接合墊 34G1 接合墊 34S1 接合墊 36 接合墊 38 接合墊 40 接合墊 42 接合墊 48 半導體晶片 49 表面 50 閘極接合墊 51 表面 52 源極接合墊/源極電極 54 接合線 56 接合線 60 晶粒附接材料 62 電連接器 63 電絕緣材料 64 接觸區帶/端 66 中心區帶 68 接觸區帶/端 156577.doc ·22· 201212200 71 焊料層 78 半導體晶片 79 表面 80 閘極接點 81 表面 82 源極接合墊/源極電極 83 導電晶粒附接材料 84 接合線 86 接合線 92 電連接器 94 端 96 中心區帶 98 端 104 介電質材料 118 半導體晶片 119 表面 120 閘極接合塾 121 表面 122 源極接合墊 124 接合線 126 接合線 150 半導體組件 152 電連接器 154 接觸端 156577.doc •23- 201212200 156 中心部分 158 接觸端 162 電連接器 164 接觸端 166 中心部分 168 接觸端 172 電連接器 174 接觸端 176 中心區帶 178 接觸端 200 半導體組件 202 電連接器/導電體 204 端/插入物區帶 206 中心區帶 208 端 218 半導體晶片 219 表面 220 閘極接合墊 221 表面 222 源極接合墊/源極接點 224 接合線 226 接合線 242 電連接器 244 端/插入物區帶 24* 156577.doc s 201212200 246 中心區帶 248 端 258 半導體晶片 259 表面 260 閘極接合墊 261 表面 262 源極接合墊 264 接合線 266 接合線 300 半導體組件 320 半導體組件 322 導電體/夾子 156577.doc ·25-S 201212200 FIG. 3 is a cross-sectional view of the semiconductor component of FIG. 2 taken along the scratch line 3 to 3; FIG. 4 is an isometric view of one of the semiconductor components of FIGS. 2 and 3 at a later stage of fabrication; Figure 5 is a cross-sectional view of the semiconductor component of Figure 4 taken along section lines 5 through 5; Figure 6 is a cross section of the semiconductor component of Figure 4 taken along section lines 6 through 6 fg!l · Figure, Figure 7 is an isometric view of one of the semiconductor components of FIGS. 4 to 6 at a later stage of manufacture; FIG. 8 is a plan view of one of the semiconductor components in accordance with an embodiment of the present invention; FIG. An isometric view of one of the semiconductor components of FIG. 8 at a later stage; FIG. 10 is an isometric view of one of the semiconductor components of FIG. 9 at a later stage of fabrication; FIG. 11 is a diagram of one of the later stages of fabrication An isometric view of one of the semiconductor components of FIG. 12; FIG. 12 is an isometric view of one of the semiconductor components of FIG. 12 at a later stage of fabrication; FIG. 13 is a semiconductor component of FIG. 12 at a later stage of fabrication - Isometric view; Figure 14 is a semiconductor component of Figure 13 at a later stage of fabrication An isometric view; 156577.doc 201212200 one of the components, one isometric view, one isometric view 15 is a semiconductor angular view of FIG. 14 at a later stage of manufacture; FIG. 16 is an embodiment in accordance with the present invention A semiconductor component diagram; and FIG. 17 is a diagram of a semiconductor component in accordance with an embodiment of the present invention. [Main component symbol description] 10 Semiconductor component 12 Support structure 12A Support structure 14 Surface 16 Surface 18 Component receiving area 19 Component contact structure 20 Bonding group 20〇 Bonding pad 20s Bonding pad 2〇gi Bonding pad 2〇Si Bonding pad 21 Thermal conduction Body 22 bonding pad set 22g bonding pad 22s bonding pad 22〇 bonding pad 156577.doc 201212200 22Si bonding pad 24 bonding pad group 24g bonding pad 24s bonding pad 24G1 bonding pad 24s, bonding pad 26 bonding pad group 26g bonding pad 26s bonding pad 26G1 bond pad 26Si bond pad 28 bond pad set 28 bond pad 28s bond pad 2B〇i bond pad 28si bond pad 30 bond pad set 30 bond pad 30s bond pad 3〇gi bond pad 3〇si bond pad 32 bond pad set 32g bond pad 32s bond pad 156577.doc • 21 201212200 32G1 bond pad 32s, bond pad 34 bond pad set 34g bond pad 34s bond pad 34G1 bond pad 34S1 bond pad 36 bond pad 38 bond pad 40 bond pad 42 bond pad 48 semiconductor wafer 49 Surface 50 Gate Bond Pad 51 Surface 52 Source Bonding / source electrode 54 bond wire 56 bond wire 60 die attach material 62 electrical connector 63 electrically insulating material 64 contact zone strip / end 66 center zone strip 68 contact zone strip / end 156577.doc · 22 · 201212200 71 solder layer 78 Semiconductor wafer 79 Surface 80 Gate contact 81 Surface 82 Source bond pad/source electrode 83 Conductive die attach material 84 Bond wire 86 Bond wire 92 Electrical connector 94 End 96 Center zone 98 End 104 Dielectric Material 118 Semiconductor Wafer 119 Surface 120 Gate Junction 121 Surface 122 Source Bond Pad 124 Bond Wire 126 Bond Wire 150 Semiconductor Component 152 Electrical Connector 154 Contact End 156577.doc • 23- 201212200 156 Center Port 158 Contact Port 162 Electrical Connection 164 contact end 166 central portion 168 contact end 172 electrical connector 174 contact end 176 central zone 178 contact end 200 semiconductor component 202 electrical connector / electrical conductor 204 end / insert zone 206 central zone 208 end 218 semiconductor wafer 219 Surface 220 Gate Bonding Pad 221 Surface 222 Source Bonding Pad/Source Contact 224 Bonding 226 Bonding wire 242 Electrical connector 244 End/insert zone 24* 156577.doc s 201212200 246 Center zone 248 end 258 Semiconductor wafer 259 Surface 260 Gate bond pad 261 Surface 262 Source bond pad 264 Bond wire 266 Bond wire 300 Semiconductor Components 320 Semiconductor Components 322 Conductors / Clips 156577.doc · 25-

Claims (1)

201212200 七、申請專利範圍： -種半導體組件，其包括： _基板’其具有—組件承接區域及複數個接合塾. -半導體晶片’其具有第一表面及第二表面，該 第：半導體晶片之該第一表面輕合至該組件承接區域； ▲電連接器’其具有第—端及第二端，該第一端 於该第一半導體晶片之該第二表面； 笛Γ第二半導體晶片，其具有第-表面及第二表面，該 ㈣：導體晶片之該第一表面耦合至該第-電連接器之 2一端，其中該第一導電體之該第一端係定位於該第 -半導體晶片與該第二半導體晶片之間； 、第一電連接器，其具有第一端及第二端，該第二電 連接器之該第-端鄰近於該第二半導體晶片之該第二表 面；及 第一半導體晶片，其具有第一表面及第二表面，該 第一半導體晶片之該第一表面耦合至該第二電連接器之 -亥第-端’纟中該第二電連接器之該第一端係在該第二 半導體晶片與該第三半導體晶片之間。 2.如請求項1之半導體組件，其中： 該第一半導體晶片之該第一表面包含一汲極之一部 分，且進一步包含在該第一半導體晶片之該第二表面之 一第一部分處的一閘極接合墊及在該第一半導體晶片之 該第二表面之-第二部分處的-源極接合墊； 該基板上的該複數個接合墊包括第一接合墊及第二接 156577.doc 201212200 合墊’且進-步包含耦合於該第一半導體晶片之該閘極 接合塾與該基板上的該第-接合墊之間的-第三電連接 器及耦合於該第一半導體晶片之該源極接合墊與該基板 上的該第二接合墊之間的一第四電連接器，· 該第二半導體晶片之該第一表面包含一汲極之一部 分，且進一步包含在該第二半導體晶片之該第二表面之 「第：部分處的-間極接合塾及在該第二半導體晶片之 該第一表面之-第二部分處的一源極接合墊； 該基板上的該複數個接合墊包括第三接合墊及第四接 合墊’且進一步包含耦合於該第二半導體晶片之該第一 部分處的該閘極接合塾與該基板上的該第三接合塾之間 的一第五電連接器及麵合於該第二半導體晶片之該源極 接合塾與該基板上的該第四接合塾之間的—第六電連接 器；及 、該第三半導體晶片之該第—表面包含—沒極之一部 :’亡進-步包含在該第二半導體晶片之該第二表面之 「第-部分處的-閘極接合墊及在該第二半導體晶片之 該第一表面之一第二部分處的一源極接合墊。 3.如凊求項2之半導體組件，其中該基板上的該複數個接 合墊包括第五接合墊及第六接合墊，且進一步包含耦合 於該第三半導體晶片之該第一部分處的該閘極接合墊： 該基板上的該第五接合墊之間的-第七電連接器及耦合 ㈣第三何體晶片之料極接合塾與該基板上的該第 ，、接合墊之間的一第八電連接器。 156577.doc 201212200 4. 如明求項3之半導體組件，其中該第一電連接器及該第 二電連接器為夾子，且該第三電連接器、該第四電連接 器、该第五電連接器、該第六電連接器、該第七電連接 器及該第八電連接器為接合線，且其進一步包含： 一第九電連接器，其具有第一端及第二端，該第九電 連接器之該第一端鄰近於該第三半導體晶片之該第二表 面；及 一第四半導體晶片，其具有第一表面及第二表面，該 第四半導體晶片之該第一表面耦合至該第九電連接器之 該第一端，其中該第九電連接器之該第一端係在該第三 半導體晶片與該第四半導體晶片之間。 5. 如請求項3之半導體組件，其中該第一電連接器及該第 二電連接器為夹子，且該第三電連接器、該第四電連接 器、該第五電連接器、該第六電連接器、該第七電連接 器及該第八電連接器為接合線，且其進一步包含： 一第十一電連接器，其具有第一端及第二端，該第十 二電連接器之該第一端鄰近於該第四半導體晶片之該第 二表面。 6. 如請求項5之半導體组件，其進一步包含具有第一表面 及第二表面之一第五半導體晶片，該第五半導體晶片之 該第一表面耦合至該第十二電連接器之該第一端，其中 該第十二電連接器之該第一端係在該第四半導體晶片與 該第五半導體晶片之間。 7. —種半導體組件，其包括： 156577.doc 201212200 一基板，其具有一晶片承接區域及複數個接合墊； 一第一半導體晶片’其柄合至該晶片承接區域，該第 一半導體晶片具有第一表面及第二表面，其中該第二表 面包含一閘極接點及一源極接點； 一第一電連接器，其耦合於該第一半導體晶片之該第 二表面與該複數個接合墊之一第一接合墊之間； 一第二半導體晶片，其輕合至該第一電連接器，該第 二半導體晶片具有第一表面及第二表面，其中該第二半 導體晶片之該第二表面包含一閘極接點及一源極接點；及 一第二電連接器，其耦合於該第一半導體晶片之該閘 極接點與該複數個接合墊之一第一接合墊之間，且一第 二電連接器耦合於該源極接點與該第一電連接器之間。 8. 一種製造一半導體組件之方法，其包括： 提供具有一組件承接區域及複數個接合墊之一支撐結 構； 、口 將第半導體晶片輕合至該支#結構之該組件承接 區域，該第一半導體晶片具有第一接合墊及第二接合 墊； 將該第一半導體晶片之該第一接合墊電耦合至該複數 個接合墊之一第一接合墊且將該第一半導體晶片之該第 一接合塾電耗合至該複數個接合塾之至少一第二接合 墊； 以一第一電連接器將該第一半導體晶片耦合至該複數 個接合墊之一第三接合墊； 156577.doc -4- 201212200 一將一第二半導體晶片耦合至該第一電連接器，該第二 半導體晶片具有一第一接合墊及一第二接合墊；及 第一半導體晶片之該第一接合墊電耦合至該複數 個接合塾之—第四接合墊，將該第二半導體晶片之該第 接合墊電耦合至該複數個接合墊之至少一第五接合 墊，且以一第二電連接器將該第二半導體晶片耦合至該 複數個接合墊之一第六接合墊。 9.如請求項8之方法，其進一步包含： "將-第三半導體晶片耦合至該第二電連接器，該第三 半導體晶片具有一第一接合墊及一第二接合墊； ^第—半導體晶片之該第一接合墊電耦合至該複數 個接合墊之—第七接合塾且將該第三半導體晶片之該第 接合墊電耦合至該複數個接合墊之一第八接合墊； 以一第三電連接器將該第三半導體晶片麵合至該複數 個接合墊之一第九接合墊； 、將-第四半導體晶片耦合至該第三電連接器，該第四 半導體晶片具有一第一接合塾及一第二接合墊； k第四半導體晶片之該第一接合墊電耦合至該複數 個接合墊之-第十接合塾且將該第四半導體晶片之該第 一接合墊電耦合至該複數個接合墊之一第十一接合墊；及 以-~第四電連接器將該第四半導體晶片&合至該複數 個接合墊之一第十二接合墊。 月求項9之方法’芩進一步包含將一第五半導體晶片 輕合至該第四電連接器。 156577.doc201212200 VII. Patent application scope: A semiconductor component, comprising: a substrate having a component receiving region and a plurality of bonding pads. The semiconductor wafer has a first surface and a second surface, the semiconductor wafer The first surface is lightly coupled to the component receiving area; ▲ the electrical connector has a first end and a second end, the first end is on the second surface of the first semiconductor wafer; the second semiconductor wafer is The first surface of the conductor wafer is coupled to one end of the first electrical connector, wherein the first end of the first electrical conductor is positioned at the first semiconductor Between the wafer and the second semiconductor wafer; a first electrical connector having a first end and a second end, the first end of the second electrical connector being adjacent to the second surface of the second semiconductor wafer And a first semiconductor wafer having a first surface and a second surface, the first surface of the first semiconductor wafer being coupled to the second electrical connector of the second electrical connector The first end Between the second semiconductor chip and the third semiconductor wafer. 2. The semiconductor component of claim 1 wherein: the first surface of the first semiconductor wafer comprises a portion of a drain and further comprising a portion at a first portion of the second surface of the first semiconductor wafer a gate bond pad and a source bond pad at a second portion of the second surface of the first semiconductor wafer; the plurality of bond pads on the substrate including a first bond pad and a second bond 156577.doc The 201212200 pad and step include a third electrical connector coupled between the gate bond pad of the first semiconductor wafer and the first bond pad on the substrate and coupled to the first semiconductor die a fourth electrical connector between the source bond pad and the second bond pad on the substrate, the first surface of the second semiconductor die includes a portion of a drain, and is further included in the second a source bonding pad at the "part: portion-to-pole junction" of the second surface of the semiconductor wafer and at the second portion of the first surface of the second semiconductor wafer; the complex number on the substrate Bond pads include a third bond pad and a fourth bond pad ′ and further comprising a fifth electrical connector coupled between the gate bond pad at the first portion of the second semiconductor wafer and the third bond pad on the substrate and a sixth electrical connector that is disposed between the source junction of the second semiconductor wafer and the fourth junction on the substrate; and the first surface of the third semiconductor wafer includes - a pole a portion: a "dead-step" comprising a "gate bond pad at the first portion of the second surface of the second semiconductor wafer and a second portion of the first surface of the second semiconductor wafer 3. A source bonding pad according to claim 2, wherein the plurality of bonding pads on the substrate comprise a fifth bonding pad and a sixth bonding pad, and further comprising coupling to the third semiconductor wafer The gate bonding pad at the first portion: a seventh electrical connector between the fifth bonding pads on the substrate and a coupling electrode of the (four) third body wafer and the first substrate , an eighth electrical connection between the pads 4. The semiconductor component of claim 3, wherein the first electrical connector and the second electrical connector are clips, and the third electrical connector, the fourth electrical connector, the The fifth electrical connector, the sixth electrical connector, the seventh electrical connector, and the eighth electrical connector are bonding wires, and further comprising: a ninth electrical connector having a first end and a second The first end of the ninth electrical connector is adjacent to the second surface of the third semiconductor wafer; and a fourth semiconductor wafer having a first surface and a second surface, the fourth semiconductor wafer a first surface coupled to the first end of the ninth electrical connector, wherein the first end of the ninth electrical connector is between the third semiconductor wafer and the fourth semiconductor wafer. The semiconductor component of 3, wherein the first electrical connector and the second electrical connector are clips, and the third electrical connector, the fourth electrical connector, the fifth electrical connector, the sixth electrical connector The seventh electrical connector and the eighth electrical connector are connected Line, and further comprising: an eleventh electrical connector having a first end and a second end, the first end of the electrical connector of the twelfth adjacent to the second surface of the fourth semiconductor wafer. 6. The semiconductor component of claim 5, further comprising a fifth semiconductor wafer having a first surface and a second surface, the first surface of the fifth semiconductor wafer being coupled to the twelfth electrical connector One end, wherein the first end of the twelfth electrical connector is between the fourth semiconductor wafer and the fifth semiconductor wafer. 7. A semiconductor component, comprising: 156577.doc 201212200 a substrate having a wafer receiving area and a plurality of bonding pads; a first semiconductor wafer s handle to the wafer receiving area, the first semiconductor wafer having a first surface and a second surface, wherein the second surface includes a gate contact and a source contact; a first electrical connector coupled to the second surface of the first semiconductor wafer and the plurality of One of the bonding pads is between the first bonding pads; a second semiconductor wafer that is lightly coupled to the first electrical connector, the second semiconductor wafer having a first surface and a second surface, wherein the second semiconductor wafer The second surface includes a gate contact and a source contact; and a second electrical connector coupled to the gate contact of the first semiconductor wafer and the first bond pad of the plurality of bond pads And a second electrical connector is coupled between the source contact and the first electrical connector. A method of manufacturing a semiconductor component, comprising: providing a support structure having a component receiving area and a plurality of bonding pads; and bonding the semiconductor wafer to the component receiving area of the branch structure, the a semiconductor wafer having a first bonding pad and a second bonding pad; electrically coupling the first bonding pad of the first semiconductor wafer to one of the plurality of bonding pads and the first semiconductor wafer a bonding pad is electrically coupled to the at least one second bonding pad of the plurality of bonding pads; coupling the first semiconductor wafer to the third bonding pad of the plurality of bonding pads by a first electrical connector; 156577.doc -4- 201212200 a first semiconductor wafer is coupled to the first electrical connector, the second semiconductor wafer has a first bonding pad and a second bonding pad; and the first bonding pad of the first semiconductor wafer a fourth bonding pad coupled to the plurality of bonding pads, electrically coupling the first bonding pad of the second semiconductor wafer to at least one fifth bonding pad of the plurality of bonding pads, and The second semiconductor wafer is coupled to a sixth bond pad of the plurality of bond pads by a second electrical connector. 9. The method of claim 8, further comprising: " coupling a third semiconductor wafer to the second electrical connector, the third semiconductor wafer having a first bond pad and a second bond pad; The first bond pad of the semiconductor wafer is electrically coupled to the seventh bond pad of the plurality of bond pads and electrically coupled to the first bond pad of the third semiconductor die to one of the plurality of bond pads; The third semiconductor wafer is bonded to one of the plurality of bond pads by a third electrical connector; and the fourth semiconductor wafer is coupled to the third electrical connector, the fourth semiconductor wafer has a first bonding pad and a second bonding pad; k the first bonding pad of the fourth semiconductor wafer is electrically coupled to the tenth bonding pad of the plurality of bonding pads and the first bonding pad of the fourth semiconductor wafer Electrically coupled to the eleventh bonding pad of the plurality of bonding pads; and bonding the fourth semiconductor wafer & to a twelfth bonding pad of the plurality of bonding pads by a fourth electrical connector. The method of claim 9 further includes lightly bonding a fifth semiconductor wafer to the fourth electrical connector. 156577.doc
TW100121480A 2010-09-15 2011-06-20 Semiconductor component and method of manufacture TWI532143B (en)

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