201207627 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種位址配置設備、系統及其方法。 【先前技術】 在一系統中，多個設備可能會耦接至一起。為 了能單獨擷取（access)每一設備，需要每一設備配 置（assign) —唯一識別碼（unique identifier)，例如，單 獨的位址。為了節省設備製造成本和時間，一般在 製造過程中，將這些設備採用同一種方式加工製 造，進而製造出彼此相同之設備。然而在操作過程 中，為了能夠擷取某一特定設備，需要分別對每一 設備配置一單獨的位址。並且，將這些設備整合至 一系統中時，一般就不需要考慮每一設備在系統中 的相應位置。因此，在製造設備的過程中，必須增 加額外的步驟以分別對每一設備配置單獨的位址， 然而增加額外的步驟將會增加製造時間，進而提高 製造成本。 【發明内容】 本發明要解決的技術問題在於提供一種位址配 置設備、系統及其方法，以於設備整合至系統後， 後，再對設備進行位址配置。 本發明提供了一種位址配置設備，包括：一第 一串列輸入埠，接收一串列資料；一第一串列輸出 0690-TW-CH Spec+Ciaim(fi!ed-20100802).doc 4201207627 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to an address configuration apparatus, system and method therefor. [Prior Art] In a system, multiple devices may be coupled together. In order to be able to access each device individually, each device needs to be assigned—a unique identifier, for example, a separate address. In order to save equipment manufacturing costs and time, these devices are generally manufactured in the same way in the manufacturing process to produce the same equipment. However, in order to be able to retrieve a particular device during operation, a separate address is required for each device. Also, when integrating these devices into a system, it is generally not necessary to consider the corresponding location of each device in the system. Therefore, in the process of manufacturing the device, additional steps must be added to separately configure a separate address for each device, but adding additional steps will increase manufacturing time and thus increase manufacturing costs. SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to provide an address configuration device, a system, and a method thereof, after the device is integrated into the system, and then the device is configured with an address. The present invention provides an address configuration apparatus comprising: a first serial input port, receiving a series of data; a first serial output 0690-TW-CH Spec+Ciaim(fi!ed-20100802).doc 4
201207627 將串列資料輸出至與位 一位址配置吟供.咕 0直叹備耦接之一另 串列輸八埠：U一移位暫存器，接收自第-调八崢之串列資料，·一第一 流排控制器，接收自 β ，以及一匯 並依撼h丨⑨自第i m人埠之串列資料， 並依據串列資料，控制第一多工器 ：： 輸出埠選擇性祕說 將第一串列 避禪『 生地耦接至第一串列輸入埠 暫存Is，其中串列資料包括 < 一自都扔_E A "心頭指令段及 一：截奴，頭指令段包括一指令碼、一目標 相應新位址之錯誤H a括—新㈣及至少一 提供一種位址配置方法包括下列步 虫· 一位址配置設備接收一串列資料，其中 串列資料包括一命令之一頭指令段及一負‘段其： 中頭指令段包括一指令碼、一目標位址及一錯誤檢 „段至少包括一新位址及至少一相應新位 址之錯誤檢驗碼’其中新位址包含一第一位址；依 據頭指令段判斷第一位址配置設備是否為串列資料 之-目標設備；當第—位址配置設備為串列資料之 目標設備日夺，則將第一位址存入第一位址配置設 備；以及依據頭指令段將第一位址輸出至一第二位 址配置設備或將第一位址鎖存至第一位址配置設 備。 本發明更提供一種位址配置系統，包括多個位址 配置設備H主管理控制單元’耗接多個位址 配置設備之一第一位址配置設備’並提供一串列資 0690-TW-CH Spec+Claim(filed-20100802).d< 5 201207627 抖至第-位址配置設備’其 之頭指令段及一負載段，頭沪入化匕括命令 - 令段包括一指令碼、 目禚位址及一錯誤檢驗碼’負載段包 :二及至少-相應新位址之錯誤檢驗碼 ： :曰，至少一個多個位址配置設備存入或輸出各自 其中每一個多個位址配置設備包 第串列輸入埠，接收串列資料；一第一串 列輸出埠，將串列資料輸出至多個位址配置設備之 位：配置設備；一第一移位暫存器，接收自 第一串列輸入埠之串列資料；一第一多工器.以及 -匯流排控制器，接收自第一串列輸入槔之串列資 料’並依據串列資料控制第—多卫器，以將第一串 列輸出埠選擇性地耦接至第一串列輸入埠或第一移 位暫存器。 與現有技術相比，通過採用本發明之位址配置設 備、系統及其方法，可以實現在製造階段統一製造 設備，而無需增加額外的步驟來對設備單獨設置位 址。因此，即可促進成本的降低並加速製造流程。 此外，多個大致相同的設備可以以一種基本隨機的 ••人序整合在一起後，即可對這些設備配置位址，進 而可以實現大量生產大致相同的設備，以降低生產 成本。再者’透過連續對這些設備進行位址配置， 進而減少每一設備之埠數量，並且可以減少在積體電 路上實現設備之接腳數量，進而降低生產成本。 0690-TW-CH Spec+Claim(filed-20100802).d( 6 201207627 【實施方式】 以下將對本發明的實施例 明將結合實施例進行闡述，值應理;這=:= 限定於這些實施例。相反地二2非幻日將本發明 專利範圍所界定的本發明精神圍=涵盖由後附申請 化、修改和均等物。和申和範圍内所定義的各種變 此外，在以下對本發明的詳細描述中，為了提201207627 Output serial data to the bit address configuration. 咕0 sighs one of the sighs and connects to the other eight: U-shift register, received from the first-to-eighth series Data, · a first flow controller, received from β, and a sink and rely on h丨9 from the first person's serial data, and according to the serial data, control the first multiplexer:: output 埠 selection The secret said that the first series of meditations are connected to the first serial input 埠 temporary storage Is, where the serial data includes < one throws _EA " heart command segment and one: interception, head The instruction segment includes an instruction code, an error corresponding to the target new address, a new (four), and at least one address providing configuration method includes the following step: The address configuration device receives a series of data, wherein the serial data The method includes a command header segment and a negative segment segment: the middle header segment includes an instruction code, a target address, and an error check segment including at least a new address and at least one corresponding new address error check code. The new address includes a first address; Whether the address configuration device is the target device of the serial data; when the first address configuration device is the target device of the serial data, the first address is stored in the first address configuration device; The instruction segment outputs the first address to a second address configuration device or latches the first address to the first address configuration device. The invention further provides an address configuration system, including multiple address configuration devices H The main management control unit 'supplied one of the multiple address configuration devices, the first address configuration device' and provides a series of columns 0690-TW-CH Spec+Claim(filed-20100802).d< 5 201207627 Shake to the first - The address configuration device's head instruction segment and a load segment, the header includes a command code, a directory address, and an error check code 'load segment packet: two and at least - corresponding new Address error check code: :曰, at least one of the multiple address configuration devices stores or outputs each of the plurality of address configuration device packets, the serial input, the received serial data; a first serial output埠, output serial data to multiple address configurations Device position: a configuration device; a first shift register, receiving serial data from the first serial input; a first multiplexer; and a bus controller receiving the first serial input The serial data 'and controls the first multi-guard according to the serial data to selectively couple the first serial output 至 to the first serial input 埠 or the first shift register. In contrast, by using the address locating device, system and method thereof of the present invention, it is possible to realize uniform manufacturing of the device at the manufacturing stage without adding an extra step to separately set the address of the device. Therefore, the cost reduction can be promoted. Accelerate the manufacturing process. In addition, multiple roughly identical devices can be integrated into a single, random human sequence to configure addresses for these devices, enabling mass production of roughly the same equipment to reduce production costs. . Furthermore, by continuously arranging the addresses of these devices, the number of devices per device is reduced, and the number of pins of the devices on the integrated circuit can be reduced, thereby reducing the production cost. 0690-TW-CH Spec+Claim(filed-20100802).d (6 201207627 [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the embodiments, and the values are reasonable; this =:= is limited to these embodiments. In contrast, the present invention is defined by the scope of the invention, which is defined by the scope of the invention, including the appended claims, modifications and equivalents, and various modifications as defined in the scope of the invention. In the detailed description, in order to mention
ί發明的完全的理解，提供了大量的具體細節。_，於 ^技=域中具有通常知識者將理解，沒有這些具體細 發明同樣可以實施。在另外的—些實例中，對於大 豕熟知的方法、程序、元件和電路未作詳細描述，以便於 凸顯本發明之主旨。 本發明闡述了 -種在系統中互_接之多個設備進 仃位址配置之裝置、系統及其方法。這些設備包括至少一 串列輸入料至少-串缝料備财他設備及 /或主控制器接收-串列資料，並通過串列埠將接收到之串 列k料提供給另一個設備。如此所述，應對這些設備的位 址進行連續配置。例如，對電池管理系統之多&設備進行 位址配置。 圖1所示為根據本發明一實施例之垂直匯流排系統電 路(vertical bus system circuitry) 100 的示意圖。在本實施例 中’垂直匯流排系統電路100配置以非公共接地 (non-common ground)的垂直匯流排形式為例。垂直匯流排 系統電路100將包括多個設備102。每一設備（device)1〇2 包括一設備電路（device circuitry)。在一實施例中，垂直匯 0690-TW-CH Spec+Claim(filed-20100802).doc 7 201207627 流排系統電路100可能包括N個設備（設備卜設備2、.·.、 設備N)。為了便於描述，在描述特定設備時，使用“設備 X”表示該設備，其中X表示1、2、…、N。而在描述多個 設備中的任一個時，則使用“設備102”表示該設備。 每一設備102可包括一第一串列輸入埠（serial input port) 110，一第一串列輸出槔（serial output port)l 12，一第 二串列輸入埠114和一第二串列輸出埠116。串列輸入蟑 110和114接收一串列資料（serial data)。串列輸出埠112 和116輸出串列資料（serialdata)。串列資料可包括發送至 設備102之命令、由設備102發出之回應、及/或與命令或 回應相關之資料。在一實施例中，串列資料可包括一種具 有一頭指令段（command section)和一負載段（payload section) 之一命令。頭指令段可包括一指令碼（command code)、一 目標位址（target address)和一錯誤檢驗碼（error check)。在一 實施例中，可由與目標位址相對應位址之設備102執行與 某條指令相對應之指令碼。錯誤檢驗碼可為一檢驗接收到 的命令是否完整和正確之封包錯誤檢驗碼（packet erroi· check)。目標位址可對應於單一個設備l〇2或可對應於多 個設備，例如，可以是多個設備響應之一廣播設備位址 (broadcast device address)。頭指令段也可以包括其他—些習 知的指令。負載段可包括如前所述之資料。 垂直匯流排系統電路100可包括一主控制器電路（卜〇贫 controller circuitry)，例如，主管理控制單元1〇4。主管理抑 制單元104可包括一記憶體105，其係存儲如前所述的命 令或資料。主管理控制單元104可和設備1〇2之串列輪入 0690-TW-CH Spec+Claim(filed-20100802).doc 8 201207627 埠和串列輸出埠耦接。在一實施例中，主管理控制單元104 可與設備1之第一串列輸入埠11〇和第二串列輸出埠116 耦接。主管理控制單元104可透過串列輸入埠110、114 及串列輸出埠112、116，將串列資料（如前所述之命令）發 送至一或多個設備102，並從一或多個設備102接受串列 資料（設備回應）。 每一設備102可透過串列輸入埠110、114及串列輸出 埠112、116與至少一其他設備102耦接。在一實施例中， • 設備1之第一串列輸出埠112與設備2之第一串列輸入埠 110耦接，並且設備2之第二串列輸出埠116與設備1之 第二串列輸入埠114耦接。這種耦接的方式可以應用於N 個設備中的每對耦接設備102。在一些實施例中，設備N 的第一串列輸出埠112和第二串列輸入埠114也可以彼此 斷開。 每一設備102可包括一匯流排控制器ι〇6〇在配置上， 匯流排控制器106與串列輸入埠11〇、114及串列輸出槔 參 112、U6耦接。匯流排控制器106從主管理控制單元1〇4 接收命令，並根據接收到的命令控制設備1〇2 ^換言之， 匯流排控制器106從主管理控制單元1〇4接收包括命令之 串列資料，並解釋（interpret)接收到之命令，例如，對接 收到之命令進行解碼，並基於接收到及被解釋之命令控制 設備102。 每一設備102可包括至少一組位準移位器〇evd shifter)108a和l〇8b。位準移位器組1〇如和1〇8b可對非公 共接地系統（垂直匯流排系統電路）1〇〇中之多個設備 0690-TW-CH Spec+Claim(filed-201〇〇8〇2).doc 201207627 之間進行電壓轉換。在一實施例中，位準移位器l〇8a可與 某一設備102之第一輸出埠112耦接，第二位準移位器 108b可與該設備102之第二串列輸入埠ι14耦接。位準移 位器108a和108b可保護設備102使其避免因耗接設備， 例如’設備1和設備2之間的電位不等（unequal pQtentials) 而受到損害。當第一設備（例如，設備1)與第二設備（例 如，設備2)耦接時，每個位準移位器組1〇8a和1〇8b可 將第一設備之電壓位準（voltage level)轉換成與第二設備 相對應之電壓位準。 每一設備102更包括至少一移位暫存器（shift register) 和至少一多工器（multiplexer)。在一實施例中，垂直匯流排 系統電路100中的每一設備102包括一第一移位暫存器 120、一第一多工器122' —第二移位暫存器124和一第二 多工器126。每一設備1〇2更包括一開關128。第一移位 暫存器120與與第-串列輸入埠11〇祕，並與第一串列 輸出琿112選擇性地搞接。在一實施例中，匯流_㈣ 106可控制第-多工器122進而將第一移位暫存器12〇或 第-丰列輸入蟑uo選擇性地與第—串列輸出痒ιΐ2輛 接。匯流排控制H 106可依據主管理控制單元1〇4所發送 的：令虫控制第-多工請。當第一設備（例如設備υ j-串列輸入琿110與第-設備之第一串列輸ι2 減，則主管理控制單元104之串列資料將輪出至與第一 設備之第-串列輸入槔112相接之第二設備之第一申列輸 入埠，例如，設備2之第一串列輸入物。當第一設備 之第一移位暫存器⑼耗接於第—串列輸出，則 0690-TW-CH Spec+Claim(filed-20100802).d〇( 10 201207627 ί與;位暫存器120所發出之串列資料將輸出 ，第-攻備之第—串列輸糾112_之第二設備之第 一串列輸入槔’例如，設備2之第-串列輸入蟑110。The full understanding of the invention has provided a large amount of specific details. _, who has the usual knowledge in the domain = will understand that no specific invention can be implemented. In other instances, well-known methods, procedures, components, and circuits have not been described in detail in order to facilitate the invention. The present invention describes an apparatus, system, and method for interfacing a plurality of devices in a system. The apparatus includes at least one series of input materials at least - a series of stock preparation devices and/or a main controller receiving - serial data, and the received series of materials received to the other device through the serial port. As described, the addresses of these devices should be continuously configured. For example, address configuration of multiple & devices in a battery management system. 1 is a schematic diagram of a vertical bus system circuitry 100 in accordance with an embodiment of the present invention. In the present embodiment, the vertical busbar system circuit 100 is configured in the form of a non-common ground vertical busbar. The vertical busbar system circuit 100 will include a plurality of devices 102. Each device 1〇2 includes a device circuitry. In one embodiment, the vertical sink 0690-TW-CH Spec+Claim(filed-20100802).doc 7 201207627 The shunting system circuit 100 may include N devices (devices, devices 2, . . . , devices N). For convenience of description, when describing a specific device, "device X" is used to denote the device, where X denotes 1, 2, ..., N. Whereas in describing any of a plurality of devices, "device 102" is used to indicate the device. Each device 102 can include a first serial input port 110, a first serial output port 12, a second serial input port 114, and a second serial output.埠116. Serial input ports 110 and 114 receive a serial data. The serial output ports 112 and 116 output serial data (serialdata). The serial data may include commands sent to device 102, responses sent by device 102, and/or materials related to commands or responses. In an embodiment, the serial data may include a command having a command section and a payload section. The header segment can include a command code, a target address, and an error check. In one embodiment, the instruction code corresponding to an instruction may be executed by device 102 corresponding to the address of the target address. The error check code can be a packet erroi check that verifies that the received command is complete and correct. The target address may correspond to a single device 〇2 or may correspond to multiple devices, for example, may be one of a plurality of device responses, a broadcast device address. The header segment can also include other - some conventional instructions. The load segment can include information as previously described. The vertical busbar system circuit 100 can include a main controller circuit (e.g., main management control unit 〇4). The master management suppression unit 104 can include a memory 105 that stores commands or materials as previously described. The main management control unit 104 can be coupled to the serial port 0690-TW-CH Spec+Claim(filed-20100802).doc 8 201207627 and the serial output port of the device 1〇2. In an embodiment, the primary management control unit 104 can be coupled to the first serial input port 11 and the second serial output port 116 of the device 1. The main management control unit 104 can send the serial data (command as described above) to one or more devices 102 through the serial input ports 110, 114 and the serial output ports 112, 116, and from one or more Device 102 accepts the serial data (device response). Each device 102 can be coupled to at least one other device 102 via serial input ports 110, 114 and serial output ports 112, 116. In an embodiment, the first serial output port 112 of the device 1 is coupled to the first serial port input port 110 of the device 2, and the second serial port output port 116 of the device 2 is coupled to the second string of the device 1. The input port 114 is coupled. This manner of coupling can be applied to each of the N devices. In some embodiments, the first serial output port 112 and the second serial port input port 114 of device N may also be disconnected from each other. Each device 102 can include a bus controller 〇6〇 in configuration, and the bus controller 106 is coupled to the serial inputs 〇11〇, 114 and the serial output ports 112, U6. The bus controller 106 receives the command from the main management control unit 〇4 and controls the device according to the received command. In other words, the bus controller 106 receives the serial data including the command from the main management control unit 1-4. And interpret the received command, for example, decoding the received command and controlling the device 102 based on the received and interpreted command. Each device 102 can include at least one set of level shifters 〇evd shifters 108a and 108b. The level shifter group 1 and, for example, 1〇8b can be used for non-common grounding systems (vertical busbar system circuits). Multiple devices 0690-TW-CH Spec+Claim (filed-201〇〇8〇) 2) Voltage conversion between .doc 201207627. In an embodiment, the level shifter 108a can be coupled to the first output port 112 of a device 102, and the second level shifter 108b can be coupled to the second string of the device 102. Coupling. The level shifters 108a and 108b can protect the device 102 from damage due to consuming devices such as 'unequal pQtentials' between device 1 and device 2. When the first device (eg, device 1) is coupled to the second device (eg, device 2), each level shifter group 1〇8a and 1〇8b can set the voltage level of the first device (voltage) Level) is converted to a voltage level corresponding to the second device. Each device 102 further includes at least one shift register and at least one multiplexer. In one embodiment, each device 102 in the vertical busbar system circuit 100 includes a first shift register 120, a first multiplexer 122' - a second shift register 124 and a second Multiplexer 126. Each device 1〇2 further includes a switch 128. The first shift register 120 is secreted from the first-serial input port 11 and selectively coupled to the first serial output port 112. In one embodiment, the sink_(four) 106 can control the first-multiplexer 122 to selectively connect the first shift register 12 or the first-rich column input 蟑uo to the first-line output itch ΐ2 . The bus control H 106 can be sent according to the main management control unit 1〇4: the worm controls the first-multiple application. When the first device (for example, the device υ j-serial input 珲 110 and the first serial device of the first device are subtracted, the serial data of the primary management control unit 104 will be rotated to the first string of the first device The first input port of the second device to which the column input port 112 is connected, for example, the first serial input of the device 2. When the first shift register (9) of the first device is consumed by the first string Output, then 0690-TW-CH Spec+Claim(filed-20100802).d〇( 10 201207627 ί;; the serial data sent by the bit register 120 will be output, the first - the first of the attack - serial transmission and correction The first serial input of the second device of 112_ is, for example, the first-serial input 蟑110 of device 2.
、㈣位暫存器124與第二串列輸入埠114搞接，並 選擇性地與第二串列輸糾116輕接。在一實施例中，匯 流，控制器106可控制第二多工器126進而將第二移位暫 存器124或第二串列輸入埠114選擇性地與第二串列輸出 埠116耦接。匯流排控制器1〇6可基於主管理控制單元1〇4 之命令控制第二多工器126。 開關128可控制第一串列輸入崞no與第二多工器 126之輸入端之間是否耦接。透過開關128的控制，第二 多工器126則可將第一串列輸入埠11〇與第二串列輸出埠 116耦接》匯流排控制器1〇6可控制開關128和第二多工 器126之狀態。開關128亦可測試多個設備1〇2間之連 關係。 此外，垂直匯流排系統1〇〇可與一電池組13〇耦接。 電池組130可包括多個電池單元。在一實施例中，電池組 130可包括鐘電池（Lithium-Ion)、鎳氫電池（Nickd_Metal Hydride)、鉛酸電池（Lead Acid)、燃料電池（Fuei cell)、超 級電容器（Super Capacitor)或一些其他能量存儲單元。其 中，部分電池單元可與多個設備102中的每一設備輕接。 設備102可檢測與該部分電池單元相關的參數。這些參數 可能包括電池單元溫度、及/或電池單元電壓、及/或電池 單元電流等。設備102可將測量到之參數提供給主管理控 制單元104。在一實施例中，可以透過第二串列輸出埠116 0690-TW-CH Spec+C!aim(filed-20100802).d< 11 201207627 將包含測量到之參數的串列資料提供給主管理控制I& 104。 因此，垂直匯流排系統電路100可為主管理控制單元 104和多個設備102之間提供串列資料通信。優點在於， 透過串列資料通信的方式可以減少每個設備蟫的數量 (number of ports)。進而降低生產成本，例如，透過減少在 積體電路上實現設備102之接腳數量（number of Pins)，進 而降低生產成本。 圖2A所示為根據本發明一實施例之鏈式系統電路 (daisy chain system circuitry)200 的示意圖。圖 2B 所示為根 據本發明另一實施例之鏈式系統電路250的示意圖。在實 施例200和250中，相同的元件具有相同的參考標識。根 據所述實施例的系統電路200和250都配置為鏈式結構。 圖2A所示的鏈式系統200的配置為非公共接地式，而圖 2B所示的鏈式系統250的配置為公共接地式。 鏈式系統200和250各包含多個設備202。每一設備 202包含設備電路。例如，鏈式系統200和250各自包含 N個設備：設備1 ’設備2、…、設備n。每一設備202 可包括一接收串列資料之串列輸入埠210和一輸出串列資 料之串列輸出埠212。串列資料可包括發送至設備202之 命令、由設備102發出之回應及/或與命令或回應相關之資 料。 在實施例中，鏈式系統200包括一主管理控制單元 104。每一設備202轉接於至少一其他設備202。至少·-設 備202耦接於主管理控制單元1〇4。第一設備之串列輸入 0690-TW-CH Spec+Claim(filed-20100802).doc 201207627 槔210耗接於主管理控制單元i〇4或第二設備202之串列 輸出槔212。第一設備之串列輸出埠212耦接於第二設備 202之串列輸入埠21〇或主管理控制單元1〇4<>舉例來說， 在鍵式系統200和25〇中，設備1之串列輸入埠21〇搞接 於主管理控制單元104，並且設備1之串列輸出埠212耦 接於設備2之串列輸入埠210。後續設備將可按此方式進 行配置和連接，其中設備N之串列輸出埠212耦接於主管 理控制單元104。 圖2A所示的鏈式系統200更包括多個隔離體 (isolator)230a ’ 230b，230c、…、和 230η。隔離體 230a， 230b、230c、...、和230η分別耦接於設備N和主管理控 制單元104之間以及多個設備202之間。在每一設備2〇2 之第一串列輸出埠與另一設備202之第一串列輸出埠或主 管理控制單元104之間都會搞接一隔離體。與圖丨中之位 準移位器類似，當耗接於鏈式系統中之多個設備2〇2沒有 公共接地時，則隔離體230a，230b，230c、…、和230η 隔離電位不等之多個設備202。 在一實施例中，鍵式系統200和250分別輕接於電池 組130。電池組130可包括多個電池單元。其中，部分電 池單元可分別與多個設備202中的每一設備耦接。這些設 備202可檢測耦接之電池單元之相關參數，並且將檢 之參數輸出至主控制管理單元104。在一實施例中，可透 過串列輸出槔將包含測量參數之串列資料輸出至主管理 控制單元104。 母一設備202可包括匯流排控制器2〇6、移位暫存器 0690.TW-CH Spec+Claim(filed-20100802).doc 13 201207627 220和多工器222。匯流排控制器讓輕接於串列輸入谭 210。移位暫存器220耗接於串列輸入埠21〇。多工器a] 選擇性地將串列輸出蟫212麵接至移位暫存_ 22〇或串列 輸入璋210。基於主管理控制單幻〇4之命令，匯流排控 制器206可控制多工器222，將移位暫存器22〇或串列輸 入埠210耦接至串列輸出埠212。 圖3A所示為根據本發明一實施例之系統（例如，系統 100、200及/或250)中之多個設備位址配置之一或多個命 令所對應之資料結構300。圖3B所示為根據本發明一實施 例之系統（例如，系統1〇〇、2〇〇及/或250)中之某個設備 更換位址之一或多個命令所對應的資料結構35〇。一或多 個命令所對應之資料結構300和35〇分別包含多個攔位。 在一貫施例中，每一攔位的長度為8bit。一或多個命令所 對應之資料結構300和350分別包含頭指令段3i〇a、310b 以及負載段320a、320b。頭指令段31〇a、310b分別包含 多個攔位，例如指令碼312a、312b，目標位址314a、314b 和封包錯誤檢驗碼316a、316b。指令碼312a、312b包含 發送至設備的指令，並由匯流排控制器進行解釋。在一實 施例中，目標位址，例如，目標位址314a，可以是一配置 於系統中多個設備之廣播位址。在另一實施例中，目標位 址314b，可以為系統中某個設備單獨配置之位址。封包錯 誤檢驗碼316a和316b可進行錯誤檢驗(err〇r check)，進而 確認是否正確地接收到頭指令段3i〇a和310b。 命令300係對耦接於系統中之多個設備配置新位址。 在一實施例中，在製造過程中，已為這些設備分別配置非 0690-TW-CH Spec+Claim(filed-20100802).doc 14 201207627 唯一之位址。負載段320a包含系統中多個設備之新位址 322a(第N個設備位址）、…、322η(第1個設備位址）及錯 誤檢驗碼324a、…、324η。每個位址對應一相應之封包錯 誤檢驗碼324a ' 324b、...、或324η。設備Ν之位址322a 和封包錯誤檢驗碼324a列為第一組，且設備1之位址322n 和封包錯誤檢驗碼324η列為最後一組。換言之，當一個 命令（例如命令300)連續發送時，則先接收頭指令段 310a，接著接收負載段320a。在負載段320a中，將先接 收到第N個設備對應之位址322a，接著收到與位址322a 對應之封包錯誤檢驗碼324a。之後再收到第N-1個設備對 應的位址322b，接著收到與位址322b對應之封包錯誤檢 驗碼324b。以此類推’直至收到設備1對應之位址322η 以及與位址322η對應之封包錯誤檢驗碼324η。位址322a， 322b、…、322η之排列順序符合系統100，2〇〇和250的 構架，並且主管理控制單元1〇4與設備1耦接。在其他實 施例中，負載段320a可能存在其他排列順序，以及與此 相對應之系統結構亦可被實施，仍然屬於本發明之範鳴。 命令350係對某一設備配置（意即更換）一新位址，進而 替換掉已存在之舊位址。 命令300可分別對系統1〇〇、2〇〇和250中多個設備 配置初始化位址。命令350可分別對系統1〇〇、2〇〇和250 中的一或多個没備更換相應之位址。如此，當設備已被整 合至系統中後，即可為每一設備配置相應之位址。 圖4A所示為根據本發明一實施例之由主管理控制單 元104執行對多個設備配置初始位址及/或對某個設備單 0690-TW-CH Spec+Claim(fi!ed-20 ] 00802).d< 201207627 獨更換位址之示範操作流程圖4〇〇。圖4B所示為根據本發 明一實施例之由系統（例如，系統100、200或250)之設備 所執行之操作流程圖43〇。在此可假設在由流程圖4〇〇和 430所描述的操作過程之前，已對系統（例如，系統1〇〇， 200或250)耦接了多個設備， 首先請參照圖4A所示，在步驟405中，該程式流程 啟動。在步驟410中，發送命令以配置一位址或多個位 址。前述命令可由主管理控制單元104發送至與主管理控 制單元104輕接之某一設備（例如，設備丨）^在一實施例 中，發出之命令300可包括指令碼312a，其係將多個位址 進行配置，並包括一對應於所有設備之位址，例如，廣播 位址。在這個例子中，可以假設主管理控制單元“知道，，系 統中的每一設備對應的序號（1〜Ν)β由此，負載段32〇a包 括對系統巾之每—設備進行位址配置之位址内容和相應 之錯誤檢驗碼。在另一實施例中，發出之命令35〇可包括 指令碼312b，其係將某—設備之原有位址更換為一個新的 預設位址。命令350之負載段320b包含目標設備之一預 設位址322及對應之封包錯誤檢測碼334。由此，頭指令 段包含對應於設備原有位址（目標位址）314b之位址内 容。當命令300或350發出後，在步驟415中，發送一個 結束標諸（endflag)。該結束標諸可告知匯流排控制器，該 命令已經被完成。程式流程即在步驟42〇姓束。 接著，請參照圖術斤示，在步驟^中，程式流程 啟動。在步驟440中，由某-設備收到命令，例如命令· 或命令350之頭指令段，例如31〇&或鳩。在步驟州 0690-TW-CH Spec+Claim(filed-20100802).doc 16 201207627 ㈣之指令是否為目標指令。在—實施例中， mL. $透過解和貞指令段和位址欄位 ，進而判斷該 人1 器之關聯設備（收到命令之設備）是否是該命 I日又備。當該匯流排控制器之關聯設備不是該命令 厂X備時’則進行步驟45。，其中匯流排控制器將會 、j命令。之後，程式流程將在步驟455結束。The (four) bit register 124 is coupled to the second serial input port 114 and is selectively coupled to the second serial line input and error 116. In one embodiment, the controller 106 can control the second multiplexer 126 to selectively couple the second shift register 124 or the second serial input port 114 to the second serial output port 116. . The bus controller 1〇6 can control the second multiplexer 126 based on the command of the main management control unit 1〇4. Switch 128 can control whether a coupling between the first serial input 崞no and the input of second multiplexer 126 is coupled. Through the control of the switch 128, the second multiplexer 126 can couple the first serial input 埠11〇 with the second serial output 埠116. The busbar controller 1〇6 can control the switch 128 and the second multiplexer. The state of the device 126. Switch 128 can also test the relationship between multiple devices 1〇2. In addition, the vertical busbar system 1 can be coupled to a battery pack 13A. Battery pack 130 can include a plurality of battery cells. In an embodiment, the battery pack 130 may include a Lithium-Ion, a Nickel_Metal Hydride, a Lead Acid, a Fuei cell, a Super Capacitor, or some Other energy storage units. A portion of the battery cells can be lightly coupled to each of the plurality of devices 102. Device 102 can detect parameters associated with the portion of the battery unit. These parameters may include battery cell temperature, and/or battery cell voltage, and/or battery cell current. Device 102 can provide the measured parameters to primary management control unit 104. In an embodiment, the serial data including the measured parameters can be provided to the main management control through the second serial output 埠116 0690-TW-CH Spec+C!aim(filed-20100802).d< 11 201207627 I& 104. Thus, the vertical busbar system circuit 100 can provide serial data communication between the main management control unit 104 and the plurality of devices 102. The advantage is that the number of ports per device can be reduced by means of serial data communication. This in turn reduces production costs, for example, by reducing the number of pins of the device 102 on the integrated circuit, thereby reducing production costs. 2A is a schematic diagram of a daisy chain system circuitry 200 in accordance with an embodiment of the present invention. 2B is a schematic diagram of a chain system circuit 250 in accordance with another embodiment of the present invention. In the embodiments 200 and 250, the same elements have the same reference design. The system circuits 200 and 250 according to the embodiment are configured in a chain structure. The configuration of the chain system 200 shown in Fig. 2A is a non-common grounding type, and the configuration of the chain system 250 shown in Fig. 2B is a common grounding type. Chain systems 200 and 250 each include a plurality of devices 202. Each device 202 contains device circuitry. For example, chain systems 200 and 250 each include N devices: device 1 'device 2, ..., device n. Each device 202 can include a serial input port 210 for receiving serial data and a serial output port 212 for outputting serial data. The serial data may include commands sent to device 202, responses sent by device 102, and/or information related to commands or responses. In an embodiment, the chain system 200 includes a master management control unit 104. Each device 202 is switched to at least one other device 202. At least the device 202 is coupled to the main management control unit 1〇4. The serial input of the first device 0690-TW-CH Spec+Claim(filed-20100802).doc 201207627 槔210 is consumed by the serial management output 212 of the main management control unit i〇4 or the second device 202. The serial output port 212 of the first device is coupled to the serial input port 21 of the second device 202 or the main management control unit 1 〇 4 <> For example, in the key systems 200 and 25, device 1 The serial input port 21 is connected to the main management control unit 104, and the serial output port 212 of the device 1 is coupled to the serial input port 210 of the device 2. Subsequent devices will be configurable and connected in this manner, with serial output 212 of device N coupled to the supervisor control unit 104. The chain system 200 shown in Fig. 2A further includes a plurality of isolators 230a' 230b, 230c, ..., and 230n. The spacers 230a, 230b, 230c, ..., and 230n are respectively coupled between the device N and the main management control unit 104 and between the plurality of devices 202. A spacer is interposed between the first serial output of each device 2〇2 and the first serial output of the other device 202 or the primary management control unit 104. Similar to the level shifter in Figure ,, when the multiple devices 2〇2 in the chain system are not connected to the common ground, the isolation bodies 230a, 230b, 230c, ..., and 230η have different isolation potentials. A plurality of devices 202. In one embodiment, the key systems 200 and 250 are lightly coupled to the battery pack 130, respectively. Battery pack 130 can include a plurality of battery cells. Wherein, some of the battery units are respectively coupled to each of the plurality of devices 202. These devices 202 can detect the relevant parameters of the coupled battery cells and output the detected parameters to the main control management unit 104. In one embodiment, the serial data containing the measurement parameters can be output to the main management control unit 104 via the serial output. The parent device 202 can include a bus controller 2〇6, a shift register 0690.TW-CH Spec+Claim (filed-20100802).doc 13 201207627 220, and a multiplexer 222. The bus controller allows the light to be connected to the Tan 210. The shift register 220 is consumed by the serial input port 21〇. The multiplexer a] selectively connects the serial output port 212 to the shift register _ 22 〇 or the string input 璋 210. Based on the command of the master management control single phantom 4, the bus controller 206 can control the multiplexer 222 to couple the shift register 22 or the serial input port 210 to the serial output port 212. 3A shows a data structure 300 corresponding to one or more of a plurality of device address configurations in a system (e.g., systems 100, 200, and/or 250) in accordance with an embodiment of the present invention. 3B shows a data structure corresponding to one or more of a device replacement address in a system (eg, system 1, 2, and/or 250) in accordance with an embodiment of the present invention. . The data structures 300 and 35's corresponding to one or more commands respectively contain a plurality of blocks. In a consistent example, each block is 8 bits in length. Data structures 300 and 350 corresponding to one or more commands include header segments 3i〇a, 310b and load segments 320a, 320b, respectively. The header segments 31A, 310b each include a plurality of intercept bits, such as instruction codes 312a, 312b, target addresses 314a, 314b, and packet error check codes 316a, 316b. The instruction code 312a, 312b contains instructions sent to the device and is interpreted by the bus controller. In one embodiment, the target address, e.g., target address 314a, may be a broadcast address of a plurality of devices configured in the system. In another embodiment, the target address 314b can be a separately configured address for a device in the system. The packet error check codes 316a and 316b can perform an error check (err〇r check) to confirm whether the header segments 3i〇a and 310b are correctly received. The command 300 configures a new address for a plurality of devices coupled to the system. In one embodiment, the unique addresses of the non-zero 690-TW-CH Spec+Claim(filed-20100802).doc 14 201207627 have been configured for each of these devices during the manufacturing process. The load segment 320a contains new addresses 322a (the Nth device address), ..., 322n (the first device address) and error check codes 324a, ..., 324n of a plurality of devices in the system. Each address corresponds to a corresponding packet error check code 324a '324b, ..., or 324n. The device 位 address 322a and the packet error check code 324a are listed as the first group, and the device 1 address 322n and the packet error check code 324η are listed as the last group. In other words, when a command (e.g., command 300) is continuously transmitted, the header instruction segment 310a is received first, followed by the load segment 320a. In the load segment 320a, the address 322a corresponding to the Nth device is received first, and then the packet error check code 324a corresponding to the address 322a is received. Then, the address 322b corresponding to the N-1th device is received, and then the packet error check code 324b corresponding to the address 322b is received. And so on until the address 322n corresponding to the device 1 and the packet error check code 324n corresponding to the address 322n are received. The order of the addresses 322a, 322b, ..., 322n is in accordance with the architecture of the systems 100, 2, and 250, and the main management control unit 1-4 is coupled to the device 1. In other embodiments, the load segment 320a may have other order of arrangement, and the system structure corresponding thereto may also be implemented, and still belong to the fan of the present invention. The command 350 configures (i.e., replaces) a new address for a device, thereby replacing the existing old address. Command 300 can configure initialization addresses for multiple devices in systems 1, 〇〇, 2, and 250, respectively. The command 350 may replace one or more of the systems 1〇〇, 2〇〇, and 250 with the corresponding addresses. Thus, once the device has been integrated into the system, each device can be configured with the appropriate address. 4A illustrates the configuration of an initial address for a plurality of devices by the primary management control unit 104 and/or a single device 0690-TW-CH Spec+Claim(fi!ed-20] by the primary management control unit 104, in accordance with an embodiment of the present invention. 00802).d< 201207627 Demonstration operation flow chart of the replacement address 4〇〇. Figure 4B shows an operational flow diagram 43A performed by a device of a system (e.g., system 100, 200, or 250) in accordance with an embodiment of the present invention. It can be assumed herein that a plurality of devices have been coupled to the system (eg, system 1, 200 or 250) prior to the operational procedures described by flowcharts 4 and 430, first referring to FIG. 4A, In step 405, the program flow starts. In step 410, a command is sent to configure a single address or multiple addresses. The foregoing commands may be sent by the primary management control unit 104 to a device (e.g., device) that is lightly coupled to the primary management control unit 104. In one embodiment, the issued command 300 may include an instruction code 312a that is multiple The address is configured and includes an address corresponding to all devices, for example, a broadcast address. In this example, it can be assumed that the primary management control unit "knows that the serial number (1 ~ Ν) β corresponding to each device in the system. Thus, the load segment 32 〇 a includes address configuration for each device of the system towel. The address content and the corresponding error check code. In another embodiment, the issued command 35〇 may include the instruction code 312b, which replaces the original address of the device with a new preset address. The load segment 320b of the command 350 includes one of the target device preset addresses 322 and the corresponding packet error detection code 334. Thus, the header instruction segment contains the address content corresponding to the device original address (target address) 314b. When the command 300 or 350 is issued, an endflag is sent in step 415. The end flag tells the bus controller that the command has been completed. The program flow is at step 42. Please refer to the figure, in step ^, the program flow starts. In step 440, a command is received by a device, such as a command or a command segment at the command 350, such as 31 〇 & or 鸠. Step State 0690-TW-CH Spec +Claim(filed-20100802).doc 16 201207627 (4) Whether the instruction is the target instruction. In the embodiment, mL. $ through the solution and the command segment and the address field, and then determine the associated device of the person (received If the command device is the same as the command I. When the associated device of the bus controller is not the command factory X, then proceed to step 45. The bus controller will be, j command. After that, the program The process will end at step 455.
當匯流排控制器之關聯設備是該命令之目標設備 、’則進行步驟460,其由匯流排控制器繼續接收負載段 之位址資訊。在—實闕巾，#鱗令是__命令（例 ^命令3GG)時，則匯流排控制器之關聯設備可被視為該命 =之目標設備。在另一實施例中，當命令（例如命令35〇) 才曰不之原位址資訊與匯流排控制器之關聯設備之位址相 1配時’則匯流排控制器之關聯設備可被視為該命令之目 才*设備。當命令是一廣播命令，並且指令碼表示對設備進 行位址配置時，則匯流排控制器將控制關聯設備中的元件 (例如’多工器和/或移位暫存器）。在步驟460中，匯流排 控制器將接收到之位址進行暫存(buffer)，例如，暫存至第 一移位暫存器中’並基於與接收到之位址相關聯之封包錯 誤檢驗碼，對該位址進行錯誤檢驗。 在步驟465中，判斷是否接收到結束標誌。當未收到 結束標誌時，則進行步驟470,其中設備將會輸出步驟460 所接收到之位址。接著，程式流程將回到步驟460，繼續 接收另一位址資訊。當收到結束標誌時，則進行步驟475， 則鎖存（latch)所收到之位址（作為該設備之新位址）。程式 流程將於步驟450處結束。 0690-TW-CH Spec+Claim(filed-20100802).doc 17 201207627 在一實施例中，如圖1和圖4B所示，其係為多個設 備依次進行位址配置之過程，詳細内容如下所述。首先， 通過配置多個設備102之第一多工器122進而將第一串列 輸入埠110與第-串列輸出蟫112麵接。主管理控制單元 1〇4發出頭指令段310a，其係指示多個位址資訊分別配置 至多個設備中。每-匯流排控卿可接收並解釋頭指 令段310a。之後，每一匯流排控制器1〇6即可控制第一多 工器122,以將第-移位暫存器12()祕至第一串列輸出 埠112。由此，设備1之第一移位暫存器丨2〇即可接收由 主官理控制單元104所發送之串列資料。之後，主管理控 制單元104即可開始發送負載段32〇a。在發送過程中，設 備1將首歧到配置設備N之第N個設備位址以及檢測該 第N個設備位址正確性之封包錯誤檢驗碼。第 N個之設備 位址將被輸入至設備1之第一移位暫存器12〇。主管理控 制單元104繼續發送負載段32〇a，即發送配置設備N_〗之 第N-1個設備位址及相應的封包錯誤檢驗碼。此後，設備 1將開始接收第N_1個設備位址，並將第N個設備位址輸 出至設備2，此時，尚未收到結束標誌。 在一實施例中，設備1之第一移位暫存器120可將第 N個设備位址以串列資料的方式發送至設備丨之第一多工 器122和第一串列輸出埠112。設備2之第一串列輸入埠 110耦合接於設備1之第一串列輸出埠112。之後，設備2 的第一移位暫存器12〇即可接收第n個之設備位址。之 後’該過程將繼續進行，直至設備N之第一移位暫存器12〇 收到配置設備N之第N個設備位址。此後，設備丨之第一 0690-TW-CHSpec+Ciaim(filed-20100802)4 18 201207627 移位暫存器120將收到配置設備1之第1個設備位址以及 所有設備之第一移位暫存器12〇都收到配置該設備之設備 位址。之後，將結束標誌發送至這些設備1〇2，其中，各 個設備102即可將暫儲於各第一移位暫存器ι2〇之位址進 行鎖存，以作為設備之新位址。 在另一實施例中’如圖2A及/或圖2B及圖4B所示， 為多個設備依次進行位址配置的過程如下所述。首先，通 過配置多個設備202之第一多工器222進而將第一串列輸 入埠210與第一串列輸入埠212耦接。串列輸入埠21〇與 設備202之匯流排控制器2〇6耦接。主管理控制單元ι〇4 發出頭指令段31〇a ’其係指示多個位址資訊分別配置入多 個設備中。每一匯流排控制器2〇6可接收並解釋頭指令段 310a。之後’每一匯流排控制器206即可控制多工器222， 以將第一移位暫存器220耦接至第一串列輸出琿212。由 此，設備1之第一移位暫存器220即可接收由主管理控制 單元104所發送之串列資料。之後，主管理控制單元1〇4 即可開始發送負載段320a。在發送過程中，設備丨將首先 收到配置設備N之第N個設備位址以及檢測該第N個設 備位址正確性之封包錯誤檢驗碼。第N個設備位址將被輸 入至設備1之第一移位暫存器22〇。主管理控制單元1〇4 繼續發送負載段320a，即發送配置設備N-1之第N-1個設 備位址及相應之封包錯誤檢驗碼。此後，設備1將開始接 收第N-1個設備位址，並將第；^個設備位址輸出至設備2, 此時’尚未收到結束標誌。 在一實施例中，設備1之第一移位暫存器22〇可將第 0690-TW-CH Spec+CIaim(filed-20100802).do< 201207627 N個叹備位址，以串列資料之方式發送至設備ι之第一多 工器222和第—串列輸出皡212。設備2之第-串列輸入 4 210耗接於設備1之第一串列輸出谭212。之後，設備 2之第移位暫存器22〇即可接收第N個設備位址。之後， 該過程將繼續進行，直至設備N之第-移位暫存器220收 到配置設備N之第N個設備位址。此後，設備1之第-移 位暫存器22G冑收到配置設備丨之第丨個設備位址以及其 後的所有設備的第—移位暫存器2 2 G都收到配置設備之設 備位址之後，將結束標誌發送至這些設備。各個設 備202即可將暫儲於各第一移位暫存器22〇中之位址進行 鎖存’作為該設備的新位址。 承上，基於命令3〇〇以及系統1〇〇、2〇〇及25〇的設 備配置結構’可在多個設備整合至系賊，❹個設備分 別配置新的唯—位址。每—設備之匯流排控制器可接收並 解釋自主管理控制單元之命令，並選擇性地料列輸出璋 搞接至串韻人料移位暫存^。移位暫存器可接收至少 -位址資訊，並且基於主管理控制單元之命令，輸出該位 址。 優點在於，在製造階段中，可以統一製造設備，而無 需對其單獨設置健。因此，即可促進成本崎低並加快 製造流程。多個大致相同的設備可以以—種基本隨機的次 序整合在一起後，即可對這些設備位址配置，從而實現 大量生產大致相同的設備，降低生產成本。此外，通過連 續對多個设備進行位址配置，可減少每個設備之埠數量， & @減少在積Hf： $ _L實現設備之接腳數量（number 〇f 0690-TW-CH Spec+Claim(filed-20100802).doc 20 201207627When the associated device of the bus controller is the target device of the command, then step 460 is performed, where the bus controller continues to receive the address information of the load segment. In the case of a real towel, if the #Scale command is a __ command (for example, the command 3GG), the associated device of the bus controller can be regarded as the target device of the command. In another embodiment, when the command (for example, the command 35〇) is not matched with the address of the associated device of the bus controller, the associated device of the bus controller can be regarded as For the purpose of the order * device. When the command is a broadcast command and the command code indicates that the device is addressed, the bus controller will control the components in the associated device (e.g., 'multiplexer and/or shift register). In step 460, the bus controller buffers the received address, for example, temporarily stored in the first shift register and based on the packet error check associated with the received address. Code, error checking the address. In step 465, it is determined whether an end flag is received. When the end flag is not received, then step 470 is performed in which the device will output the address received in step 460. The program flow then returns to step 460 to continue receiving another address information. When the end flag is received, then step 475 is performed to latch the received address (as the new address of the device). The program flow will end at step 450. 0690-TW-CH Spec+Claim(filed-20100802).doc 17 201207627 In an embodiment, as shown in FIG. 1 and FIG. 4B, it is a process in which a plurality of devices sequentially perform address configuration, and the details are as follows: Said. First, the first serial input port 110 is connected to the first serial output port 112 by arranging the first multiplexer 122 of the plurality of devices 102. The main management control unit 1〇4 issues a header instruction segment 310a indicating that a plurality of address information are respectively configured into a plurality of devices. Each of the bus masters can receive and interpret the head command segment 310a. Thereafter, each bus controller 1〇6 can control the first multiplexer 122 to secrete the first shift register 12() to the first serial output 埠112. Thus, the first shift register 设备2 of the device 1 can receive the serial data transmitted by the main official control unit 104. Thereafter, the primary management control unit 104 can begin transmitting the load segment 32〇a. During the transmission process, the device 1 will first discriminate to the Nth device address of the configuration device N and the packet error check code for detecting the correctness of the Nth device address. The Nth device address will be input to the first shift register 12 of device 1. The main management control unit 104 continues to send the load segment 32〇a, that is, the N-1th device address of the configuration device N_〗 and the corresponding packet error check code. Thereafter, device 1 will start receiving the N_1th device address and output the Nth device address to device 2, at which point the end flag has not been received. In an embodiment, the first shift register 120 of the device 1 can send the Nth device address to the first multiplexer 122 and the first serial output of the device in serial data. 112. The first serial input port 110 of the device 2 is coupled to the first serial output port 112 of the device 1. Thereafter, the first shift register 12 of the device 2 can receive the nth device address. Thereafter, the process will continue until the first shift register 12 of device N receives the Nth device address of configuration device N. Thereafter, the first 0690-TW-CHSpec+Ciaim(filed-20100802)4 18 201207627 shift register 120 of the device will receive the first device address of the configuration device 1 and the first shift of all devices. The device 12〇 receives the device address configuring the device. Thereafter, the end flag is sent to the devices 1〇2, wherein each device 102 can latch the address temporarily stored in each of the first shift registers to be the new address of the device. In another embodiment, as shown in FIG. 2A and/or FIG. 2B and FIG. 4B, the process of sequentially performing address configuration for a plurality of devices is as follows. First, the first serial input port 210 is coupled to the first serial input port 212 by configuring the first multiplexer 222 of the plurality of devices 202. The serial input 埠 21 耦 is coupled to the bus controller 2 〇 6 of the device 202. The main management control unit ι〇4 issues a header instruction segment 31〇a ’ which indicates that a plurality of address information are respectively configured in a plurality of devices. Each bus controller 2〇6 can receive and interpret the header segment 310a. Thereafter, each of the bus controllers 206 can control the multiplexer 222 to couple the first shift register 220 to the first serial output port 212. Thus, the first shift register 220 of the device 1 can receive the serial data transmitted by the primary management control unit 104. After that, the main management control unit 1〇4 can start transmitting the load segment 320a. During the transmission process, the device 首先 will first receive the Nth device address of the configuration device N and the packet error check code for detecting the correctness of the Nth device address. The Nth device address will be input to the first shift register 22 of device 1. The primary management control unit 1-4 continues to transmit the load segment 320a, i.e., transmits the N-1th device address of the configuration device N-1 and the corresponding packet error check code. Thereafter, device 1 will begin receiving the N-1th device address and output the first device address to device 2, at which point the end flag has not been received. In an embodiment, the first shift register 22 of the device 1 may use the 0690-TW-CH Spec+CIaim(filed-20100802).do< 201207627 N sigh address to serialize the data. The mode is sent to the first multiplexer 222 and the serial-to-serial output 212 of the device ι. The first-serial input 4 210 of device 2 is consuming the first tandem output tan 212 of device 1. Thereafter, the first shift register 22 of the device 2 can receive the Nth device address. Thereafter, the process will continue until the first shift register 220 of device N receives the Nth device address of configuration device N. Thereafter, the first shift register 22G of the device 1 receives the device address of the configuration device and the first shift register 2 2 G of all subsequent devices receives the device configuring the device. After the address, the end flag is sent to these devices. Each device 202 can latch the address temporarily stored in each of the first shift registers 22' as the new address of the device. In the above, the device configuration structure based on the command 3〇〇 and the systems 1〇〇, 2〇〇 and 25〇 can be integrated into the thief in multiple devices, and each device is configured with a new unique address. Each-device bus controller can receive and interpret the commands of the self-management control unit, and selectively output the output to the serial shift register. The shift register can receive at least - address information and output the address based on a command from the primary management control unit. The advantage is that in the manufacturing phase, the equipment can be manufactured uniformly without having to set it up separately. As a result, cost reductions and manufacturing processes can be accelerated. Multiple roughly identical devices can be integrated in a substantially random order, and these device addresses can be configured to achieve mass production of roughly the same equipment and reduce production costs. In addition, by continuously configuring multiple devices for address reduction, the number of devices per device can be reduced, & @ reduction in the product Hf: $ _L to achieve the number of devices (number 〇f 0690-TW-CH Spec+ Claim(filed-20100802).doc 20 201207627
Pins)，來降低生產成本β 當然，雖然圖4Α和4Β根據一些實施例以說明示範性 操作流程，但本領域技術人員應該理解，在其他一些實施 例中，不一定需要實現圖4Α及/或圖4Β說明之全部操作 流程和步驟。特別地，在不脫離後附申請專利範圍所界定 之本發明精神和保護範圍的前提下，在本發明的其他一些 實施例中，可以包括圖4Α及/或圖4Β所闡述的操作流程 及/或一些額外的操作的子集《因此，根據本發明所界定之 申請專利範圍並非完全由某一幅圖所表示，而是落入本發 明的精神和保護範圍中。 除此之外，記憶體105可以包括一個或多個如下所述 的記憶體類型’例如半導體韌體記憶體（semic〇nduetor firmware memory)、可編程記憶體(programmable mem〇iy)、 非揮發性記憶體（non-volatile memory)、唯讀記憶體（rea(j only memory)、電可編程記憶體（electrically pr〇grammable memory)、動態隨機存取記憶體（rand〇m access mem〇jy)、快 閃記憶體（flashmemory)、磁碟記憶體（magneticdiskmem〇ry：) 及/或光碟記憶體（optical disk memory)。當然，記憶體 也可以包括其他類型，及/或今後開發之電腦可讀類型的記 憶體。 本發明所闡述的方法實施例可以由處理器，及/或其他 可編程設備實施。由此，本發明所闡述的方法所述方法可 以通過運行計算機電路的一部分或執行機器可讀的指令 序列或它們的組合進行實現。所述指令可以駐留在各種 類型的信號或資料存儲介質上，所述資料存儲介質可以是 21 0690-TW-CH Spec+Claim(filed-20100802).doc 201207627 =存儲介質、次級或者第三級存儲介質。所述介質可能包 含，例如，通過無線網路的元件存取或駐留在所屬無線網 路的元件之内的ram (未顯示)。無論被包含在Ram， 磁片，或其他次要的存儲介質中，所述指令可以被存儲在 各，機器可讀數據存儲介質上，諸如DASD存儲（例如， 傳統的"硬碟"或陣列），磁帶，電唯讀記憶體（例如， ROM ’ EPROM ’或EEPROM)，快閃記憶卡，光存儲設 備（例如CD-ROM，WORM，DVD，數位光帶），紙“打 孔卡，或其他適當的包括數位和類比傳輸介質的資料存儲 介質。 上文具體實施方式和附圖僅為本發明之常用實施 例三顯然，在不脫離權利要求書所界定的本發明精神和發 明範圍的前提下可以有各種增補、修改和替換。本領域技 術人員應該理解，本發明在實際應用中可根據具體的環境 和工作要求在不背離發明準則的前提下在形式、結構、佈 局、比例、材料、元素、元件及其它方面有所變化。因此， 在此披露之實施例僅用於說明而非限制，本發明之範圍由 後附權利要求及其合法㈣物界定，而不限於此前之描 述0 【圖式簡單說明】 以下結合附圖和具體實施例對本發明的技術方法進 行詳細的描述，以使本發明的特徵和優點更為明顯。其中： 圖1所示為根據本發明一實施例之垂直匯流排系統電 路的示意圖； 0690-TW-CH Spec+Ciaim(fiIed-20100802).doc 22 201207627 圖2A所示為根據本發明一實施例之鏈式系統電路的 不意圖； 圖2B所示為根據本發明另一實施例之鏈式系統電路 的不意圖； 圖3A所示為根據本發明一實施例之對系統中多個設 備分配位址之一或多個命令所對應之資料結構圖； 圖3B所示為根據本發明一實施例之對系統中某個設 備更換位址之一或多個命令所對應之資料結構圖； _ ® 4A所示為根據本發明—實施例之對多個設備配置 位址之示範操作流程圖；以及 圖4B所不為根據本發明一實施例之對多個設備分配 位址之示範操作流程圖。 【主要元件符號說明】 100 :垂直匯流排系統電路 :設備 104 :主管理控制單元 • 105 :記憶體 106 :匯流排控制器 l〇8a:位準移位器 l〇8b :位準移位器 110 第一 串列輸出埠 112 第二 串列輸出埠 114 第一 串列輸入埠 116 第二 串列輸出埠 120 移位暫存器 0690-TW-CH Spec+Claim(filed-201〇〇8〇2).doc 23 201207627 122 :多工器 124 :移位暫存器 126 :多工器 128 :串列輸出埠 130 :電池組 200 :鏈式系統 202 :設備 206 :匯流排控制器 210 :串列輸入埠 212 :串列輸出埠 220 :移位暫存器 222 :多工器 230a〜230η :隔離體 250 :鏈式系統 300 : —或多個命令所對應之資料結構 310a〜310b :頭指令段 312a〜312b :指令碼 314a〜314b :目標位址 316a〜316b :封包錯誤檢驗碼 320a〜320b :負載段 322a :第N個設備位址 322η :第1個設備位址 324a :第Ν個錯誤檢驗碼 324η :第1個錯誤檢驗碼 332 :預設位址 0690-TW-CH Spec+Claim(filed-20100802).doc 24 201207627Pins), to reduce production costs. Of course, although FIGS. 4A and 4B illustrate exemplary operational procedures in accordance with some embodiments, those skilled in the art will appreciate that in other embodiments, it is not necessary to implement FIG. 4 and/or Figure 4 illustrates all the operational procedures and steps. In particular, other embodiments of the present invention may include the operational procedures set forth in FIG. 4A and/or FIG. 4B without departing from the spirit and scope of the invention as defined by the appended claims. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; In addition, the memory 105 may include one or more memory types as described below, such as a semiconductor firmware memory, a programmable memory (programmable mem〇iy), and a non-volatile memory. Memory (non-volatile memory), read-only memory (rea (j only memory), electrically programmable memory (electrically pr〇grammable memory), dynamic random access memory (rand〇m access mem〇jy), Flashmemory, magnetic disk memory (magneticdiskmem〇ry:) and/or optical disk memory. Of course, the memory can also include other types, and/or computer readable types developed in the future. The method embodiments of the present invention can be implemented by a processor, and/or other programmable device. Thus, the method of the present invention can be performed by running a portion of a computer circuit or executing a machine readable The instruction sequences or a combination thereof are implemented. The instructions may reside on various types of signal or data storage media, the data storage media may 21 0690-TW-CH Spec+Claim(filed-20100802).doc 201207627=Storage medium, secondary or tertiary storage medium. The medium may contain, for example, component access or resident through a wireless network. A ram (not shown) within the components of the associated wireless network. The instructions may be stored on each, machine readable data storage medium, whether contained in a Ram, magnetic disk, or other secondary storage medium. , such as DASD storage (for example, traditional "hard disk" or arrays), magnetic tape, electrical read-only memory (for example, ROM 'EPROM' or EEPROM), flash memory card, optical storage device (such as CD-ROM) , WORM, DVD, digital light strip), paper "punch card, or other suitable data storage medium including digital and analog transmission media. The above detailed description and drawings are merely illustrative of the common embodiment of the present invention. Various additions, modifications, and substitutions are possible without departing from the spirit and scope of the invention as defined by the appended claims. Those skilled in the art will appreciate that the invention may be The context and work requirements are subject to change in form, structure, layout, proportions, materials, elements, elements, and other aspects without departing from the inventive subject matter. Therefore, the embodiments disclosed herein are for illustration and not limitation only. The scope of the invention is defined by the appended claims and their legal (four), and is not limited to the foregoing description. [FIG. BRIEF DESCRIPTION OF THE DRAWINGS The technical method of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The features and advantages are even more pronounced. 1 is a schematic diagram of a vertical busbar system circuit according to an embodiment of the invention; 0690-TW-CH Spec+Ciaim(fiIed-20100802).doc 22 201207627 FIG. 2A shows an embodiment according to the present invention. FIG. 2B shows a schematic diagram of a chain system circuit according to another embodiment of the present invention; FIG. 3A shows a bit allocation for a plurality of devices in a system according to an embodiment of the present invention. A data structure diagram corresponding to one or more commands; FIG. 3B is a data structure diagram corresponding to one or more commands of a device replacement address in the system according to an embodiment of the invention; 4A is a flowchart showing an exemplary operation of configuring addresses for a plurality of devices in accordance with the present invention; and FIG. 4B is not an exemplary operational flow diagram for assigning addresses to a plurality of devices in accordance with an embodiment of the present invention. [Main component symbol description] 100: Vertical busbar system circuit: Device 104: Main management control unit • 105: Memory 106: Busbar controller l〇8a: Level shifter l〇8b: Level shifter 110 first serial output 埠 112 second serial output 埠 114 first serial input 埠 116 second serial output 埠 120 shift register 0690-TW-CH Spec+Claim (filed-201 〇〇 8 〇 2).doc 23 201207627 122: multiplexer 124: shift register 126: multiplexer 128: serial output 埠 130: battery pack 200: chain system 202: device 206: bus controller 210: string Column input 埠 212: serial output 埠 220: shift register 222: multiplexer 230a 230 230n: isolator 250: chain system 300: - or data structure 310a~310b corresponding to multiple commands: header instruction Segments 312a to 312b: instruction codes 314a to 314b: target addresses 316a to 316b: packet error check codes 320a to 320b: load segment 322a: Nth device address 322n: first device address 324a: first error Check code 324η: 1st error check code 332: preset address 0690-TW-CH Spec+Claim(filed-20100802).doc 24 201207627
334 :封包錯誤檢測碼 350: —或多個命令所對應的資料結構 400 :對多個設備配置位址之示範操作流程圖 405〜420、435〜480 :步驟 430 :對多個設備分配位址之示範操作流程圖 0690-TW-CH Spec+Claim(filed-20100802).doc 25334: packet error detection code 350: - or data structure corresponding to multiple commands 400: exemplary operation flow chart 405~420, 435~480 for configuring a plurality of devices: step 430: assigning addresses to multiple devices Demonstration operation flow chart 0690-TW-CH Spec+Claim(filed-20100802).doc 25