201205828 六、發明說明： 【發明所屬之技術領域】 本發明係有關於-種太陽能電池及其製程方法，特別有關 於^一種具有異質接面之石夕基太陽能電池及其製程方法。 【先前技術】 由於能源危機與環縣制抬頭’使太陽能電池受到大家的 重視。此外’由於人們對於石夕原料的製作及元件加工技術的經驗 鲁累、積，使石夕原料成為理想的太陽能電池材料。然而，以石夕晶做成 的太陽能電池的轉換效率，因其僅能吸收hl電子伏特（eV)以 上的太陽缝之關、反射統成_失、材料對太陽光的吸收 此力不足、載子在尚未被導出之前就被材料中的缺陷捕捉而失 效，或是載子受到材料表面的懸浮鍵結捕捉產生復合等諸多因 素’皆使其效率下降。因此，現在市售石夕晶太陽能電池的轉換效 率僅約15 %，即表示石夕晶太陽能電池的高效率化其實還有相當大 的空間。 • 參照美國公告專利第6,38〇,479號，標題為：光伏單元元件及 其製作方法(Photovoltaic element and method foi* manufketure thereof)，其主要揭示一種太陽能電池的製程方式。其利用糙化之 基板以增加入射光之使用率，藉以改善電流特性，進而把反射 光的比率降到10 %以下，並增加電池整體之光電轉換效 率。 此外，參照美國公告專利第7,199,395號，標題為：光伏元件 及其製作方法(Photovoltaic cell and method of fabricating the 201205828 same)，其主要揭示一種太陽能電池的製程方式。主要係將pN接 面製作於同一平面，冑而使電極T製作於太陽㈣池之-平面， 使太陽能板的受光面不受電極的遮蔽，進而增加電池整體之光 電轉換效率。然而，上述之專利皆未詳細揭示較佳之光電轉換 層材料，組成結構與厚度。職是之故，申請人提出一種具有 異質接面之矽基太陽能電池及製程。本發明係引用美國公告 專利第6,380,479號，標題為：光伏單元元件及其製作方法 (Photovoltaic element and method for manufacture thereof)，以及美國 公告專利第7，199,395號，標題為：光伏元件及其製作方法 (Photovoltaic cell and method of fabricating the same )作引證參考 文獻。 【發明内容】 本發明提供一種具有異質接面之矽基太陽能電池，其包含： 一基板；一第一本質型（i型）半導體層；一 p型半導體層；一第 電極，一第二本質型（i型）半導體層；—N型半導體層；以及 一第二電極。其巾’基板具有第-樹t表面以及第二縫化表面； 第-本質型（1型）半導體層聽置於m化表面上且包含微晶 矽質，微晶矽質係鑲埋於第一本質型（i型）半導體層，且於第一 本質型（1型）半導體層中的比例係介於30%至5〇%之間，此外， 微晶石夕質之氫含f係介於3%至10%之間；p型半導體層係配置於 第一本質型（i型）半導體層上，氧含量係介於1><1〇17至5xl〇ls 原子/立方公分之間；第一電極係配置於p型半導體層上；第二本 質型（1型）半導體層係配置於第二糙化表面上，且包含微晶矽質， 微晶石夕質係鑲埋於第二本質型（i型）半導黯，且於第二本質型 201205828 (i型）半導體層中的比例係介於30%至50%之間，此外，微晶破 質之氫含量係介於3%至10%之間；N型半導體層係配置於第二本 質型（i型）半導體層上，氧含量係介於lxlO17至5χ1018原子/立 方公分之間；以及第二電極，係配置於N型半導體層上。其中p 型半導體層與N型半導體層之能隙皆大於第一本質型（丨型）半導 體層與第二本質型（i型）半導體層之能隙。 本發明更提供一種具有異質接面之矽基太陽能電池製程方 法，包含下列步驟：（一）清洗並蝕刻一基板；（二）以化學氣相 • 沉積法沈積第一本質型0型）半導體層於第一糙化表面上；（三） 沈積P型半導體層於第一本質型（i型）半導體層上；（四）沈積 第一電極於P型半導體層上；（五）以化學氣相沉積法沈積第二 本質型（i型）半導體層於第二糙化表面上；（六）沈積N型半導 體層於第二本質型（i型）半導體層上；以及（七）沈積第二電 極於N型半導體層上。茲進一步說明各步驟如下··步驟（一）在 於使基板形成第一糖化表面以及第二縫化表面；步驟（二）除了 沉積第一本質型（i型）半導體層外，亦使微晶矽質鑲埋於第一 本質型（i型）半導體層中，而微晶矽質於第一本質型〇型）半 導體層中的比例係介於30%至50%之間，且微晶石夕質之氮含量係 介於3%至10%之間；步驟（三）中’ p型半導體層之氧含量係 介於IxlO17至5xl〇18原子/立方公分之間；步驟（五）除了沉積 第二本質型（i型）半導體層外，亦使微晶矽質鑲埋於第二本質 型（i型）半導體層，而微晶破質於第二本質型（i型）半導體層 中的比例係介於30%至50%之間，且微晶矽質之氫含量係介二 3%至10%之間；於步驟（六）中，N型半導體層之氧含量係介於 201205828 1x1017至5x1018原子/立方公分之間。 本發明藉由微晶矽質之材質與結晶來填補p型半導體 層、N型半導騎解晶雜祕發生之雜，域由微晶石夕質 之能隙特性紐1光電雜’達成高效能具有異f接面之石夕基 太陽能電池的量產目標。 為讓本發明之上述和其他目的、特徵、和優點能更明顯易 懂’下文特舉數她佳實施例，並配合所附赋，作詳細說明如 下。 【實施方式】 雖然本發明可表現為不哪式之實施例，但關所示者及於 下文中說财係為本發明可之較佳實關，麟了解本文所揭示 者係考量為本發明之—範例，且並非意圖用⑽本發赚制於圖 式及/或所描述之特定實施例中。 現凊參照第1圖，為本發明第一實施例之示意圖，揭示一種 具有異質接面切基太陽能電池1G()結構，包含：基板11〇 ;第 一本質型（i型）半導體層120;1>型半導體層13〇;第一電極16〇; 第二本質型（i型）半導體層14〇 ; N型半導體層15G ;以及第二 電極1?0。需注意的是，P型半導體層130與N型半導體層15〇 之能隙係皆大於第-本質型（i型）半導體層12G與第二本質型 型）半導體層140之能隙。 基板110係選自P型半導性基板、N型半導性基板、p型石夕基 板以及N型矽基板之一。基板110之厚度介於15〇微米至25〇微 米之間。較佳地，基板11〇係為N型單晶矽基板，且其厚度為15〇 微米至180微米之間。此外，本發明之基板11〇具有第一链化表 201205828 面111以及第二縫化表面112。 第一本質型（丨型）半導體層120係配置於第一縫化表面111 上，並包含微晶矽質，微晶矽質係鑲埋於第一本質型（i型）半導 體層120中，且於第一本質型（丨型）半導體層12〇中的比例係介 於30%至50%之間，此外’微晶矽質之氮含量係介於3%至ι〇〇/0 之間。本實施例之第一本質型（i型）半導體層120的能隙係介於 1.2eV 至 1.6eV 之間。 第二本質型（i型）半導體層140係配置於第二糙化表面112 # 上’並包含微晶矽質’微晶矽質係鑲埋於第二本質型（i型）半導 體層140中’且於第二本質型〇型）半導體層14〇中的比例係介 於30%至50%之間，此外’微晶矽質之氳含量係介於3%至1〇0/〇 之間。本實施例之第二本質型（i型）半導體層14〇的能隙係介於 1.2eV 至 1.6eV 之間。 第一本質型（i型）半導體層120與第二本質型（丨型）半導 體層140可選用電漿增強型化學式氣相沈積製程(piasma_enhanced chemical vaP〇r deposition，PECVD)、熱絲化學氣相沉積法(Hot_wire chemical vapor deposition, HW-CVD)或特高頻電漿增強型化學式 氣相沈積（Very high frequency-plasma enhance chemical vapor deposition, VHF-PECVD)製程作為主要製程方式，並通入石夕化合 物（Silicide )氣體如矽烷（silane, SH4 )並混和氳氣（Hydrogen, H2)、 氬氣（Argon，Ar)等氣體作為製程氣體。其中，第一本質型〇型） 半導體層120與第二本質型（i型）半導體層14〇對於薄膜型太陽 能電池之電特性影響最大，其是由於電子與電洞在材料内部傳導 時，若第一本質型（i型）半導體層120與第二本質型（丨型）半 7 201205828 導體層HG厚度過厚，兩者重合鮮極高。為聽此現象發生， 第本質型（i型）半導體層12〇與第二本質型（i型）半導體層 140不且過厚。反之，第一本質型（i型）半導體層120與第二本 質型（1型）半導體層14Q厚度過_，又易造成吸光性不足。 於本發明之較佳實施例中，第-本質型（i型）半導體層120 ，第一本質型（i型）半導體層14G之厚度係介於5奈米至⑼奈 米之間’錢含量皆齡於3%至祕之間。需注意，氫含量的不 同將影響光電轉換特性。此外，第一本質型〇型）半導體層12〇 與第二本質型型）半導體層140亦可用以填補p型半導體層13〇 與基板110接面處或N型半導體層⑼與基板11〇接面處發生之 缺陷，以增加轉換效率。 P型半導體層130係配置於第一本質型（i型）半導體層12〇 上，且其氧含量係介於lxl0i7至5xl〇i8原子/立方公分之間。其中， 在原本質材料中加入雜質（Impurities)用以產生多餘的電 洞，以電洞構成多數載子之半導體，則稱之為p型半導體層 130。例：就矽或鍺半導體而言，在其本質半導體中，摻入3 4貝原子的雜質時’即形成多餘的電洞，且該電洞係為電流的 運作方式。其中’ P型半導體層130之摻雜方式於本發明中係 採用可選用氣體摻雜、熱擴散法（Thermal diffusion)、固相 結晶化（Solid phase crystalline，SPC)或準分子雷射退火 (Excimer laser anneal，ELA)等製程作為主要的製程方式。此 外，P型半導體層130係選自非晶矽、非晶矽鍺、非晶碳化破以及 奈米晶矽之一。在一較佳實施例中，P型半導體層130係為奈米晶 矽。P型半導體層130之厚度係介於10奈米至1〇〇奈米之間，p 201205828 型半導體層130之能隙係介於1<66¥至i 9eV之間，且大於第一 本質型（i型）半導體層120之能隙。 ' N型半導體層ISO係配置於第二本質型（i型）半導體層 上，且其氧含量係介於lxlO17至5xl〇i8原子/立方公分之間。其 中，N型半導體層150係指在本質材料中加入的雜質可產生 多餘的電子，以電子構成多數載子之半導體。例如，就石夕和 鍺半導體而言，若在其本質半導體中摻入5價原子的雜質 時，即形成多餘之電子。其中，電子流係以電子為主來運作。 φ N型半導體層150之摻雜方式可選用於氣體摻雜、準分子雷 射退火（Exdmer laser anneal，ELA )、固相結晶化（s〇Ud沖咖 crystalline，SPC)、熱擴散法（Thermaldiffusi〇n)或離子佈植 法（Ion implantation).等作為主要製程方式。此外，半導體 層150係選自非晶矽、非晶矽鍺、非晶碳化矽以及奈米晶矽之一。 在-較佳實施射，N型半導體層15〇係為奈米晶⑪。N型半導 體層150之厚度係介於10奈米至1〇〇奈米之間，N型半導體層15〇 之能隙係介於L6…至1.9 eV之間，且大於第二本質型〇型） 胃半導體層14G之能隙。 第-電極160以及第二電極17〇係分別配置於p型半導體層 130上以及N型半導體層150上’用以取出電能與提昇光電轉換 之效率。其中，第-電極160以及第二電極17〇之材料可選用铜 錫氧化物、二氧化錫、氧化辞、含雜質的二氧化錫、含雜質的氧 化鋅、錄、金、銀、鈦、銅、把、及銘。在一較佳實施例中，第 - 160以及第二㈣17〇之材料係選用♦雜質的二氧化锡， 其具有85%以上之透光度，且其片電阻值係介於5 Ω/口至ι〇 ω/口201205828 VI. Description of the Invention: [Technical Field] The present invention relates to a solar cell and a method for fabricating the same, and more particularly to a stone solar cell having a heterojunction and a process method thereof. [Prior Art] Due to the energy crisis and the rise of the county system, solar cells have received the attention of everyone. In addition, due to people's experience in the production of Shi Xi raw materials and component processing technology, it has become a ideal solar cell material. However, the conversion efficiency of a solar cell made of Shi Xijing is only capable of absorbing the sun seam of hl electron volts (eV) or more, the reflection system is _ lost, the material absorbs sunlight, and the force is insufficient. Subgenerators are either captured by defects in the material before they are exported, or the carrier is captured by the suspension bond on the surface of the material to produce a composite. Therefore, the conversion efficiency of the commercially available Shi Xijing solar cell is only about 15%, which means that there is still a considerable room for the high efficiency of the Shi Xijing solar cell. • Refer to U.S. Patent No. 6,38, 479, entitled Photovoltaic element and method foi* manufketure thereof, which mainly discloses a process for manufacturing a solar cell. It utilizes a roughened substrate to increase the usage rate of incident light, thereby improving current characteristics, thereby reducing the ratio of reflected light to less than 10%, and increasing the overall photoelectric conversion efficiency of the battery. In addition, reference is made to U.S. Patent No. 7,199,395, entitled Photovoltaic cell and method of fabricating the 201205828 same, which mainly discloses a process for manufacturing a solar cell. Mainly, the pN interface is formed on the same plane, so that the electrode T is formed on the plane of the sun (four) pool, so that the light receiving surface of the solar panel is not shielded by the electrodes, thereby increasing the overall photoelectric conversion efficiency of the battery. However, none of the above patents disclose the preferred photoelectric conversion layer material, composition and thickness. For the sake of the job, the applicant proposed a germanium-based solar cell with a heterojunction and a process. The present invention is citing U.S. Patent No. 6,380,479, entitled: Photovoltaic element and method for manufacture thereof, and U.S. Patent No. 7,199,395, entitled: Photovoltaic Element and Method of Making Same (Photovoltaic cell and method of fabricating the same) is cited as a reference. SUMMARY OF THE INVENTION The present invention provides a germanium-based solar cell having a heterojunction comprising: a substrate; a first intrinsic (i-type) semiconductor layer; a p-type semiconductor layer; an electrode, a second essence a type (i type) semiconductor layer; an N type semiconductor layer; and a second electrode. The towel 'substrate has a first-tree t surface and a second sewn surface; the first-essential type (1 type) semiconductor layer is placed on the m-ized surface and contains microcrystalline enamel, and the microcrystalline enamel system is embedded in the An intrinsic type (i type) semiconductor layer, and the ratio in the first intrinsic type (type 1) semiconductor layer is between 30% and 5%, and further, the hydrogen of the microcrystalline stone contains f Between 3% and 10%; the p-type semiconductor layer is disposed on the first intrinsic type (i-type) semiconductor layer, and the oxygen content is between 1 > 1〇17 to 5xl〇ls atoms/cm 3 The first electrode is disposed on the p-type semiconductor layer; the second intrinsic (type 1) semiconductor layer is disposed on the second roughened surface, and includes microcrystalline enamel, and the microcrystalline enamel is embedded in the first The two intrinsic type (i type) semiconducting yttrium, and the proportion in the second essential type 201205828 (i type) semiconductor layer is between 30% and 50%, in addition, the hydrogen content of the microcrystalline breakage is between Between 3% and 10%; the N-type semiconductor layer is disposed on the second intrinsic type (i-type) semiconductor layer, and the oxygen content is between lxlO17 and 5χ1018 atoms/cm 3 ; A second electrode system disposed on an N-type semiconductor layer. The energy gap between the p-type semiconductor layer and the N-type semiconductor layer is greater than the energy gap between the first intrinsic (丨-type) semiconductor layer and the second intrinsic (i-type) semiconductor layer. The invention further provides a method for manufacturing a germanium-based solar cell having a heterojunction, comprising the steps of: (1) cleaning and etching a substrate; and (2) depositing a first intrinsic type 0 semiconductor layer by chemical vapor deposition; On the first roughened surface; (3) depositing a P-type semiconductor layer on the first intrinsic type (i-type) semiconductor layer; (4) depositing the first electrode on the P-type semiconductor layer; (5) depositing a chemical vapor phase Depositing a second intrinsic type (i type) semiconductor layer on the second roughened surface; (6) depositing an N type semiconductor layer on the second intrinsic type (i type) semiconductor layer; and (7) depositing a second electrode On the N-type semiconductor layer. Further explaining the steps as follows: Step (1) consists in forming the substrate into a first saccharified surface and a second spliced surface; in step (2), in addition to depositing the first intrinsic (i-type) semiconductor layer, the microcrystalline enamel is also The quality is embedded in the first intrinsic (i-type) semiconductor layer, and the proportion of the microcrystalline tantalum in the first intrinsic germanium type semiconductor layer is between 30% and 50%, and the microcrystalline stone The nitrogen content of the mass is between 3% and 10%; in step (3), the oxygen content of the p-type semiconductor layer is between IxlO17 and 5xl〇18 atoms/cm3; in step (5), except for the deposition In addition to the intrinsic (i-type) semiconductor layer, the microcrystalline enamel is also embedded in the second intrinsic (i-type) semiconductor layer, and the proportion of the microcrystals in the second intrinsic (i-type) semiconductor layer The system is between 30% and 50%, and the hydrogen content of the microcrystalline tannin is between 3% and 10%; in the step (6), the oxygen content of the N-type semiconductor layer is between 201205828 1x1017. 5x1018 atoms / cubic centimeter. The invention fills the p-type semiconductor layer and the N-type semi-conductor riding crystal by the material and crystallization of the microcrystalline enamel, and the domain is characterized by the energy gap of the microcrystalline stone. A mass production target of a Shih-Xi solar cell capable of having a different f junction. The above and other objects, features, and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; [Embodiment] Although the present invention can be embodied in an embodiment of the present invention, it is to be understood that the present invention is a preferred embodiment of the present invention. The examples are not intended to be used in the drawings and/or in the specific embodiments described. 1 is a schematic view of a first embodiment of the present invention, showing a structure of a heterojunction dicing solar cell 1G (), comprising: a substrate 11 〇; a first intrinsic (i-type) semiconductor layer 120; 1>-type semiconductor layer 13A; first electrode 16A; second intrinsic type (i-type) semiconductor layer 14A; N-type semiconductor layer 15G; and second electrode 1?0. It is to be noted that the energy gaps of the P-type semiconductor layer 130 and the N-type semiconductor layer 15 are larger than the energy gaps of the first intrinsic (i-type) semiconductor layer 12G and the second intrinsic type semiconductor layer 140. The substrate 110 is selected from one of a P-type semiconducting substrate, an N-type semiconducting substrate, a p-type Schindler substrate, and an N-type germanium substrate. The thickness of the substrate 110 is between 15 Å and 25 Å. Preferably, the substrate 11 is an N-type single crystal germanium substrate and has a thickness of between 15 μm and 180 μm. Further, the substrate 11 of the present invention has a first chaining table 201205828 surface 111 and a second stitching surface 112. The first intrinsic (丨-type) semiconductor layer 120 is disposed on the first sewn surface 111 and includes microcrystalline tantalum, and the microcrystalline tantalum is embedded in the first intrinsic type (i-type) semiconductor layer 120. And the ratio in the first intrinsic (丨-type) semiconductor layer 12〇 is between 30% and 50%, and the nitrogen content of the microcrystalline tannin is between 3% and ι〇〇/0. . The first intrinsic type (i type) semiconductor layer 120 of this embodiment has an energy gap of between 1.2 eV and 1.6 eV. The second intrinsic type (i type) semiconductor layer 140 is disposed on the second roughened surface 112 # and includes a microcrystalline tantalum 'microcrystalline tantalum system embedded in the second intrinsic type (i type) semiconductor layer 140 The ratio in the semiconductor layer 14〇 is between 30% and 50%, and the content of the microcrystalline tantalum is between 3% and 1〇0/〇. . The second intrinsic type (i type) semiconductor layer 14 of the present embodiment has an energy gap of between 1.2 eV and 1.6 eV. The first intrinsic type (i type) semiconductor layer 120 and the second intrinsic type (germanium type) semiconductor layer 140 may be selected from a plasma enhanced chemical vapor deposition process (PECVD), a hot wire chemical vapor phase process. High-frequency chemical vapor deposition (HW-CVD) or high-frequency-plasma enhance chemical vapor deposition (VHF-PECVD) process as the main process, and passed into Shi Xi A compound (Silicide) gas such as silane (SH4) is mixed with a gas such as hydrogen (H2) or argon (Argon, Ar) as a process gas. Wherein, the first intrinsic type) semiconductor layer 120 and the second intrinsic type (i type) semiconductor layer 14 have the greatest influence on the electrical characteristics of the thin film type solar cell, because electrons and holes are conducted inside the material, The first intrinsic type (i type) semiconductor layer 120 and the second intrinsic type (丨 type) half 7 201205828 The conductor layer HG is too thick, and the two overlap are extremely high. In order to hear this phenomenon, the first intrinsic type (i type) semiconductor layer 12A and the second intrinsic type (i type) semiconductor layer 140 are not excessively thick. On the other hand, the thickness of the first intrinsic type (i type) semiconductor layer 120 and the second intrinsic type (type 1) semiconductor layer 14Q is too large, and the light absorption property is insufficient. In a preferred embodiment of the present invention, the thickness of the first intrinsic type (i type) semiconductor layer 120 and the first intrinsic type (i type) semiconductor layer 14G is between 5 nm and (9) nm. All are between 3% and secret. It should be noted that the difference in hydrogen content will affect the photoelectric conversion characteristics. In addition, the first intrinsic germanium type semiconductor layer 12 and the second intrinsic type semiconductor layer 140 may also be used to fill the junction of the p-type semiconductor layer 13 and the substrate 110 or the n-type semiconductor layer (9) and the substrate 11 Defects occurring at the surface to increase conversion efficiency. The P-type semiconductor layer 130 is disposed on the first intrinsic type (i-type) semiconductor layer 12A, and has an oxygen content of between lxl0i7 and 5xl〇i8 atoms/cm 3 . Among them, an impurity is added to the original intrinsic material to generate excess holes, and a semiconductor in which a plurality of carriers are formed by holes is called a p-type semiconductor layer 130. Example: In the case of a germanium or germanium semiconductor, in its intrinsic semiconductor, when three or four atoms of impurities are doped, an extra hole is formed, and the hole is a current operation mode. The doping method of the 'P-type semiconductor layer 130 is selected in the present invention by gas doping, thermal diffusion, solid phase crystallization (SPC) or excimer laser annealing (Excimer). Laser anneal, ELA) and other processes as the main process. Further, the P-type semiconductor layer 130 is selected from one of amorphous germanium, amorphous germanium, amorphous carbonized, and nanocrystalline germanium. In a preferred embodiment, the P-type semiconductor layer 130 is a nanocrystal. The thickness of the P-type semiconductor layer 130 is between 10 nm and 1 nm, and the energy gap of the p 201205828 semiconductor layer 130 is between 1 < 66 ¥ to i 9 eV, and is larger than the first essential type. (i-type) The energy gap of the semiconductor layer 120. The N-type semiconductor layer ISO is disposed on the second intrinsic type (i-type) semiconductor layer, and has an oxygen content of between 1 x 10 17 and 5 x 1 〇 i 8 atoms / cubic centimeter. Here, the N-type semiconductor layer 150 refers to a semiconductor in which an impurity added to an intrinsic material generates excess electrons and electrons constitute a majority carrier. For example, in the case of Shi Xi and Hee semiconductors, if impurities of a pentavalent atom are doped into the intrinsic semiconductor, excess electrons are formed. Among them, the electronic flow system operates mainly on electronics. The doping mode of the φ N-type semiconductor layer 150 can be selected for gas doping, exdmer laser anneal (ELA), solid phase crystallization (SPC), thermal diffusion method (Thermaldiffusi) 〇n) or ion implantation (Ion implantation), etc. as the main process. Further, the semiconductor layer 150 is selected from one of amorphous germanium, amorphous germanium, amorphous tantalum carbide, and nanocrystalline germanium. Preferably, the N-type semiconductor layer 15 is a nanocrystal 11 . The thickness of the N-type semiconductor layer 150 is between 10 nm and 1 nm, and the energy gap of the N-type semiconductor layer 15 is between L6... and 1.9 eV, and is larger than the second intrinsic type. The energy gap of the gastric semiconductor layer 14G. The first electrode 160 and the second electrode 17 are disposed on the p-type semiconductor layer 130 and the N-type semiconductor layer 150, respectively, for taking out electrical energy and improving the efficiency of photoelectric conversion. The material of the first electrode 160 and the second electrode 17〇 may be selected from copper tin oxide, tin dioxide, oxidized, impurity-containing tin dioxide, impurity-containing zinc oxide, gold, silver, titanium, copper. , put, and Ming. In a preferred embodiment, the material of the -160th and the second (fourth) 17〇 is selected from the impurity tin dioxide, which has a transmittance of 85% or more, and the sheet resistance value is between 5 Ω/□. 〇〇ω/口
C 201205828 之間。於本實施例中，其厚度係介於100奈米至9〇〇奈米之間。 此外，第-電極16G以及第二電極17G之材料亦可選用二層二上 不同材質之透明導電層所組成。 本發明之基板110所具有之_縣面侧叫加入射光之 散射率’藉由增加入射光之散射率，可增加光補限（Ught娜㈣ 的效率’改良電特性。第-本質型（i型）半導體層12〇、p型半 導體層130、第一電極160、第二本質型〇型）半導體層i4〇、n 型半導體層150以及第二f極m亦具有粗糙化表面，其功能與 基板110所具有之粗縫化表面功能相同。C 201205828. In this embodiment, the thickness is between 100 nm and 9 nm. In addition, the material of the first electrode 16G and the second electrode 17G may also be composed of two layers of transparent conductive layers of different materials. The substrate 110 of the present invention has a scattering rate of the incident light. By increasing the scattering rate of the incident light, the optical compensation limit (Ught Na (four) efficiency) can be increased to improve the electrical characteristics. The first essential type (i The semiconductor layer 12, the p-type semiconductor layer 130, the first electrode 160, the second intrinsic germanium type semiconductor layer i4, the n-type semiconductor layer 150, and the second f-pole m also have a roughened surface, the function of which The roughened surface of the substrate 110 has the same function.
需注意，當基板110為P型石夕基板時，則照光面為N型半導 體層150’且P型半導體層13G與第—本質型（i型）半導體層⑶ 則可形成背向表面電場(Back Surface Field，BSF)的效果。反之， 當基板110為N型矽基板時’則照光面為p型半導體層13〇，且N 型半導體層15G與第二本質型（i型）半導體層14()則可形成背向 表面電場(Back Surface Field，BSF)的效果。 為說明本發明之具有異質接面之⑦基太陽能電池丨⑽之製 程，現請參照第2圖，為本發明之製織賴，包含以下步驟： 步驟210 .清洗並银刻基板。 步驟22G:侧化學氣相沉積法並以氫氣與魏鐘作為製程 氣體沈積第-本質型（i型）半導體層12〇於第一縫化表面⑴上。 步驟230 :沈積P型半導體層13〇於第一本質型〇型）半導 體層120上。 步驟240 :沈積第一電極160於p型半導體層ι3〇上。 步驟250:利用化學氣相沉積法以氫氣與魏氣體作為製程氣 201205828 體，沈積第二本質型（i型）半導體層14〇於第二糙化表面112上。 步驟260 :沈積Ν型半導體層15〇於第二本質型（i型）半導 體層140上。 步驟270為：沈積第二電極17〇於ν型半導體層15〇上。 於步驟210中，因基板110表面容易殘留微粒子、有機物、 金屬殘留物、化合物…等污染，所以必須先將基板11〇經過清洗 以得乾淨之表面。此外，蝕刻基板110之目的在於形成第一糙化 表面111以及第二糙化表面112，用以增加入射光之散射率，藉由 籲 增加入射光之散射率’可增加光補限（light-traping)的效率’改良 電特性。 需注意的是’ P型半導體層130與N型半導體層150之能隙 皆大於第一本質型（i型）半導體層丨2〇與第二本質型（丨型）半 導體層140之能隙。 步驟220以及步驟250中，在電漿增強型化學式氣相沈積製 程、熱絲化學氣相沉積法與特高頻電漿增強型化學式氣相沈積等 φ 方法中擇一，並使用氫氣與矽烷氣體作為製程氣體，使第一本質 型（i型）半導體層120以及第二本質型（i型）半導體層140分 別沈積於第一糙化表面111上以及第二链化表面112上，且藉由 控制氫氣流量與矽烷氣體流量之比例在10至100之間，使第一本 質型（i型）半導體層120以及第二本質型（i型）半導體層140 内皆鑲埋微晶矽質。其中微晶矽質於第一本質型（i型）半導體層 120以及第二本質型（i型）半導體層140中之比例介於30%至50% 之間，而其氩含量皆係介於3%至10%之間。於本實施例中，微晶 矽質之晶粒尺寸係介於10奈米至25奈米之間，而氫氣流量與矽 201205828 烷氣體流量之比例係介於25至80之間。此外，本發明之第一本 質型（i型）半導體層120以及第二本質型（i型）半導體層“ο 之較佳厚度係介於5奈米至150奈米之間，較佳之氫含量係介於 3%至10%之間。需注意，氫含量的不同將影響光電轉換特性。 於步驟230中，P型半導體層130之氧含量係介於lxl〇i7至 5xl〇18原子/立方公分之間，其選用電漿增強型化學式氣相沈積製 程、熱絲化學氣相沉積法或特高頻電漿增強型化學式氣相沈積製 程等作為主要製程方式，並藉由使用石夕化合物（Silicide)氣體如 矽烷（silane，SH4)並混和氫氣（Hydrogen, H2)、氬氣（Argon，At) 等氣體作為製程氣體。如：搭配以矽烷氣體與氫氣混合；矽烷氣 體、氫氣與氬氣混合；矽烷氣體、鍺烷氣體與氫氣混合；矽炫氣 體、鍺烷氣體、氫氣與氬氣混合所組成族群中之任何一種製程完 成。藉由改變>5夕烧及氫氣混合比例及製程氣體，可使p型半導體 層130係為非晶矽、非晶矽鍺、非晶碳化矽以及奈米晶矽之一。 於步驟260中，N型半導體層15〇之氧含量係介於lxl〇]7至 5xl018原子/立方公分之間’其選用電漿增強型化學式氣相沈積製 程、熱絲化學氣相沉積法或特高頻電漿增強型化學式氣相沈積製 程等作為主要製程方式，並使用石夕化合物（Silicide)氣體如石夕炫 (silane，SH4)且混和氫氣（Hydr〇gen H2)、氬氣（Arg〇n Ar)等 氣體作為製程氣體。如：搭配以矽烷氣體與氫氣混合；矽烷氣體、 氫氣與氬氣混合；矽烷氣體、鍺烷氣體與氫氣混合；矽烷氣體、 錯烧乳體風氣與氬氣混合所組成族群中之任何一種製程完成。 藉由改變矽烷及氫氣混合比例及製程氣體，可使N型半導體層150 係為非晶矽、非晶矽鍺、非晶碳化矽以及奈米晶矽之一。 12 201205828 步驟240以及步驟270中，第一電極160以及第二電極170 係採用蒸鍵法、濺鍍法、化學氣相沈積法、電鍍法、濕式化學法 與印刷法所組成族群中之任何一種製程，且第一電極160以及第 二電極170之材料可選用銦錫氧化物、二氧化錫、氧化鋅、含雜 質的一氧化錫、含雜質的氧化辞、錄、金、銀、欽、銅、把、及 链。第一電極160以及第二電極170之厚度係介於100奈米至900 奈米之間，片電阻值係介於5Ω/口至10Ω/口之間，並具有85%以上 之透光度。此外，第一電極160以及第二電極170之材料亦可選 • 用二層以上不同材質之透明導電層所組成。 需注意的是，不同的第一電極160以及第二電極170製備方 式亦會影響其所具有之光電特性的品質。然而為了得到較佳之表 面粗糙度，第一電極160以及第二電極170係以低壓化學氣相沈 積法沈積’或以濺鍍法配合後蝕刻製程處理形成。較佳地，第一 電極160以及第二電極170係由二層不同材質之透明導電層所組 成。 於本發明實施例中，P型半導體層130摻雜濃度在1〇18至1〇20 原子/立方公分之間，而N型半導體層150摻雜濃度在1〇〗8至1〇20 原子/立方公分之間。 此外，於本發明之實施例中，係採用熱絲化學氣相沈積系統 以製備具有異質接面之矽基太陽能電池100,且不同的第一本質型 (i型）半導體層120、P型半導體層130、第二本質型（丨型）半 導體層140以及N型半導體層150的製程方式亦會影響其所具有 之光電特性的品質。在一較佳實施例中，第一本質型（i型）半導 體層120、P型半導體層130、第二本質型（i型）半導體層140 13 201205828 以及N型半導體層150所採用之熱絲化學氣相沈積系統，其熱絲 溫度係介於。(:至·。C之間，且-較佳之熱·度係^ 1800C至2000C之間，其腔體之壓力係介於5 mtorr至5〇 mt〇rr 之間，且一較佳之腔體壓力係介於10 mtorr至30 mtorr之間；其 基板110的溫度係介於20。〇至35(TC之間，且較佳之基板110的 /里度係介於25C至200。(：之間；其腔體之鍍率係介於3〇人^沈至 60 A /sec之間’且一較佳之腔體的鍍率係介於4〇 A々沈至刈a尨沈 之間。 於本發明之另-實施射，雜職合式化學氣相沈積裝置 以製備具有微⑽m _之具有異質接面之德太陽能電池 100。其中，混合式化學氣相沈積裝置利用置入電極產生電漿，用 以製備具有異質接面之縣太陽能電池卿所需之微晶珍質⑵ 薄膜’並藉由複數健絲單元進行加熱，_時提升薄膜鐘膜之 速率。因此，混合式化學氣相_裝置除了可降低製作成本 外’更可降低微祕質121雜之氫含量以達到較佳 需注意，當基板no為p型石夕基板時，則照光面為Ν7半導 體層15〇’且p型半導體層130與第一本質型〇型）半導體層⑼ 則可形成背向表面電場(Back Surface Field，BSF)的效果。反之，It should be noted that when the substrate 110 is a P-type substrate, the illuminating surface is an N-type semiconductor layer 150' and the P-type semiconductor layer 13G and the first-type (i-type) semiconductor layer (3) can form a back-surface electric field ( Back Surface Field, BSF). On the other hand, when the substrate 110 is an N-type germanium substrate, the light-emitting surface is a p-type semiconductor layer 13A, and the N-type semiconductor layer 15G and the second intrinsic type (i-type) semiconductor layer 14 () can form a back-surface electric field. (Back Surface Field, BSF) effect. In order to illustrate the process of the 7-base solar cell crucible (10) having a heterojunction of the present invention, please refer to FIG. 2, which is a woven fabric of the present invention, comprising the following steps: Step 210. Clean and silver-etch the substrate. Step 22G: side chemical vapor deposition and using hydrogen gas and Weizhong as a process gas to deposit a first-instant type (i-type) semiconductor layer 12 on the first sewn surface (1). Step 230: depositing a P-type semiconductor layer 13 on the first intrinsic germanium type semiconductor layer 120. Step 240: depositing the first electrode 160 on the p-type semiconductor layer ι3. Step 250: depositing a second intrinsic (i-type) semiconductor layer 14 on the second roughened surface 112 by chemical vapor deposition using hydrogen gas and Wei gas as the process gas 201205828. Step 260: depositing a germanium-type semiconductor layer 15 on the second intrinsic type (i-type) semiconductor layer 140. Step 270 is: depositing a second electrode 17 on the ν-type semiconductor layer 15 。. In step 210, since the surface of the substrate 110 is likely to remain contaminated with particles, organic substances, metal residues, compounds, etc., the substrate 11 must be cleaned to obtain a clean surface. In addition, the purpose of etching the substrate 110 is to form a first roughened surface 111 and a second roughened surface 112 for increasing the scattering rate of incident light, and by increasing the scattering rate of the incident light to increase the light compensation limit (light- The efficiency of traping) improves electrical characteristics. It is to be noted that the energy gaps of the 'P-type semiconductor layer 130 and the N-type semiconductor layer 150 are larger than the energy gaps of the first intrinsic type (i type) semiconductor layer 丨2 〇 and the second intrinsic type (丨 type) semiconductor layer 140. In step 220 and step 250, one of φ methods such as plasma enhanced chemical vapor deposition process, hot wire chemical vapor deposition method and UHF plasma enhanced chemical vapor deposition is used, and hydrogen and decane gas are used. As the process gas, the first intrinsic type (i type) semiconductor layer 120 and the second intrinsic type (i type) semiconductor layer 140 are deposited on the first roughened surface 111 and the second chained surface 112, respectively, by The ratio of the hydrogen gas flow rate to the decane gas flow rate is controlled to be between 10 and 100, so that the first intrinsic type (i type) semiconductor layer 120 and the second intrinsic type (i type) semiconductor layer 140 are embedded with microcrystalline germanium. The proportion of the microcrystalline tantalum in the first intrinsic type (i type) semiconductor layer 120 and the second intrinsic type (i type) semiconductor layer 140 is between 30% and 50%, and the argon content thereof is between Between 3% and 10%. In this embodiment, the grain size of the microcrystalline tantalum is between 10 nm and 25 nm, and the ratio of the hydrogen flow rate to the 201205828 alkane gas flow rate is between 25 and 80. Further, the first intrinsic type (i type) semiconductor layer 120 and the second intrinsic type (i type) semiconductor layer of the present invention have a preferred thickness of between 5 nm and 150 nm, preferably a hydrogen content. The system is between 3% and 10%. It should be noted that the difference in hydrogen content will affect the photoelectric conversion characteristics. In step 230, the oxygen content of the P-type semiconductor layer 130 is between lxl〇i7 and 5xl〇18 atoms/cubic. Between the centimeters, the plasma enhanced chemical vapor deposition process, the hot wire chemical vapor deposition process or the UHF plasma enhanced chemical vapor deposition process is used as the main process, and by using the stone compound ( Silicide) gas such as silane (SH4) and mixed with hydrogen (Hydrogen, H2), argon (Argon, At) and other gases as process gases, such as: mixed with decane gas and hydrogen; decane gas, hydrogen and argon mixed The decane gas, the decane gas is mixed with the hydrogen gas; the process of any one of the group consisting of hydrazine gas, decane gas, hydrogen gas and argon gas is completed. By changing the ratio of the cooking gas and the hydrogen gas mixture and the process gas, Can make The p-type semiconductor layer 130 is one of amorphous germanium, amorphous germanium, amorphous tantalum carbide, and nanocrystalline germanium. In step 260, the oxygen content of the N-type semiconductor layer 15 is between lxl and 7 Between 5xl018 atoms/cm3, the plasma-enhanced chemical vapor deposition process, hot-wire chemical vapor deposition or ultra-high-frequency plasma-enhanced chemical vapor deposition process is used as the main process, and Shi Xi is used. A compound (Silicide) gas such as silane (SH4) and a mixed gas such as hydrogen (Hydr〇gen H2) or argon (Arg〇n Ar) is used as a process gas. For example, mixing with decane gas and hydrogen; decane gas Mixing hydrogen with argon; mixing decane gas, decane gas and hydrogen; performing any of the processes of decane gas, misfired emulsion gas and argon mixture. By changing the mixing ratio of decane and hydrogen and process gas The N-type semiconductor layer 150 can be made into one of amorphous germanium, amorphous germanium, amorphous tantalum carbide, and nanocrystalline germanium. 12 201205828 In step 240 and step 270, the first electrode 160 and the second electrode 170 are use Any one of a group consisting of a steaming method, a sputtering method, a chemical vapor deposition method, an electroplating method, a wet chemical method, and a printing method, and the materials of the first electrode 160 and the second electrode 170 may be indium tin oxide. , tin dioxide, zinc oxide, impurity-containing tin oxide, impurity-containing oxidation, recording, gold, silver, chin, copper, handle, and chain. The thickness of the first electrode 160 and the second electrode 170 are introduced. Between 100 nm and 900 nm, the sheet resistance is between 5 Ω/□ and 10 Ω/□, and has a transmittance of 85% or more. Further, the materials of the first electrode 160 and the second electrode 170 Also available • Consists of two or more transparent conductive layers of different materials. It should be noted that the different first electrode 160 and second electrode 170 preparation methods also affect the quality of the photoelectric characteristics they have. However, in order to obtain a better surface roughness, the first electrode 160 and the second electrode 170 are deposited by low pressure chemical vapor deposition or formed by a sputtering process followed by an etching process. Preferably, the first electrode 160 and the second electrode 170 are composed of two transparent conductive layers of different materials. In the embodiment of the present invention, the doping concentration of the P-type semiconductor layer 130 is between 1 〇18 and 1 〇20 atoms/cm 3 , and the doping concentration of the N-type semiconductor layer 150 is 1 〇 8 to 1 〇 20 atoms/ Between cubic centimeters. Further, in an embodiment of the present invention, a hot wire chemical vapor deposition system is employed to prepare a germanium-based solar cell 100 having a heterojunction, and different first intrinsic (i-type) semiconductor layers 120, P-type semiconductors The manner in which the layer 130, the second intrinsic type (丨) semiconductor layer 140, and the N type semiconductor layer 150 are processed also affects the quality of the photoelectric characteristics thereof. In a preferred embodiment, the first intrinsic type (i type) semiconductor layer 120, the p type semiconductor layer 130, the second intrinsic type (i type) semiconductor layer 140 13 201205828, and the hot wire used in the N type semiconductor layer 150 A chemical vapor deposition system in which the hot wire temperature is between. (Between: C and C, and - the preferred heat degree is between 1800C and 2000C, the pressure of the cavity is between 5 mtorr and 5〇mt〇rr, and a preferred cavity pressure The system is between 10 mtorr and 30 mtorr; the temperature of the substrate 110 is between 20 and 35 (TC), and the preferred substrate 110 is between 25 C and 200. The plating rate of the cavity is between 3 ^ and 60 A / sec' and the plating rate of a preferred cavity is between 4 〇 A 々 刈 刈 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Another-implementation, miscellaneous chemical vapor deposition apparatus to prepare a solar cell 100 having a heterojunction of micro (10) m _. wherein the hybrid chemical vapor deposition apparatus uses a built-in electrode to generate a plasma for use in Prepare the microcrystalline precious (2) film required by the county solar cell with a heterojunction and heat it by a plurality of silk cells to increase the rate of the film. Therefore, the hybrid chemical vapor device can be used. Reduce the production cost, 'more can reduce the hydrogen content of the micro-mystery 121 to achieve better attention, when the substrate no is p-type Shixi substrate , The illuminating surface of the semiconductor layer 15〇 Ν7 'and p-type semiconductor layer 130 and the first I-square-type) semiconductor layer ⑼ back surface field effect (Back Surface Field, BSF) can be formed in. On the contrary,
當基板no為n型石夕基板時，則照光面為p型半導體層i3〇 = N 型半導體層⑼與第二本質型㈣）半導體層M㈣可形成背向 表面電場_k Surface Field，BSF)的效果。其中更包含下列步驟· 對第-電極⑽、第二電極170、第一本質型〇型）半導體層⑼、 第二本質型（i型）半導體層14G、P型半導體層13()以及_ 導體層i50進行-表面織化之製程，以增加入射光之散射率。 201205828 此外，步驟250至步驟270之流程可與步鄉22〇至步驟24〇互換， 亦即，將步驟250至步驟270提前至步驟21〇後實施。 、 本發明之-較佳實施射至少有—製減體經過純化步驟， 以減少製魏财_氣含量。縣氣财減含量過多將會在 沈積之薄麟構中產生過多氧空缺，造成太陽能電池中的載子移 動率降低，進而使發電效率降低。藉由進行純化氣體之步驟，該 較佳實施例中成長之薄膜之氧氣濃度低於5xl〇18原子/立方公分。 需注意的是，本發明所揭示之結構與方法，不僅適用於單一單元 ί 電池扣11) ’更可實施於模組化之太陽能電池製程。 综上所述，根據本發明之具有異質接面之石夕基太陽能電池 100及其製程方法，藉由微晶树薄膜之配置，使所製備之太陽能 電池具有下列優點：提升入射光之使用率與其光電轉換效率，達 到-提高電流特性與效率之具有異質接面之梦基太陽能電池。相 較於傳統單晶教陽能電池，本發明提出具有異質接面之石夕基太 陽能電池100具有的優點如下所示： I 1.無須高溫爐管製程，可降低生產耗能。 2·可有效增加紫外光的利用。 3. 可縮短製程時間，以提昇效能。 4. 與傳統單晶矽太陽能電池相比，其具有較高之轉換效率。 雖然本發明已以刖述較佳實施例揭示，然其並非用以限定本 發明，任何熟習此技藝者，在不脫離本發明之精神和範圍内，當 可作各種之更動與修改。如上述的解釋，都可以作各型式的修正 與變化，而不會破壞此發明的精神。因此本發明之保護範圍當視 後附之申請專利範圍所界定者為準。 15 201205828 【圖式簡單說明】 第1圖為本發明第一實施例之示意圖。 第2圖為本發明第一實施例之製程流程圖。 【主要元件符號說明】 1〇〇具有異質接面之矽基太陽能電池 110基板 111第一糙化表面 112 第二糙化表面 120第一本質型（i型）半導體層 121微晶矽質 130 P型半導體層 140第二本質型（i型）半導體層 150 N型半導體層 160 第一電極 170 第二電極When the substrate no is an n-type slab substrate, the illuminating surface is a p-type semiconductor layer i3 〇 = N-type semiconductor layer (9) and a second intrinsic type (four)) semiconductor layer M (4) can form a back surface electric field _k Surface Field, BSF) Effect. The method further includes the following steps: a first electrode (10), a second electrode 170, a first intrinsic germanium type semiconductor layer (9), a second intrinsic type (i type) semiconductor layer 14G, a p type semiconductor layer 13 (), and a _ conductor Layer i50 is subjected to a process of surface weave to increase the scattering rate of incident light. 201205828 In addition, the process from step 250 to step 270 can be interchanged with step 42 to step 24, that is, step 250 to step 270 are advanced to step 21 and implemented. Preferably, the present invention - at least one of the reduction bodies is subjected to a purification step to reduce the amount of Wei Cai - gas. Too much gas reduction in the county will result in excessive oxygen vacancies in the thin layer of sediment, resulting in a decrease in carrier mobility in solar cells, which in turn will reduce power generation efficiency. The film grown in the preferred embodiment has an oxygen concentration of less than 5 x 1 〇 18 atoms/cm 3 by the step of purifying the gas. It should be noted that the structure and method disclosed in the present invention are applicable not only to a single unit ί, but also to a modular solar cell process. In summary, according to the invention, the stone solar cell 100 having a heterojunction and a manufacturing method thereof, the solar cell prepared by the microcrystalline tree film has the following advantages: increasing the utilization rate of incident light With its photoelectric conversion efficiency, it achieves a dream-based solar cell with a heterojunction that improves current characteristics and efficiency. Compared with the conventional single crystal solar cell, the present invention proposes that the advantages of the Shiheji solar cell 100 having a heterojunction are as follows: I 1. The high-temperature furnace control process is not required, and the production energy consumption can be reduced. 2· can effectively increase the use of ultraviolet light. 3. Shorten process time to improve performance. 4. Compared with traditional single crystal germanium solar cells, it has higher conversion efficiency. While the invention has been described with respect to the preferred embodiments of the present invention, it is not intended to limit the invention, and various modifications and changes can be made without departing from the spirit and scope of the invention. As explained above, various modifications and variations can be made without departing from the spirit of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 15 201205828 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a first embodiment of the present invention. Figure 2 is a flow chart showing the process of the first embodiment of the present invention. [Main component symbol description] 1 矽 太阳能-based solar cell 110 substrate 111 having a heterojunction first roughened surface 112 second roughened surface 120 first intrinsic type (i-type) semiconductor layer 121 microcrystalline enamel 130 P Type semiconductor layer 140 second intrinsic type (i type) semiconductor layer 150 N type semiconductor layer 160 first electrode 170 second electrode