201143120 六、發明說明： 【發明所屬之技術領域】 e-vt·本么月係關於種使用於太陽能電池(S〇lar Ce丨丨）的製 程設備及方法’糾是針龍擇性射極(seleGtiveemjtter) 太陽能電池的製程設備及其製備方法。 【先前技術】201143120 VI. Description of the invention: [Technical field to which the invention pertains] e-vt·This month is a process equipment and method for the use of solar cells (S〇lar Ce丨丨) seleGtiveemjtter) Process equipment for solar cells and a method for preparing the same. [Prior Art]
I年來由於環保意識的抬頭和其他能源遂漸的枯 U使得世界各國開始重視再生能源的利用。由於太陽光 4 的天然能源’除了沒有能源耗盡的 σ 、卜，也可以避免能源被壟斷的問題。 ^而目$太陽能電池的光電轉換效率以及其製造成本， ==目前石化能源的條件，因此，如何增加太陽能源 1=/、1，以降低對石化能源驗賴’是目前最熱門的研 之*—。 =考1MA〜1G ’為習知的太陽能電池製程的剖面示意 U物:供一半_基材1’經過清洗後’將晶圓表面的雜質 趟面^低入除射光^圖反^接著，以酸液將基材1表面餘刻成粗 低入射叙反解，使人射光能得以充分_，如圖1B。 入含p型半導體基材1,在—含氧氣氛導 管進行吳的氣體’例如P2〇5、叫或％之退火爐 上，漆4丄柘放1私，以形成一摻雜層10於P型半導體基材1 域10換效應所需的P_N介面。與此同時，在N型區 牛驟曰同時形成一磷的氧化層16(P2〇5)，因此，在下一 / ‘而再以侧移除。否則以後續製程形成電極後，會增 4 201143120 增加電極與摻雜層1Q的串聯電阻，如® 1D所示。 接著，請參照圖1E，為了提高光的轉換效率，一層 成於摻雜層10上，緊接著在圖1F中顯示利用ιί L同Ρ方式將金屬槳料14印製於預定位置。最後，以掉姓 思使金屬漿料14穿透正面抗反射層13並滲入半導體二 1表層的換雜芦1Π择您人 -暴才才 1G所^ 合，以形成電極來使電流導出，如圖 併=般說來，太陽能電池電極14下方的推雜層1〇 祕 ^貝 >雜濃度愈高，愈能形成良好的歐姆 然：，重摻雜雖然可以降低電極14與摻雜層；。 卻^高電子和電洞__復合(「e_natim= 低光電轉換效率。 俄手而降 因此，-種稱為選擇性射極(se丨ective =就被發料來，㈣顧是只加重在金 電極導線外的吸光關是輕摻雜的以減少電子_電=對再 方面，電極導線是細的，以降低電極導線的 後率，但n刀佈是密的以利於導出電流。習知的 用雷射來輔助形成重摻雜區，或是在網印二木 摻雜的雜質，如:磷的化合物於繼 二ί透抗反射層與半導體基材結麵，购 然而，雷射辅助摻雜成本高，且製程時間 燒結形成電極的製程同時做摻雜的動作，复 、· 制，難以兼顧歐姆接觸的效果及摻雜的濃度。、^數不易控 在公開案號為20090309039的美國專利申請案中，揭示了 201143120 一種製備選擇性射極έ士+二、，ΕΙ ΟΛ « 2C 2D , 2H 〇 ^ 在半導料#1 ^ 麵成—層輕摻雜層1〇 體基材1表面’並去除氧化層之後， 遮罩15上細_口，定義出在半導 $ 摻雜區i2。之後，子植佈〇,由開口植入以形成蹵 9P . ν成抗反射層13於半導體基材1上，如同 ，並於重摻雜區12的預定處，以二 ===—金:漿= 單片電池的成本較高’離子佈植霉 池，發明之-目的係針對選擇性射極太陽能電 宜、=新的衣程’使之具有良好的光電轉換效率，又兼具便 省日寸的優點，為當前重要的研發課題之一。 【發明内容】 有#於上述課題’本發明之目_提供—種快速升溫 :RTA)加熱裝置，可針對—待處理之半導體基材上所 =疋的區域加熱，其特徵在於，快速升溫退火加熱裝置包 ^ -選區加減，選區加熱板上表面具有―熱反射膜 二.、、、反射膜層疋義-選區加熱圖案於&中，當進行快 ^溫退火時’選區加熱板置於半導體基材上方，以使選區 如熱板圖案開口下裸露的半導體基材被快速升溫加熱。 本發明之另-目的係提供—種形成太陽能電池選擇 性射極(selective emitter)結構的方法，包括：提供一 201143120 雜第一型導電性雜質的半導體基材；對摻雜第一型導電性 雜貝的半&體基材施以粗糙化處理（SU「faCe丨狀⑴卩丨叩）； ，一含氧氣氛導入含第二型導電性雜質的氣體之退火爐 官對該半導體基材進行雜質擴散製程，使該半導體基材表 層依序形成一第二型導電性雜質輕摻雜層及一第二型 電性雜質氧化層於其上。 设有，死以 拓， 咖圯人灭娜，亚提供一選區加熱In the past year, due to the rise of environmental awareness and the gradual decline of other energy sources, countries around the world have begun to pay attention to the use of renewable energy. Because of the natural energy of sunlight 4, in addition to the lack of energy σ, Bu, it can also avoid the problem of energy monopoly. ^ And the solar photovoltaic cell photoelectric conversion efficiency and its manufacturing costs, == current petrochemical energy conditions, therefore, how to increase the solar energy source 1 = /, 1 to reduce the petrochemical energy test 'is the most popular research *—. = test 1MA ~ 1G 'is a schematic view of the conventional solar cell process U: for half of the substrate 1 'after cleaning 'the surface of the wafer surface ^ low into the de-emitter ^ ^ ^ The acid solution engraves the surface of the substrate 1 into a coarse and low incidence, so that the human light can be sufficiently _, as shown in Fig. 1B. Into the p-type semiconductor substrate 1, in an oxygen-containing atmosphere conduit for the gas of wu, such as P2 〇 5, or % of the annealing furnace, the paint 4 丄柘 1 private, to form a doped layer 10 in P The semiconductor substrate 1 has a P_N interface required for the domain 10 switching effect. At the same time, a phosphorus phosphorous layer 16 (P2〇5) is formed simultaneously in the N-type region, so that it is removed on the next / ‘ side. Otherwise, after forming the electrode in a subsequent process, the series resistance of the electrode and the doped layer 1Q is increased by 4, 2011,320, as shown by ® 1D. Next, referring to Fig. 1E, in order to improve the light conversion efficiency, a layer is formed on the doped layer 10, and then the metal paddle 14 is printed at a predetermined position by the ιί L Ρ method in Fig. 1F. Finally, the metal paste 14 is passed through the front anti-reflective layer 13 and infiltrated into the surface of the semiconductor layer 1 to replace the surface of the semiconductor layer 1 to select the electrode to form an electrode to conduct current, such as In the same way, the higher the impurity concentration of the doping layer under the solar cell electrode 14 is, the better the ohmic is formed: the heavy doping can reduce the electrode 14 and the doped layer; . But ^ high electrons and holes __ compound ("e_natim = low photoelectric conversion efficiency. The Russian hand is down, therefore - the type is called selective emitter (se丨ective = it is sent, (4) Gu is only aggravated in The light-absorbing off-out of the gold electrode wire is lightly doped to reduce electrons. The electrode wire is thin to reduce the post-rate of the electrode wire, but the n-knife is dense to facilitate the current extraction. Laser-assisted formation of heavily doped regions, or impurities doped in screen-printed wood, such as: phosphorus compounds in the anti-reflective layer and semiconductor substrate surface, purchased, laser-assisted The doping cost is high, and the process of sintering to form an electrode simultaneously performs the doping action, and the complex and the system are difficult to achieve both the effect of ohmic contact and the concentration of doping. The number is difficult to control in the US with the publication number 20090309039 In the patent application, revealing 201143120 a preparation of selective emitters gentleman + two, ΕΙ ΟΛ « 2C 2D , 2H 〇 ^ in the semi-conducting material #1 ^ surface into a layer of lightly doped layer 1 〇 substrate 1 After the surface's removal of the oxide layer, the mask 15 is fine-mouthed and defined in the semi-conducting $ After the sub-region i2, the sub-plant fabric is implanted by the opening to form 蹵9P. ν is formed into the anti-reflective layer 13 on the semiconductor substrate 1, as in the predetermined portion of the heavily doped region 12, with two == =—Gold: Pulp = the cost of a single-chip battery is higher. 'Ion cloth mold pool, the invention - the purpose is to selectively emit solar energy, = new clothing process' to have good photoelectric conversion efficiency, and It is one of the most important research and development topics in the future. [Summary of the Invention] There is a problem in the above-mentioned subject 'The present invention provides a rapid temperature rise: RTA) heating device, which can be targeted Heating the area of the semiconductor substrate on the semiconductor substrate, characterized in that the rapid heating annealing device comprises the addition and subtraction of the selection region, and the surface of the heating plate on the selection region has a heat-reflecting film II, a reflective film layer, and a heating pattern of the selected region. In &, when the rapid annealing is performed, the 'selective heating plate is placed above the semiconductor substrate so that the semiconductor substrate exposed under the opening of the hot plate pattern is rapidly heated and heated. - Formation of solar cell selectivity A method of a selective emitter structure, comprising: providing a semiconductor substrate of a first type conductivity impurity of 201143120; and roughening a semi- & body substrate doped with the first type conductive beast ( SU "faCe丨(1)卩丨叩); an annealing furnace for introducing a gas containing a second type of conductive impurity into an oxygen-containing atmosphere, and performing an impurity diffusion process on the semiconductor substrate to form a surface of the semiconductor substrate in sequence A second type of conductive impurity lightly doped layer and a second type of electrically conductive impurity oxide layer are disposed thereon.
^有熱反射膜層，定義一選區加熱圖案於其中，撰 於半導體基材上方，使選區加熱板圖案開口下 含的第^基材被快速升溫加熱’以使雜質氧化層内所 區域電性雜質向内擴散，於半導體基材表層部分 成第一型導電性雜質重摻雜區。 之後’利用蝕刻方式將第二型導電性雜皙番换私 ;卜以導電_氧化層移除’二=以 ’以增加太陽能電池的 ^^There is a heat reflective film layer defining a selected area heating pattern therein, which is written on the semiconductor substrate, so that the first substrate contained in the opening of the selected area heating plate pattern is rapidly heated and heated to make the electric region in the impurity oxide layer The impurities diffuse inwardly into a heavily doped region of the first type of conductive impurities in the surface layer portion of the semiconductor substrate. After that, the second type of conductive enthalpy is exchanged by etching; the conductive _ oxide layer is removed and the second is replaced by ’ to increase the solar cell.
〜與、、z金/漿料於第二㈣電性雜質重摻雜區，ί;最 極^該些第二型導電性雜質重摻雜 區域的^提供-種以快速升溫退大(RTa 方法。同樣g句與輕摻雜區（丨咖〜a: 形成-第雜第—轉_时導縣材表:)的 質氣化=上導:性雜質輕摻雜層及-第二型導， 半導體。所t’利用本發明的快速升溫返火裝I、 雜質#的區域施以一快速升溫退火4鮮 體基材部^的第二型導電性雜質二次擴散，％ 域表層形成-第二型導電性雜^^攀 201143120 同時，本發明相對於先前製備太陽能電池選擇性射極 結構的方法而言，不但方法簡便，成本低廉，並且，縮短 了製程所花費的時間。 【貫施方式】 為使本發明之上述目的、特徵和優點能更明顯易 懂’下文依本發明太陽能電池選擇性射極（selective emitter)結構的製程設備及方法’特舉較佳實施例，並配 合所附相關圖式，作詳細說明如下，其中相同的元件將 以相同的元件符號加以說明。要說明的是，圖中各區域 尺寸比例僅為方便指明相對位置，而非實際計結構之放 大。 凊參照圖3A至圖3H，顯示本發明所提供形成太陽 能電池選擇性射極(selective emitter)結構的方法。請參 照圖3A，首先，提供一 n型或P型導電性雜質的半導 體基材3。本發明實施例中，係提供一 p型半導體基材 3。半導體基材3經過清洗(wafer cleaning)，以去除附 著於晶片表面的微粒及髒污。在太陽能電池的製程中，常使 用的溶液是氫氧化鈉(sodium hydroxide ;NaOH)或氫氧化卸 (potassium hydroxide ; KOH)。 接著’對P型半導體基材3施以粗糙化處理（surface texturing)，如圖3B所示。由於平坦的半導體基材3表 面會使部分太陽光反射而無法貢獻發電，為了減少反射 光的損失’會使用鹼性或酸性溶液以對半導體基材3表面 產生方向性姓刻(anisotropicetching)。比如，針對表面為⑴〇) 方向的石夕晶片而§，是利用氫氧化納（Na〇H)加^丙醇 (isoprcpyl alcohol ; IPA)溶液來使其表面產生大小不一的散亂 8 201143120 分布金子塔結構粗I造面。~ and , z gold / paste in the second (four) electrical impurity heavily doped region, ί; the most extreme of the second type of conductive impurities heavily doped region - provide rapid temperature rise (RTa) Method: The same g sentence and lightly doped area (丨 〜 ~ a: formation - the first miscellaneous - turn _ Shixian County material list:) quality gasification = upper: sexual impurities lightly doped layer and - second type Conducting, semiconductor, using the rapid temperature rise-return I, impurity # region of the present invention to apply a rapid temperature annealing 4 fresh-type substrate portion of the second type of conductive impurities secondary diffusion, % domain surface formation -Second Type Conductive Hybrid 201143120 At the same time, the present invention is not only simple in method, low in cost, but also shortens the time taken for the process, compared to the conventional method for preparing a solar cell selective emitter structure. The above objects, features and advantages of the present invention will be more apparent and understood. The following is a preferred embodiment of the process apparatus and method for a selective emitter structure of a solar cell according to the present invention. The attached drawings are described in detail below, in which the same elements are The same component symbols will be used for explanation. It should be noted that the size ratio of each region in the figure is only for convenience of indicating the relative position, and is not an enlargement of the actual structure. Referring to FIG. 3A to FIG. 3H, the solar energy provided by the present invention is shown. A method for selecting a selective emitter structure of a battery. Referring to FIG. 3A, first, a semiconductor substrate 3 having an n-type or P-type conductive impurity is provided. In the embodiment of the present invention, a p-type semiconductor substrate is provided. 3. The semiconductor substrate 3 is subjected to wafer cleaning to remove particles and dirt adhering to the surface of the wafer. In the process of solar cells, the commonly used solution is sodium hydroxide (NaOH) or hydroxide. (potassium hydroxide; KOH) Next, 'P-type semiconductor substrate 3 is subjected to surface texturing as shown in Fig. 3B. Since the surface of the flat semiconductor substrate 3 reflects part of sunlight, it cannot contribute to power generation. In order to reduce the loss of reflected light, an alkaline or acidic solution is used to produce anisotropicetching on the surface of the semiconductor substrate 3. For example, The surface is (1) 〇) direction of the stone wafer and §, is the use of sodium hydroxide (Na〇H) plus propanol (isoprcpyl alcohol; IPA) solution to make the surface of different sizes of scattered 8 201143120 distribution of gold tower The structure is thick and I is made.
請參照圖3C ’在-含氧氣氛導入含N型導電性雜質 氣體’例如P2〇5、PH3或PF3之退火爐管進行雜質擴鮮程， 以形成-雜_ 30於P料箱紐3上，戦p_N 體。而在此-製程中，也同時會形成—魏化層 ^ 於P型半導體基材3的表面上。 ~Referring to FIG. 3C, an impurity annealing process is performed in an annealing furnace tube containing an N-type conductive impurity gas such as P2〇5, PH3 or PF3 in an oxygen-containing atmosphere to form a hetero- 30 on the P-tank 3 , 戦p_N body. In this process, a Weiwei layer is also formed on the surface of the P-type semiconductor substrate 3. ~
本發明實施例和習知的製程不同的是，接下來會對 P型半導體基材3施以一快速升溫退火（RTA)製 圖3 D所示。 所提供的快速升溫退火裝置（RTA)的剖面示音圖， 可以針對半導體基材3上所選定的區域加熱。快^升溫 退火加熱裝置4至少包括一加熱源43及一選區加埶二 40,選區加熱板40設置於半導體基材3與加熱源4〇之 間，而選區加熱板40面對於加熱源40的表面具有一熱 反射膜層401。 ' 選區加熱板40為一透明基板，在本發明實施例 中，選區加熱板40是使用一石英基板。熱反射膜層4〇1 疋義一選區加熱圖案於其中，並選自輻射係數 (Emissivity Coefficient)介於 0.01 至 〇_〇75 之間的材 料’主要是用來阻擋熱源。本發明實施例中，熱反射膜 層401的材料通常為金屬’可選自金、録、銀、銅及其 任意組合所形成的群組其中之一種，或者是選用這些材 料的合金，可以達到較佳的效果，特別是在拋光後，效 果更佳。 當半導體基材3進行快速升溫退火時，僅使選區加 熱圖案開口下裸露的半導體基材3被快速升溫加熱，使 201143120 %氧化層31内所含的磷原子，向内擴散進入半導體基 材表層3，於部分區域形成一重摻雜區32，作為在後續 製程中即將要形成電極的位置。 以一較佳的實施例而言，選區加熱板3〇與半導體 基材3相距約〇.彳至數拾mm。當然，被局部加熱擴散 的區域將隨距離加大而擴大。換言之，選區加熱板30 開口大小並不需要和預定被加熱擴散的區域成1:1的關 係。在本發明實施例中，選區加熱板3〇和半導體基材3 相距約0.1至50 mm，有較佳的局部加熱效果。 圖3E中，顯示利用蝕刻方式將殘餘在半導體基材3 表面的碟氧化層31移除，以減少電子_電洞的再復合 (recombination)效應。 接著’為了增加太陽能電池的光使用效率，形成一 抗反射層33於半導體基材3表面’如圖3F。抗反射層 33的材料可選自二氧化矽（Si〇2)、二氧化鈦(Ti02)或氮 化矽（S^N4)其中之一種，並可採用濺鍍、蒸鍍或電漿辅 助化學氣相沉積等方式來製備。 下一步請參照圖3G，利用刮棒36將金屬漿料34 對準碟的重摻雜區32的位置，以網印方式印製於半導 體基材3表面。最後，施以一燒結處理，使金屬漿料34 穿透正面抗反射層43，並滲入半導體基材3表層，與重摻 雜區32緊密結合以形成電極34，如圖3H所示。 另外，配合本方法所使用的快速升溫退火加熱裝置 4詳細結構的剖面示意圖，可參照圖4 a。快速升溫退火 加熱裝置4具有一腔體41，除了前述元件之外，更包括 一溫控器42、一溫度感測器44、一載台45及一冷卻裝 m 10 201143120 置46。 腔體41内壁鍍著—熱反射膜層，以使加熱源43所 提供的熱此皆能集中至欲加熱的半導體基材3，使之能 夠快速升溫。 /凰#工為32疋用來設定加熱的參數及加熱程式，比 如·加熱源43所使用的功率、電流、將半導體基材3 加熱f某—溫度範圍所需時間、持溫的時間及降溫所需The embodiment of the present invention differs from the conventional process in that a P-type semiconductor substrate 3 is subsequently subjected to a rapid thermal annealing (RTA) pattern as shown in Fig. 3D. A cross-sectional sound map of the provided rapid temperature annealing device (RTA) can be applied to selected regions of the semiconductor substrate 3 for heating. The temperature heating annealing device 4 includes at least a heating source 43 and a selection region plus 40, the selection heating plate 40 is disposed between the semiconductor substrate 3 and the heating source 4, and the selection heating plate 40 faces the heating source 40. The surface has a heat reflective film layer 401. The selection heating plate 40 is a transparent substrate. In the embodiment of the invention, the selection heating plate 40 uses a quartz substrate. The heat-reflecting film layer 4〇1 selects a heating pattern therein and is selected from a material having an Emissivity Coefficient of between 0.01 and 〇_〇75, which is mainly used to block the heat source. In the embodiment of the present invention, the material of the heat reflective film layer 401 is generally one of a group selected from the group consisting of gold, recording, silver, copper, and any combination thereof, or an alloy of these materials can be used. The preferred effect, especially after polishing, is more effective. When the semiconductor substrate 3 is subjected to rapid temperature rising annealing, only the bare semiconductor substrate 3 under the opening of the selection heating pattern is heated rapidly, so that the phosphorus atoms contained in the 201143120% oxide layer 31 are diffused inward into the surface of the semiconductor substrate. 3. A heavily doped region 32 is formed in a portion of the region as a location where an electrode is to be formed in a subsequent process. In a preferred embodiment, the selection heating plate 3 is spaced from the semiconductor substrate 3 by a distance of about 彳. Of course, the area that is diffused by local heating will expand as the distance increases. In other words, the size of the opening of the selection heating plate 30 does not need to be in a 1:1 relationship with the area to be heated and diffused. In the embodiment of the present invention, the selection heating plate 3 is spaced apart from the semiconductor substrate 3 by about 0.1 to 50 mm, and has a better local heating effect. In Fig. 3E, the dish oxide layer 31 remaining on the surface of the semiconductor substrate 3 is removed by etching to reduce the recombination effect of the electron-hole. Next, in order to increase the light use efficiency of the solar cell, an antireflection layer 33 is formed on the surface of the semiconductor substrate 3 as shown in Fig. 3F. The material of the anti-reflection layer 33 may be selected from the group consisting of cerium oxide (Si〇2), titanium dioxide (Ti02) or tantalum nitride (S^N4), and may be sprayed, vapor-deposited or plasma-assisted chemical vapor phase. Preparation by deposition or the like. Next, referring to Fig. 3G, the metal paste 34 is aligned with the position of the heavily doped region 32 of the dish by the bar 36, and printed on the surface of the semiconductor substrate 3 by screen printing. Finally, a sintering treatment is applied to cause the metal paste 34 to penetrate the front anti-reflective layer 43 and penetrate into the surface layer of the semiconductor substrate 3 to closely bond with the heavily doped region 32 to form the electrode 34, as shown in Fig. 3H. Further, referring to Fig. 4a, a schematic cross-sectional view showing the detailed structure of the rapid temperature annealing heating device 4 used in the present method can be referred to. The rapid temperature annealing heating device 4 has a cavity 41 which, in addition to the foregoing components, further includes a temperature controller 42, a temperature sensor 44, a stage 45, and a cooling device m 10 201143120. The inner wall of the cavity 41 is plated with a heat reflective film layer so that the heat supplied from the heat source 43 can be concentrated to the semiconductor substrate 3 to be heated, so that it can be heated quickly. / ##工为32疋 is used to set the heating parameters and heating program, such as the power and current used by the heating source 43, the time required to heat the semiconductor substrate 3 to a certain temperature range, the temperature holding time and the temperature drop Required
時間等。而半導體基材3的溫度則藉由溫度感測器44 來監控。 1冷卻裝置46設置於載台45内部。當加熱源43 ^ 半導體基材3加熱以進行重摻雜區32的製程時，冷名 裝46可以控制半導體基材3的溫度曲線(the⑽ 吏雜質的擴散深度沖細-depth)及擴散電四 (res丨stance)達到最佳化。 、欣迅丨」 其中，加熱源43、溫度感測器44及冷卻 材3的溫度後，回度^心44制半導體！ 材3的溫度。胃於酿控$ 41，以精確控制半導體！ 載台45用來承載半導體基材 4〇即設置於載台月加熱由 快速升溫退火加^^^43中間。值得注意的是 選區加熱。只要改變載台45的尺寸，3 材’並於熱反射膜層_定義多個重動 m導=材Γ對準不同的半導體基材’就可以_ u + ¥體基材3同步進行選區加熱。 圖4B為本發明實施例選區加熱板4〇的俯視示清 201143120 圖。熱反射膜層401的選區加熱圖案是依據太陽能電池 的匯流排（busbar)及栅線（grid line)的位置來設計， 所以在本發明實施例中，橫向開口 4010即代表在後續 製程中將要形成匯流排的位置，縱向開口 4012代表將 要形成柵線的位置。當然匯流排及柵線的位置會依據美 觀需求做不同的調整，所以，選區加熱圖案也可以因應 匯流排及栅線的位置做不同的變化，並不限於本實施例 中所採用的圖案。 • 本發明的快速升溫退火裝置，在本實施例中雖然是 用在製備選擇性射極的太陽能電池，但是其應用並不僅 限於此’實質上也可以應用在其他製程。比如，可以利 用本發明之快速加熱退火裝置，於半導體表層區域選擇 重摻雜區與輕摻雜區。 其作法同樣是在半導體基材表層先形成一輕摻雜層 及一雜質氧化層後，再對半導體基材所選定的區域做快 速升溫加熱’㈣成-重摻雜區。最後，制射虫刻方 0 式將雜質氧化層移除。 综上所述，本發明所提供的形成太陽能電池選擇性 射極（Se丨ective emitter)結構的方法及快速升溫退火裝 置，相較於習知技術而言具有下列優點： ⑴方法簡便，成本低廉。本發明中只要在快速升溫 =罢破置中牦:又一砥區加熱板，就可以只加熱預設的 。應用在形成太陽能電池選擇性射極（selective emitter)結構時，本發明相較於採用離子佈值的習知技術 而言，不但製程方法簡單，且成本更低。 (2)快速升溫退火裝置可使多片半導體基材同步進 [S3 12 201143120 行選區力η熱製程，有利於大量生產。 (3)由於熱反射膜層的圖案會對應到半導體表面 要形成電極的位置。所以，當半導體表面的電極為了你 建築物美觀，而做出不同的花紋設計時，熱反射膜屛= 圖案在製備fl#也㈣合作變更。但本發財的選區^教 板及熱反射膜層圖案製備十分容易，所W卩使要ς 導體表面電極的分布做變更時，不需要耗費太 即可達到上述需求。 ' 承’ 本發明雖以較佳實例闡明VJL，然其並非 本發明精神與發明實體僅止於上述實施例。凡孰朵2 技術者，當可輕易了解並利用其它元件或方式來產目 同的功效。是以，在不脫離本發明之精神與範轉内所作 之修改，均應包含在下述之申請專利範圍内。 201143120 【圖式簡單說明】 圖1A至1G顯示習知的太陽能電池製程的示意圖； 圖2A至2H顯示習知的選擇性射極太陽能電池製程的 不意圖， 圖3A至3H顯示本發明之選擇性射極太陽能電池製程 的示意圖； 圖4A本發明實施例之快速升溫退火裝置之剖面示意 圖，及 圖4 B本發明實施例之選區加熱板之俯視圖。 【主要元件符號說明】 1 3 ： 半導體基材 10 、30 :輕掺雜層 11 、31 :雜質氧化層 12 > 32 :重摻雜區 13 、33 :抗反射層 14 、34 :金屬 15 :遮罩 16 、36 :到棒 4 ： 升溫退火加熱裝置 40 •選區加熱板 401 :熱反射膜層 41 :腔f 酸 42 :溫控器 [s] 14Time and so on. The temperature of the semiconductor substrate 3 is monitored by a temperature sensor 44. The cooling device 46 is disposed inside the stage 45. When the heating source 43 ^ semiconductor substrate 3 is heated to perform the process of the heavily doped region 32, the cold name package 46 can control the temperature profile of the semiconductor substrate 3 (the (10) 扩散 impurity diffusion depth-depth) and diffusion electricity (res丨stance) to achieve optimization. After the temperature of the heating source 43, the temperature sensor 44 and the cooling material 3, the semiconductor 44 is made up! The temperature of the material 3. The stomach is brewed for $41 to precisely control the semiconductor! The stage 45 is used to carry the semiconductor substrate 4, that is, it is placed on the stage and heated by the rapid temperature annealing plus ^^^43. It is worth noting that the selection is heated. As long as the size of the stage 45 is changed, the 3 material 'and the heat reflective film layer _ define a plurality of repetitive m guides = material Γ aligned with different semiconductor substrates' can be _ u + ¥ body substrate 3 synchronous selection heating . FIG. 4B is a top plan view of the selection zone heating plate 4 2011 according to an embodiment of the present invention. The selection heating pattern of the heat reflective film layer 401 is designed according to the position of the busbar and the grid line of the solar cell, so in the embodiment of the invention, the lateral opening 4010 represents that it will be formed in the subsequent process. The position of the bus bar, the longitudinal opening 4012 represents the position at which the grid lines are to be formed. Of course, the position of the bus bar and the grid line are adjusted differently according to the aesthetic requirements. Therefore, the selection heating pattern can also be changed according to the position of the bus bar and the grid line, and is not limited to the pattern used in the embodiment. The rapid temperature annealing device of the present invention is used in the preparation of a selective emitter solar cell in this embodiment, but its application is not limited to this, and can be applied to other processes. For example, the rapid heating annealing apparatus of the present invention can be used to select heavily doped regions and lightly doped regions in the semiconductor surface region. The method is also to form a lightly doped layer and an impurity oxide layer on the surface of the semiconductor substrate, and then rapidly heat up the selected region of the semiconductor substrate to form a (four) into a heavily doped region. Finally, the insect-injection method removes the impurity oxide layer. In summary, the method for forming a solar cell selective emitter (Equivalent Emitter) structure and the rapid temperature annealing device provided by the present invention have the following advantages compared with the prior art: (1) The method is simple and the cost is low. . In the present invention, as long as the rapid heating = breaking the 牦: another 加热 zone heating plate, it is possible to heat only the preset. When applied to the formation of a solar cell selective emitter structure, the present invention is simpler and less costly than conventional techniques using ion cloth values. (2) The rapid temperature annealing device can synchronize multiple semiconductor substrates into the [S3 12 201143120 row selection force η thermal process, which is conducive to mass production. (3) Since the pattern of the heat reflective film layer corresponds to the position at which the semiconductor surface is to be formed. Therefore, when the electrodes on the surface of the semiconductor make a different pattern design for the aesthetic appearance of your building, the heat reflective film 屛 = pattern is changed in the preparation of fl# (4). However, the preparation of the selection and the heat-reflecting film layer of the present invention is very easy, and the above-mentioned requirements can be achieved without consuming too much when the distribution of the electrode surface of the conductor is changed. The present invention, while exemplifying VJL by a preferred embodiment, is not the spirit of the invention and the inventive entity is merely limited to the above embodiments. Anyone who knows how to use it can easily understand and use other components or methods to produce the same effect. Modifications made without departing from the spirit and scope of the invention are intended to be included within the scope of the appended claims. 201143120 [Simplified Schematic] FIGS. 1A to 1G show schematic views of a conventional solar cell process; FIGS. 2A to 2H show a conventional process of a selective emitter solar cell process, and FIGS. 3A to 3H show the selectivity of the present invention. FIG. 4A is a schematic cross-sectional view of a rapid temperature annealing device according to an embodiment of the present invention, and FIG. 4B is a top view of a selection heating plate of an embodiment of the present invention. [Description of main component symbols] 1 3 : Semiconductor substrate 10, 30: lightly doped layer 11, 31: impurity oxide layer 12 > 32: heavily doped region 13, 33: antireflection layer 14, 34: metal 15: Mask 16, 36: to rod 4: temperature-annealing annealing device 40 • selection heating plate 401: heat-reflecting film layer 41: cavity f acid 42: thermostat [s] 14