201142968 t、發明說明： 【發明所屬之技術領域】 本發明係有關一種半導體封裝技術，特別是一種半導體 封裝結構及其製造方法。 【先前技術】 於半導體封裝製程中，由於電子產品輕薄短小的趨勢加 上功能不斷增多，使得封裝密度隨之不斷提高，亦不斷縮小 封裝尺寸與改良封裝技術。如何開發高密度與細間距的封裝 製程與降低製造成本一直為為此技術領域之重要課題。 【發明内容】 • * · - . .. . . 本發明目的之一係提供一種半導體封裝結構及其製造方 法，利用介電材料層電性隔絕複數導電跡線以形成介電材料 層基板，可獲得高密度與細間距的封裝製程且提高製程與產 品良率。 本發明目的之一係提供一種半導體封裝結構之製造方 法，係包括下列步驟：提供一封裝載板，其中封裝載板之至 少一表面設置一可剝離金屬層；形成一第一導電跡線於該可 剝離金屬層上，其中第一導電跡線環繞於一晶片承載區域之 周圍，且第一導電跡線含有複數導電接墊設置於其上；形成 一介電材料層覆蓋第一導電跡線與可剝離金屬層，並露出導 電接塾的上表面，以形成一介電材料層基板；設置一晶片於 介電材料層基板上並位於封裝載板之晶片承載區域上方，且 電性連接晶片之主動面與導電接墊；形成一封裝膠體覆蓋晶 片與介電材料層基板之上表面；移除封裝載板以暴露出介電 201142968 材料層基板之下表面；形成一圖案化防焊層於介電材料層基 板之下表面’其中部分第一導電跡線之多個對外導電接點係 暴露於圖案化防焊層之外；以及形成一第一金屬最終表面處 理層於對外導電接點上。 本發明目的之一係提供一種半導體封裝結構，係包括： "電材料層基板，包括一第一導電跡線環繞於一晶片承載 區域之周圍且複數導電接墊設置於該第一導電跡線上；以及 一介電材料層包覆第一導電跡線與導電接墊，使第一導電跡 線電性隔絕，其中部份導電接墊暴露於介電材料層基板之上 表面；及部分第一導電跡線曝露於介電材料層基板之下表 面。一晶片設置於介電材料層基板上，並與導電接墊電性連 接。一封裝膠體覆蓋晶片、第一導電跡線與介電材料層基板 之^表面。一圖案化防焊層設置於介電材料層基板之下表面 ，露出第一導電跡線之多個對外導電接點。以及一第一金屬 最終表面處理層設置於對外導電接點上。 以下藉由具體實施例配合所附的圖式詳加說明，當更容 易瞭解本發明之目的、技_容、特點及其所達成之:效。 【實施方式】 以限 其詳細說明如下’所述較佳實施例僅做 疋本發明。 造方11為本發明—實關之半導體封裝結構之製 之意圖。於本實施例中，半導體封裝結構 載板_，其中封料板_之至彡、一封裝 離金屬層uo。於一實施例中 置-可剝 為金屬材質或易剝離金屬表面，心二= 201142968 除作業。之後，如圖1B所示，於可剝離金屬層上形成 第導電跡線（conductive trace )，如導電跡線12〇，且導 電跡線120含有複數導電接墊122設置於其上。 接續上述說明，此導電跡線12〇可利用電鍍、蝕刻或轉 印方式所製成。此外，導電跡線120係環繞設置於封裝載板 11〇上之一晶片承載區域112之周圍。接著，請參照圖， 形成一介電材料層130覆蓋導電跡線120與可剝離金屬層 110’並暴露出導電接墊122的上表面以形成一介電材料層基 板130’。再來，請參考圖1D，將一晶片14〇設置於介電材料 層基板130’上並位於封裝載板1〇〇之晶片承載區域ιΐ2上 方，且如圖1E所示，電性連接晶片140之主動面與導電接 墊122。接著，請參照圖1F，形成一封裝膠體15〇覆蓋晶片 140與介電材料層基板13〇’之上表面。 再來’移除封裝載板100，如圖1G所示·。導電跡線12〇 暴ji·於介電材料層基板130’之下表面。接著，請參照圖〖Η， 形成一圖案化防焊層160於介電材料層基板130,之下表面， 其中部分導電跡線120之多個對外導電接點123係暴露於圖 案化防焊層160之外。之後，如圖II所示，形成一第—金屬 最終表面處理層，如金屬最終表面處理層170，於對外導電 接點123上。於此，上述步驟可形成一四邊扁平無接聊晶片 封裝結構。於又一實施例中，亦可設置多個導電焊球18〇於 對外導電接點123上並藉由金屬最終表面處理層17〇與其電 性連接’而形成如圖1J所示之球柵陣列晶片封裝結構（ball grid array，BGA )。 於上述實施例中，晶片140係以打線方式與介電材料層 基板130’上的導電接墊122電性連接。於不同實施例中，如 圖2所示’晶片140可有不同的設置方式，例如可將晶片14〇 之主動面朝下並以覆晶（flip-chip)方式與導電接墊122電性連 6 201142968 接。如圖所示，晶片140可利用導電焊球或凸塊(bump)182 與導電接墊122電性連接。 於又一實施例中，請參照圖3 A至圖3L，形成導電跡線 120包括下列步驟。於本實施例中，係採用電鍍方式製作導 電跡線120。首先，如圖3B所示，形成一第一圖案化光阻層 2〇〇於可剝離金屬層11〇上用以定義出導電跡線120之圖案。 之後，電鐘形成導電跡線120於可剝離金屬層110上。 接著，請參照圖3C，在形成導電跡線120後與移除第一 圖案化光阻層200前，更包括形成一第二圖案化光阻層202 於第一圖案化光阻層200與導電跡線120上，其中第二圖案 化光阻層202係暴露出導電跡線120之多個導電接點ι21。 接著，如圖3D所示，電鍍形成導電接墊122於導電跡線12〇 之導電接點121上。再來，如圖3E所示，同時移除第一圖 案化光阻層200 (如圖3D)與第二圖案化光阻層202 (如圊 3D )以完成導電跡線120與導電接墊122之製作。 接著，請參考圖3F及圖3G，利用沉積或者塗布方式形 成介電材料層130覆蓋利用上述步驟所完成的導電跡線 120、其上之導電接墊122與可剝離金屬層11〇後，利用研磨 的方式移除部分介電材料層130以露出上述導電接墊122， 於此，即完成介電材料基板130,之製作。 ' 與上述實施例不同的是，於此實施例中，如圖3h所示， 在設置晶片之前，更包括形成一第二導電跡、線，如導電跡線 124’於介電材料層基板13G，上轉高其後晶片打線的位置， 其中導電跡線124與導電祕122上的導電接塾122係電性 連接，著’繼續參考圖3H’可選擇性於導電跡線124上形 成-第二金屬最終表面處理層。此金屬最終表面處理層Μ 可有助於晶片與導電跡線124之電性連接。 201142968 接、.只上述，參照圖31與圖3J，將晶片14〇設置於介電材 料層基板請’上後進行打線及封裝程序，與上述實施例差異 在於，晶片140與導電跡線124上的金屬最終表面處理層π 電性連接，稍微將打線位置塾高，可提高打線製程良率。 接著，如圖3K及圖3L所顯示移除封裝載板後之步驟與 上一實施例相同，此處即不再贅述。 利用上述實施例之製作方法所形成之結構如圖π、圖 1Η、圖2與圖3L所示，可實作成四邊扁平無接腳晶片封裝 結構（如圖11、圖3L )亦或者球柵陣列晶片封裝結構（如圖 1Η、圖2)。一實施例中，本發明之半導體封裝結構包括：一 介電材料層基板130’，包括一第一導電跡線，如導電跡線 120，繞於·一晶片承載區域II2之周圍且複數導電接塾122 設置於導電跡線120上；以及一介電材料層丨3〇包覆上述導 電跡線120與導電接墊Γ22 ,使導電跡線no電性隔絕，其 中部份導電接墊122暴露於介電材料層基板130’之上表面； 及部分導電跡線120曝露於介電材料層基板130’之下表面。 一晶片140設置於介電材料層基板130’上，並與導電接墊122 電性連接，於一實施例中，複數個金線142用以電性連接晶 片140與導電接墊122 (如圖Π、圖1J);於又一實施例中， 複數個凸塊182用以電性連接晶月140與導電接墊122 (如 圖2)。一封裝膠體150覆蓋晶片140與介電材料層基板130’ 之上表面。一圖案化防焊層160設置於介電材料層基板130’ 之下表面以露出導電跡線120上之多個對外導電接點123 ; 以及一第一金屬最終表面處理層，如金屬最終表面處理層 170,設置於對外導電接點123上供半導體封裝結構與外界裝 置電性連接。 於一實施例中，如圖1J所示，一黏著層190設置晶片140 與介電材料層基板130’之間以供晶片140固著於介電材料層 201142968 基板130’上之用。於又一實施例中，如圖3L所示，為提高 晶片140打線良率，結構中更可包括一第二導電跡124線設 置於介電材料層基板130’上，其中第二導電跡124線一端與 導電接墊122電性連接，一另端與晶片140電性連接。此外， 如又一實施例中，更包括一第二金屬最終表面處理層172選 擇性設置於導電接墊122 (如圖1J)，以增加金線142與導電 接墊122的鍵結力；或者第二金屬最終表面處理層172選擇 性設置於第二導電跡線124上（如圖3L)，以增加金線142 與第二導電跡線124的鍵結力。 更者，如圖1J、圖2，所示，多個導電焊球180，係設置 於介電材料層基板130’之下表面並與導電跡線122透過金屬 最終表面處理層170電性連接。 根據上述說明，本發明之特徵在於本發明製程方法所製 成之半導體封裝結構可為需要高密度與細間距之四邊爲平無 接腳晶片封裝結構，或者，為球柵陣列晶片封裝結構，應用 上相當彈性。導電跡線的製作可用多種方式，如直接轉印、 電鍍或蝕刻等。導電跡線除了可為單層結構外亦可為多層結 構，可因應晶片需要提供不同變化。 綜合上述說明，本發明之半導體封裝結構及其製造方 法，利用介電材料層電性隔絕複數導電跡線以形成介電材料 層基板，可獲得高密度與細間距的封裝製程且提高製程與產 品良率。 以上所述之實施例僅係為說明本發明之技術思想及特 點，其目的在使熟習此項技藝之人士能夠瞭解本發明之内容 並據以實施，當不能以之限定本發明之專利範圍，即大凡依 本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本 發明之專利範圍内。 201142968 【圖式簡單說明】 圖1A、圖1B、圖1C、圖1D、圖1E、圖1F、圖1G、圖1H、 圖II與圖1J與為本發明實施例之剖面示視圖。 圖2為本發明不同實施例之剖面示視圖。 圖3A、圖3B、圖3C、圖3D、圖3E、圖3F、圖3G、圖3H、 圖31、圖3 J、圖3K與圖3L為本發明又一實施例之剖面示視 圖。 【主要元件符號說明】 100 封裝載板 102 表面 110 .. 可剝.離金屬層. 112 晶片承載區域 120, 124 導電跡線 121, 123 導電接點 122 導電接墊 130 介電材料層 130， 介電材料層基板 140 晶片 142 金線 150 封裝膠體 160 圖案化防焊層 170, 172 金屬最終表面處理層 201142968 180 導電焊球 182 凸塊 190 黏著層 200, 202 圖案化光阻層201142968 t, invention description: TECHNICAL FIELD The present invention relates to a semiconductor package technology, and more particularly to a semiconductor package structure and a method of fabricating the same. [Prior Art] In the semiconductor packaging process, as the trend of thinner and lighter electronic products increases, the package density continues to increase, and the package size and package technology are further reduced. How to develop high-density and fine-pitch packaging processes and reduce manufacturing costs has always been an important issue in this technology field. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package structure and a method of fabricating the same, which electrically isolates a plurality of conductive traces by using a dielectric material layer to form a dielectric material layer substrate. Get high-density and fine-pitch packaging processes and increase process and product yield. One object of the present invention is to provide a method of fabricating a semiconductor package structure, comprising the steps of: providing a loading board, wherein at least one surface of the package carrier is provided with a strippable metal layer; and a first conductive trace is formed thereon a strippable metal layer, wherein the first conductive trace surrounds a wafer carrying region, and the first conductive trace includes a plurality of conductive pads disposed thereon; forming a dielectric material layer covering the first conductive trace and Stripping the metal layer and exposing the upper surface of the conductive interface to form a dielectric material layer substrate; disposing a wafer on the dielectric material layer substrate and above the wafer carrying region of the package carrier, and electrically connecting the wafer The active surface and the conductive pad; forming an encapsulant covering the upper surface of the substrate and the dielectric material layer substrate; removing the package carrier to expose the lower surface of the dielectric 201142968 material layer substrate; forming a patterned solder mask layer a plurality of outer conductive contacts of the lower surface of the electrically conductive layer substrate are exposed to the outside of the patterned solder resist; and forming a The first metal final surface treatment layer is on the outer conductive contact. An object of the present invention is to provide a semiconductor package structure comprising: an electric material layer substrate comprising a first conductive trace surrounding a wafer carrying region and a plurality of conductive pads disposed on the first conductive trace And a dielectric material layer covering the first conductive trace and the conductive pad to electrically isolate the first conductive trace, wherein a portion of the conductive pad is exposed on the upper surface of the dielectric material substrate; and part of the first The conductive traces are exposed to the underlying surface of the dielectric material layer substrate. A wafer is disposed on the dielectric material layer substrate and electrically connected to the conductive pads. An encapsulant covers the surface of the wafer, the first conductive trace and the dielectric material layer substrate. A patterned solder mask is disposed on the lower surface of the dielectric material layer substrate to expose a plurality of external conductive contacts of the first conductive trace. And a first metal final surface treatment layer is disposed on the outer conductive contact. The details of the present invention, the features, the features, and the effects achieved by the present invention will be more apparent from the detailed description of the embodiments. [Embodiment] The present invention is described in detail by the following detailed description. The manufacturer 11 is the intention of the invention to manufacture the semiconductor package structure. In this embodiment, the semiconductor package structure carrier board _, wherein the sealing board _ to 彡, one package away from the metal layer uo. In one embodiment, it can be stripped to a metal material or an easily peelable metal surface, and the heart is = 201142968. Thereafter, as shown in FIG. 1B, a conductive trace, such as conductive trace 12, is formed over the strippable metal layer, and conductive trace 120 includes a plurality of conductive pads 122 disposed thereon. Following the above description, the conductive traces 12 can be formed by electroplating, etching or transfer. In addition, the conductive traces 120 are disposed around one of the wafer carrying regions 112 on the package carrier 11A. Next, referring to the figure, a dielectric material layer 130 is formed to cover the conductive traces 120 and the strippable metal layer 110' and expose the upper surface of the conductive pads 122 to form a dielectric material layer substrate 130'. Referring to FIG. 1D, a wafer 14 is disposed on the dielectric material substrate 130' and above the wafer carrying region ι2 of the package carrier 1A, and electrically connected to the wafer 140 as shown in FIG. 1E. The active surface and the conductive pad 122. Next, referring to FIG. 1F, an encapsulant 15 is formed to cover the upper surface of the wafer 140 and the dielectric material layer substrate 13'. Then, the package carrier 100 is removed, as shown in Fig. 1G. The conductive traces 12 are on the lower surface of the dielectric material layer substrate 130'. Next, referring to the figure, a patterned solder mask layer 160 is formed on the lower surface of the dielectric material layer substrate 130, and a plurality of outer conductive contacts 123 of the portion of the conductive traces 120 are exposed to the patterned solder resist layer. Outside of 160. Thereafter, as shown in FIG. II, a first metal final surface treatment layer, such as a metal final surface treatment layer 170, is formed on the outer conductive contact 123. Here, the above steps can form a four-sided flat non-talking chip package structure. In another embodiment, a plurality of conductive solder balls 18 may be disposed on the outer conductive contacts 123 and electrically connected to the metal final surface treatment layer 17 to form a ball grid array as shown in FIG. 1J. A ball grid array (BGA). In the above embodiment, the wafer 140 is electrically connected to the conductive pads 122 on the dielectric material substrate 130' in a wire bonding manner. In different embodiments, as shown in FIG. 2, the wafer 140 may be provided in different manners, for example, the active surface of the wafer 14 may be turned down and electrically connected to the conductive pads 122 in a flip-chip manner. 6 201142968 Pick up. As shown, the wafer 140 can be electrically connected to the conductive pads 122 using conductive solder balls or bumps 182. In yet another embodiment, referring to Figures 3A through 3L, forming conductive traces 120 includes the following steps. In the present embodiment, the conductive traces 120 are formed by electroplating. First, as shown in FIG. 3B, a first patterned photoresist layer 2 is formed on the strippable metal layer 11 to define a pattern of conductive traces 120. Thereafter, the electric clock forms conductive traces 120 on the strippable metal layer 110. Next, referring to FIG. 3C, after forming the conductive traces 120 and before removing the first patterned photoresist layer 200, further comprising forming a second patterned photoresist layer 202 on the first patterned photoresist layer 200 and conducting On the trace 120, the second patterned photoresist layer 202 exposes a plurality of conductive contacts ι21 of the conductive traces 120. Next, as shown in FIG. 3D, a conductive pad 122 is formed on the conductive contacts 121 of the conductive traces 12A. Then, as shown in FIG. 3E, the first patterned photoresist layer 200 (as shown in FIG. 3D) and the second patterned photoresist layer 202 (such as 圊3D) are simultaneously removed to complete the conductive traces 120 and the conductive pads 122. Production. Next, referring to FIG. 3F and FIG. 3G, the dielectric material layer 130 is formed by deposition or coating to cover the conductive traces 120 completed by the above steps, the conductive pads 122 and the strippable metal layer 11 thereon, and then utilized. A portion of the dielectric material layer 130 is removed by polishing to expose the conductive pads 122, thereby completing the fabrication of the dielectric material substrate 130. Different from the above embodiment, in this embodiment, as shown in FIG. 3h, before the wafer is disposed, a second conductive trace, such as a conductive trace 124' is formed on the dielectric material layer substrate 13G. The position of the wafer is turned up, wherein the conductive trace 124 is electrically connected to the conductive interface 122 on the conductive secret 122, and can be selectively formed on the conductive trace 124 by continuing to refer to FIG. 3H. The final surface treatment layer of the two metals. This metal final surface finish layer can facilitate electrical connection of the wafer to conductive traces 124. Referring to FIG. 31 and FIG. 3J, the wafer 14 is placed on the dielectric material substrate, and then the wiring and packaging process is performed. The difference from the above embodiment is that the wafer 140 and the conductive trace 124 are on the same. The metal final surface treatment layer π is electrically connected, and the wire position is slightly increased to improve the wire bonding process yield. Next, the steps after removing the package carrier as shown in FIG. 3K and FIG. 3L are the same as those in the previous embodiment, and are not described herein again. The structure formed by the manufacturing method of the above embodiment can be realized as a four-sided flat chipless chip package structure (such as FIG. 11 and FIG. 3L) or a ball grid array, as shown in FIG. π, FIG. 1A, FIG. 2 and FIG. 3L. Chip package structure (Figure 1, Figure 2). In one embodiment, the semiconductor package structure of the present invention comprises: a dielectric material layer substrate 130' including a first conductive trace, such as a conductive trace 120, around a wafer carrying region II2 and a plurality of conductive connections The conductive layer 120 is disposed on the conductive trace 120; and a conductive material layer 〇3 〇 covers the conductive trace 120 and the conductive pad 22 to electrically isolate the conductive trace no, wherein a portion of the conductive pad 122 is exposed The upper surface of the dielectric material layer substrate 130'; and a portion of the conductive traces 120 are exposed on the lower surface of the dielectric material layer substrate 130'. A wafer 140 is disposed on the dielectric material substrate 130' and electrically connected to the conductive pads 122. In one embodiment, the plurality of gold wires 142 are used to electrically connect the wafer 140 and the conductive pads 122 (as shown in the figure). 1, FIG. 1J); in still another embodiment, a plurality of bumps 182 are used to electrically connect the crystal moon 140 and the conductive pads 122 (FIG. 2). An encapsulant 150 covers the upper surface of the wafer 140 and the dielectric material layer substrate 130'. A patterned solder mask layer 160 is disposed on a lower surface of the dielectric material layer substrate 130' to expose a plurality of outer conductive contacts 123 on the conductive traces 120; and a first metal final surface treatment layer, such as a metal final surface treatment The layer 170 is disposed on the external conductive contact 123 for electrically connecting the semiconductor package structure to the external device. In one embodiment, as shown in FIG. 1J, an adhesive layer 190 is disposed between the wafer 140 and the dielectric material substrate 130' for the wafer 140 to be adhered to the dielectric material layer 201142968 substrate 130'. In another embodiment, as shown in FIG. 3L, in order to improve the wire bonding yield of the wafer 140, the structure further includes a second conductive trace 124 disposed on the dielectric material layer substrate 130', wherein the second conductive trace 124 One end of the wire is electrically connected to the conductive pad 122, and the other end is electrically connected to the chip 140. In addition, as another embodiment, a second metal final surface treatment layer 172 is further disposed on the conductive pads 122 (FIG. 1J) to increase the bonding force between the gold wires 142 and the conductive pads 122; The second metal final surface treatment layer 172 is selectively disposed on the second conductive trace 124 (as in FIG. 3L) to increase the bonding force of the gold line 142 and the second conductive trace 124. Furthermore, as shown in FIG. 1J and FIG. 2, a plurality of conductive solder balls 180 are disposed on the lower surface of the dielectric material layer substrate 130' and electrically connected to the conductive traces 122 through the metal final surface treatment layer 170. According to the above description, the present invention is characterized in that the semiconductor package structure formed by the process method of the present invention can be a flat chipless package structure with four sides requiring high density and fine pitch, or a ball grid array chip package structure, application. It is quite flexible. Conductive traces can be fabricated in a variety of ways, such as direct transfer, electroplating, or etching. In addition to being a single layer structure, the conductive traces can also be multi-layer structures that can vary depending on the needs of the wafer. In summary, the semiconductor package structure and the method of fabricating the same according to the present invention utilize a dielectric material layer to electrically isolate a plurality of conductive traces to form a dielectric material layer substrate, thereby obtaining a high-density and fine-pitch packaging process and improving processes and products. Yield. The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the objects of the present invention can be understood by those skilled in the art, and the scope of the present invention cannot be limited thereto. That is, the equivalent variations or modifications made by the spirit of the present invention should still be included in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, II and 1J are cross-sectional views of an embodiment of the present invention. Figure 2 is a cross-sectional view of a different embodiment of the present invention. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 31, 3J, 3K and 3L are cross-sectional views showing still another embodiment of the present invention. [Major component symbol description] 100 package carrier 102 surface 110 .. strippable metal layer. 112 wafer bearing area 120, 124 conductive traces 121, 123 conductive contacts 122 conductive pads 130 dielectric material layer 130, Electrical material layer substrate 140 wafer 142 gold wire 150 encapsulant 160 patterned solder mask 170, 172 metal final surface treatment layer 201142968 180 conductive solder ball 182 bump 190 adhesive layer 200, 202 patterned photoresist layer