TW201131731A - Semiconductor multi-package module having wire bond interconnection between stacked packages - Google Patents

Abstract

A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Description

201131731 VI. INSTRUCTIONS: CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Application Serial No. 60/41, the entire disclosure of which is incorporated herein by reference. This application also claims the priority of the following U.S. applications, each of which was filed on August 2, 2003: U.S. Application Serial No. 10/632,549, entitled "Semiconductor Multi-Package Module with Wire Junction Interconnects in Stacked Packages ("Semi-multiple-package module having wire bond interconnection between stacked packages"; US Application No. 1 0/632,568, entitled "Package with Stacked on Ball Grid Array Package, with Wire Connection Between Stacked Packages" "Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnection between stacked packages"; US application number 10/632,551, entitled "Between stacked packages " Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield"; US application number 10/632,552, entitled "with stacking Flip wafer ball on grain facing up " Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect" Between stacked packages"); United States 155479. Doc 201131731 Application No. l〇/632,553, entitled "Semiconductor Multipackage Package Module with Packages Stacked on a Chip-Back Flip Chip Ball Grid Array Package with Wire Junction Interconnect Between Stacked Packages Having package stacked over die-down flip chip ball grid array package and having wire bond mterconnect between stacked packages"); US Application No. 10/632,550, entitled "Includes stacked die packages and has wire bonds between stacked packages " " " Semiconductor mufti-package modules including stacked-die packages and having wire bond interconnect between stacked packages"; each of which is incorporated herein by reference. TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor packages. [Prior Art] Portable electronic products, such as mobile phones, mobile computing devices, and a variety of consumer products, require high semiconductor function and performance, minimum thickness and weight in a limited trajectory, and have the lowest cost. This will drive the industry to increase integration on individual semiconductor wafers. Recently, the industry has begun to implement the whole = on the "z-axis", that is, by stacking the wafers ϋ has been used in a package of four (four) five wafers. This provides a dense wafer structure with a trajectory of a single chip package ranging from 5x5 mm to 40 χ 40 mm, and its thickness has been: continued by 2. 3 _ lower to 〇. 5 mm. - The cost of stacked die packages is only incrementally higher than the cost of a single-die package, and the yield of the assembly is 155479. Doc 201131731 'The final cost of force compared to packaging the die in individual packages. The number of wafers that can be stacked in a stacked die package is limited to the low final test yield of the stacked die package. =, (d) Some of the grains in the package have certain disadvantages, so the final yield will be the product of individual die test yields, each of which is _. This is particularly problematic - even if there are only two stacks of two dies in the __ package, one of them has low yield due to design complexity or technology. The heat is transferred from one die without a significant heat dissipation path. The limitation is the low power dissipation of the package. Go to another 'except for the ball from the solder ball to the motherboard. Another limitation is the electromagnetic interference between the grains of the stack, especially between the RF and the digital die, since each die does not have electrical shielding. Another way is to integrate the "die" to stack the die packages to form multiple package modules. Stacked packages offer several benefits over stacked die packages. For example, each package with RF dies can be electrically tested and rejected before stacking the packages unless they exhibit satisfactory performance. As a result, the final packaged multi-package module yield can be maximized. More efficient cooling can be provided in a stacked package by inserting a heat sink between the package in the stack and the top of the module. The package stack allows electromagnetic shielding of the RF die and avoids interference with other dies in the module. 155479. Doc • 6 - 201131731 Each s day grain, or more than one die, can be packaged in a different package. The most efficient first-order interconnections and connections for the wafer type and configuration are used. The rest, such as wire contacts or flip chip, maximizes efficiency and minimizes cost. : The z-interconnection between packages in a multi-package module is a key technology in terms of manufacturability, flexibility and cost. The z-interconnects that have been proposed include a perimeter connection and a flexible substrate that is bent over the top of the bottom package. The use of perimeter solder balls in a stacked multi-package module limits the number of connections that can be made and limits design flexibility and results in thicker, higher cost packages. Although, the use of a flexible f-cursor substrate can provide design flexibility, there is no established manufacturing mechanism for the bending process. Furthermore, the use of a flexible curved substrate requires a two-layer metal flexible substrate. It is very expensive. The method of flexing the flexible substrate is limited by the application of low-foot digits. The limitation of the winding circuit in the layer substrate. Please refer to Figures 1-4 for further details of the different z interconnect structures. Figure 1 shows a cross-sectional view of a structure of a standard ball grid array ("BGA") that has been well established in the industry as a bottom package in a stacked multi-package module ("MPM"). As shown in Fig. 1, the bga includes a die 14 attached to a substrate 12 having at least one metal layer. It can use a variety of substrate types including, for example, a plywood having a 2-6 metal layer, or an enlarged substrate having a 4-8 metal layer, or a flexible polyimide having a 丨_2 metal layer, or A ceramic multilayer substrate. The substrate 12, shown by way of example, has two metal layers 121, 123, each of which is patterned to provide a suitable 155479. Doc 201131731 The circuit ' is connected by via 122. The die is conventionally attached to a surface of the substrate using an adhesive, which is basically referred to as a die attach epoxide, as shown in FIG. 1 and 13, and in the configuration of the figure, The surface of the substrate to which the die is attached may be referred to as the "upper" surface, and the metal layer on the surface may be referred to as the "upper" metal layer, although the die attach surface does not need to have any particular use in use. direction. In the BGA of Figure 1, the die tie contacts the wire contact side of the metal layer above the substrate to establish an electrical connection. The die 14 and the wire bonds 16 are coated with a molding compound 丨7 which provides protection against ambient and mechanical stresses to facilitate handling and provides a surface for identification. Solder balls 18 are reflowed onto the contact pads on the underlying metal layer of the substrate to provide a host board (not shown) interconnected to a final product, such as a computer. The masks 125, 127 are patterned onto the metal layers 121, 123 to expose the underlying metal at the contacts for electrical connection, such as at the line contacts and the contact pads to engage the wires Point 16 and solder ball Η. Figure 2 shows a cross-sectional view of a 24#Mp]v^ exemplary structure, designated 2〇' where the 2 interconnects between the packages in the stack are made of solder. In this MPM, a first package (which may be referred to as a "bottom" block is similar to a standard BGA' as shown in Figure 1 (and a similar reference number is used to refer to the bottom of Figure 2). a feature of the package. A second package (which may be referred to as the top package) is stacked on the bottom package, which is similar in structure to the bottom package, and the solder ball system in the top package It is disposed at the periphery of the top package substrate, so it will affect the z-interconnect without interfering with the cladding of the bottom BGA. In particular, the top seal 155479 in Figure 2. The doc 201131731 package includes a die 24 attached to a substrate 22 having at least a metal layer. The appropriate package is provided by, for example, the top package substrate 22 shown in FIG. 2 having two metal layers 221, each patterned, and connected by vias 222. The die is conventionally adhered to a surface of the substrate ("above the surface of the sea"), which is basically referred to as the die attach epoxide' as shown in Fig. 2-23. In the top package of the MPM of Figure 2, as in the bottom package, the die tie contacts establish electrical connections to the line contacts on the metal layer above the substrate. The top package die 24 and wire contacts 26 are covered by a top package molding compound 27. Solder balls 28 are reflowed over the contact pads on the peripheral voids of the underlying metal layers of the top package substrate to provide z interconnects to the bottom package. The solder masks 225, 227 are patterned over the metal layers 221, 223 to expose the underlying metal at the contacts for electrical connection, such as at the line contacts and the contact pads to engage the wires. Point % and solder ball 28 ° The MP interconnection of Figure 2 can be reflowed by solder balls 28 attached to the peripheral contact pad on the metal layer under the top package substrate to the metal layer Ji above the bottom bga The surrounding contacts are 塾±. In this configuration, (4) the distance h between the top and bottom packages must be at least as large as the cladding height of the bottom package, which can be 0. 3 mm or higher, and substantially less at 〇 5 mm 1. Between 5 mm range. The solder balls 28 must therefore have a sufficiently large diameter when reflowed, and have good contact with the contact pads of the bottom BGA; that is, the solder balls 28 must have a larger diameter than the cladding. height. A larger ball diameter specifies a larger ball spacing, which limits Cocoon I55479. Doc 201131731 The number of balls placed in this free space. In addition, the perimeter of the solder balls is configured such that the bottom BGA is significantly larger than the mold cover of a standard BGA. In a small BGA, it is commonly referred to as a wafer level package ("CSP"), which is substantially larger than the die. 7 mm. In a standard BGA, the body size is about 2 mm larger than the mold cover. In this configuration, the top package substrate must have at least two metal layers to facilitate the electrical connection. Figure 3 is a cross-sectional view showing an exemplary structure of a known 2_stacked flip chip mpm, which is generally indicated at 30. In this configuration, the bottom BGA flip chip package includes a substrate 32 having a patterned metal layer 31 on which the die 34 is connected by the flip chip bumps 36, such as solder bumps. A block, a gold button bump, or an anisotropic conductive film or paste. The flip chip bumps are attached to an array of patterned bump pads on the active surface of the die and because the active surface of the die faces the patterned metal layer of the substrate facing down This configuration can be referred to as a "down" flip chip package. Filling the polymer side between the die and the substrate 3 provides protection for the surrounding and adds mechanical integration to the structure. The flip chip package, wherein the substrate has a metal layer only on the upper surface, which is connected to the lower layer circuit (for example, a motherboard by solder balls 38 connected to the metal layer through the solder vias 35) It is not shown in the figure). The top BGA in this configuration is similar to the bottom Bga except that the top BGA has a z-connected solder ball 338 connected to a metal layer j only around the top substrate (via solder in the top substrate) Through hole 335). Solder balls 338 are reflowed onto metal layer 331 of the bottom substrate to provide the 2 interconnects. In particular, in this configuration, the top BGA includes a substrate 332, I55479. Doc -10· 201131731 It has the patterned metal layer 331 on which the top BGA die 334 is connected by flip chip bumps 336. A polymer side is filled 333 between the top BGA die and the substrate. The structure of Figure 3 is more suitable for high-power performance, but the configuration of the type & shown in Figure 2 has a limit of _. It has been improved over the configuration of Figure 2. Where the bottom BGA is not molded, a smaller diameter (h) solder ball is allowed to be attached between the packages around the top BGA. Fig. 4 is a cross-sectional view showing an exemplary structure of a known 2-fold curved flexible substrate MpM, as shown at 40. The bottom package in the configuration of Figure 4 has a 2-metal layer flexible substrate upon which the die is bonded through a post to the first metal layer of the substrate. The second metal layer of the bottom package substrate carries the solder balls for connection to the underlying circuitry, such as a motherboard (not shown). The substrate is sufficiently large to be bent over the top of the package, thereby being brought up into the electrical interconnect, wherein they can be connected to the top package by an array of solder balls on the top package (as described below) example). The space around the die and the space between the die and the bent substrate is covered to provide protection and strength. Referring to FIG. 4, the 2-metal layer bottom package substrate 42 includes a first metal layer 141 and a second metal layer 143, each of which is patterned to provide a suitable circuit '# connected by vias 142. A portion of the first metal layer over a portion of the bottom portion: (eg, using a perforated array) to present an array of cantilevers or sheets 46 configured to correspond to the crystal at the bottom An array of interconnect pads on the active surface of the particles 44. In this portion of the substrate, it may be referred to as the "die attach portion", the first metal layer ΐ 4ι 155479. Doc 11 201131731 Department up. The die is aligned on the die attach portion of the substrate with the active surface down' and the cantilever beam and corresponding interconnect pads are bonded, typically for example by a combination of pressure, heat and The thermal sonic process of ultrasonic energy 'to complete the electrical connection. The die 44 is attached to the die attaching portion of the flexible substrate 42 using an adhesive 43. The first metal layer 143 of the bottom package substrate 42 is directed downward into the die attach portion of the substrate. The solder balls 48 are reflowed into the contacts 位 on the array of the second metal layer 143 facing the lower portion to provide interconnection of the MPM to the underlying circuit (a solder mask 147 is not shown to be patterned to the first a contact pad on the second metal layer 143 for exposing the underlying metal as an electrical connection, comprising a contact pad connected to the underlying circuit by solder balls 48, and a soldering ball connected to the top package a contact pad, as described below. Another portion of the bottom package substrate 42 extends adjacent to the die attach portion and is bent upwardly and positioned over the bottom package die 44 to be flexible The substrate 42 is bent over the upper portion, and the first metal layer 143 faces upward. In the configuration of Figure 4, the top package is generally similar to the BGA of Figure i, wherein the die is connected Pointing in place at the line contact above the metal layer above the substrate to establish an electrical connection. In particular, the top package die 14 is attached to the substrate 12 having two metal layers 121, 123 (in this example Medium) 'each of which is patterned to provide appropriate circuitry and connected by vias 122. The die is coated with an adhesive 13 attached to the upper surface of the top 4 package substrate, typically a die attach epoxide. The die 14 and the wire contacts 16 utilize a molding compound 17 Covered to provide protection against ambient and mechanical stress for handling operations, and 155479. Doc -12- 201131731 Provides a surface for marking for identification. Solder balls i 8 are soldered back to the contacts 143 on the upper facing metal layer of the bottom package substrate to interconnect the Z between the top and bottom packages. An advantage of the structure of FIG. 4 is that the substrate folded over can provide a fill area over the upper surface of the bottom package substrate on which the ridge is folded to accommodate a complete array of solder balls in the top package, And accommodate more complex interconnects between the two packages. It also provides a small package trajectory. The main disadvantage of this configuration is that the cost of the substrate is high and that bending techniques and equipment are not available. A common feature of all of these stacked package configurations is that they can protect each package and provide production at a higher final test yield. SUMMARY OF THE INVENTION The present invention is directed to a multi-package module having a stacked package. In accordance with the present invention, the connections between the stacked packages in the MPM are based on line contacts. In general, the present invention features a configuration with a plurality of different stacked packages and a method of stacking and interconnecting different packages by means of 2 interconnects based on wire contacts. In a multi-package module in accordance with the present invention, the package stack can include a variety of BGA packages and/or any type of platform flip LLGA package: the package stack can include wire bonds and/or flip chip packages. The package stack can include a thermal enhancement feature generated on or in the stack; the package stack can include - or a plurality of wire contacts to the BGA or LGA: a flip chip die at the bottom or bottom Package; the package stack may include more than one die- or multiple BGA and/or LGA packages in the stacked package or side-by-side encapsulation; the stack may include - or more than 155479. D〇i 13 201131731 Electromagnetic shielding of the package; and the stack may comprise any substrate, plywood or assembly or ceramic, which provides for the formation of z interconnects by being bonded around the packages. In a general aspect, the invention features a stacked underlying and upper packaged epoch packaging module, each of which includes a ruthenium attached to a substrate, wherein the upper and lower substrates are connected by wires Point to interconnect. The invention can provide excellent manufacturability, high design flexibility, and low cost to manufacture a stacked package module with a low wheel temple and a small track. The wire contact interconnection technology has been well established in the industry. It is the lowest cost interconnect technology and can be used directly, without the need for significant modifications, to be used in the multi-package module of the present invention. It provides design flexibility for the relative dimensions of the BGA to which it can be bridged by the length of the wire. With the available technology and equipment, the wire in the wire contact can be as short as 0 5 or as long as 5 mm. The configuration of the Z interconnect pads can be implemented by either BGA and LGA substrate design or one of them. In addition, with the wire contacts according to the present invention, the germanium interconnects can be formed between pads that are not precisely aligned with each other, by means of so-called out-of-order bonding, which is currently used In this industry, the line-to-point spacing is the finest in the industry, at 50 microns, and is expected to reach 25 microns. This can result in a large number of interconnects. Both manufacturability and design flexibility can contribute to the river. 1>1^ Low cost. The minimum trajectory of a typical BGA or LGA is 丨7 mm larger than the grain size. Adding the z-interconnect point pad according to the present invention will increase Β〇α minimum os mm. A typical BGA The thickness is 1. 〇 mm, and lga thickness is 0. The typical adhesion thickness of 8 mm is in the range of 0. 025 mm to 0. Between 100 mm. 155479. Doc • 14· 201131731 The trajectory and thickness of the stacked package MPM according to the present invention can fall within an acceptable range for most applications. In some embodiments, the multiple package module includes three or more packages that are sequentially fixed to form a stack. In another aspect, the present invention features a first ("bottom"): second ("top") package of multiple package modules, each package including a die attached to a substrate, and by A wire contact is connected to the substrate, wherein the top package substrate and the bottom package base (4) are interconnected by wire contacts. In some specific implementations, each package is completely covered with a molding material 'in other embodiments, at least one package is only coated to a certain extent' to protect the crystal during subsequent processing and testing. A line junction between the grain and the substrate. In some embodiments, the second package is a core package and in some such embodiments, the lga package substrate is a single metal layer substrate. In another aspect, the invention features a multi-package module having a first ("bottom") and a second ("top") package stacked, the bottom package being a two-GA package 'each package including being attached to a die of a substrate, wherein the top package substrate and the BGA package substrate are interconnected by wire contacts. In another aspect, the invention features a multi-package module of a stacked package in which at least one of the packages has an electrical shield. In some such configurations, the electrical shield can additionally be configured as a heat sink. In some embodiments, the packages having an electrical shield include __rf dies, and the occlusion is used to limit electromagnetic interference between the RF dies and other dies in the multiple package module. In some embodiments, the bottom package is 155479. Doc -15· 201131731 has - electric shielding. In another aspect, the _ & and the second ("top ar, characterized by a stacked first ("bottom"), negative port p") package in the guest-on-die configuration The bottom package is packaged in the top substrate and the bottom package BGA package. In the embodiment, the top cover is interconnected. In some embodiments, the stack:;, - stacked die package; in a specific spacer to separate. On the 1st of the next day. The adjacent stacked dies in the stand can be interposed between the wafers, and the inverted package substrate on the bottom package includes - embedded in some embodiments, the bottom is used for heat dissipation and - Electric shielding. #也千面系叹为成在其他-'the invention is the second and the second ("top only has the (bottom)" τ曰 in multiple package modules; the bottom package is in the = configuration - flip chip - flipping one: for; top of the top. p substrate and the bottom ... in the body embodiment, at the bottom = to interconnect. In some masked 卩 package on the flip chip die has In one aspect, the present invention is characterized in that a plurality of (top) packaged multi-packages (the bottom #) and the first board of the "Lee* Yishan (four) package comprise a 曰 particles attached to the substrate, and The bottom package substrate is connected by at least one of the wire contact and the top package, and the top package and the bottom are worn by the bottom package. 0 褒 white for - stacked die seal 155479. Doc •16·201131731 In another general aspect, the method of grouping includes at least a first (bottom) package on a first (bottom) package substrate of a multi-package die. The top-of-the-box package includes a first and a second (top and bottom) substrate on a first (on-package) and a second (-eight-first) package substrate Between the formation of line contacts 2, clean feet = cellar '5 hai and other packages can be tested before the group crack, which can discard the not six warehouses:: • or reliability of the package, so it is better to test The first package and the first package are used in the assembled module. In terms of aspect, the invention features a method of fabricating a multi-package module, including a lga package stacked on a BGA package. Wherein the top port P and the bottom package are interconnected by wire contacts. According to this aspect, a BGA package is provided which is typically an undivided strip of a molded bga package; preferably in the scarf BGA package for performance and reliability testing' and identify A "good" The seal is then subjected to subsequent processing; the adhesive is attached to the upper surface of the molded & BGA package; an analog molded platform grid array package is provided; preferably, the LGA package is tested '" and identified as "good"; these "good" LGA packages are the adhesive placed over the molding on the BGA package and cure the adhesive, as needed and preferably, A plasma cleaning operation is performed after forming a line contact z interconnection between the top portion 1ga of the stack and the bottom BGA package; an additional plasma cleaning may be performed as needed, and preferably, to form the MPM mold. Further steps include attaching a second layer of interconnected solder balls to the underside of the module; testing and separating the completed module from the strip, for example by sawing or by punching; and for other uses Come to 155479. Doc 17 201131731 Packaging. In some embodiments, the LGA (top) package is fully molded 'having a generally planar upper surface of the LGA package; in other embodiments, the line contacts, but not the LGA The entire upper die surface of the package is molded, and the LGA is molded by dispensing the molding compound only around the die and near the gap of the s-shaped LGA package substrate. In another aspect, the invention features a method of stacking a multi-package module on a LGA package stacked on a BGA package, wherein the top and bottom packages are interconnected by wire contacts, and wherein The bottom package has an electromagnetic shield. In accordance with this aspect, a ball grid array package is provided, which is typically a strip of undivided strips of a BGA package; the BGA packages have a shield that is secured over the die; preferably in the strip The Β〇α package is tested for performance and reliability and identified as “good” for subsequent processing; the adhesive is dispensed over the upper surface of the mask on the “good” BGA package; a separate mold is provided a platform grid array package; preferably, the LGA package is tested and identified as "good"; the "good" LGA package is placed on the dispensing agent over the mask and the adhesive is cured "in accordance with It is desirable and preferred that after the interconnection of the top contact 1ga of the stack and the portion of the BGA package is formed, the electrical connection cleaning operation is performed; if necessary, and preferably, an external power can be performed. (d) washing, followed by forming the stamping. The step of stepping includes attaching a second layer of interconnecting solder balls to the underside of the module; testing and separating the completed module from the strip, for example by sawing Segmentation or separation by punching.  The knife is separated and packaged for other uses. 155479. Doc -18- 201131731 In some concrete implementations (4), the method includes the steps of providing the multi-module and a heat sink. In this aspect of the invention, the process of performing 'has additional steps to insert--"falls into" the molding operation to install the supported radiator command, or inserts a "drop-in" molding operation to the installation: a planar heat sink; or by applying an adhesive to the upper surface of the top package molding, or to the upper surface of a spacer on the top package, and fixing the planar heat sink to the adhesive. In another aspect, the invention features a method of fabricating a set comprising a top seal placed on the bottom of the lower die (four) wafers, and the top and bottom packages are connected by wires in the outer pull. According to this aspect, it is provided that the bottom of the die-flip wafer BGA is sealed by two 2" moldings, which are usually attached to the lower die wafer wafer grid array, and (4) the ground is in the long strip. The package that is identified as "good" by the BGA package is accepted as a "good" package: (4) is assigned to the top of the die on a "good" BGA package): on top to provide a separate top (eg platform The grid array armor, 11 is molded as needed; preferably, and identified as the adhesive of the package test η, and the adhesive is cured; as needed and preferably the point r interconnect = stack A wire connection is formed between the top lga and the bottom bga package, which can be performed immediately - electropolymer cleaning operation; as needed and preferably ": 'Next to form the system. ??? Test and separation =:: ::Welding: Under the module (4) Chess Hing, long strips, for example by sawing split or 155479 . Doc •19· 201131731 is separated by punching; and is packaged for other uses. In another aspect, the invention features a multi-package mold including a top-mounted stacked-sub-die flip chip BGA bottom package, wherein the top and bottom packages are lined The contacts are interconnected, and wherein the bottom package has an electrical shield. In accordance with this aspect, similar to the aforementioned processing of the unmasked bottom flip chip bottom package, it has an additional step of inserting the shield to the bottom package flip chip die. Provide a die-wafer BGA bottom package, optionally molded, in a lower die-flip wafer flip-flop array bottom package; preferably in a package for performance and reliability testing in the strip The package identified as "good" is subjected to subsequent processing; the adhesive is dispensed over the upper surface (back side) of the die on a "good" package; a separate top is provided (eg, a platform grid array) a package, which can be molded as needed; preferably 'tested for the LGA package and identified as 'good'; the #"good" pass package is placed on the adhesive over the mask' and cured The adhesive; as needed and preferably, after the wire-to-I interconnection is formed between the top LGA of the stack and the bottom BGA package, a plasma cleaning operation is performed; as desired, an additional The plasma is cleaned and then molded to form the MPM. The step of stepping includes attaching a second layer of interconnected solder balls to the underside of the module, testing and separating the completed module from the strip, for example by splitting or separating by punching; Other uses for packaging. At m, the invention features a method comprising a top package stacked on top of an upper wafer flip chip BGA package, wherein 155479. Doc •20-201131731 For the first package, some of the specific implementations can be a stack of edge top and bottom packages electrically interconnected by wire contacts. In accordance with this aspect, an upper die-flip wafer ball grid array package is provided, which is typically unmolded and is typically an undivided strip of an upper die-flip wafer ball grid array package; preferably The BGA package in the strip performs a tree of performance and reliability. The package identified as "good" accepts subsequent processing; the adhesive is dispensed onto the top surface of the substrate on a "good" BGA package. . 严兄》v die, ..., as needed and usually molded; preferably, the lga package is tested and identified as "good"; the "good" LGA packages are placed on top of the substrate Adhesive, and curing the adhesive; if desired, it is preferred to form a wire joint Z interconnected between the top lga of the stack and the bottom BGA package.  Thereafter, a plasma cleaning operation is performed; it is preferably carried out as needed - additional plasma cleaning, followed by formation of the MPM molding. The step of progressing includes attaching a second layer of interconnected solder balls to the underside of the module; a J-shaped knives separate from the module and the strip, for example by sawing apart or by punching; Other uses for packaging. In another aspect, the invention features a method of fabricating a multi-package module that includes a top package stacked on top of a stacked bottom package, wherein the top and bottom packages are interconnected by wire contacts . In accordance with this aspect, a stacked die BGA package is provided that is typically molded and is typically provided as an undivided strip of a stacked die ball grid array package; preferably in the strip The package that is identified as "good" by the performance and reliability test of the package is subjected to subsequent processing; the adhesive is dispensed onto the upper surface of the "good" stacked die BGA package; 155479. Doc -21 · 201131731 is usually on the often planar upper surface of the package; a separate second package is provided, usually molded, which can be used as a stacked die package, preferably Is to test the first: package, and _ "good" j "good" second package is placed on the sticky moon above the upper surface of the BGA and cure the adhesive; it is preferably as needed An electric cleaning operation is performed after the wire contact z interconnection is formed between the top and bottom packages of the stack; it is preferably (four) preferably performed - additional electric cleaning, and then the MPM molding is formed. The step of stepping includes attaching a second layer of interconnected solder balls to the underside of the module; testing and separating the completed module from the strip 'eg by _ splitting or by punching; and for Package. + In some embodiments of the method, two or more first-molded packages are provided in the un-separated strip, and two or more die-type (four) assemblies are performed on the strip. And separating the two or more modules after the assembly is completed. In the method of fabricating a multi-package module in accordance with the present invention, the electrical connections between the stacked packages use wire contacts for f to interconnect the package substrates L above and below the stack. Special benefits include the use of established manufacturing architectures, low production costs, design flexibility and thin package products. The z interconnect contact can be implemented in a variety of package and module configurations by pulling a wire from a bump formed by a conductive pad of the first package substrate i to the first package substrate a conductive pad on the conductive pad; or a bump formed on a conductive pad on the first package substrate to pull the wire to a conductive bump on the first package substrate. 155479. Doc • 22· 201131731 The present invention provides more than one semiconductor package in a thin and minimal track package at the lowest cost and highest final test yield. Moreover, some of the stacked configurations in accordance with the present invention allow for high thermal performance, high electrical performance, or electrical isolation of a digital component from a component. Other stacked configurations can be used (for very thin structures for handheld or sleek products. All methods of assembly are allowed to allow individual testing of the stacked packages to maximize the final quality of the module. The additional process steps will be used to complete the multi-sealing module according to the present invention. Preferably, the solder balls for the connection of the lowermost package in the stack are not attached to the motherboard. Rather, until the final step before the separation of the MpM. And 'for example, the electricity cleaning can be done at any point in the process, for example, after the adhesive is cured, and before the coating, and like the interconnection in 2 Preferably, the individual packages are provided as strips of several packages, connected in a row for easy processing during manufacturing, and the multi-package module is in the process step Then, in the method according to the present invention, the package stacks can be formed on a strip of a non-single-first package of a selected type by a fixedly separated second package, and are completed. After the process of the modules, the interconnects of the line contacts are formed, and then the modules are separated. The MPM according to the present invention can be used to construct computers, telecommunication equipment, and consumer and industrial electronic devices. [Embodiment] The present invention will now be described in further detail with reference to the drawings, which are referred to as 155479. Doc • 23-201131731 Other embodiments of the invention are apparent. The drawings are merely illustrative and illustrate the relationship between the features of the present invention and other features and structures, and are not drawn to scale. In order to improve the clarity of the presentation, in the drawings illustrating the specific embodiments of the present invention, the elements corresponding to the elements shown in the other drawings are not specifically renumbered, although they are clear in all drawings. Identification. Referring now to FIG. 5A, there is shown a cross-sectional view at 5 具体 of a specific embodiment of a multi-package module according to one aspect of the present invention, including stacked (bottom) and second ("top" Package) wherein the stacked packages are interconnected by wire contacts. In the embodiment shown in Figure 5A, the bottom package 400 is a conventional BGA package, such as shown in Figure 1. Thus, in this embodiment, the bottom package 4A includes a die 414 attached to a bottom package substrate 412 having at least one metal layer. It can use any of a variety of substrate types, including, for example, a plywood having a 2-6 metal layer, or a structured substrate having a 4-8 metal layer, or a flexible polyimide tape having a 2 metal layer, or A ceramic multiple layer substrate. The bottom package substrate 412 shown by the example of Fig. 5 has two metal layers 421, 423' each patterned to provide appropriate circuitry and connected through vias 422. The die is conventionally attached to a surface of the substrate using an adhesive 'substantially referred to as a die attach epoxide, as shown at 413 in Figure 5a' and in Figure VIII. In the configuration, the surface of the substrate to which the die is attached may be referred to as an "upper" surface and the metal layer on the surface may be referred to as an "upper" metal layer, although the die attach surface is not required for use. Have any specific directionality. 155479. Doc •24- 201131731

Grain line contact to the substrate

Brain and so on. The solder masks 415, 427 are patterned onto the metal layer 421, circuitry, such as electricity 1, 423, to expose the underlying metal at the contacts for electrical connections, such as at the line contacts, and for bonding the lines Contact pad 416 and solder ball 41 8 contact pads. In the embodiment shown in FIG. 5A, the top package 5A is a platform grid array (LGA) package, which can be similar to a BGA package, such as shown in the figure, but without solder balls mounted to The contact pad on the lower surface of the substrate. Particularly in this example, the top package 5A includes a die 5 14 attached to a top package substrate 51 having at least one metal layer. It can use any of a variety of substrate types; the top package substrate 5 12 shown by the example of FIG. 5A has two metal layers 521, 523, each of which is patterned to provide appropriate circuitry and pass through The holes 522 are connected. The die is conventionally attached to a surface of the substrate using an adhesive, substantially referred to as a die attach epoxide, as shown at 5 13 in Figure 5A, and in Figure 5A. In the configuration, the surface of the substrate to which the die is attached may be referred to as an "upper" surface and the metal layer on the surface may be referred to as a "top" metal layer, although the die attach surface is not in use. Need to have any specific directionality. 155479.doc -25- 201131731 In the top Lga package of the embodiment of Figure 5A, the die tie contacts to the line contacts of the metal layer above the substrate to establish an electrical connection. The die 516 and the wire bond 516 are coated with a molding compound 517, which provides protection against ambient and mechanical stress for processing operations and has a top package upper surface 5 19. The top package 500 is stacked on top of the bottom package 400 and is attached using an adhesive 503. Solder caps 515, 527 are patterned over the metal layers 521, 523 to expose the underlying metal at the contacts for electrical connection, such as at the wire contacts to engage the wire contacts 5 1 6. The z-interconnect between the top package 500 and the bottom package 400 of the stack is made by wire contacts 518 that connect the top metal layers of the individual package substrates. On the one hand, each of the wire contacts 518 is electrically connected to the upper surface of the pad on the gold layer 521 above the top package substrate 512. On the other hand, each wire contact is connected to the bottom package substrate 412. The upper surface of the crucible on the upper metal layer 42 1 . The wire contacts can be formed by any of the wire contact techniques known in the art, for example, as described in U.S. Patent No. 5,226,582, the disclosure of which is incorporated herein by reference. The package-to-package z interconnect line is illustrated by the example in FIG. 5A by forming a bump or bump on the upper surface of a pad on the upper metal layer of the top substrate, and then The pull-down wire is oriented and fused to a pad of the metal layer above the bottom substrate. As described below, the wire contact can be completed in the reverse direction, that is, by forming a bump or bump on the surface of a pad of the metal layer above the base substrate, and then pulling the wire toward the wire And fused to a pad on the metal layer above the top substrate. The selection of the wire contact strategy for the package z interconnect will be determined as follows 155479.doc -26- 201131731 depending on the geometric configuration of the gaps of the stacked substrates and the bonding surface thereon. In the stacked package embodiment of FIG. 5A, the z interconnect pads on the individual package substrates are disposed on the upper metal layer near the gap of the package substrate, and the position and order of the z interconnects are generally configured. The Z interconnect pads on the top package substrate substantially cover the corresponding 2 interconnect pads on the bottom package when stacking the packages. Conventionally, the top package 500 has a smaller substrate track than the bottom package 400 to allow voids in the wire contacts from shorting to the edges of the metal layer of the substrate. Once the z-connector contacts have been formed, a module package is formed to cover and protect the Z-connector contacts and provide mechanical integration of the completed modules. . The arrangement of the Z interconnect pads on the top and bottom package substrates is shown by the example of the plan views in Figures 5B and 5C, which are at 5 〇〇 and 4 分别, respectively. Referring to FIG. 5B, the top package 2 interconnect pads 524 are formed by patterning regions of the upper metal layer at the voids 501 on the upper surface 525 of the top package substrate 51. The void 〇1 extends beyond the edge 526 of the top package cladding material and has an upper surface 519. Referring now to FIG. 5C, the bottom package z interconnect pads 424 are formed by patterning regions of the upper metal layer at the voids 401 on the top surface 425 of the top package substrate 412. The void 401 extends beyond the track 5' of the stack and overlies the top package substrate 512' and further beyond the edge 426 of the bottom package cladding material, having an upper surface 419. As shown in Figures 5A, 5B and 5C, the Z interconnect between the top and bottom seals 155479.doc • 27-201131731 in accordance with the present invention is interconnected by a top package interconnect in the top of the top package substrate. The 塾524 is formed by a line contact between the bottom package interconnect 424 (the upper contact or the lower contact) of the (4) 4〇1 of the bottom package substrate. The multi-package module structure is protected by forming a module cover 5〇7, and the solder ball W8 is soldered to the solder ball bump exposed on the metal layer under the bottom package substrate to be connected to the lower layer circuit. , for example, a motherboard (not shown). As previously mentioned, the structure according to the present invention allows the BGA and LGA to be pre-tested prior to assembly into the multi-package module to allow for the exclusion of non-compliant packages prior to assembly, thereby ensuring a high final module test. rate. In order to improve the heat dissipation from the multiple package module, a heat sink can be provided on the top package. The top heat sink is formed of a heat conductive material. At least S has more of its upper surface. The area is used to expose the upper surface of the MPM to the surrounding environment for more efficient heat exchange. For example, the top heat sink can be a sheet of metal (e.g., a copper sheet) that can be secured to the PCT bag during the curing process of the molding material. Alternatively, the heat sink may have a -it portion that is generally planar on the top package and a peripherally-selected portion, or a spacer member placed on or near the upper surface of the bottom package substrate . By way of example, Figure 5E shows a cross-sectional view of a stacked BGA + LGA MPM 54 in accordance with another aspect of the present invention, wherein a "top" cooling stomach is provided at the upper surface of the MpM. The structure of the package stacked in the MPM 54 is generally similar to the MPM 5 in Figure 5A, and similar structures can be identified by similar reference numbers in the figures. The top heat sink in this example is formed from a thermally conductive material having a central portion 544, typically 155479.doc -28 - 201131731 plane, over the top package, and extending to the bottom package structure 4i2 A support member 546 is supported around the upper surface. The upper surface of the planar portion 544 is attached to the upper surface of the MPM to be exposed to the surroundings to efficiently serve the tropics. For example, the top heat sink can be formed by a sheet of metal, such as copper, for example by stamping. The support members 546 can be secured to the upper surface of the bottom package substrate (not shown) using an adhesive as needed. The multi-package module structure can be protected by forming a module cover 5〇7, and the heat sink support member is embedded in the MpM cladding during the molding material curing process. In the embodiment of Figure 5E, a stepped recessed feature 545 is provided around the planar upper portion 544 of the heat sink to allow for better mechanical integration of the structure, rather than with the mold. Separation of the compound: In the specific embodiment, the space between the lower surface of the heat sink 544 and the surface of the L (the upper surface 5 19 of the JA molding 5 17 is filled with the MpM molded thin layer. A top heat sink can be attached to the LGA molded upper surface as shown in the cross-sectional view of Figure 5D. The structure of the stacked package in the MPM 52 is generally similar to the MPM 5 in Figure 5A, and similar. The structure can be identified on the drawing by similar reference numerals. The top heat sink 504 in the example of Figure 5D is a generally planar sheet of thermally conductive material having at least a more central region of its upper surface exposed Go to the surrounding environment to more efficiently discharge the tropical MPM, as shown in the example in Figure 5E. For example, the top heat sink can be a metal plate (such as copper). However, here the top heat sink 5〇4 An adhesive 506 is used to secure the upper package cover 517 Upper surface 519. The adhesive 506 can be a thermally conductive adhesive to provide improved heat dissipation. Typically, after the top package molding has been at least partially cured, the 155479.doc -29-201131731 top heat sink is fixed to The top package is molded, but before the molding material is ejected to the enamel cladding 5G 7. The periphery of the top heat sink may be coated with the MPM molding material. In the specific embodiment of FIG. The periphery of the heat sink 504 is provided with a stepped recessed feature 5〇5 to allow for a better mechanical integration of the structure 'without being separated from the molding compound. In another alternative' In the case of a simple planar heat sink, it does not have a branch member that does not adhere to the upper surface of the top package molding. In these embodiments, as in Figure 5 In a specific embodiment, the top heat sink can be a generally planar sheet of thermally conductive material, such as, for example, a sheet of metal (eg, copper), and at least a more central region of the upper surface of the planar heat sink is exposed to the surroundings. more efficient The tropic is separated from the MPM. Here, the space between the lower surface of the simple planar heat sink and the upper surface 5 19 of the LG molding 5 17 is filled with a thin layer of MpM molding, and this simple The planar heat sink can be secured to the MPM cover 507 during the molding material curing process. The unattached, simple planar top heat sink can be wrapped around the MPM molding material as in Figure 5D. An attached planar heat sink can be provided with a stepped recessed feature 505 on the periphery to allow for better mechanical integration with the structure and less separation from the molding compound. Figure 5D, 5E The illustrated MPM with a heat sink provides improved thermal performance. Referring now to FIG. 6A, there is shown a cross-sectional view of a stacked package multi-package module in accordance with an aspect of the present invention having a 155479.doc • 30·201131731 -lga top package on a BGA bottom package. The package LGA is partially coated. That is, the molding material of the top LGA package is applied to a limited area&apos; and is of a limited amount&apos; which is sufficient to protect the line contacts during (d) processing, particularly during subsequent (d) testing. In terms of it, the configuration of Fig. 6 is substantially shown in Fig. 5A. Therefore, in this particular embodiment, . The structure of the bottom package 400 is as described in Fig. 5A, and the structure of the top package 6 (8) is substantially as shown in Fig. 5A except for the difference in the upper package cladding: In particular, the top package 600 includes a die 614 attached to a top package substrate 612 having at least one metal layer. It can use any of a variety of substrate types; the top package substrate 512 shown by the example of FIG. 6A has two metal layers 621, 623, each patterned to provide a suitable circuit and through the via 622 connection. The die is conventionally attached to a surface of the substrate using an adhesive, substantially referred to as a die attach epoxide, as shown at 613 in Figure 6A, and in the group of Figure 6-8. In the state, the surface of the substrate to which the die is attached may be referred to as a "top" surface, and the metal layer on the surface may be referred to as an "upper" or "top" metal layer, although the die attach surface is in use. There is no need to have any specific directionality. In the top LGA package of the embodiment of Figure 6A, the die tie contacts to the line contacts of the metal layer above the substrate to establish an electrical connection. The crystal 614 and the wire contact 616 are coated with a molding compound 617 which provides protection against ambient and mechanical stresses for handling operations. The formation of the cladding 617 in this embodiment is only used to cover the wire contacts and their individual connections to the top package substrate and the top package die, so the 155479.doc • 31 · 201131731 Most of the upper surface of the pellet 614 is not covered by the coating. The top package 600 is stacked on top of the bottom package 4 and is secured there using an adhesive. Solder caps 615, 627 are patterned over the metal layers 621, 623 to expose the underlying metal at the contacts for electrical connection, such as at the wire contacts to engage the wire bonds 61 6 . The z-interconnection between the top package 600 and the bottom package 4A of the stack is made by connecting the line contacts 618 of the top metal layer of the individual package substrates. The set is covered with 6〇7 for protection, and the solder balls 418 are reflowed to the solder ball pads exposed on the metal layer under the bottom package substrate to be connected to the underlying circuit, such as a motherboard (not shown) . The benefit of this configuration is to reduce costs. The partial coating is implemented in accordance with the line contact processing (e.g., by dispensing through a fine nozzle, as with a syringe from a needle) and thus provides a higher flow rate and uses fewer packages Cover material. After the partial cladding, the top lga package can be tested without the need for rearrangement (four) processing to avoid damage to the top package line junction. The factory has improved the multiple packages shown in the example in Figure 6Α. Bulk production of the module: a heat sink can be provided on top of the top package. The top heat sink (10) is formed of a thermally conductive material having a more central (4) exposed upper surface to the surrounding environment to more efficiently remove the heat. For example, the top heat sink can be a metal plate (e.g., copper) that can be applied to the Mm cladding during the molding material curing process. The heat sink may have _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Branch building components. By Fig. 6B is a perspective view of a stacked BGA + LGA MPM 62 in accordance with another aspect of the present invention, wherein a "top" heat sink is provided at the upper surface of the MPM. The structure of the package stacked in the MPM 62 is generally similar to the MPM 60' in Figure 6A and similar references can be identified in the figures by similar reference numbers. The top heat sink in this example is formed from a thermally conductive material having a generally planar central portion 644 over the top package and surrounding support members extending to the upper surface of the bottom package structure 412 646. The upper surface of the planar portion 646 is attached to the upper surface of the MPM to be exposed to the surroundings to efficiently tropic. For example, the top heat sink can be formed by a sheet of metal, such as copper, for example by stamping. The support members 646 can be secured to the upper surface of the bottom package substrate (not shown) using an adhesive as needed. The multi-package module structure can be protected by forming a module cover 6〇7, and the heat sink support member is embedded in the ΜρΜ cladding 607 during the molding material curing process. In the particular embodiment of the print, a stepped recessed feature Μ 5 is provided around the planar upper portion 644 of the heat spreader to allow for better mechanical integration of the structure, rather than with the mold. The compound is isolated. In this embodiment, the space between the lower surface of the heat sink 644 and the upper surface of the die 614 may be filled by a die, which is sufficiently thick that the heat sink 644 does not interfere with the The surrounding LGA is molded 617. Additionally, the MpM in this particular embodiment of Figure 6A can have a simple planar heat sink without support members and is not attached to the top surface of the package 155479.doc -33·201131731. In these embodiments, as in the embodiment of Figure (7), the top heat sink can be a generally planar thermally conductive (four) plate such as a silicon metal sheet (e.g., copper), and at least the planar heat sink. The more central area of the surface is exposed to the surroundings to more efficiently bring the tropics to the MPM. Here, as shown in the specific embodiment of FIG. 6B, the space between the lower surface of the planar heat sink and the upper surface of the die 614 is filled by a layer of MPM molding, which is sufficiently thick so that the heat sink It does not interfere with the surrounding LGA molding 617. While in the particular embodiment of Figure 6B, such a simple planar heat sink can be secured to the MPM cover 607 during the molding material curing process. The unattached simple planar top heat sink may be covered with the MPM molding material, a planar heat sink attached to FIG. 5, and may provide a stepped concave feature on the periphery. To allow for better mechanical integration with the structure and less separation from the molding compound. Another option, as in an embodiment of FIG. 6A, allows attachment of a simple planar heat sink to the top package 60A, the lower surface of the simple planar top heat sink and the upper surface of the die 614 A spacer can be provided between. The spacer may be fixed to the die and the heat sink using an adhesive; or the spacer may be formed as a whole part, and a spacer portion of the heat sink, and in these embodiments In the example, the lower surface of the spacer portion of the heat sink may be fixed to the upper surface of the die by using an adhesive. The spacer is preferably made of a thermally conductive material and the adhesive can be a thermally conductive adhesive&apos; to provide improved heat dissipation. In these embodiments, the top heat sink can be ejected from the package 155479.doc -34 - 201131731 607 after the top package molding has been at least partially cured, but it is coated with the molding material for the Xia PM. material. 22 I / heat ^ ... can be coated with the surrounding of the molder =::: in the embodiment of the mechanical characteristics of the simple TM concave features to allow better structural degrees and less Will be separated from the molding compound. For example, the improved thermal performance of 罝右_私# shown in Figure 6B. The structure of the '', </ RTI> </ RTI> provides a stacked multi-package module according to another aspect of the present invention, which has a top lig package stacked on top of the BGA bottom package. The top LGA package uses a single metal layer substrate. In other respects, the configuration of Fig. 7 is substantially shown in the figure. Therefore, in the specific embodiment, the structure of the bottom package is as shown in FIG. 5A, and the structure of the top package 700 is as shown in FIG. 5A except that the structure of the top package substrate is different. . In particular, the top package 7A includes a die 714 attached to a top package substrate 712 having a metal layer 721 that is patterned to provide suitable circuitry. The die is conventionally attached to the surface of the substrate using an adhesive, which is basically referred to as a die attach epoxide, as shown at 713 in Figure 7, and in the configuration of Figure 7, The surface of the substrate to which the crystal grains are attached may be referred to as an "upper surface". Therefore, the metal layer on the substrate may be referred to as an "upper" or "top" metal layer, although the die attach surface does not need to be used in use. Any special direction. In the top LGA package of the embodiment of Figure 7, the die tie contacts to the line contacts of the metal layer above the substrate to establish an electrical connection. The 兮曰 曰 granule 714 and the line contact 716 are coated with a molding compound 717, which provides 155479.doc -35·201131731 for the surrounding and mechanical stress _ 卞 edge for processing. In the specific embodiment of Fig. 7, the coated 7〇7 wounder system 5 is again placed as in the specific embodiment of Fig. 5A, so the covering 7〇7 frost 筌 7 minutes 曰 κ 'covered The day granules and the wire bonds and their connections, and the cladding has a surface 719 over the entire day granules and interconnects as described below. 'The cladding here may be formed as shown in FIG. 6A. The specific embodiment 'that is to say' is formed by only wrapping (four) equal-line contacts and their individual connections to the top package substrate and the top package die, so that the upper surface of most of the die is not covered by the package. Covered. The top package 700 is stacked on top of the bottom package 400 and secured there using an adhesive as shown at 703. A solder mask 715 is patterned over the metal layer to expose an underlying metal incoming connection at the junction, such as at a line junction for bonding the line contacts 716. The z-interconnect between the top package 700 and the bottom package 4A of the stack is made by wire contacts 718 connecting the top metal layers of the individual package substrates. The multi-package module structure is protected by forming a module package 7〇7, and the solder ball 418 is soldered back to the solder ball pad exposed on the metal layer under the bottom package substrate to be connected to the lower layer circuit. For example, a motherboard (not shown). The benefit of this configuration is that the cost can be reduced compared to the configuration of the substrate using two metal layers in the top LGA package because of the lower cost of the single metal layer substrate. This configuration may additionally provide a lower package profile because the single metal layer substrate is thinner than a substrate having two or more metal layers. FIG. 8A shows a stack of bga according to another aspect of the present invention. +lga 155479.doc -36- 201131731 MPM 80 cross-section, i 裎 /, 裢 — - heat sink and electric shield to the bottom package. The embodiment shown in the example of FIG. 8A has a top grid array ("LGA"), which is stacked on top of a bottom ball grid array BGA package 402, where #丹Τ The top LGA package is typically constructed as the top Lga package in Figure 5. As follows, a LGA' having a single metal layer is as described below with reference to the accompanying drawings, which can also be used as the top LGA in the specific embodiment of Fig. 8a. Referring to S8A, the top lga package _ can be similar to a -BGA package, such as * in the figure, (4) having solder balls mounted on the contact pads on the lower surface of the substrate. In particular, in this example ten, the top P package 800 includes a die 814 attached to a top package substrate 812 having at least a metal layer. It can use any of a variety of substrate types; the top package substrate 812 shown by the example of circle 8A has two metal layers 821 823' each patterned to provide appropriate circuitry and connected through vias 822 . The die is conventionally attached to a surface of the substrate using an adhesive, substantially referred to as a die attach epoxide, as shown at 813 in Figure 8A, and in the group of Figure 8 In the state, the surface of the substrate to which the die is attached may be referred to as an "upper" surface and the metal layer on the surface may be referred to as an "upper" or "top" metal layer, although the die attach surface is in use. There is no need to have any specific directionality. In the top LGA package of the embodiment of Figure 8A, the die tie contacts to the line contacts of the metal layer above the substrate to establish an electrical connection. The crystal grains 814 and the wire bonds 816 are coated with a molding compound 817 which provides protection against ambient and mechanical stresses for handling operations and has a top package upper surface 819. The solder masks 815, 827 are patterned over the 155479.doc • 37-201131731 metal layers 821, 823 to expose the underlying metal at the contacts for electrical connection, such as for bonding the wire contacts 8 1 6 line contact. The bottom BGA package 402 of the embodiment of Figure 8A is a conventional BGA package 'as shown, for example, in Figure 1, except that the bottom BGA package of Figure 8A is not coated with a molding compound; rather, it has a A heat sink, which can additionally be used as an electrical shield, is described below. Thus, in this embodiment, the bottom package 402 includes a die 414 attached to a bottom package substrate 412 having at least one metal layer. It can use any of a variety of substrate types 'for example, including: a plywood having a 2-6 metal layer, or a construction substrate having a 4-8 metal layer, or a flexible polyimide tape having a 丨 2 metal layer Or a ceramic multiple layer substrate. The bottom package substrate 412 shown by the example of Fig. 8a has two metal layers 421, 423, each of which is patterned to provide a suitable circuit 'and connected through vias 422. The die is conventionally attached to a surface of the substrate using an adhesive, substantially referred to as a die attach epoxide, as shown at 413 in Figure 8A, and in the configuration of Figure 8A. The surface of the substrate to which the die is attached may be referred to as an "upper" surface, and the metal layer on the surface may be referred to as an "upper" metal layer, although the die attach surface does not need to have any use in use. Specific directionality. In the bottom BGA package of Figure 8A, the die line contacts are connected to the line contacts of the metal layer above the substrate to establish an electrical connection. Solder balls 418 are reflowed onto the contact pads on the metal layer below the substrate to provide circuitry interconnected to the bottom, such as a motherboard for a final product (not shown), such as a computer. Solder caps 415, 427 are patterned over the metal layers 42 }, 423 to expose the underlying metal at 155479.doc -38 - 201131731 contacts for electrical connection, such as at the wire contacts The wire contact 416 and the solder ball 418. The bottom BGA package 4〇2 of the multi-package module 80 has a metallized (e.g., copper) heat sink that can additionally serve as an electrical shield to electrically include any electromagnetic radiation from the die in the lower BGA. And thereby preventing interference with the crystal grains in the upper package. The "top" planar portion of the heat sink 4〇6 is supported on the substrate 412 and is placed over the crystal grain 414 by the foot or side wall 4〇7. A dot or line 4 〇 8 on the adhesive is used to secure the heat sink support 407 to the upper surface of the base substrate. The adhesive can be a conductive adhesive and can be electrically connected to the top metal layer 42 i of the substrate 4 , 2, particularly to a ground plane of the circuit, and thereby establishing the heat sink as an electrical shield. Alternatively, the adhesive may be non-conductive, and in this configuration, the heat sink is only used as a heat sink. The support of the radiator 4〇6 is Deng and the top. The crucible partially coats the die 4丨4 and the wire contacts 416 and can be used to protect those structures for ambient and mechanical stresses to facilitate handling operations, particularly subsequent testing prior to assembly of the MPM. The top package 8 of the multi-package module 80 is stacked on top of the bottom package 4〇2 on the flat surface of the heat sink/mask 406 and secured thereto using an adhesive 803. The adhesive 8〇3 may be thermally conductive to improve heat dissipation; and the adhesive 803 may be electrically conductive to establish electrical connection between the heat sink and the underlying metal layer of the lga package substrate, or it may be electrically insulated Thereby preventing electrical connections. The z-interconnection between the top package 800 and the bottom package 4〇2 according to the present invention is made up of a top package interconnection pad in the gap of the top package substrate 812 and 155479.doc • 39·201131731 in the bottom package substrate 402 A line contact 818 between the bottom package interconnect pads in the gap is formed. The line contacts can be formed by means of a contact or a lower contact. The multiple package structure is protected by forming a module covering 8〇7

. An opening may be provided in the support portion 407 of the heat sink to allow the MpM molding material to be filled in the enclosed space during cladding. Solder balls 41 8 are reflowed onto the exposed solder ball pads on the metal layer below the bottom package substrate 412 for connection to a lower layer circuit, such as a motherboard (not shown). As previously mentioned, the structure according to the present invention allows the BGA and LGA to be pre-tested prior to assembly into the multi-package module to allow for the exclusion of non-compliant packages prior to assembly, thereby ensuring a high final module test. rate. To improve heat dissipation from the multi-package module, a heat sink can be provided on the top package. The top heat sink is formed of a conductive material that exposes its upper surface to at least a more central region at the upper surface of the MPM to the surrounding environment to more effectively displace the tropics from the MpM. For example, the top heat sink can be a sheet of metal (e.g., copper) and it can be secured to the MPM cladding during the molding material curing process. Alternatively, the heat sink can have a generally planar portion over the top package and a surrounding support portion or a spacer member disposed on or near the upper surface of the bottom package substrate. By way of example, Figure 8B shows a cross-sectional view of a stacked BGA + LGA MPM 82 in accordance with another aspect of the present invention in which a "top" heat sink is provided at the upper surface of the MPM. The structure of the package stacked in the MpM 82 is generally similar to the MPM 8G in Figure 8A, and a similar structure can be identified in Figure t by a similar reference number 155479.doc 201131731. The top heat sink in this example is formed from a thermally conductive material having a generally planar central portion 804 positioned over the top package and surrounding support members extending to the upper surface of the bottom package substrate 412 806. The upper surface of the planar portion 804 is attached to the upper surface of the MPM to be exposed to the surroundings to efficiently discharge the MpM from the tropics. For example, the top heat sink can be formed by a sheet of metal, such as copper, for example by stamping. The support members 8A can be secured to the upper surface of the bottom package substrate (not shown) using an adhesive as needed. The multi-package module structure can be protected by forming a module cover 8〇7, and the heat sink support member is embedded in the M p m cladding during the molding material curing process. In the embodiment of Figure 8B, a stepped recessed feature 8〇5 is provided around the surface of the heat sink 804 to allow for better mechanical integration of the structure, rather than with The molding compound is separated: in this embodiment, the space between the lower surface of the heat sink_ and the upper surface 819 of the LGA molded 181 is filled into the MpM molded thin layer. Alternatively, the top heat sink can be a thermally conductive material, typically a flat sheet, such as, for example, a sheet of metal (e.g., copper) that does not require a support member. At least this: the more central # region of the upper surface of the surface heat sink is exposed to the surrounding ring disturbance to more effectively slant the tropical zone from the MPM » such a simple planar heat sink to 844 in Figure 8C, wherein The heat sink is secured to the top surface of the top package molding. However, in Figure 8B, the heat sink is not attached to the top of the ceiling.卩 Encapsulate the molded upper surface. Rather, the space between the surface and the upper surface 819 of the LGA molding 817 is filled with a thin layer of MPM molding, and the simple planar heat sink can be used in the molding material. 155479.doc • 41· 201131731 During the curing process to be fixed to the MPM cladding 807 » - around a simple planar top heat sink in a specific embodiment such as in Figure 8B, which may be coated with the MPM molding material 'and There may be a stepped recessed feature around the perimeter (referred to as a recessed feature 845 in the simple planar heat sink 844 of Figure 8C) to allow for better mechanical integration of the structure, and less The molding compound is detached. Alternatively, a top heat sink can be attached to the upper surface of the LGA molding as shown in the cross-sectional view of Figure 8C. The structure of the package stacked in the MpM 84 is generally similar to the MPM 80 of Figure 8A, and similar structures can be identified by similar reference numbers in the figures. The top heat sink 844 in the example of Figure 8c is a generally planar plate of thermally conductive material that exposes at least the uppermost area of the upper surface to the surrounding to more effectively remove the tropics from the MpM, as The example in Figure 8B. For example, the top heat sink can be a sheet of metal (e.g., copper). However, here the top heat sink 8〇4 is secured to the upper surface 819 of the upper package wrap 817 using an adhesive 846. The adhesive 846 can be a thermally conductive adhesive to provide improved heat dissipation. Typically, after the top package molding has been at least partially cured, the top heat sink is fixed to the top package molding, but before the molding material is ejected for the MpM package 847. The molding material can be coated around the top heat sink. In the embodiment of Figure 8C, a stepped recessed feature 845 is provided around the heat sink 4 to allow for better mechanical integration of the structure without being detached from the molding compound. The benefits of the structure shown in Figures 8A 8B, 8C are significant thermal performance 'and optionally 'electrical masking at the bottom package, for example in combination 155479.doc -42 - 201131731 RF and digital wafers A more important key in MPM. For all applications, it does not need to have both a bottom package heat sink and a top heat sink. In addition, depending on the needs of the end product, one of several is appropriate. Figure 9 A Shown as a front view of a multiple package module according to another aspect of the present invention, wherein the lower die flip chip BGA is stacked on an LGA. In the lower BGA, the die is a flip chip connected to the substrate. And the space between the die and the δ-shaped substrate is filled side. The bga can be measured in the assembled mpm. The back surface of the die can be used to attach the top LGA with an adhesive. The top LGA is interconnected with the module substrate Through the wire contacts, the turns are molded. A major benefit of this configuration is that the flip chip connection on the bga provides high electrical performance. Referring to Figure 9A, the bottom BGA flip chip package includes a A substrate 312 having a patterned metal layer 321 to which the die 314 is attached by flip chip bumps 316, such as solder bumps, &amp; bump bumps, or an anisotropic conductive film or paste. It is possible to use any substrate type; the bottom package substrate 312 shown by way of example is provided with two metal layers, M3, each of which is provided to provide appropriate circuitry and vias 322. An inverted flip chip bump is attached to a patterned bump array 'on the active surface of the die and as an active surface of the die' which faces the upwardly facing patterned metal layer of the substrate Downward, this configuration can be called: Flip-chip package for the next 曰曰 pellet. Filling a polymer side between the die and the substrate provides protection against the surrounding and adds mechanical integration to the structure. Atop 155479.doc 43- 201131731 The top LGA package 900 of the multi-package module 90 is typically constructed as a top LGA package 700 similar to the multi-package module 70 of FIG. In particular, the top package 900 includes a die 914' attached to a top package substrate 912 having a metal layer 921 that is patterned to provide suitable circuitry. The die is conventionally attached to the surface of the substrate using an adhesive, which is essentially referred to as a die attach epoxide, as shown in 913 of Figure 9A, and in the configuration of Figure 9A. The surface of the substrate to which the die is attached may be referred to as an "upper" surface. Therefore, the metal layer on the substrate may be referred to as an "upper" or "top" metal layer, although the die attach surface is not required for use. Has any special direction. In the top LGA package of the embodiment of Figure 9A, the die tie contacts to the line contacts of the metal layer above the substrate to establish an electrical connection. The crystal 914 and the wire contact 916 are coated with a molding compound 917 which provides protection against ambient and mechanical stress for handling operations. The cladding 907 in the embodiment illustrated in Figure 9A covers the die and the wire contacts and their connections, and the cladding has a surface 919 over the entire die and interconnect. As described below, the coating herein may be formed in the same manner as the embodiment of Fig. 6A. The image may be formed to cover only the wire contacts, and the individual wires are connected to the top package substrate and the top package die, so that the upper surface of most of the die is not covered by the cladding . The top package 9 is stacked on top of the bottom package 300 and secured thereto using an adhesive, as in 9〇3. A solder mask 915 is patterned over the metal layer 921 to expose an underlying metal call connection at the junction, such as at a line junction for bonding the line contacts 916. 155479.doc •44-201131731 &amp;## 顶 顶 顶 顶 顶 p p p p p p p 〇〇 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z The group structure is protected by the formation-module cladding 9〇7, and the solder ball 3 18 is back to the solder ball pad exposed on the metal layer under the bottom package substrate to connect to the lower layer circuit, for example, a final The motherboard of the product (not in the picture), like a computer. The solder masks 315, 327 are patterned over the metal layer 321 323 'to expose the underlying metal at the contacts for electrical connection', such as at the line contacts to engage the line contacts 918 and the ball 318 〇 has a structure of lga stacked on a flip chip BGA having a lower die 'see, for example, FIG. 9A' which can be combined - a heat sink and an electric shield, as shown in FIG. 8B or FIG. 8C. 9B is a cross-sectional view of a multi-package module in accordance with another aspect of the present invention, wherein the flip chip BGA of the lower die is a folded LGA, as in the embodiment of FIG. 9A, and wherein the lower portion has a Radiator / shade. In particular, referring to FIG. 9B, the bottom BGA package 300 of the multi-package module 92 has a metallized (eg, copper) heat sink that additionally serves as an electrical shield to include any of the BGAs in the lower BGA. The electromagnetic radiation of the grains 'and thereby prevents interference with the grains in the upper package. The "top" planar portion of the heat spreader 906 is supported on the substrate 312 and supported on the die 314 by a foot or sidewall 909. An adhesive dot or line 9〇8 is used to secure the heat sink support 909 to the upper surface of the base substrate. The adhesive can be a conductive adhesive 'and can be electrically connected to the top metal layer 321 of the substrate 312', in particular to a ground plane of the circuit, and thereby establish 155479.doc • 45·201131731 the heat sink is made For an electric shield. Alternatively, the adhesive can be a non-conductive 'and in this configuration' the heat sink acts only as a heat sink. The support and top portions of the heat sink 906 enclose the die 314 and can be used to protect those structures against ambient and mechanical stresses to facilitate processing operations, particularly subsequent testing prior to assembly of the MPM. The top package 900 of the multi-package module 92 is stacked on top of the bottom package 300 on the flat surface of the heat sink/mask 906 and secured thereto using an adhesive 903. The adhesive 903 can be thermally conductive to improve heat dissipation; and the adhesive 903 can be electrically conductive to establish electrical connection between the heat sink 9〇6 and the underlying metal layer of the package substrate, or it can be electrically insulated. This prevents electrical connections. The z-interconnection between the top package 900 and the bottom package 3A according to the present invention is interconnected by a top package interconnect in the gap of the top package substrate 91 2 and a bottom package interconnect in the void of the bottom package substrate 300. A line contact 918 is formed between the pads. The line contacts can be formed by means of a contact or a lower contact. The multi-package module structure is protected by forming a module cover 9〇7. An opening is provided in the support portion 907 of the heat sink to allow the MPM molding material to be filled in the enclosed space during cladding. The ball 3 18 is reflowed onto the exposed solder ball pads on the metal layer below the bottom package substrate 3 for connection to a lower layer circuit, such as a motherboard (not shown). As previously mentioned, the structure according to the present invention allows the BGA and LGA to be pre-tested prior to assembly into the multi-package module to allow for the exclusion of non-compliant packages prior to assembly, thereby ensuring a high final module test. rate. 155479.doc -46- 201131731 In the wafer bottom package in accordance with this aspect of the invention, the chip can be, for example, an ASIC, GPU or CPU, typically as = can be a -memory-package. Wherein:::::: : memory sealing material, which can be - heap (four) grain record _ package. The bottomed package of the flip-chip w is particularly suitable for higher speed applications, ', especially RF processing, such as in mobile communications applications. It may have a heat sink in the next die configuration such that the MPM having a flip chip bottom package (as shown in Figure 9A or Figure 9B). In order to improve the heat dissipation of the multiple package modules as shown in the example of Figure 9A or ,, a heat sink can be provided over the top package. The top diffuser is formed of a conductive material that exposes its upper surface to at least a more central region at the upper surface of the crucible to the surrounding environment to more effectively displace the tropic from the MPM. For example, the top heat sink can be a sheet of metal (e.g., copper)&apos; and it can be secured to the MpM cladding during the molding material curing process. Alternatively, the heat sink can have a generally planar portion over the top package, and - a peripheral support portion, or a support member disposed on or near the upper surface of the bottom package substrate. By way of example, Figure 9C is a cross-sectional view of a stacked BGA + LGA MPM 94 in accordance with another aspect of the present invention, wherein a "top" heat sink is provided at the upper surface of the MpM. The structure of the package stacked in the MPM 94 is generally similar to the MPM 92 in Figure 9B, and similar structures can be identified in the drawings by similar reference. The top heatsink in this example is formed of a thermally conductive material having a generally planar central portion 944 over the top package and extending over the bottom package substrate 3丨2, Table 155479. Doc -47- 201131731 The surrounding support member 946. The upper surface of the planar portion 944 is attached to the upper surface of the MPM to be exposed to the surroundings to efficiently discharge the tropical MPM. For example, the top heat sink can be formed by a metal sheet such as copper, for example by punching. The support members 946 can be secured to the upper surface of the bottom package substrate (not shown) by an adhesive as needed. The multi-package module structure is protected by the formation of a module cover 907, and the heat sink support member is embedded in the MPM cladding 907 during the molding material curing process. In the embodiment of Figure 9C, a stepped recessed feature 945 is provided around the planar upper portion 944 of the heat sink to allow for better mechanical integration of the structure and less The molding compound is detached. In this embodiment, the space between the lower surface of the heat sink 944 and the upper surface of the die 914 is filled with a layer of ^1&gt;], which is thick enough so that the 6 hai radiator 944 is not Will interfere with the surrounding lga molding 91 7 . Additionally, the MPM in a particular embodiment like 9A or 9B can have a simple planar heat sink that does not have a support member. This simple planar heat sink can be secured to the upper surface 519 of the top package module 517 using an adhesive. Alternatively, the MPM of the embodiment of Figure 9A or Figure 9B may have a simple planar heat sink that does not adhere to the top surface of the top closure molding. In these embodiments, as in the particular embodiment of Figure 5D, the top heat sink T is - a generally planar thermally conductive material, such as, for example, a metal sheet (e.g., copper), and at least the planar heat sink The more central area of the surface is exposed to the surrounding ridges to more effectively remove the tropics (4) (10). Here, in the embodiment of Fig. 9C, the space between the lower surface of the planar heat sink and the top package 900 may be filled with a layer of MpM. And such a simple planar heat sink as in the embodiment of Figure 9c 155479.doc -48-201131731, which can be secured to the MPM cladding 907 during the molding material curing process. The unattached, simple planar top heatsink may be wrapped around the (10) transition material, such as the planar heat sink attached in Figure 5D, and may provide a

A stepped recessed feature to allow for better mechanical integration with the structure and less separation from the molding compound. Q

For example, the MpM with a heat sink shown in Figure 9C provides the thermal performance of the cover. D. The bottom package of the MPM according to the present invention may be in a flip chip package 'λ in an upper die configuration, the bottom package crystal (4) being carried on the lower surface of the bottom package substrate. Typically, the bottom seal die attach area in such a configuration is tied to a center of the substrate area, and the second order interconnect ball can be disposed on the perimeter close to two or more of the The edge of the substrate. The upper die-flip wafer and its flip chip interconnect structure are within the landing height of the second-order interconnect structure, and thus the bottom-sealed die in this configuration is integral to the die The thickness did not contribute. Moreover, the upper die configuration avoids a net column reversal effect, which is essentially the result of the lower die configuration. In particular, by way of example, FIG. 10A is a cross-sectional view of a multiple package module 101 in accordance with another aspect of the present invention, wherein a stacked die platform grid array package 1000 is stacked in an upper die configuration 302. Above a flip chip BGA, and the stacked packages are interconnected by wire contacts. In the bottom BGA package 302, the die 344 is attached to the lower side of the BGA substrate 342. 155479.doc •49- 201131731 As shown in the figure, 'this structure provides a thinner MPM because the bottom package die is in the region between the solder ball and the bottom side of the bottom package. The configuration can have a higher electrical performance, not only because it uses a flip chip connection, but also because it provides a more direct electrical connection of the die to the solder balls for the die and the solder The connection between the balls has a shorter metal trace and does not require a through hole (as required in the configuration in Figure 9 or )). In addition, the upper die configuration allows the package to be compatible with wire contacts on the grid as required in some applications. The mesh is the sum of all the connections between the die and the solder balls. When the grain faces the "lower grain", it has a connected pattern which is a mirror image of the same type in the same grain when the grain faces the "upper grain". In the configuration of Figure 10A, the top LGA package is attached to the upper side of the BGA with an adhesive, then wire contacts and molding. In the specific embodiment of the example of Figures ia to i〇e, more than one die (two or more) is stacked in the top package. Stacked die packages have been well established in the industry, and these versions can achieve up to five stacked dies in the package. The dies have different sizes' and the dies in a stacked die package can Have relative dimensions that are identical or different. The schm grains are substantially square or rectangular, and rectangular and square dies of different sizes can be stacked in the stacked die package +. When the crystal grains are rectangular or have different sizes, the crystal grains can be stacked, so in the stack, the voids of the lower crystal grains protrude beyond the voids of the upper crystal grains stacked thereon. Figure 1A shows an example in which the two grains are the same size in the stack. In the example, or when the upper grain in the stack is larger than the lower crystal: 155479.doc • 50· 201131731, a spacer is assembled between the crystal grains to form a line connection of all the crystal grains. Click on the LGA substrate. Figure iB shows an example in which the upper die in the stack is smaller than the lower die; or alternatively, the die is stacked such that the upper stacked voids protrude beyond the void of the lower die. In the particular embodiment of Fig. 10B, no spacers are required because the line contacts at the line exit of the underlying crystal grain allow the line contacts to not interfere with the grains stacked thereon. Referring to FIG. 10A, the bottom flip chip BGA package 3〇2 includes a substrate 342 having a patterned metal layer 353, which is a portion of the die 344 connected by flip chip bumps 346, such as solder bumps. A block, a gold dot bump or an anisotropic conductive film or paste. Any of a variety of substrate types can be used: The bottom package substrate 342 shown in the example of Figure 10A has two metal layers 351, 353' each patterned to provide a suitable circuit. The bottom package substrate 342 additionally has a metal layer 355 sandwiched between the dielectric layers 354, 3f6. The metal layer 355 has voids at selected locations to allow the metal layers 351, 353 to pass through the via connections, such that selected portions of the patterned metal layers 351, 353 are connected by vias. The substrate layers 3 54 , 3 56 , and the voids in the metal layer 355 sandwiched therein. The selected portion of the patterned metal; f 353 is connected through via substrate 356 to the sandwiched metal layer 355 via vias. Flip-chip bumps 341 are attached to a patterned bump pad on the active surface of the die, and because the active surface of the die faces the patterned metal layer of the substrate facing down This configuration can be referred to as an "upper die" flip chip package. A polymer side fill 343 between the die and the die attach region of the substrate 155479.doc 201131731 provides protection against the surrounding and adds mechanical integration to the structure. As described above, the metal layers 351, 353 are patterned to provide a suitable circuit, and the sandwiched metal layer 355 has voids at selected locations to allow selection on the upper and lower metal layers 351, 353. Interconnection is allowed between the traces (not touching the sandwiched metal layer 355). In particular, for example, the underlying metal layer is patterned in the die attach region to provide adhesion to the flip chip interconnect bump 343; and for example, the underlying metal layer is patterned closer to the bottom package substrate 342 The voids provide the attachment of the second-order interconnect solder balls 348 whereby the completed MpM is reflow soldered to the underlying circuitry (not shown). For example, in particular, the upper metal layer is patterned adjacent to the void of the bottom package substrate 342 to provide attachment of the wire contacts to the top package to the bottom package. A ground line in the circuit of the metal layer 353 is connected to the sandwiched metal layer 355 through a via; a selected one of the balls 348 is a ground ball 'which is attached to the underlying circuit when mounted Ground wire. Therefore, the sandwiched metal layer acts as a ground plane for the MPM. These solder balls are selected for input/output, or power balls 'so' these are attached to the solder balls of the input/output or power lines in the circuit of the metal layer (5). Still referring to @10A, the top package is a stacked-grain grid array in which the dies 1 〇 14, 1 〇 24 are separated by a spacer (9) and stacked on a top (four) substrate. The top package substrate includes a dielectric layer having a metal layer on the surface of the upper substrate and patterned to provide traces, for example, having an attachment for the top package 155479.doc • 52· The 201131731 substrate line contacts are interconnected to the stacked die, and the line contacts for the top package are interconnected to the bottom package substrate. The lower die 1014 is attached to a die attach region of the top package substrate using a dot implant 1013, such as a grain adhesion epoxide. The die 1014 is electrically coupled to the top substrate by wire contacts 1016, connected at line contacts on the active surface of the die to the line contacts on the selected trace 10U. A spacer 1〇15 is attached to the upper surface of the lower die 1014 using an adhesive (not shown), and the upper die 1024 is fixed to the spacer using an adhesive (not shown). The upper surface of the device 1015. The spacer is selected to have a sufficient thickness to provide a void so that the protruding voids of the upper die 1024 do not invade the wire bonds 1016. The die 1024 is connected to the top substrate by wire contacts 1 〇 26 which are connected at line contacts on the active surface of the die to the line contacts on the selected trace 1011. The stacked die and the wire contact assembly on the top package substrate are wrapped in a molding material 1 〇 17 to provide a top package upper surface 1019 and leave the exposed mutual Connect the gap between traces 1 and 11. The top package can be tested at this point and then stacked to the die attach area on the top surface of the 5 liter bottom package substrate and secured thereto using an adhesive 1003. The electrical interconnections of the top and bottom packages are subjected to lines on the traces exposed on the traces 1〇1 of the top package substrate and on the traces of the metal layer above the bottom package substrate. The contact at the contact is affected by the wire contact 1018. The MpM assembly is then wrapped in a molded 1007 to protect the package-to-package wire contacts and provide mechanical integration in the finished MpM 101. The stacked die top package stacked on top of the upper die flip chip 155479.doc -53 - 201131731 piece BGA package in these embodiments may have various configurations depending, for example, in the stack The number of crystal grains, and according to the size of the crystal grains. For example, in a wearing diagram, circle 1〇B is shown as another MpM configuration 103, wherein the LGA has two stacked dies, and wherein the upper die 1044 is smaller in size than the lower dies 1〇34 should be small, at least on the plane of the cross-sectional view. In this configuration, the gap between the wire contact in the gap of the lower die/the upper die is protruded, so that it is not necessary to include a spacer. The bottom package 3〇2 in the MPM 1〇3 of Fig. 10B is substantially similar to the bottom seal in the MPM 101 of Fig. 10A, and the corresponding portions are similar to those shown in the drawings. The top package in the MPM 1〇3 is diced into a stacked die platform grid array package having die 1〇34, 1〇44 stacked on top of a top package substrate. The top package substrate includes a dielectric layer 〇12 having a metal layer on the surface of the upper substrate and being visualized to provide traces, such as 032, with an attachment for the top package substrate line A junction is interconnected to the stacked die and a line contact for the top package is interconnected to the bottom package substrate. The lower die 1034 is attached to a die attach region of the top package substrate using an adhesive 1 〇 33, such as a die attach epoxide. The die 1034 is electrically coupled to the top substrate by wire bonds 1〇36 which are connected at line contacts on the active surface of the die to the line contacts on the selected trace 1031. The upper die (7) is affixed to the top surface of the die 1034 using an adhesive 。. The die 1 〇 44 is electrically connected to the top substrate by wire contacts 1046, which are connected to the die. The line contact on the active surface is at the line contact on the selected trace 1〇31. The stacked die and wire contact assembly on the top package substrate is wrapped to provide a 155479. Doc-54-201131731 The top package encloses the upper surface 1039 of molding material 1037 and leaves the void portion of the exposed interconnect trace 1031. The top package 1〇3〇 can be tested at this time' and then stacked a die attach area on the top surface of the bottom package substrate and secured thereto using an adhesive 1003. The electrical interconnections of the top and bottom packages are exposed by traces 101 1 of the top package substrate The line contact is affected by the line contact 1018 at the line contact on the trace 35 1 of the metal layer above the bottom package substrate. Then the assembly is wrapped in a molded 1007 To protect the package-to-package line contacts and provide mechanical integration in the completed MPM 103 The processor chip in the flip chip bottom package according to this aspect of the invention may be, for example, an ASIC, GPU or CPU; and the top package may be a memory package, in particular, for example, in FIG. 10A and FIG. One of the stacked die memory packages is shown. The bottom-mounted flip-chip on-die configuration provides a very thin module and is especially well suited for higher speed applications such as mobile communications. In a specific embodiment such as MPM 101 or 1 〇 3, the ground plane 355 in the bottom package substrate is additionally used as an electromagnetic shield to significantly reduce interference between the BGA die and the covered LGA die, and For example, MPM can be particularly applied in applications where the bottom package die is a high frequency die (eg, radio frequency). In some applications, it is also required to shield the bga die in the bottom package from the MPM. The lower layer circuit. Figure 1〇c shows an example of a multi-package module 105 in which a stacked die platform grid array package 1 is stacked in an upper die configuration 302 in a flip chip bga上^ 155479.doc •55· 201131731 Wherein the stacked packages are interconnected by wire contacts, wherein an electromagnetic shield is provided at the flip chip BGA to limit radiation downward toward the underlying circuitry (not shown). In the MPM 105 of Figure 10C, The top package 10A and the bottom package 302 are substantially constructed as shown in FIG. 1AiMPM 1〇1, and the corresponding features can be correspondingly identified in the figure. The bottom package of the MPM 1〇5 is 3〇2 That is, having a metallized (e.g., copper) electrical shield electrically includes electromagnetic radiation from the die in the lower BGA and thereby prevents interference with circuitry under the installed MPM. The lower planar portion of the shield 3() 4 is supported by the foot or side wall 305. An adhesive dot or line 3〇6 is used to secure the heat sink support 305 to the lower surface of the base substrate. The adhesive can be a conductive adhesive&apos; and can be electrically connected to traces in the metal layer beneath the substrate, particularly to the ground traces of the circuit. The support portion and the lower planar portion of the shield enclose the die 344 and, in addition to shielding the underlying die in the finished device, can be used to protect the underlying die for ambient and mechanical stress for processing Work, and especially during subsequent testing prior to assembly of the MpM, or prior to installation. Additionally, as described below, the masking described with reference to Figure (4) can be used to mask the top die flip chip bottom package in the MPM with other stacked tantalum top package configurations. For example, the stacked die top package does not have a spacer between adjacent crystal grains, as shown in Fig. 10B. In addition, the masking as described with reference to Figure 10C can be used to mask the die-flip wafer bottom package 3〇2 in the MpM, except for the top package of the stacked die top package. For example, the top package can be a - platform grid array 155479.doc • 56-201131731 package, such as the 2LGA top package shown in Figure 5A. Furthermore, in order to improve the heat dissipation of the multi-package module, which is usually disposed in FIG. 1A, a heat sink can be provided on the top package. The top heat sink is formed of a conductive material that exposes its upper surface to at least a more central portion of the surface of the MPM to the surrounding environment to more effectively move the tropics away from the MpM. For example, the top heat sink can be a metal sheet (e.g., copper) and it can be secured to the »HPM coating during the molding material curing process. Alternatively, the heat sink can have a generally planar portion &/or a perimeter portion of the top package or a support member disposed on or near the upper surface of the bottom package substrate. By way of example 'FIG. 10E, a cross-sectional view of MpM } 〇9 including a stacked die top package stacked on top of the upper die pad flip chip BGA is provided, wherein a "provided" is provided at the upper surface. Top" radiator. The structure of the top and bottom packages in the deletion 109 is generally similar to the MPM 105' in Figure (10) and similar structures can be identified in the drawings by similar reference numerals. The top heat sink in this example is formed of a thermally conductive material having a generally planar central portion ι_ above the top package 1 , and extending over the bottom package substrate 342 The surrounding branch member 1046 of the surface. The upper surface of the planar portion 1〇〇4 is attached to the surface of the MpM to be exposed to the surroundings to efficiently discharge the MpM from the tropics. For example, the top heat sink may be formed of a metal piece (for example, copper). For example, by stamping, the supporting member HM6 may be fixed to the upper surface of the bottom package substrate by an adhesive as needed (not shown). ). The multi-package module structure can be protected by a forming-module coating H) ' 7 and the heat sink supporting member is embedded in the MPM cladding 1007 during the curing process of the mold 155479.doc • 57· 201131731 . In the embodiment of Figure 10E, a stepped recessed feature 1045 is provided around the portion of the flat surface 44 above the plane of the heat sink to allow for better mechanical integration of the structure, rather than with The molding compound is detached. In this embodiment, the space between the lower surface of the heat sink 1 044 and the upper surface 1019 of the LGA molded 1 〇 17 is filled into the MPM molded thin layer. Alternatively, the top heat sink can be a thermally conductive material, typically a flat sheet, such as, for example, a sheet of metal (e.g., copper) that does not require a support member. At least a more central region of the upper surface of the planar heat sink is exposed to the surrounding area to more effectively remove the tropics from the Mpm. This simple planar heat sink is shown in Fig. 10D, which is fixed to the top surface of the top package molding. The structure of the package stacked in the crucible 107 is generally similar to the MPM1Q9 in the figure, and similar structures can be identified by similar reference numerals in the drawings. The top heat sink 1004 in the example of FIG. 10D is a generally planar sheet of thermally conductive material having at least a more central region of its upper surface exposed to the surrounding environment to more efficiently extract the tropical MPM, As shown in the example in the figure. For example, the top diffuser can be a metal sheet (for example, copper. However, the top heat sink is fixed to the upper surface of the upper package (7) ^HH9 by an adhesive 1006. The adhesive can be a thermally conductive adhesive to provide improved heat dissipation. Typically, after the top seal molding has been at least partially cured, the top heat sink is fixed to the top package molding, but it is attached to the molding material for the Before the coating is ejected, the MPM molding material may be wrapped around the top (four). In the specific embodiment of Fig. 1 , a stepped shape is provided around the radiator 1004 at 155479.doc • 58-201131731. The feature 1〇〇5 is recessed to allow for better mechanical integration of the structure without being detached from the molding compound. A simple planar heat sink, such as 1〇〇4 in Figure 10D, does not It is necessary to adhere to the top surface of the top package molding. Rather, the space between the lower surface of the simple planar heat sink and the surface 1〇19 of the LGA molded 1〇17 is filled with a thin layer of MPM. Molded, and this simple flat heat sink can be The molding material is fixed to the coating during the curing process. Around the simple planar top heat sink, in this embodiment, it may be coated with the MPM molding material. And having a stepped recessed feature around the circumference (referred to as a recessed feature ι〇〇5 in the simple planar heat sink 1〇〇4 in Fig. 10D) to allow the structure to have a better mechanical Integration is less detached from the molding compound. The advantages of the structure as in Figures 1D, 10E are to improve thermal efficiency. For all applications, it does not need to have both bottom package shielding and a top In addition, depending on the requirements of the end product, one of several is appropriate. Figure η shows another specific real-world cross-sectional view of the MpM (i.e., nG) according to the present invention, wherein - the stacked die The LGA top package 1 〇 (9) is stacked on top of a stacked die BGA, and the top and bottom packages are interconnected by wire contacts. In the specific example of Figure EJ i 1 The bottom BGA package 408 is in the stack and the ancient + plus 曰 ~ _ τ eight The granules of the day, and the top LGA package has two dies in the stack. For example, the structure with this configuration is particularly suitable for use in a fixed trajectory 155479.doc • 59· 201131731 Note: In the application of degrees. The stacked dies may be the same or different °: formula, including flash, SRAM, PSRAM, etc. 1 The top package 1000 is substantially constructed to resemble the top seal 1000 of the figure, and similar features are similar The reference package is identified. In particular, the top package is a - stacked die platform grid array package 'where the die 1〇14, 1〇24 are separated by a spacer (8) 5 and stacked in a top package On the substrate. The top package substrate includes an &quot;electric layer 1012' having a metal layer on the upper substrate surface and patterned to provide traces 'eg 1 '11' having attachments for the upper package substrate line contacts The die is interconnected to the material #, and the line of the upper package is connected to the bottom package substrate. The lower die (7) "use-adhesive 1013 is attached to a die attach region of the top package substrate, such as a die attach epoxide. The die 1014 is connected to the top by a wire contact. Connected to the line contact on the active surface of the die at the line contact on the selected trace 1011. A spacer 1〇15 is secured to the wire using an adhesive (not shown) The upper surface of the lower die 1014 and the upper die 1024 are secured to the upper surface of the spacer 1 15 using an adhesive (not shown). The spacer is selected to have a sufficient thickness to provide a void, so The protruding voids of the upper die 1024 do not invade the wire contacts 1016. The die 1024 is connected to the top substrate by wire contacts 1〇26, which are connected to the wire contacts on the active surface of the die. At a line contact with the selected trace 丨〇丨i. The stacked die and the wire contact assembly on the top package substrate are wrapped in a molding material 1 〇17, A top package upper surface 1019 is provided and the exposed interconnect traces are left 丨空隙 空隙 155479.doc -60- 201131731 part. The top package 1000 is tested at this time and then stacked on top of the bottom package 408 'as detailed below. The bottom package of the MPM 11 〇 4 〇 8 The structure is similar to the top package 1000. In particular, the bottom package 408 is a stacked platform grid array package that separates the dies 444, 454 from a spacer and is stacked on a bottom package substrate. The bottom package substrate acts as the completed MpM interconnect substrate 'and it can be constructed, for example, in a manner similar to the bottom substrate 412 of the bottom package 400 of the MPM 500 of Figure 5A. In particular, in this particular embodiment, the bottom The package 408 includes a bottom package substrate 442 having at least one metal layer, which may use any of a variety of substrate types, including, for example, a plywood having a 2-6 metal layer, or a construction substrate having a 4-8 metal layer, or having a flexible polyimide layer of 1-2 metal layer, or a ceramic multiple layer substrate. The bottom package substrate 442 shown by the example of FIG. 11 has two metal layers 451, 453, each of which is patterned Appropriate circuits are provided and connected by vias 452. The lower die 444 is conventionally attached to an "upper" surface of the substrate using an adhesive 443, which is basically referred to as the die attach ring. The oxide is shown as 443 in FIG. The lower die is electrically connected to the base substrate by wire contacts 446 that are connected at line contacts in the active surface of the die 444 to the line contacts on the selected trace 45A. A spacer is secured to the upper surface ′ of the lower die 444 using an adhesive (not shown) and the upper die 454 is stacked thereon and secured thereto using an adhesive (not shown). The upper surface of the spacer. The spacer is selected to be sufficiently thick to provide a void so that the protruding void of the upper die 454 does not conflict with the wire contact 6. The upper die 454 is connected to the bottom substrate by a 155479.doc -61 · 201131731 wire bond 456 that is connected to the line contact in the active surface of the die 454 and the line on the selected trace 451 At the junction. The bottom seals the lower die 444 and the upper die 454, and the wire contact is coated with a mold compound 447 which provides protection against ambient and mechanical stress for handling operations and provides The top stacked die package 1000 can be stacked on the bottom package upper surface thereon. The solder balls are reflowed onto the contacts on the metal layer below the substrate to provide circuitry interconnected to the bottom, such as the motherboard of the final product (not shown in the figure, the solder mask, the 457 system is patterned Above the metal layers 451, 453, the underlying metal is exposed at the contacts for electrical connection, such as bonding the wire contacts and solder balls 418 at the wire contacts. The top package surface can be tested And then stacked to the die attach area on the top surface of the bottom package substrate and secured thereto using a layer of the dopant (10). The electrical interconnections of the top and bottom packages are subject to traces 1011 on the top package substrate. The exposed line contacts are affected by line contacts 1118 at the line contacts on the trace 451 of the metal layer above the bottom package substrate. The MPM assembly is then wrapped in a molded 11〇7 To protect the package from the wire bond of the package, and to provide mechanical integration in the finished Lai Gang 11", the MPM in the top package and the bottom package, or both in the top and bottom packages can be special Suitable for applications with high memory small tracks. For example A multi-package module of FIG. 11 can include a stacked die memory top package on a stacked ASIC bottom package; or a top, bottom, and top package can be stacked die memory packages. Forming a high-density memory phantom 155479.doc-62-201131731 group. Other stacked die package configurations may be applied to the bottom or top stacked die package in the MPM according to this aspect of the invention, for example according to The number of grains in the stack, and according to the grain size in the stack. For example, an upper die in a bottom packed stack may have a smaller size than a lower germanium B grain. In this configuration, there is no gap above the wire contact in the gap of the lower die without the gap of the upper die, so that it is not necessary to include a spacer between adjacent dies in the stack. In this aspect of the invention, other top package configurations can be stacked on a stacked tantalum bottom package. For example, as shown in the specific embodiment of Figure 5, the BGA top package can be stacked in a stacked die bottom package. In order to improve from Heat dissipation of a multi-package module having a stacked die bottom package, such as shown in Example 10 of Figure U, on which a heat sink can be provided. The top heat sink is formed of a thermally conductive material ,

There are more areas of appeal in the upper surface to expose the upper surface of the MPM to the surrounding environment to more effectively remove the tropics from the MPM. For example, the top heat sink can be a sheet of metal (e.g., a steel sheet) that can be secured to the river during the curing process of the molding material. ]^Coated. Alternatively, the heat sink can have a generally planar portion over the upper package, and a portion of the perimeter of the perimeter or a support member disposed on or adjacent to the bottom package substrate. The top heat sink shown by the examples of Figures 5D and 5E can also be applied to a top MpM heat sink in a package with a -stacked die bottom package. (Or have stacked die bottom and top packages) 155479. Doc-63 - 201131731 For example, referring to the MPM structure of FIG. 2 and the heat sink in the figure, the top heat sink is formed of a thermally conductive material having a generally planar central portion 544 positioned above the top package. And a surrounding support member 546 that extends to the upper surface of the bottom package substrate 442. The surface of the planar portion 5 is attached to the upper surface of the MPM to be exposed to the surroundings to efficiently discharge the tropical MPM. For example, the top heat sink can be formed from a sheet of metal, such as copper, such as by stamping. The support members 546 can be secured to the upper surface of the bottom package substrate using an adhesive as needed. The multi-package module structure can be protected by forming a module cover 11 ’ 7 and the heat sink support member is embedded in the MPM cladding 11 〇 7 during the molding material curing process. A stepped recessed feature 545 is provided around the planar upper portion 544 of the heat sink to allow for better mechanical integration of the structure without being detached from the molding compound. In this embodiment, the space between the lower surface of the heat sink 544 and the top surface ι 9 of the top package molding 1 〇 17 is filled into the MPM molded thin layer. Additionally, a top heat sink can be attached to the top surface of the top package molding. Referring to the MPM structure of FIG. 5A, and referring to the heat sink of FIG. 5D, for example, the top heat sink 504 can be a generally planar plate of a thermally conductive material that exposes at least a more central region of its upper surface to the periphery. To more effectively remove the tropics from the MPM. For example, the top heat sink can be a metal plate (e.g., copper). However, here, the top heat sink 5〇4 is fixed to the upper surface 1〇19 of the upper package by an adhesive using an adhesive. The adhesive can be a thermally conductive adhesive to provide improved heat dissipation. Typically, the top heat sink is attached to the 155479 after the top package molding has been at least partially cured. Doc -64- 201131731 Z package molding 'but it is before the molding material is shot for the enamel cladding 1107: before. The periphery of the top heat sink may be coated with the molding material. The heat dissipation (four) 504 is provided with a stepped concave feature 505 = a mechanically integrated degree of the preferred structure, and less than the molding. The compound is detached. As an alternative, as in the figure, Mm can have a simple flat and does not have a binding component, which does not attach (10) the top package. The upper surface of #. In some embodiments, the top heat sink can be a generally planar plate of thermal material, such as, for example, a metal sheet (eg, copper) + 'and at least a more central region of the upper surface of the planar heat sink. Department, the road to the surrounding to more effectively remove the tropics. Here, the space between the lower surface of the simple planar heat sink and the upper surface 1019 of the LGA molding 1017 is filled with a thin layer of tantalum molding, and the simple planar heat sink can be used in the mold. The material is fixed to the ΜρΜ cladding 11〇7 during the curing process of the material. The periphery of the unattached, simple planar top heat sink may be coated with the tantalum molding material, as in the planar heat sink attached in Figure 5D, and may provide a stepped recessed feature on the periphery. 5, to allow for better mechanical integration with the structure, i is less separated from the molding compound. As understood from the foregoing, in all of the different aspects, the invention is characterized as being between stacked packages. The line junction of the z interconnect method. In summary, all LGAs stacked on a lower BGA must have less than the BGA (at least one dimension on the x_y plane) for the line contacts to allow space around. The wire diameter is usually at the level of 〇〇25 (〇〇5〇 to 155479. The range of doc-65-201131731) the distance to the edge of the lga substrate is different in many embodiments, but not less than a wire diameter. The relative sizes of the BGA and LGA are primarily determined by the maximum grain size of each. The thickness of the die and the thickness of the mold cover primarily determine how many grains can be stacked in one package. The process for fabricating the BGA package and the LGA package used in the present invention has been well established in the industry for both the wire contact and the flip chip type package. BGA testing has been well established in the industry and is basically accomplished by making contact with such solder ball pads. The LGAs can be tested in one of two ways, namely by accessing a jlga pad on the lower surface of the LGA of the substrate, similar to a solder ball pad in a BGA; or by accessing the substrate The z interconnect pads on the upper surface. These completed 1^11&gt;]^ assemblies can be tested in the same way as the test BGA. The MPM assembly process is similar for configurations in accordance with various aspects of the present invention. In summary, the processing includes the following steps: providing a first molding package including a first package substrate and at least one die attached to the first package substrate, and dispensing an adhesive to an upper surface of the first molding package Depositing a second molded package including a second package substrate and at least one die such that the lower surface of the second substrate can contact the adhesive on the upper surface of the first package during bonding, and A z-interconnect is formed between the first and second substrates. Preferably, the packages can be tested prior to assembly, which can discard packages that do not meet performance or reliability requirements, so the first package and the second package that are tested as "good" are used in the module for assembly. . 155479. Doc-66 - 201131731 Figure 12 is a flow chart showing the assembly process of the multi-package module shown in Figure 5A or Figure 7, for example. In step 1202, it provides an undivided strip of ball grid array package. The die and wire contacts on the ball grid array package are protected by a mold. The BGA package in the strip is preferably tested for performance and reliability prior to subsequent steps in the process (as shown in the figure). Only packages identified as "good" will be processed. In step 1204, the adhesive is dispensed over the molded upper surface of the "good" BGA package. In step 1206, a separate platform grid array package is provided. The separate LGA package is protected by -molding, and is preferably tested as (")" and identified as "good". In step i, a check and placement operation is performed to place a "good" L (M packaged on the adhesive over the molding of the "good" GA package. In step 丨〇2, the The adhesive is cured. In step 1212, an electric incineration cleaning operation is performed during preliminary step i2i4, wherein a wire contact z interconnection is formed between the top 1ga of the stack and the bottom BGA package. In step 1216, An additional power cleaning, then forming the m 1 (10) in step 1218, the second-order interconnect solder ball is attached to the bottom side of the module;; the completed module is tested (7), and Separating from the strip 'for example by separation or by punching, and being packaged for further use. Figure 13 shows a group of multiple package modules such as shown in Figure 68. 2 (4) Flowchart. In step _, provide the ball grid array package is not a strip. In the 兮 姑 』 措 措 措 措 措 措 措 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 That is, by a mold only on the ', 濩. 8 in the strip (3 eight package is preferably in I55479. Doc -67- 201131731 The performance and reliability test is performed before the subsequent steps in the process (the package marked as *good in the figure shown in the figure will be subjected to subsequent processing. In step 1304, the adhesive is Distributed over the molded upper surface on a "good" BGa package. In step 13A6, a separate platform grid array package is provided. The separate LGA package is protected by a perimeter molding to protect the The line contact, and preferably the test (7), is identified as "good." In step 1308, a selection and placement operation is performed to place the "sound" package on the "good" BGA package. Molding over (4) the agent. In step 1310, the adhesive is cured. In step UK, a cleaning operation is performed in the preliminary step 13 14 , "the top LGA and the bottom BGA in the stack" Wire contacts z interconnections are formed between the packages. In step !316, 'may be performed - additional electrical backwashing, followed by forming the mold in step (10) I. In step 132, second order interconnect solder balls That is attached to the bottom side of the module. The completed module is tested (*) and separated by the strip, for example by separation or by punching, and packaged for further use. Figure MA shows an example A flow chart of an assembly process of a multi-package module shown in the circle. In step (10), an undivided strip of a ball matrix package is provided. The BGA packages have a shadow fixed on the die. The mask can protect the die and wire contact structure on the ball grid array package. Therefore, no package molding is required. The BGA package in the strip is preferably before the subsequent steps in the process. Tests for performance and reliability (indicated by * in the figure). Only identified as accepting follow-up processing. In step 404, the adhesive is assigned to "good" 155479. Doc -68 - 201131731 Above the upper surface of the shield on the BGA package. In the tearing of step 1, a separate platform grid array is provided to seal the shock. The separate LGA package is protected by -molding and is preferably tested (7) and identified as "good". In (4) 1408, a selection and placement operation is performed to place a "good" [Μ" adhesive over the molding packaged on the "good" BGA package. The adhesive is cured in step 1410. In step 1412, a plasma cleaning operation is performed during preliminary step 1414, wherein a wire contact z interconnect is formed between the top and bottom BGA packages of the stack. In step 1416, additional plasma cleaning is performed, followed by formation of the MPM molding in step 1418. In the first step, a light removal operation is performed to decompose and remove unwanted organic matter. The light removal system is performed by laser or may be cleaned by chemical or plasma. In step 1422, a second-order interconnect solder ball can be attached to the bottom side of the module. In step 1424, the completed module is tested (*) and separated by the strip, for example by sawing. Separated or separated by punching and packaged for further use. Figure 14B is a flow chart showing an assembly process of a multi-package module such as that shown in Figure 8B. This process is similar to that shown in Figure 4A, with an additional step of inserting a "drop-in" mold operation prior to installation of the heat sink. Similar steps in the process are identified by similar reference numerals in the figure. In step 1402, an undivided strip of a ball grid array package is provided. The BGA packages have a shield that is fixed over the die. The masks protect the die and wire contact structures on the ball grid array package and therefore do not require package molding. The BGA package in the strip is preferably 155479 before it takes the next step in the process. Doc •69· 201131731 Test 4 (as indicated by the circle in the circle). Only follow-up processing identified as "good". The package at step "...4" will accept that in step 1404, the adhesive is dispensed onto the package on the top of the mask. In step 1406, a separate thousand is provided. Grid array package. This point, and 敕 (4) &quot; (d) LGA package is protected by the - mold protection (7), and identified as "good." In the step "= good check and placement operation", place the "good" core on the 14/πφ \"BGA package on the mask on the #agent. In the step 'the adhesive is cured. In step 1412, a plasma cleaning operation is performed during preliminary step 7, wherein a line junction z interconnection is formed between the top LGA of the stack and the portion of the BGA package. In step 1416, an additional plasma cleaning can be performed. In step 1415, the heat sink is dropped into each of the cavities in a cavity molding apparatus. In step 1417, the cleaning package stack from step 1416 falls into the cavity above the heat sink. In step 1419, a cladding material is injected into the cavity and cured to form the MPM molding. In step 1421, a light removal operation can be performed to decompose and remove unwanted organic matter. The light removal system is performed by laser or can be cleaned by chemical or electropolymerization. In step 1422, a second order interconnect solder ball can be attached to the bottom side of the module. In step 1424, the completed module is tested (*)&apos; and separated by the strip, e.g., by splitting or by punching&apos; and packaged for further use. Figure 14C is a flow chart showing an assembly process of a multi-package module such as that shown in Figure 8C. This process is similar to that shown in Figure 4A, where an additional step of attaching to the top package is inserted in the document. Similar steps in this process are given by reference numbers like Figure 155479. Doc -70- 201131731 Identification. In step 1402, an undivided strip of a ball grid array is provided. The BGA packages have (iv) a shadow over the die. These masks protect the die and wire contact structures on the ball grid array package and therefore do not require package molding. The BGA package of the strip is preferably tested for performance and reliability prior to subsequent steps in the lamp manufacturing process (not shown). Only packages identified as "good" will be processed. At step 14G4, the adhesive is dispensed over the masked upper surface of the "good" BGA package. In step 14〇6, a separate platform grid array package is provided. The off-the-shelf LGA package is protected by a molding, and is preferably 4 (*)' tested and identifies "good". In step ^, a selection and placement operation is performed to place the "good J LGA package" on the mold on the mask of the "good" BGA package. In the first step i4i, the adhesive is cured. In step 1412, a plasma cleaning operation is performed prior to the preliminary step 1414, wherein a wire contact z interconnection is formed between the top 1ga and bottom bga packages of the stack, followed by an additional plasma cleaning. In step 1431, an adhesive is dispensed onto the upper surface of the top LGA package molding, and in step 1433, a selection and placement operation is performed to place a planar heat sink to the top package molded adhesive. Above. In step 1435, the adhesive is cured. At step 1416, additional plasma cleaning is performed, and in step 418, the MPM molding is formed. In step 142, a light removal operation can be performed to decompose and remove unwanted organic matter. The de-lighting can be carried out by #射 or chemical and electrical cleaning. At step 1422, the second-order interconnect solder balls can be attached to the bottom side of the module. In step 1424, the completed module is tested (*)' and separated by the strip, for example by 155479. Doc 71 201131731 The saw is separated or separated by punching and packaged for further use. Figure 15 is a flow chart showing the assembly process of a multi-package module such as that shown in Figure 9A. In step 1502, an undivided strip of the bottom package of the lower die wafer wafer grid array is provided. The BGA package may or may not have and may not have a second order interconnect ball. The BGA package in the strip is preferably tested for performance and reliability (as shown in *) when it is followed by a subsequent step in the process. Only packages identified as "good" will be processed. In step 15〇4, the adhesive is dispensed over the upper surface (back side) of the die on a "good" BGA package. In step 1506, a separate platform grid array package is provided. The separate LGA package is protected by a mold and is preferably tested (7) and identified as "good". In the step-by-step procedure, a selection and placement operation is performed to place a "good" LGA package on the adhesive on the die on the "good" bga package. In step 151, the adhesive is cured. In step 1512, a plasma cleaning operation is performed at a preliminary step 1514, wherein a wire-to-I interconnection 4 is formed between the top LGA and the bottom BGA package of the stack, step 1516, which can be performed - additional power cleaning, The MPM molding is then formed in step 1518. In step 152, the second-order interconnect solder balls are attached to the bottom side of the module. In step 522, the completed module is tested (*) and separated by the strip, for example by staggered separation or by punching, and packaged for further use. Fig. 16 is a flow chart showing the assembly process of the multi-package module shown in Fig. 9B, for example. This process is similar to that shown in Figure 15 which has an additional step of inserting the mask over the bottom package flip chip die. In the process 155479. Doc • 72· 201131731 Similar steps are identified by similar reference numbers in the figure. In step 1602, the undivided strips of the bottom package of the die-flip wafer ball grid array are provided. The BGA package may or may not have, and has a first 0 interconnect solder ball. The B G A package of the strip card is preferably tested for performance and reliability prior to its subsequent steps in the process (shown as * in the figure). Only the job is "good" (4) The peasant association accepts the follow-up treatment. In step! 6〇3, the electrical shield is fixed on the "good" bottom B "the grain on the GA package. In step _, the adhesive is distributed on the BGA package." Above. In step Μ%, a separate platform grid array package is provided. The separate lga package is protected by -mold and is preferably tested (*) and identified as "good". In step 16-8, a -selection and placement operation is performed to place the "good =" LGA package on the adhesive over the mask on the "good" BGA package. In step 1610, the adhesive is cured. In step i6i2, at the preliminary step 1614, a plasma cleaning operation is performed in which a line junction z interconnection is formed between the top LGA and the bottom BGA package of the stack. In step 1616, an additional electropolymer cleaning can be performed. The MPM molding is then formed in step 1618. In step 162(), the second-order interconnect solder balls are attached to the bottom side of the module. In step 1622, the completed module is tested (*)&apos; and separated by the material, e.g., separated by (4), and packaged for further use. Figure 17 is not a multi-package mode as shown, for example, in Figure 1A or Figure 10B! And the process of assembly processing 圚. In step (10), an undivided strip of the bottom seal of the upper die wafer wafer grid array is provided. The flip 155479. Doc •73- 201131731 The wafer interconnect is protected by the filling or molding of one side between the die and the die attach surface of the base substrate, so no overmolding is required. The BGA package in the strip is preferably tested for performance and reliability prior to its subsequent steps in the process (shown as * in the figure). Only packages that are identified as "good" will be processed. In step 17〇4, the adhesive is dispensed onto the upper surface of the substrate on a "good" BGA package. In step 1706, a separate second package ' is provided which may be a stacked die package, such as shown in Figures 1-8 and 1-8. The separate second package is protected by a molding 'preferably tested (*) and identified as "good". In step 1708, a selection and placement operation is performed to place a "good" package of adhesive on the substrate on the "good" BGA package. In step 1710, the adhesive is cured. In step 1712, a plasma cleaning operation is performed during preliminary step 1714, wherein a line junction z interconnection is formed between the top of the stack (stacked particles) and the bottom die-flip wafer BGA package. An additional plasma cleaning can be performed in step 1716, followed by formation of the MPM molding in step 1718. In step 172, the second-order interconnect solder balls are attached to the bottom side of the module. In step 1722, the completed module is tested (*) and separated by the strip, for example by sawing apart or by punching, and packaged for further use. Figure 18 is a flow chart showing the assembly process of the multi-package module shown in Fig. 18, for example. In step 1802, an undivided strip of a stacked die ball grid array package is provided. The stacked die BGA package is molded and provides an overlying package surface. The BGA package in the strip is preferably tested for performance and reliability before it is subjected to subsequent steps in the process. Doc •74- 201131731 (shown as * in the figure). Only recognized as "good. In the step orchid, the adhesive is assigned in the "Guanghui meeting - the second part of the continuation,: =: two. In step _, provide one (four) for the stack The die package, such as the second package in the center of the drawing, can be molded, and preferably enters L()' and is identified as "good." In step 18〇8, the = and placement operation is performed to place the "good" second package on the adhesive on the substrate on the "good BGA package." In step (8), the primer is cured. In step 1812, at preliminary step 1814, a "electropolymer cleaning operation is performed in which a line junction z interconnection is formed between the top of the stack (stacked die) and the bottom die-flip wafer BGA package. In step 1816, an additional plasma cleaning can be performed, and then the MPM molding is formed in step 1818. In the step, the second-order interconnect solder balls are attached to the bottom side of the module. The completed module is tested () and separated by the strip, for example by separation or by punching and is packaged for further use. The process according to the invention can be carried out as follows The individual steps of many of the steps are based on the methods described herein, using substantially conventional techniques, but as described herein, 'use of conventionally modified manufacturing facilities. These changes in conventional technology' and conventional manufacturing equipment Amendment The use of the methods described herein to accomplish 'does not require further experimentation. Other specific embodiments are set forth in the following patent claims. [Simplified Schematic Description] Figure 1 is not through a conventional ball grid array Section of the semiconductor package 155479. Doc -75- 201131731 Figure; Figure 2 shows a cross-sectional view of a conventional multi-package module with solder ball z interconnections between stacked ball grid array semiconductor packages; Figure 3 shows the flip through the stack A cross-sectional view of a conventional flip chip multi-package module having solder ball z interconnections between wafer semiconductor packages; FIG. 4 is a view showing a flexible substrate and solder balls z between the stacked semiconductor packages A cross-sectional view of a conventional multi-package module; FIG. 5A shows a specific implementation of a multi-package module having a wire contact z interconnection between a stacked bga and an LGA semiconductor package in accordance with an aspect of the present invention. Figure 5B is a plan view of a bottom BGA substrate having a z-connected dot pad in a configuration suitable for use in the embodiment of the invention illustrated in Figure 5a; Figure 5C is shown in Figure 5C Figure 5A is a plan view of a top LGA substrate having a z-interconnect dot pad configured in a particular embodiment of the invention; Figure 5D is shown with a bga and LGA semiconductor package between the stacked layers according to an aspect of the invention. Multiple interconnections of line contacts A cross-sectional view of a specific embodiment of a module having a heat sink secured to an upper surface of the top package; Figure 5E shows a wire contact z interconnect between the stacked BGA and LGA semiconductor packages A cross-sectional view of a specific embodiment of a multiple package module and having a heat sink according to another aspect of the invention; FIG. 6A illustrates a wire connection between stacked BGA and LGA semiconductor packages by one aspect in accordance with the present invention; A cross-sectional view of another embodiment of a multi-package module interconnected by a point z, wherein the top package has a peripheral molding; 155479. Doc-76-201131731 Figure 6B is a cross-sectional view showing another embodiment of a multi-package module having interconnects with wire bonds z between stacked and ga semiconductor packages in accordance with the present invention. t The top package has a peripheral package and the module has a heat sink; FIG. 7 shows a multiple package with a wire contact z interconnection between the stacked bga and the semiconductor package in accordance with aspects of the present invention. A cross-sectional view of another embodiment of the module in which the top package substrate has a metal layer substrate; FIG. 8A shows a line contact 2 between the stacked bga and LGA semiconductor packages by another aspect in accordance with the present invention. A cross-sectional view of a multi-package module interconnected, in which an electrical shield is provided on the bottom package; FIG. 8B illustrates the presence of a stacked bga between the semiconductor package and the semiconductor package in accordance with an aspect of the present invention. A cross-sectional view of another embodiment of a multi-package module interconnected by a wire contact z, wherein an electrical shield is provided over the bottom package, and the module has a heat sink; According to this issue A cross-sectional view of another embodiment of a multi-package module having a wire bond z interconnect between a stacked BGA and a semiconductor package, wherein an electrical shield is provided over the bottom package and the mode The set has a heat sink 3S fixed to an upper surface of the top package, and FIG. 9A shows a line between the stacked flip chip BGA (lower die) and the LGA semiconductor package by another aspect of the present invention. A cross-sectional view of a multi-package module interconnected by a contact z; 155479. Doc-77·201131731 Figure 9B shows a multi-package module with interconnects z between the stacked flip chip BGA (lower die) and the LGA semiconductor package in accordance with another aspect of the present invention. A cross-sectional view in which an electrical shield is provided on the bottom package; FIG. 9C illustrates a line contact z between the stacked flip chip BGA (lower die) and the LGA semiconductor package by another aspect of the present invention. A cross-sectional view of a multi-package module in which an electrical shield is provided on the bottom package and the module has a heat sink; and FIG. 10A shows a flip chip mounted on the stack by another aspect of the present invention. A cross-sectional view of a multi-package module having a wire contact z interconnect between a BGA (upper die) and a stacked die LGA semiconductor package, wherein adjacent stacked die in the second package is A spacer is separated; FIG. 10B is not a multiple of interconnects having a wire contact z between a stacked flip chip BGA (upper die) and a stacked die LGA semiconductor package in accordance with another aspect of the present invention. a cross-sectional view of the repackaged module, in which The adjacent stacked dies in the second package have different sizes; FIG. 10C shows that there is a flip-chip BGA (upper die) between the stacked flip chip BGA (upper die) and the stacked die LGA semiconductor package according to another aspect of the present invention. A cross-sectional view of a multi-package module interconnected by a wire contact z, and wherein an electrical shield is provided on the bottom package; a totem is shown in a flip-chip BGA (on-chip) stacked in accordance with additional aspects of the present invention a cross-sectional view of a multi-package module having a wire contact z interconnection between the stacked die and the stacked LGA semiconductor package, and wherein - the electric shield is provided on the bottom package and has a fixed on the top The above table 355479. Doc -78- 201131731 One of the heat sinks; Figure 10E shows the synergy of the other side of the invention by the synergistic ten "π force surface in the stacked flip chip BGA (top die) and stacked die LGA A cross-sectional view of a multi-package module having interconnects z-connected between the semiconductor packages, wherein an electrical shield is provided on the bottom package and has a heat sink in accordance with another aspect of the present invention; Shown is a cross-sectional view of a multiple package module having wire bonds 2 interconnected between a stacked BGA (stacked die) and an LGA (stacked die) semiconductor package in accordance with another aspect of the present invention; Shown as a flow chart of, for example, the assembly process shown in FIG. 5A or FIG. 7; FIG. 13 is a flow chart showing an assembly process of a multi-package module, such as shown in FIG. FIG. 14B is a flow chart showing an assembly process of a multiple package module shown in FIG. 8B; FIG. 14B is a flow chart showing an assembly process of a multiple package module shown in FIG. 8B; Figure 14C shows a multiple package such as that shown in Figure 8C. Flowchart of the assembly process of the group; FIG. 15 is a flow chart showing an assembly process of a multi-package module shown in FIG. 9A; FIG. 16 is a diagram showing, for example, a multiple shown in FIG. 9B. Flowchart of the assembly process of the package module; Figure 17 shows a multiple seal 155479, for example, shown in Figure 1A or Figure 1B. Doc 79-201131731 Flowchart of an assembly process for assembling a module; and Figure 18 is a flow chart showing a assembly process of a multi-package module such as that shown in Figure 11. [Main component symbol description] 10 MPM bottom package 12, 22 substrate 13 ' 23 die attach epoxide 14, 24 &gt; • 34, • 44 die 16, 26 wire contacts 17, 27, . 47 Molding compound 18 ' 28, '38, '48 solder ball 20 stacked MPM 30 2-stack flip chip MPM 33 polymer side filled 35 through hole 36 bump 40 2-stack curved flexible substrate MPM 42 metal layer Bottom package substrate 43 Adhesive 46 Cantilever beam 50 &gt; 52, 60, 70, 84 Multi-package module 54, 62, • 82, 94 BGA + LGA multi-package module 155479. Doc -80- 201131731 90, 92, 101, 103 Multiple package modules 105, 107, 109, 110 Multi-package modules 121, 123 Metal layer 122 &gt; 142 Through holes 125, 127, 147 Weld cover 141 First metal layer 143 second metal layer 221 &gt; 223 metal layer 222 via 225 '227 solder mask 300 bottom package 302 bottom BGA package 304 shield 305 sidewall 306 line 312 bottom package substrate 314 die 315 ' 327 solder mask 316 flip chip bump 318 solder ball 321 &gt; 323 metal layer 322 through hole 155479. Doc -81 - 201131731 155479. Doc 331 Metal Layer 332 Substrate 333 Polymer Side Filled 334 Die 335 Through Hole 336 Bump 338 z Interconnect Solder Ball 342 BGA Substrate 343 Interconnect Bump 344 Die 346 Flip Chip Bump 348 Second Order Interconnect Solder ball 351 Metal layer 353 Patterned metal layer 354, 356 Dielectric layer 355 Metal layer 400 Bottom package 401 Void 402 Bottom ball grid array (BGA) package 406 Heat sink / shield 407 Side wall 408 line) C -82- 201131731 412 Bottom package substrate 413 die attach epoxide 414 die 415, 427 cap 416 wire contact 417 molding compound 418 solder ball 419 bottom package upper surface 421 ' 423 metal layer 422 via 424 bottom package z interconnect pad 425 Upper surface 426 upper surface 442 bottom package substrate 443 adhesive 444 '454 die 446, 456 wire contact 447 molding compound 448 solder ball 451, 453 metal layer 452 through hole 455 '457 welding cap - 83 - 155479. Doc 201131731 500 Top Package 501 Void 503 ' 506 Adhesive 505 ' 545 Recessed Feature 507 Module Wrap 511 Trace 512 Top Package Substrate 513 Grain Attachment Epoxide 514 Die 515 Solder Cover 516 Line Contact 517 Molding Compound 518 line contact 519 upper surface 521 metal layer 522 through hole 523 metal layer 524 top package z interconnection pad 525 upper surface 526 edge 527 solder mask 544, 504 heat sink 155479. Doc -84- 201131731 546 Support member 600 Top package 607 Module cover 612 Top package substrate 613 Die attach epoxide 614 Die 615 Solder mask 616 Line contact 617 Mold compound 618 Line contact 621 Metal layer 622 pass Hole 623 Metal Layer 627 Weld Cover 644 Heat Sink 645 Recessed Feature 646 Support Member 700 Top Package 707 Module Cover 712 Top Package Substrate 713 Grain Attachment Epoxide 714 Grain 155479. Doc -85- 201131731 715 Weld Cover 716 Line Contact 717 Molding Compound 718 Line Contact 719 Surface 721 Metal Layer 800 Top Platform Grid Array (LGA) Package 803 Adhesive 804 Heat Sink 805 Recessed Feature 806 Support Member 807 Mode Group cladding 812 top package substrate 813 die attach epoxide 814 die 815, 827 solder mask 817 molding compound 818, 816 wire contact 819 upper surface 821 metal layer 822 through hole 823 metal layer 155479. Doc • 86 - 201131731 844 Heatsink 845 Recessed Features 846 Adhesive 847 Wrapped 900 Top LGA Package 903 Adhesive 907 Module Wrap 908 Line 909 Sidewall 912 Top Package Substrate 913 Grain Attachment Epoxy 914 Die 915 Solder Cover 917 Molding compound 918, 916 wire contact 919 Surface 921 Metal layer 944 Heat sink 945 Recessed feature 946 Support member 1000 Die plate grid array package 1003, 1006 Adhesive 155479. Doc • 87 - 201131731 1004 Heatsink 1005 Recessed features 1007 Module covered 1011 Trace 1012 Dielectric layer 1013 Adhesive 1014 Die 1015 Spacer 1017 Molding material 1018, 1016, 1026 Line contact 1019 Upper surface 1024 crystal Grain 1030 Top Package 1031 Trace 1033 Adhesive 1034 Die 1035 Adhesive 1036 Wire Contact 1037 Molding Material 1039 Upper Surface 1044 Grain 1045 Recessed Feature 155479. Doc -88- 201131731 1046 Line contact 1103 Adhesive 1107 Molded 1118 Line contact 155479. Doc -89-

Claims (1)

201131731 VII. Applying for a patent garden 1. A multi-package package having a second package stacked on the module has an electrical shield. I have at least one of these 2. As in the scope of the patent application, the item has an electric shield. (4) The group, wherein the first package is configured as a heat sink as the multiple package module of the first application of the patent scope. The multi-package module of the first aspect of the invention, wherein the multi-package module of the first aspect of the invention, wherein the shield is as defined in the multi-package mode, the group between the die and the other die Electromagnetic interference. 5. The multi-package module of claim 2, wherein the first seal = a flip chip ball grid array package having a flip chip in the on-die die configuration. 6. The multiple package module of claim i, wherein the first package is a flip chip wafer flip array package having a flip chip in the under-die configuration. 7. The multi-package module of claim 3, wherein the second package is a stacked die package. 8. The multiple package module of claim 7, wherein adjacent stacked die are separated by a spacer in the stacked die package. 9. The multi-package module of claim 2, the first package 3 is a first package substrate, and the second package comprises a second package substrate, wherein the first package substrate comprises an embedded ground plane . 155479.doc 201131731 ίο 1112. 13. 14. 15. 16. 17. The multi-package module configuration as claimed in item 9 of the patent application is used for heat dissipation. The ground plane is as in claim 9 of the patent application. The method is configured to be used as an electric shield for manufacturing a multi-package module including a second stack on top of the first cover. The method includes providing a first package having a mask, providing a second package, stacking the second package to the shielded surface, and generally planarly interconnecting the first and second packages by wire bonding. For example, in the method of claim 12, Α Λ &amp; 沄 沄 沄 提供 提供 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The method of claim 12, wherein stacking the second package onto the upper surface of the shield comprises applying an adhesive onto an upper surface of the shield, and placing the second package to the Above the adhesive. The method of claim U, wherein the adhesive is a curable adhesive, and further comprising curing the adhesive. For example, the method of claim n, wherein the first package 3 is provided for testing the package for an effect and reliability requirement, and selecting the first package satisfies the requirement. The method of claim 12, wherein the second package is provided to test the package for a performance and reliability requirement, and the second package is selected to meet the demand. The method of claim 12, further comprising attaching a second-order interconnecting ball to the first package substrate. 19. The method of claim 12, further comprising cladding the stacked packages in a multi-package module molding. 20. The method of claim 12, wherein the first package is provided to provide a ball grid array package. The method of claim 12, further comprising providing the multi-package module with a heat sink. The method comprises the steps of: providing a heat sink comprising a 5 liter heat sink before forming a module molding. 22, as in claim 21, performing a drop into the mold operation, and placing it into a mold. The method of claim 21, wherein the heat sink comprises a generally planar portion of the heat sink to the second package - generally a planar upper surface. The method of claim 12, wherein the first package is provided for flip chip wafer grid array packaging. 25. The method of claim 12, wherein the method of providing a masked = first package comprises providing a lower die wafer flip-chip array package 26. = please = item, wherein providing - masking a package containing a θ 〃 上 上 上 上 倒 倒 球 球 球 球 球 球 上 上 上 中 上 中 中 中 中 中 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上A flip chip wafer grid array is sealed by a package of 155479.doc 201131731, which includes a patch A 98 , ^ ± ^ which is typically a planar portion over the die. 28. The method of claim 100, wherein a ± 曰f # s , medium ki, ball grid array package having a shadow comprises providing a portion having a shadow - a mask - a generally planar portion Below the grain. 29. A mobile device comprising a multi-package chess set having a second package, and a package is electrically interconnected by a wire, eight to &gt; The package has an electrical shield. 30. A computer comprising a multi-package module having a second package, the material stack package being electrically interconnected by wire bonding, wherein at least one of the packages has an electrical shield. 3 1 'a kind of multi-package module comprising stacked first and second packages & ^ ^ Τ, each of which comprises a day-to-day grain attached to a substrate, wherein the first and the first The second violent pull is interconnected by a wire, and its φ &amp; " ^ first package contains a flip chip in the upper die ··· -i, a clever hair day ball grid array package 0 32 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ^ including the bonding of the second package die and the second package substrate and the die and the wiring in the second package are completely covered by a molding material. The multi-package module of the item, wherein the second package is wrapped around to some extent enough to cover the wire between the die and the substrate. 155479.doc 4- 201131731 35. 36. 37. 39. 40. 41. 42. 43. 44. 45. The multiple package module of claim 32, wherein the second The package substrate is a single metal layer substrate, such as the multiple package module of claim 31, wherein the flip chip package has an electrical shield, such as the multiple package module of claim 36, wherein the electrical shield The multi-package module of claim 31, wherein the flip-chip package comprises an RF die, such as the multi-package module of claim 36, wherein The flip-chip package includes an RF die, and the shielding acts as an electromagnetic interference between the RF die and the other die in the multiple package module, such as the multiple package module of claim 31, wherein The first package has an electrical shield. The multiple package module of claim 31, wherein the second package is a stacked die package, such as the multiple package module of claim 41, wherein In the stacked die package, the adjacent stacked die is separated by a spacer. 'As in the multi-package module of claim 31, the package is stacked in the first The first package substrate includes an embedded ground plane. The multi-package module of claim 31, wherein the first package substrate comprises an embedded ground plane. For example, in the multi-package module of claim 44, the ground plane is configured to be used for heat dissipation. 155479.doc 201131731 46. The multi-package module of claim 44, the ground plane configuration is used 47. The multi-package module of claim 3, wherein at least one of the first and second packages is a stacked die package. 48. The multiple package module of claim 31, wherein the second package is a stacked die package. 9. The multi-package module of Section 31 of the patent application scope further comprises a heat sink. A method of fabricating a multi-package module, comprising: providing - including a first package of a die-flip wafer on a first package substrate, providing a second die including a die and a second package substrate a first package is mounted on the first package, and the first package is connected by a wire connecting the first package substrate and the second package substrate, wherein an upper die is provided The wafer first package includes a die flip chip package for a performance and reliability requirement test, and a package that meets the demand is selected as the first package. 51. The method of claim 5G, wherein the upper-die die-chip is provided with a strip that provides a split-up of the upper die. #对装不一个一第二包包 and selects the method according to the 52. PCT Patent Application No. 5, which provides a package containing the requirements for a performance and reliability, and the package required as the second package. The second package is provided. 53. The method of claim 5, 155479.doc 201131731 includes providing a platform grid array package. 54. The method of claim 5, wherein the stacking the second package comprises a solid surface on the first package. The second package is applied to the first package substrate 55. As disclosed in the patent application No. 54-Hyunwan, the second package is fixed to the surface of the first package substrate, and the adhesive is added to the surface of the first package substrate. Adhesive to the die attach area of the first package surface substrate. The upper package is contacted with 56. The method of claim 55, wherein the applying the adhesive comprises a yoke plus a curable adhesive, as in the scope of claim 5th. The second step involves curing the adhesive. The method of interconnecting the ball onto the first substrate further includes a method of attaching the second step 58.2 of the scope of the patent, the method comprising coating a feature on the first substrate with a molding compound. 59. If the method of claim 51 is applied, the completed module is removed. The 匕6海长条分 further includes providing an electromagnetic further comprising providing a heat sink wherein a heat sink is provided to the 60. The method of claim 5 is masked to the first package. 61. The method is applied to the module as claimed in item 5 of the patent application. 62. The method module of claim 61 of the invention patent scope includes performing a drop-in molding operation in which a heat sink is provided to the 63. The method of claim 61 describes the intrusion and the heat exchanger. The module contains a fixed θ ten-sided political heat onto the surface of the second package above the 155479.doc 201131731. 64. A communication device comprising a multi-package module as claimed in claim 4 (4). 65. A multi-package model comprising the 31st item of the patent application. The multi-package module includes a stacked first and second package, the first package includes a die attached and electrically connected to a first substrate, and the second package includes an attached and electrically connected a die to a second substrate, wherein the first and second substrates are interconnected by wire bonding, wherein the first package comprises a flip chip ball having a flip chip in a lower die configuration The thumb array package, and wherein the segmented whistle and the first package are covered by a package, the module further comprises a second-order interconnection solder ball pad on a lower side of the lower package substrate. 67. The Penang Group is further packaged as on the 66th of the patent application, wherein the second package is a one-wire platform grid array package. 68. The multi-package module of claim 67, wherein the die and the wire bonding in the second package are completely covered by a molding material / 69. The multiple of claim 67 The package module, wherein the second package is wrapped around to some extent, which is sufficient to cover the wire between the die and the substrate. Soil 70. As claimed in the 67th scope of the patent application, the second package substrate is a single metal layer substrate. 71. A package module is also provided as claimed in claim 66, wherein the electrical shield is configured to function as a heat sink. The multi-package module of claim 66, wherein the flip-chip package comprises an RF die. 73. The multiple package module of claim 66, wherein the flip chip package comprises an RF die, and the shielding is limited between the RF die and the other die in the multiple sealing module Electromagnetic interference. 74. The multi-package module of claim 1, wherein the first package has an electrical shield. 75. The multi-package module of claim 66, wherein the second package is a stacked die package. 76. The multi-package module of claim 75, wherein adjacent stacked crystal grains in the stacked die package are separated by a spacer. 77. The multi-package module of claim 66, wherein the second package is stacked on the first package, and wherein the flip chip die on the first package has an electrical shield. 78. The multi-package module of claim 66, wherein the first package substrate comprises an embedded ground plane. For example, the multi-package module of the patent scope of item 78 is configured to be used for heat dissipation. For example, in the multi-package module of claim 78, the ground plane is configured to be used as an electrical shield. 81. The multi-package module of claim 66, wherein at least one of the first and first packages is a stacked die package. 82. The multi-package module of claim ", wherein the second package is a stacked die package. I55479.doc 201131731 83. The multiple package module of claim 66, further comprising a heat A method of manufacturing a multi-package module, comprising: providing a first package comprising a lower die flip chip and a first package substrate, and providing a second package including a wire die; The die is at least as large as the lower die flip chip, and is electrically connected to a second package substrate on both sides, wherein the slap die is encapsulated in a first cladding, and the second package is stacked in the first On the first package, the first and second packages are electrically connected by connecting the two sides of the first package substrate and the second package substrate, and the second package is molded by the second package. Encapsulating the method of claim 84, wherein the first die and the wire are applied, wherein the lower die (four) die-package comprises a supply-lower die flip chip [package separation strip. ·The 84th item The method of 'providing - the lower die flipping' ten-pack contains the die for the performance and reliability requirements test: loading the chip package and selecting the package that meets the demand as the first 87. 7 patent The method of claim 84, wherein the second package spoon and the reliability requirement are provided to test the package, and the selector:: the package of the clothing is used as the second package. 88. The method of claim 84 </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> The second package is over the upper surface of the lower die wafer die. 90. The method of claim 89, wherein the second package is fixed to the upper surface of the lower die wafer die The method of applying an adhesive to the upper surface of the celite and contacting the second package with the adhesive. The method of claim 9, wherein the applying the adhesive comprises a target Additive curable adhesive And the method comprising the method of claim 84, further comprising attaching the second-order interconnecting ball to the first substrate. 93. The method of claim 1, wherein Molding the second cladding to encapsulate the first package includes features that are overcoated on the first substrate with a molding compound. Further comprising the length of the strip 94 as set forth in claim 85 The method further comprises providing an electromagnetic further comprising providing a heat sink 95. The method is masked to the first package as in the scope of the patent application. 96. Module. A method of providing a heat sink to the method of the method of claim 96 includes performing a drop molding operation, wherein a heat sink is provided to the 98. The method of claim 155479.doc The 201131731 module includes a heat sink that is generally planar to the upper surface of the second package. 99. The method of claim 95, wherein providing electromagnetic shielding to the first package comprises solidifying onto the lower die wafer die 0, as claimed in claim 99 The method wherein the second package is stacked over the first package to include a solid (four) second package over the upper surface of the shield. The method of claim 10, wherein the fixing the second package onto the upper surface of the shield comprises applying an adhesive to the upper surface of the shield, and contacting the second package with the adhesive . For example, the method of claim 101, wherein applying the adhesive comprises applying a force to cure the adhesive, and further comprising curing the adhesive. 103. A multi-package module communication device as claimed in claim 66. Said - a multi-package brain containing the scope of claim 66. A multi-package module comprising a stacked lower and upper package, the lower package includes a die attached and electrically connected to the -τ square substrate, and the upper package includes a crystal attached and electrically connected to an upper substrate a grain, wherein: the upper and lower substrates are interconnected by wire bonding, wherein at least one of the germanium packages comprises a -stacked die package and wherein at least one of the stacked crystal cells: is packaged. τ For example, the multi-package module of claim 105, wherein the lower 155479.doc -12-201131731 package comprises a stacked die package. The multiple package module as claimed in claim 10 (wherein each of the (4) lower package and the upper package includes a stacked die package. 108. The method of claim 1 , wherein the upper package comprises a stacked die package. The multi-package module of the patent scope 1G5 is skipped, wherein the adjacent stacked crystal grains in the stacked die package are separated by a spacer. No. As claimed in claim 105, the multi-package module further includes a heat sink on the upper package. The method for manufacturing a multi-package module includes: providing a first package, providing a second package, each package comprising a die attached and electrically connected to the substrate, at least one of the packages comprises a stacked die package, wherein at least the stacked die package is coated, the second package is stacked on the first package, and electrical interconnection is formed between the first package and the second package by wire bonding 〇 · 112. The method of claim 1, wherein providing the package includes - stacking the die package includes testing the stacked die package for the performance and reliability requirements, and identifying the package that meets the requirement as the stack Die package. 113. The method of claim 4, wherein a second package is provided to test the package for the performance and reliability requirements, and to identify the package that meets the requirements of 155479.doc -13·201131731 as the second package . 114. The method of claim 111, wherein the package comprises a strip. The die package includes a method of providing an undivided extended range of item (1) of a stacked die package, wherein providing the package comprises a particle package comprising providing a first to the first substrate to be fixed to the package substrate, - a second die fixed on the first die, and a package of wire bonding between the first and second die and the substrate. 116. The method of claim 115, wherein the package p-stack is provided: the package comprises a package, the package further comprising a spacer interposed between the first and second dies. 117. If the method of claim m is applied, the further step includes the provision of heat. Further comprising the attachment of 118. The method of claim 111, wherein the interconnecting ball is over the first package substrate further comprises cladding the 119. The method of claim </ br> The module in the molding compound is a mobile device comprising a multi-package module as claimed in claim 1 of the patent application. 121. A computer containing a multi-package module such as the patent application 笳圊坌 月 扪 扪 第 第 第 。. 155479.doc