201122691 AU0908099 32903twf.doc/d 六、發明說明： 【發明所屬之技術領域】 本發明是有關於-種陣列基板及其製造方法，且特別 是有關於一種主動元件陣列基板及其製造方法。 【先前技術】 -般而言’液晶顯示面板主要是由—主動元件陣列基 板、-對向基板以及-夾於主動元件陣列基板與對向基板 之間的液晶層所構成，其中主動元件陣列基板可分為顯示 區（display region)與非顯示區（n〇ndisplay regi〇n)，其 中在顯示區上配置有以陣列排列之多個畫素單元，而每二 晝素單元包括薄膜電晶體（TFT)以及與薄膜電晶體連接 之晝素電極（pixel electrode)。此外，在顯示區内配置有 多條掃描線（scanline)與資料線（dataline),每一個晝 素單元之薄膜電晶體是與對應之掃描線與資料線電性^ 接。在非顯示區内則配置有訊號線、源極驅動器（s〇urce driver)以及閘極驅動器（gate driver)。 當液晶顯示面板欲顯示影像晝面時，其必須透過閘極 驅動器來依序開啟顯示面板内的每一列晝素，且每—列書 素在開啟的時間内會對應的接收源極驅動器所提供的資料 。如此一來，每一列晝素中的液晶分子就會依據其所 接收的資料電壓而作適當的排列。 然而’隨著液晶顯示面板的解析度提昇，液晶顯示器 就必須藉由增加閘椏驅動器與源極驅動器的使用數目來配 201122691 AU0908099 32903twf.doc/d 合解析度之提昇，且_極鶴器與源極驅_的使 目增加會讓非顯示區（或稱為邊框)之面積變大。基於上逑 理由，液晶顯示器之生產成本便隨著閘極驅動^源極^ 二 ==增加’同時邊框也越來越大。若能將間 極驅動裔及/或源極驅動器的使用數目減少，便可輕易地 決成本紐降低的_以及做Μ雜，即麵示 击办，丨、今立σ、 〜Τ貝201122691 AU0908099 32903twf.doc/d VI. Description of the Invention: TECHNICAL FIELD The present invention relates to an array substrate and a method of fabricating the same, and more particularly to an active device array substrate and a method of fabricating the same. [Prior Art] Generally, a liquid crystal display panel is mainly composed of an active device array substrate, an opposite substrate, and a liquid crystal layer sandwiched between an active device array substrate and a counter substrate, wherein the active device array substrate It can be divided into a display region and a non-display region (n〇ndisplay regi〇n), wherein a plurality of pixel units arranged in an array are arranged on the display region, and each of the dioxad cells includes a thin film transistor ( TFT) and a pixel electrode connected to the thin film transistor. In addition, a plurality of scan lines and data lines are arranged in the display area, and the thin film transistors of each of the pixel units are electrically connected to the corresponding scan lines and data lines. In the non-display area, a signal line, a source driver (s〇urce driver), and a gate driver are disposed. When the liquid crystal display panel is to display the image surface, it must sequentially open each column of the display panel through the gate driver, and each column of the pixel will be provided by the corresponding receiving source driver during the opening time. data of. In this way, the liquid crystal molecules in each column of halogens are properly arranged according to the data voltage they receive. However, as the resolution of the liquid crystal display panel increases, the liquid crystal display must be equipped with an increase in the resolution of the 201122691 AU0908099 32903twf.doc/d by increasing the number of use of the gate driver and the source driver, and the _ pole crane and The increase in the source drive _ will increase the area of the non-display area (or the border). For the reason of the captain, the production cost of the liquid crystal display increases with the gate drive ^ source ^ 2 == while the frame is also larger. If you can reduce the number of uses of the driver and/or source driver, you can easily reduce the cost of the button and make it noisy, that is, face-to-face, 丨, 今立σ, ~Τ
【發明内容】 本發明提供—種絲元件_基板，其透過介電層的 =十可大幅降低資料線與共通線之間的寄生電容(ρ咖咖 Capacitance ^ 〇 本發明還提供-種主動元件_基板的製造方法，並 共通線亦可作為反射層，可有效齡製程步驟。 ' 本發明提出-種主動元件陣列基板，其包括一 多條掃描線、多條資料線、多個 : 傳遞線、一介電層、一丘土甬娩，、，夕知谉枯h旒 配置於从卜Μ,線—電谷介電層。掃描線 定:=置於基板上，並與掃描線交錯以 ，義出夕個顯不區域。顯示單元配置於顯示 =衫分職其中二條掃描線以及資^ ，。每-顯示單元包括-第-子晝素以== 素°第「子晝素包括-第-主動元件以及— 旦 件電性連接之帛—錄餘。帛二子纟素包^ ^ 兀:二及:與第二主動元件電性連接之第二畫素電極。^ 一主動兀件以及第二主動元件分別與不同掃描線電^ 201122691 ΑΌ0908099 32903twf.d〇c/d 第的資料線電 與不同τ電性連接二; 主動元件以及第二主動元件，且第 =一： 電極配置於㈣層上。共通線配置於第::畫素電二^ 層ϋ及第—晝素電極與介電層之間。電容介電層配置 =了旦素電極與共猶謂以及第二晝素電極與二通線 在本發明之一實施例令’上述之播 質上垂直於資料線的延伸方向。田、——延方向貝 在本發明之一實施例中，上述之射 量少於或等於資料_數量。 。唬傳遞線的數 在本發明之一實施例+，上述之 分別位於相鄰二資料線之間。 域傳遞線 在本發明之一實施例中，上述之掃 伸方向與資料線的延伸方向實質上平行。田u傳遞線的延 在本發明之一實施例中，上述之每〜 包括一第一導電圖案以及―第：導電圖戒傳遞線 與第-導電圖案電性連接，其中第二導導電圖案 錯。 策圖案與掃描線交 在本發明之實施例中，上述之介 微米（//m)至4微米（从m)之間。日、厚度介於1.5 在本發明之一實施例中，上述之介 (bumps) ’而共通線覆蓋於凸塊±。 3具有多個凸塊 201122691 AUU9U8099 32903twf.doc/d 射材^本發狀—實施射，上述之共通線之材料包括反 傳遞狀實奴’上述之共通線位於掃描信號 在本發明之一實施例巾，μ 二畫素電極分顺共轉部分重錄電極以及第 包括之口=义之主動元件陣列基板更 動元件以及黛- 士、1保4層覆盒掃描線、資料線、第一主 接觸。 一動70件，且保護層與介電層的一底表面 包括t明還提出—種主動元件陣列基板的製造方法，其 3:ί之f;驟。首先’於-基板上形成多條掃描線、多 動元件以及多條掃描信號傳遞線。接著， 梅仲偉以覆*掃描線、資料線、线$件以及掃 電容介^ 成一電容介電層。最後，於介電層以及 迤| ㈢上形成多個晝素電極，其中每一晝素電極分別 /、/、中一個主動元件電性連接。 一 動元發，之一實施例中，上述之掃描線、資料線、主 被上幵二„信號傳遞線的製造方法包括：首先’於基 第—、^雷夕條掃描線、多個與掃描線電性連接的閘極以及 婦·^、圖案。接著，於基板上形成一閘絕緣廣’以覆蓋 多導閘極以及第一導電圖案。然後，閘絕緣層上形成 多個盘次？圖案。最後’於閘絕緣層上形成多條資料線、 /、_貝；斗線電性連接的源極、多個汲極以及〆與第一導 201122691 AU0W^9 32903twf.doc/d 電圖案電性連接之第二導電圖案， 圖案構成掃描信號傳遞線。 电 製造= 月，上述之主動元件陣列基板的 ϊ蓋資㈣=域〃電層之喊形成—賴層，以 t 科線、主動兀·件以及掃描信號傳遞線。 作乎f本伽之—實_巾，上软介電相厚度介於L5 楗未（em)至4微米（仁m)之間。 =發„實施例中，上述之主動元件陣列基板的 ^^介電層之—頂表面上形成多個凸塊 基於上述，本發明之主動元件陣列基板的設計是採用 ^射材質的共通線，因此共通線亦可視為_反射層，可減 >、=私步驟以及降低生產成本。另外，本實施例之介電層 的:汁可增加共通線與資料線之間的距離，以達到減少寄 生电=的電各值。再者，由於本發明之主動元件陣列基板 具有旎夠與晝素電極耦合成儲存電容器的共通線，因此有 助於提高儲存電容的電容值。 〜為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 【實施方式】 圖1A為本發明之一實施例之一種主動元件陣列基板 的俯視不意圖。圖1B為沿圖1A之線w的剖面示意圖。 圖1C為沿圖1A之線π-ll的剖面示意圖。圖id為沿圖 201122691 AU0908099 32903twf.doc/d 1A之線ΙΠ-ΙΙΙ的剖面示意圖。請先參考圖1A與圖1B，本 實施例之主動元件陣列基板100包括一基板11〇、多條掃 描線120、多條資料線130、多個顯示單元140、多條掃描 信號傳遞線150、一介電層160、一共通線170以及一電容 介電層180。SUMMARY OF THE INVENTION The present invention provides a seed element _ substrate, which can reduce the parasitic capacitance between the data line and the common line through the dielectric layer = (the invention also provides an active element) _ The manufacturing method of the substrate, and the common line can also be used as a reflective layer, which can be an effective process step. The invention proposes an active device array substrate comprising a plurality of scanning lines, a plurality of data lines, and a plurality of: transmission lines , a dielectric layer, a hilly soil, and, in the future, the 谉 谉 旒 旒 旒 旒 旒 旒 Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ The display unit is configured in the display = shirt divided into two scan lines and the resources ^. Each display unit includes - the first - sub-success to == prime ° "the child element includes - The first active component and the electrical connection of the electrical component are recorded. The second component is a second pixel element electrically connected to the second active component. The second active component is respectively connected to different scanning lines ^ 201122691 ΑΌ0908099 32903twf.d The first data line of the c/d is electrically connected to the different τ; the active component and the second active component, and the first one: the electrode is disposed on the (four) layer. The common line is disposed on the :: pixel power layer ϋ And between the first-dielectric electrode and the dielectric layer. The capacitance dielectric layer configuration = the denier electrode and the common layer and the second halogen electrode and the two-way line are in the embodiment of the present invention. The direction perpendicular to the extending direction of the data line. Field, extending direction, in one embodiment of the present invention, the above-mentioned amount of radiation is less than or equal to the data_number. The number of the 唬 transmission line is an embodiment of the present invention. +, the above is located between the adjacent two data lines. The domain transmission line is an embodiment of the present invention, wherein the swept direction is substantially parallel to the extending direction of the data line. The extension of the field transfer line is in the present invention. In one embodiment, each of the above includes a first conductive pattern and a “first: conductive pattern or a transfer line electrically connected to the first conductive pattern, wherein the second conductive pattern is misaligned with the scan line. In an embodiment of the invention, the above-mentioned micron (//m) to Between 4 micrometers (from m), the thickness of the day is 1.5. In one embodiment of the invention, the above-mentioned bumps 'and the common line cover the bumps ±. 3 has a plurality of bumps 201122691 AUU9U8099 32903twf. Doc/d 射 ^ 本 本 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 本 本 μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ d d d Transfer part of the re-recording electrode and the included port = the active component array substrate moving element and the 黛-士, 1保 4 layer over-package scanning line, data line, first main contact. One move 70 pieces, and the protective layer and the medium A bottom surface of the electric layer includes a method for manufacturing an active device array substrate, which is 3: ί; First, a plurality of scanning lines, a multi-motion element, and a plurality of scanning signal transmission lines are formed on the substrate. Next, Mei Zhongwei forms a capacitor dielectric layer by covering the * scan line, data line, line piece and sweep capacitor. Finally, a plurality of halogen electrodes are formed on the dielectric layer and 迤|(3), wherein each of the halogen electrodes is electrically connected to /, /, one of the active elements. In one embodiment, the above-mentioned scanning line, data line, and main 被2 „signal transmission line manufacturing method include: firstly, the first base, the ^ ray scan line, multiple scans a gate electrically connected to the gate and a pattern, and then a gate insulating layer is formed on the substrate to cover the plurality of gates and the first conductive pattern. Then, a plurality of patterns are formed on the gate insulating layer. Finally, a plurality of data lines, /, _ shells are formed on the gate insulating layer; the source of the bucket line is electrically connected, a plurality of drains, and the first guide 201122691 AU0W^9 32903twf.doc/d The second conductive pattern of the connection, the pattern constitutes the scanning signal transmission line. Electrical manufacturing = month, the above-mentioned active device array substrate (4) = domain shunting layer formation - the layer, the t line, the active 兀The piece and the scanning signal transmission line. The thickness of the upper soft dielectric phase is between L5 楗 not (em) and 4 micrometers (min m). Forming a plurality of bumps on the top surface of the dielectric layer of the active device array substrate To the above, the active matrix substrate designs of the present invention is the use of a common line ^ shot material, and therefore can be regarded as common lines _ reflective layer, a Save >, = private step and reduce the production cost. In addition, the juice of the dielectric layer of this embodiment can increase the distance between the common line and the data line to achieve a reduction in the electrical value of the paraelectric power. Furthermore, since the active device array substrate of the present invention has a common line which is coupled with the halogen electrode to form a storage capacitor, it contributes to an increase in the capacitance value of the storage capacitor. The above described features and advantages of the present invention will become more apparent from the following detailed description of the embodiments. [Embodiment] FIG. 1A is a plan view of an active device array substrate according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view taken along line w of Fig. 1A. 1C is a schematic cross-sectional view taken along line π-ll of FIG. 1A. Figure id is a schematic cross-sectional view of the line ΙΠ-ΙΙΙ along the line 201122691 AU0908099 32903twf.doc/d 1A. Referring to FIG. 1A and FIG. 1B , the active device array substrate 100 of the present embodiment includes a substrate 11 , a plurality of scan lines 120 , a plurality of data lines 130 , a plurality of display units 140 , and a plurality of scan signal transmission lines 150 . A dielectric layer 160, a common line 170, and a capacitor dielectric layer 180.
詳細來說，掃描線12〇以及資料線丨3〇皆配置於基板 110上，其中掃描線12〇的延伸方向實質上垂直於資料線 130的延伸方向。在本實施例中，資料線13〇與掃描線12〇 交錯以定義出多個顯示區域R，而顯示單元14〇配置於顯 示區域R中。特別是，在本實施例中，每一顯示單元14〇 为別與其中二條掃描線12〇以及其中一條資料線13〇電性 連接。每一顯示單元140包括一第一子晝素14加以及一第 二子畫素140b。第-子畫素M〇a包括一第—主動元件购 以及一與第一主動元件142a電性連接之第一晝素電極 144a第—子晝素i4〇b包括-第二主動元件142b以及- 與第二主動元件142b電性連接之第二晝素電極14牝。其 中，請同時參考® 1八與圖lc，本實施例之主動元件142 曰(包括第-絲元件l42a以及第二絲元件咖）例如 是由閘極G'閘絕緣層GI、半導體_ 143、歐姆接觸層 145、源極S以及汲極〇所組成之薄膜電晶體（了印。 進-步而言，本實施例之第—主動元件咖以及第 一主動7L件142b分別與不同掃描線12〇電性連接，而第二 透過帛—主動I件仙與對應的資料線 13〇電性連接。於其它實施例中，第一主動元件脸透過 201122691 AU0908099 32903twf.doc/d 第二主動元件142a與對應的資料線13〇電性連接。換言 之，在本實施例之主動元件陣列基板100中，並非所有白°勺 主動元件142都會與資料線130 t性連接。當然，在其他 可行之實施例中，各主動元件142亦可分別與對應之資料 線130電性連接。此外，在同—列之顯示單元14〇中，二 相鄰之顯示單元140分別與不同資料線][3〇電性連接。 簡言之’本實施例之主動元件陣列基板1〇〇的設計是 使兩相鄰的第一子晝素140a與第二子晝素14〇b與同一條 資料線130電性連接’因而得以使所需之資料線go的數 目減半’進而減少源極驅動器（未繪示）的使用數量。此 處’所述之畫素結構的設計即為所謂的半源極驅動（Haif Source Driving，HSD)架構。 請再同時參考圖1A與圖IB，在本實施例中，每一掃 描信號傳遞線150分別與其中一條掃描線120電性連接。 詳細而言，本實施例之每一掃描信號傳遞線15〇分別位於 相鄰二資料線130之間，且掃描信號傳遞線150的延伸方 向與資料線130的延伸方向實質上平行。換言之，本實施 例之掃描信號傳遞線150的設計可有效減少掃描線120末 端之扇出線路（fan-outtrace)的數量。此處所述之掃描信 號傳遞線150的設計即為一種於晝素上沿閘極線（Tracking Gate-line in Pixel, TGP )的佈線架構。 更進一步來說，本.實施例之每一掃描信號傳遞線150 包括一第一導電圖案152以及一第二導電圖案154 ’而第 一導電圖案152是於製作掃描線120時同時形成’第二導 201122691In detail, the scan line 12A and the data line 丨3〇 are disposed on the substrate 110, wherein the extending direction of the scan line 12〇 is substantially perpendicular to the extending direction of the data line 130. In the present embodiment, the data lines 13A are interleaved with the scanning lines 12A to define a plurality of display areas R, and the display unit 14A is disposed in the display area R. In particular, in this embodiment, each display unit 14A is electrically connected to two of the scan lines 12A and one of the data lines 13A. Each display unit 140 includes a first sub-pixel 14 plus a second sub-pixel 140b. The first sub-pixel M〇a includes a first active element and a first halogen electrode 144a electrically connected to the first active element 142a, the first sub-element I4〇b includes a second active element 142b and The second halogen electrode 14 is electrically connected to the second active element 142b. In the meantime, please refer to both the 1800 and the lc. The active device 142 本 (including the first wire element l42a and the second wire component) of the present embodiment is, for example, a gate G' gate insulating layer GI, a semiconductor _ 143, A thin film transistor composed of an ohmic contact layer 145, a source S, and a drain electrode (printing. In the first step, the first active device and the first active 7L member 142b are respectively associated with different scanning lines 12 The second active device is electrically connected to the corresponding data line 13A. In other embodiments, the first active device face transmits through the 201122691 AU0908099 32903twf.doc/d second active component 142a. In the active device array substrate 100 of the present embodiment, not all of the active devices 142 are connected to the data line 130 t. Of course, in other feasible embodiments, The active elements 142 can also be electrically connected to the corresponding data lines 130. In addition, in the same column display unit 14, the two adjacent display units 140 are respectively connected to different data lines. Connected. In short' The active device array substrate 1 of the embodiment is designed to electrically connect two adjacent first sub-stimuli 140a and the second sub-salectin 14〇b to the same data line 130. The number of lines go is halved' to reduce the number of source drivers (not shown). The design of the pixel structure described here is the so-called Haif Source Driving (HSD) architecture. Referring to FIG. 1A and FIG. 1B simultaneously, in the embodiment, each of the scan signal transmission lines 150 is electrically connected to one of the scan lines 120. In detail, each scan signal transmission line 15 of the embodiment is respectively Located between the adjacent two data lines 130, the extending direction of the scanning signal transmission line 150 is substantially parallel to the extending direction of the data line 130. In other words, the design of the scanning signal transmission line 150 of the present embodiment can effectively reduce the end of the scanning line 120. The number of fan-out traces. The design of the scan signal transmission line 150 described herein is a wiring structure of a Tracking Gate-line in Pixel (TPP). Enter one , The present. Each embodiment of the scanning signal transmission line embodiment 150 comprises a first conductive pattern 152 and a second conductive pattern 154 'and the first conductive pattern 152 is formed at the same time the production of the scanning line 120' of the second guide 201 122 691
Auuyu8099 32903twf.doc/d 電圖案154是於製作資料、線13〇時同時形成。第 案154與第一導電圖案152電性連接，其 Μ與掃_12〇交錯’意即第二導電圖案 線120。換δ之，本貫施例之每―掃描信號傳遞線⑼分 別與其中-條掃描線12G電性連接，而與其他條掃描線⑽ 電性絕緣。值得-提的是’掃描信號傳遞線15()的數 少於或等於資料線130的數量’在此並不加以限制。Auuyu8099 32903twf.doc/d The electric pattern 154 is formed simultaneously when the material is produced and the line is 13 inches. The first 154 is electrically connected to the first conductive pattern 152, and the Μ and 扫12〇 are interlaced, that is, the second conductive pattern line 120. For the δ, each of the scanning signal transmission lines (9) of the present embodiment is electrically connected to the scanning line 12G, and is electrically insulated from the other scanning lines (10). It is worth mentioning that the number of scanning signal transmission lines 15() is less than or equal to the number of data lines 130' is not limited herein.
請再同時參考圖1A與圖1C，本實施例之介電層16〇 覆蓋抑私線120、>料線130、主動元件m2 (包括第—主 動元件142a以及第二主動元件142b)，且晝素電極144 (包括第一晝素電極144a與第二晝素電極144b)配置於 介電層160上。特別是，在本實施例中，介電層16〇的厚 度例如是介於約1.5微米（/zm)至約4微米（#m)之間。 此外’介電層160具有多個凸塊162 ’而這些凸塊162例 如是形成於介電層160上的表面微結構。 請同時參考圖1A、圖1B與圖10，共通線170配置 於第一晝素電極丨44&與介電層160之間以及第二晝素電極 144b與介電層160之間。其中’本實施例之共通線170例 如為一環形共通線（Comm〇n-ring) ’且與掃描線12〇以 及資料線130分屬於不同膜層。特別是’本實施例之共通 線170位於掃描信號傳遞線150上方’且共通線no覆蓋 於凸塊162上。第，晝素電極144a以及第二晝素電極144b 分別與共通線170部分重疊’且共通線170之材料例如是 反射材料。 11 201122691 AU0908099 32903twf.doc/d 在本實施例中，由於主動元件陣列基板丨〇〇的設計是 採用反射材質的共通線170，因此此共通線17〇亦可視為 一反射層。值得一提的是，在本實施例中，設置有共通線 170的位置可視為一反射區，例如是共通線17〇與畫素電 極144所重疊的區域，而未設置有共通線17〇的位置可視 為一穿透區，例如是晝素電極144未與共通線170重疊的 區域。換言之，每一子晝素（例如是第一子畫素14〇a或第 二子晝素140b)可同時具有穿透區與反射區。因此，當本 實施例之主動元件陣列基板100搭配一對向基板（未繪示） 與一液θβ層（未繪示）而構成一顯示面板（未繪示）時， 此顯示面板可同時具有反射光線與使光源穿透的功能，此 即為一種半穿透半反射式顯示面板（Transflective LCD, TR-LCD)。再者，由於本實施例之介電層16〇的厚度例 如是介於約1.5微米（㈣至約4微米（"m)之間，因 此可增加共通線17G與資料線13()之_距離，可達到減 /共通線17G與貝料線13〇之_電容所造成的電源消耗 (power consumption) ° 值得-提的是，本發明並不限定共通線17〇的形態， 雖然此處所提及的共通線17G具魏為環形共通線，且部 ，共通線170位於㈣線請的上方，但於其他未繪示的 貫施例中，共通線17G亦可為條狀、L型、u型、Η型或 可降料料m _躲(:歸線及掃 描線)之_電讀造成的電源消耗；或者 可不配置於眺線13〇的上方，以❹共· m與資二 12 201122691 Αυυνυ8099 32903twf.doc/dReferring to FIG. 1A and FIG. 1C simultaneously, the dielectric layer 16 of the present embodiment covers the private line 120, the feed line 130, the active element m2 (including the first active element 142a and the second active element 142b), and The halogen electrode 144 (including the first halogen electrode 144a and the second halogen electrode 144b) is disposed on the dielectric layer 160. In particular, in the present embodiment, the thickness of the dielectric layer 16 is, for example, between about 1.5 micrometers (/zm) and about 4 micrometers (#m). Further, the dielectric layer 160 has a plurality of bumps 162' which are, for example, surface microstructures formed on the dielectric layer 160. Referring to FIG. 1A, FIG. 1B and FIG. 10 simultaneously, the common line 170 is disposed between the first halogen electrode 丨44& and the dielectric layer 160 and between the second halogen electrode 144b and the dielectric layer 160. The common line 170 of the present embodiment is, for example, a ring-shaped common line (Comm〇n-ring) and belongs to different film layers from the scan line 12A and the data line 130. Specifically, the common line 170 of the present embodiment is located above the scanning signal transmission line 150 and the common line no is overlaid on the bump 162. First, the halogen element electrode 144a and the second halogen element electrode 144b are partially overlapped with the common line 170, respectively, and the material of the common line 170 is, for example, a reflective material. 11 201122691 AU0908099 32903twf.doc/d In this embodiment, since the active device array substrate 丨〇〇 is designed to use the common line 170 of the reflective material, the common line 17 can also be regarded as a reflective layer. It should be noted that, in this embodiment, the position where the common line 170 is disposed can be regarded as a reflective area, for example, a region where the common line 17〇 overlaps with the pixel electrode 144, and a common line 17〇 is not disposed. The position can be regarded as a penetration area, for example, a region where the halogen electrode 144 does not overlap the common line 170. In other words, each sub-tendin (e.g., the first sub-pixel 14a or the second sub-stimulus 140b) can have both a transmissive region and a reflective region. Therefore, when the active device array substrate 100 of the present embodiment is combined with a pair of substrates (not shown) and a liquid θβ layer (not shown) to form a display panel (not shown), the display panel can have both The function of reflecting light and penetrating the light source is a transflective display panel (TR-LCD). Furthermore, since the thickness of the dielectric layer 16A of the present embodiment is, for example, between about 1.5 micrometers ((4) to about 4 micrometers ("m), the common line 17G and the data line 13() can be increased. The distance can reach the power consumption caused by the capacitance of the subtraction/common line 17G and the bead line 13〇. It is worth mentioning that the present invention does not limit the form of the common line 17〇, although here The common line 17G mentioned is a ring-shaped common line, and the common line 170 is located above the (four) line. However, in other embodiments not shown, the common line 17G may also be strip-shaped, L-shaped, u type, Η type or fallable material m _ hiding (: return line and scan line) _ electric power consumption caused by electric reading; or may not be placed above the 眺 line 13 ,, to ❹ · m and 资二12 201122691 Αυυνυ8099 32903twf.doc/d
線130之間的電容所造成的電源消耗；或者，共通線π〇 延伸至部分第一晝素電極144a與部分第二晝素電極144b 的正下方’以增加半穿透半反射式顯不面板之反射區的面 積’同時亦可提高晝素電極144與共通線HO之間的儲存 電谷的電谷值’且亦不會造成開口率的損失。簡言之，共 通線170的形態可以依據不同的使用需求而有多種變化， 而圖1A所繪示的共通線no的結構設計僅是用以舉例說 明’以讓此領域具有通常知識者能夠據以實施本發明，然 其並非用以限定本發明所欲涵蓋之範_。 請同時參考圖1A與圖1D，在本實施例中，電容介電 層180配置於第一晝素電極14如與共通線17〇之間以及第 二晝素電極144b與共通線no之間。其中，晝素電極144 (包括第-晝素電極144a以及第二晝素電極可與 ^通線17G搞合成—儲存電容器⑶，有助於提高儲存電 容的電容值。 瞌請再參相1人與® 1C，本實施例之主動元件 射—保護層m，其中保護層190覆蓋 及第17。、主動元件142(包括第-主動元 μ 16〇 —動70件142b)，且保護層190與介電 觸:值得-提的是，在本_ ^ 中接^貝穿保護層190的接觸窗164，苴 中接^⑹暴露出主動元件】 朽 :。透過捿觸窗164直接與主動元件142的二J二 201122691 AU0908099 32903 twf.doc/d 簡5之，由於本實施例是採用半源極驅動（hsd)的 畫素架構搭配掃描信號傳遞線15〇的設計（即TGP的佈緩 架構）’因此’可有效減少資料線13〇的使用數量以及有 效減少掃描線120末端之扇出線路（fan 〇uttrace)的數量， 故可以輕易地達成窄邊界以及無邊界之設計需求。此外， 本貫施例之介電層160的設計可增加共通線17〇與資料線 130之間的距離，可達到減少共通線17〇與資料線13〇之 間的電容所造成的電源消耗。再者，由於本實施例之主動 元件陣列基板1〇〇具有能夠與畫素電極144耦合成儲存-電 容器的共通線170,因此有助於提高儲存電容的電容值。 以上僅介紹本發明之主動元件陣列基板1〇〇的結構， 並未介紹本發明之主動元件陣列基板1〇〇的製造方法。對 此，以下將以圖1A中的主動元件陣列基板1〇〇作為舉例 說明，並配合圖2A至圖2F對本發明的主動元件陣列基板 的製造方法進行詳細的說明。 土 圖2A至圖2F為本發明之一實施例之一種主動元件陣 列基板的製造方法的流程示意圖。依照本實施例之主動元 件陣列基板的製造方法’請同時參考圖1A與圖2A，先於 基板110上形成多條掃描線120、多條資料線多個 主動元件142以及多條掃描信號傳遞線15〇。其中， 線⑽、資料線130、主動元件142卩及掃描;^號傳^ 150的製造方法包括下述步驟：首先，於基板ιι〇上^ 多條掃描線120、多個與掃描線120電性連接的間極^ = 及第-導電圖案152。也就是說，第〜導電圖帛152是^ 201122691 Auuyu8099 32903twf.doc/d 製作掃描線.120時同時形成。接著，於基板n〇上形成、 閘絕緣層GI，以覆蓋掃描線120、閘極G以及第一導電 案 152。 ^ 然後’閘絕緣層GI上形成多個半導體圖案m3以及 位於半導體圖案143上方的歐姆接觸層145。最後，於間 絕緣層GI上形成多條資料線130、多個與資料線13〇電忮 連接的源極S、多個汲極D以及一與第—導電圖案152電 性連接之第二導電圖案154。也就是說，第二導電圖案15斗 是於製作資料線130時同時形成。特別是，在本實施例中， 閘極G、半導體圖案丨43、源極S以及汲極D構成主動元 件142，而第一導電圖案152與第二導電圖案⑼構 描信號傳遞線150。 接著，請參考圖2B，形成一保護層19〇，以覆蓋資 、，130 (請參考’ 1A)、主動元件142以及掃描信號 線 150。 ^ 接著，請參考圖2C，形成一介電層16〇，以 =12〇、資料、線130、主動元件142以及掃描信號“ 。在本實施例中，介電層160的厚度例如是介於約15 微米（//m)至約4微米（#„!)之間，且介電層16〇之 :頂表面上形成有多個凸塊162,其中這些凸塊日162例如 疋形成於介電層160上的表面微結構。再者，本實施例之 介電層160具有至少一貫穿保護層190的接觸窗'二，'= 中接觸窗164暴露出主動元件142的汲極D。其中介電^ 160可為單層或多層結構，而其材料包含有機材料(例如^ 光阻、苯並環丁烯(enzocyclobutane，BCB)、環烯類、聚醯 15 201122691 AU0908099 32903twf.doc/d 亞胺類、聚醯胺類、聚酯類、聚酸 笨類、樹脂類、聚醚類、聚酮f 乙烧類 '聚 述之組合)、無機材料(例如：氮化石，二:口適材料、或上 其它合適的材料、或上述之組合）亂氧化石夕、 述之組合。 其匕合適的材料、或上 成一時it圖1A與圖2D’於介電層160上形 成A、.表170’其中共通線17〇例如為一環形丘通 n.g)。特別是，本實施例之共通線Μ是位 於知描^傳遞線15G上方，且共通線m覆蓋於凸塊162 上。此外，共通線no可為單層或多層結構，其材料例如 是反射材料，舉例而言，金、銀、銅、m鶴、 翻、、上述之合金、上述的氧化物、上述的氮化物、立它 合適的化合物、其它合適的材料、或上述之組合。 、由於本實施例是採用反射材質的共通線17°0 ,因此此 共通線170亦可視為一反射層。故’本實施例可省略習知 製作反射層的製程步驟，可有效降低生產成本。 值得一提的是，在本實施例中，設置有共通線17〇的 位置可視為一反射區，而未設置有共通線17〇的位置可視 為一穿透區。再者，由於本實施例之介電層16〇的厚度例 如是介於約1.5微米（Mm)至約4微米（Mm)之間，因 此可增加共通線170與資料線130之間的距離，可達到減 少電容值與電源消耗的效果。 / 然後，請參考圖2E，於共通線170以及介電；16〇 上形成-電容介電層1δ〇。 蹲 最後，請參2F，於介電層160以及電容介電層18〇 16 201122691 Λυυ^υδ〇99 32903twf.doc/d 上形成多個晝素電極144，其中每一畫素電極144分 過接觸窗164直接與其中一個主動元件142的汲極〇電= 連接。特別是，在本實施例中，畫素電極144可與共^線 Π0耦合成一儲存電容器Cst’有助於提高儲存電容的電>容 值。至此，已完成主動元件陣列基板100的製作。 谷 綜上所述，由於本發明是採用半源極驅動（hsd) ς素架構搭配掃描信號傳遞線的設計（即TGp的佈加 掃㈣^此’可有效減少資料線的使用數量以及有效減少 易出線路(fan韻trace)的數量，故可以輕 主動達t邊界以及無邊界之設計需求。此外，本發明之 政反的設計是採用反射材質的共通線，因此 ==視反射層’可減少製程步驟以及降低= 轉，可_減少共通線 電= 造成的電源消耗。另冰山#丄々 夺所 具有能夠與畫素電極•合列基板 助於提高料電容的^=齡W的共祕，因此有 本發施例減如上，财並非用以限定 本發明之精神和範_領=具有通f知識者’在不脫離 發明之保護範圍當視後附:=1:= 【圖式簡單說明】 圖1A為本發明之一實施例之一種主動元件陣列基板 17 201122691 AU090S〇y9 32903twf.doc/d 的俯視示意圖。 圖1B為沿圖1A之線I-Ι的剖面示意圖。 圖1C為沿圖1A之線II-II的剖面不意圖。 圖1D為沿圖1A之線III-III的剖面示意圖。 圖2A至圖2F為本發明之一實施例之一種主動元件陣 列基板的製造方法的流程示意圖。 【主要元件符號說明】 100 :主動元件陣列基板 110 :基板 120 ·掃描線 130:資料線 140 :顯示單元 140a :第一子晝素 140b :第二子晝素 142 :主動元件 142a :第一主動元件 142b :第二主動元件 143 :半導體圖案 144 :晝素電極 144a :第一晝素電極 144b :第二晝素電極 145 :歐姆接觸層 150 :掃描信號傳遞線 201122691 AU0908099 32903twf.doc/d 152 第一導電 圖 案 154 第二導電 圖 案 160 介電層 162 凸塊 164 接觸窗 170 共通線 180 電容介電 層 190 保護層 Cst 儲存電容 器 D ： 及極 G : 間極 GI ： 閘絕緣層 R :顯示區域 S :源極The power consumption caused by the capacitance between the lines 130; or the common line π 〇 extends to directly below the portion of the first halogen element 144a and the portion of the second halogen element 144b to increase the transflective display panel The area of the reflection zone can also increase the electric valley value of the storage valley between the halogen electrode 144 and the common line HO and also does not cause loss of aperture ratio. In short, the form of the common line 170 can be varied according to different usage requirements, and the structural design of the common line no shown in FIG. 1A is only used to illustrate 'to enable the general knowledge in this field to be The invention is not intended to limit the scope of the invention as intended. Referring to FIG. 1A and FIG. 1D simultaneously, in the present embodiment, the capacitor dielectric layer 180 is disposed between the first halogen electrode 14 and the common line 17A and between the second halogen electrode 144b and the common line no. Wherein, the halogen electrode 144 (including the first-germanium electrode 144a and the second halogen electrode can be combined with the power line 17G) to store the capacitor (3), which helps to increase the capacitance of the storage capacitor. With the ® 1C, the active device of the present embodiment - the protective layer m, wherein the protective layer 190 covers and the 17th, the active device 142 (including the first-active element μ 16 - 70 70b), and the protective layer 190 and Dielectric touch: It is worth mentioning that, in this _ ^, the contact window 164 of the protective layer 190 is connected, and the active component is exposed by the ^(6) in the 】 ^ 朽: directly through the contact window 164 and the active component 142 The second J 2 201122691 AU0908099 32903 twf.doc / d Jane 5, because this embodiment is a half-source driven (hsd) pixel architecture with a scan signal transmission line 15 〇 design (ie TGP's layout structure) 'Therefore' can effectively reduce the number of data lines 13〇 and effectively reduce the number of fan 〇uttrace lines at the end of the scan line 120, so that narrow boundary and borderless design requirements can be easily achieved. The design of the dielectric layer 160 of the embodiment can increase the common line The distance between the 17 〇 and the data line 130 can reduce the power consumption caused by the capacitance between the common line 17 〇 and the data line 13 。. Furthermore, since the active device array substrate 1 of the present embodiment has the ability Coupling with the pixel electrode 144 to form a common line 170 of the storage capacitor, thereby contributing to increasing the capacitance value of the storage capacitor. The structure of the active device array substrate 1 of the present invention is only described above, and the active device of the present invention is not described. The manufacturing method of the array substrate 1A. In this regard, the active device array substrate 1A of FIG. 1A will be exemplified below, and the manufacturing method of the active device array substrate of the present invention will be described in detail with reference to FIGS. 2A to 2F. 2A to 2F are schematic flowcharts of a method for manufacturing an active device array substrate according to an embodiment of the present invention. [Manufacturing method of active device array substrate according to the present embodiment] Please refer to FIG. 1A and FIG. 2A simultaneously. A plurality of scan lines 120, a plurality of data lines, a plurality of active elements 142, and a plurality of scan signal transmission lines 15A are formed on the substrate 110. Among them, the line (10), the capital The manufacturing method of the line 130, the active element 142 卩 and the scanning; the ^ number transmission 150 includes the following steps: First, a plurality of scanning lines 120 on the substrate ι, and a plurality of inter-electrodes electrically connected to the scanning line 120^ And the first conductive pattern 152. That is, the first conductive pattern 152 is ^201122691 Auuyu8099 32903twf.doc/d is formed simultaneously when the scan line 120 is formed. Then, the gate insulating layer GI is formed on the substrate n〇, The scan line 120, the gate G, and the first conductive trace 152 are covered. Then, a plurality of semiconductor patterns m3 and an ohmic contact layer 145 located over the semiconductor pattern 143 are formed on the gate insulating layer GI. Finally, a plurality of data lines 130, a plurality of source electrodes S connected to the data lines 13 , a plurality of drain electrodes D, and a second conductive layer electrically connected to the first conductive patterns 152 are formed on the interlayer insulating layer GI. Pattern 154. That is, the second conductive pattern 15 is formed simultaneously when the data line 130 is formed. In particular, in the present embodiment, the gate G, the semiconductor pattern 丨43, the source S, and the drain D constitute the active element 142, and the first conductive pattern 152 and the second conductive pattern (9) constitute the signal transmission line 150. Next, referring to FIG. 2B, a protective layer 19A is formed to cover the capital, 130 (refer to '1A), the active device 142, and the scan signal line 150. ^ Next, referring to FIG. 2C, a dielectric layer 16A is formed, ie, 12 〇, data, line 130, active device 142, and scan signal. In this embodiment, the thickness of the dielectric layer 160 is, for example, Between about 15 micrometers (//m) and about 4 micrometers (#„!), and the dielectric layer 16 is formed: a plurality of bumps 162 are formed on the top surface, wherein the bumps 162, for example, 疋 are formed in the dielectric layer The surface microstructure on the electrical layer 160. Furthermore, the dielectric layer 160 of the present embodiment has at least one contact window 'crossing the protective layer 190', and the middle contact window 164 exposes the drain D of the active element 142. The dielectric ^ 160 may be a single layer or a multilayer structure, and the material thereof comprises an organic material (for example, photoresist, benzocyclobutane (BCB), cycloolefin, polyfluorene 15 201122691 AU0908099 32903twf.doc/d Imines, polyamines, polyesters, polyacids, resins, polyethers, polyketones, e-firings, combinations, and inorganic materials (eg, nitride, two: mouth A combination of materials, or other suitable materials, or combinations thereof, as described above. The appropriate material, or the like, is shown in FIG. 1A and FIG. 2D' on the dielectric layer 160 to form A, the table 170' wherein the common line 17 is, for example, a circular junction n.g. In particular, the common line 本 of the present embodiment is located above the known transfer line 15G, and the common line m covers the bump 162. In addition, the common line no may be a single layer or a multilayer structure, and the material thereof is, for example, a reflective material, for example, gold, silver, copper, m crane, turn, the above alloy, the above oxide, the above nitride, Establish suitable compounds, other suitable materials, or combinations thereof. Since the common line 17°0 of the reflective material is used in this embodiment, the common line 170 can also be regarded as a reflective layer. Therefore, the manufacturing process of the conventional reflective layer can be omitted in the present embodiment, and the production cost can be effectively reduced. It is worth mentioning that in the present embodiment, the position where the common line 17 is disposed can be regarded as a reflection area, and the position where the common line 17 is not provided can be regarded as a penetration area. Furthermore, since the thickness of the dielectric layer 16A of the present embodiment is, for example, between about 1.5 micrometers (Mm) and about 4 micrometers (Mm), the distance between the common line 170 and the data line 130 can be increased. The effect of reducing the capacitance value and power consumption can be achieved. / Then, referring to FIG. 2E, a capacitor dielectric layer 1δ〇 is formed on the common line 170 and the dielectric; 16〇. Finally, please refer to 2F to form a plurality of halogen electrodes 144 on the dielectric layer 160 and the capacitor dielectric layer 18〇16 201122691 Λυυ^υδ〇99 32903twf.doc/d, wherein each pixel electrode 144 is in contact with each other. The window 164 is directly connected to the drain of one of the active elements 142. In particular, in the present embodiment, the pixel electrode 144 can be coupled to the common line Π0 to form a storage capacitor Cst' to help increase the electrical capacity of the storage capacitor. So far, the fabrication of the active device array substrate 100 has been completed. According to the above description, the present invention adopts a half-source-driven (hsd) pixel structure with a scan signal transmission line design (ie, TGp's cloth sweep (four)^ this' can effectively reduce the number of data lines used and effectively reduce The number of easy-out lines (fan rhythm traces), so it can be lightly active to reach the t-boundary and borderless design requirements. In addition, the political inverse design of the present invention uses a common line of reflective materials, so == visual reflection layer ' Reduce the process steps and reduce = turn, you can _ reduce the common line power = caused by the power consumption. Another iceberg # 丄々 所 has the ability to work with the pixel electrodes to help improve the material capacitance ^ = age W Therefore, there is a reduction in the above embodiments, and the money is not intended to limit the spirit and scope of the present invention. The person who has knowledge of the invention is attached to the scope of protection of the invention: = 1:= [Simple description of the schema 1A is a top plan view of an active device array substrate 17 201122691 AU090S〇y9 32903twf.doc/d according to an embodiment of the present invention. FIG. 1B is a cross-sectional view taken along line I-Ι of FIG. 1A. FIG. Section II-II of Line 1A is not intended 1D is a schematic cross-sectional view taken along line III-III of FIG. 1A. FIG. 2A to FIG. 2F are schematic flowcharts showing a method of manufacturing an active device array substrate according to an embodiment of the present invention. Active device array substrate 110: substrate 120 · scan line 130: data line 140: display unit 140a: first sub-element 140b: second sub-element 142: active element 142a: first active element 142b: second active element 143 Semiconductor pattern 144: halogen electrode 144a: first halogen electrode 144b: second halogen electrode 145: ohmic contact layer 150: scanning signal transmission line 201122691 AU0908099 32903twf.doc/d 152 first conductive pattern 154 second conductive pattern 160 dielectric layer 162 bump 164 contact window 170 common line 180 capacitor dielectric layer 190 protective layer Cst storage capacitor D: and pole G: interpole GI: gate insulating layer R: display area S: source