TW201121004A - Semiconductor chipsets. - Google Patents

Abstract

A semiconductor chipset comprises at least one semiconductor element, a heat sink, a substrate and an adhesive layer, wherein the semiconductor device is electrically connected to the substrate, and thermally attached to the heat sink; the heat sink at least comprises a protruding column and a heat dissipating base, and the protruding column extends upward through one opening of the adhesive layer to go through one through-hole in the substrate; the heat dissipating base extends laterally and supports the substrate; the adhesive layer extends between the protruding column and the substrate, and between the heat dissipating base and the substrate; the substrate at least comprises a first and a second electrically-conductive layers and a dielectric layer between the first and the second electrically-conductive layers. Accordingly, this system can provide vertical signal routing between one of the welding pads above the first electrically-conductive layer and one of the terminals under adhesive layer.

Description

201121004 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor wafer package, and more particularly to a device suitable for high-power semiconductor devices, in particular, a semiconductor device, a substrate, an adhesive layer and a heat sink. A semiconductor wafer package and a method of manufacturing the same. [Prior Art]

Semiconductor components such as packaged and unpackaged semiconductor wafers provide high voltage, high frequency, and high performance applications; these applications require a very high amount of power to perform a specific function, but the higher the power, the higher the semiconductor component The more heat it produces. In addition, after the package density is increased and the size is reduced, the surface area available for heat dissipation is also reduced, which leads to an increase in heat generation. Semiconductor components are prone to performance degradation and reduced service life at high temperatures, and may even fail immediately. High heat not only affects wafer performance, but also thermally stresses the wafer and its surrounding components due to thermal expansion mismatch. Therefore, the wafer must be quickly and efficiently dissipated to ensure the efficiency and reliability of its operation. A high thermal conductivity path typically conducts and dissipates thermal energy to a larger area than the die pad where the wafer or wafer is located. Light Emitting Diodes (LEDs) have recently become popular alternatives to incandescent sources, fluorescent sources, and halogen sources. Led provides long-term illumination with high energy efficiency and low cost for medical, military, signage, signal, aerospace, marine, vehicle, portable, commercial and residential lighting applications. For example, 'LEDs can provide light sources for fixtures, flashlights, headlights, searchlights, traffic lights, and displays. The high-power chips in the LEDs also provide large 201121004 calorimetric energy while providing high-brightness output. However, under high temperature operation, LEDs may suffer from color shift, brightness reduction, shortened use of life, and immediate failure. In addition, LEDs have limitations in terms of heat dissipation, which in turn affects their light output and reliability. As a result, LEDs highlight the need for high-power chips with good thermal dissipation. The LED package typically includes an LED chip, a pedestal, an electrical contact, and a thermal contact. The pedestal is thermally coupled to the LED chip and used to support the LED chip; the electrical contact is electrically connected to the anode and the cathode of the LED chip, and the thermal contact is thermally coupled to the LED via the pedestal The wafer, the carrier underneath, can dissipate heat sufficiently to prevent overheating of the LED chip. The industry is actively investing in the development of high-power chip packages and thermal boards with a variety of design and manufacturing technologies to meet performance needs in this extremely cost-competitive environment. A Plastic Ball Grid Array (PBGA) package encloses a die and a laminate substrate in a plastic case and then adheres to a printed circuit board (PCB) with solder balls. . The laminated substrate comprises a dielectric layer usually composed of glass fibers, and the thermal energy generated by the wafer can be transmitted to the solder balls through the plastic and dielectric layers, and then transferred to the printed circuit board. However, due to the low thermal conductivity of the plastic and dielectric layers, the heat dissipation effect of pBGA is not good. A quad flat no-lead (QFN) package places the wafer on a copper die pad soldered to a printed circuit board. The heat generated by the wafer can be transferred to the printed circuit board via the die pad. However, due to the limited routing capability of the vias in its leadframe, QFN packages are not suitable for high input/output (I/O) chips or passive components. The thermal pad provides electrical routing, thermal management and mechanical support for the semiconductor components 201121004. The heat conducting board usually comprises a substrate for signal routing, a heat sink or heat sink for providing a heat removing function, a solder pad electrically connectable to the semiconductor component, and a terminal electrically connectable to the next layer assembly. The substrate may be a stamped structure having a single layer or a plurality of routing circuit systems and one or more dielectric layers; the heat sink may be a metal base, a metal block or a buried metal layer.

The heat conducting plate engages the next layer of the body. For example, the next layer of the body can be a lamp holder having a printed circuit board and a heat sink. In this example, an LED package system is disposed on the heat conducting plate, and the heat conducting plate is disposed on the heat dissipating device, and the heat conducting plate/heat dissipating device and the printed circuit board are disposed in the lamp holder. The heat conducting plate is electrically connected to the printed circuit board via a wire. Thereby, the substrate 5 radiates heat from the printed circuit board to the LED package _ package and is transmitted to the heat sink. The board provides an important thermal path for the LED wafer. U.S. Patent No. 6,5,7,1,2, issued toJ.S.A., issued to U.S. Pat. The heat-dissipating block of the square or the square spurs is combined with the upper and lower ends of the plate, and the upper and lower conductive layers are adhered to the top and bottom of the plate, respectively. Electrical connection. Furthermore, (5) is provided with the side and wire bonded to the upper conductive layer, and the material is formed on the day of the film, and the lower conductive layer is provided with a solder ball. When the above-mentioned special store was manufactured, the job board was originally - placed on the lower conductive layer on the Ge B (4) kiss) resin film. The heat dissipating block is inserted into the central opening, the i layer, and is spaced apart from the substrate, and the upper conductive layer is on the substrate. After the upper and lower conductive layers are heated and pressed together, the 201121004 resin is melted and solidified in the forefoot, and the upper and lower conductive layers are patterned, thereby forming circuit wiring on the substrate and allowing the resin to overflow. The material is exposed on the heat sink block. Then, the grease is removed, and the dispersion is exposed. Finally, the wafer is placed on the heat sink and bonded and packaged. Therefore, the thermal energy generated by the above wafer can be transmitted to the printed circuit board via the heat sink. However, when mass production is made, the scattering is manually placed in the center: the operation in the mouth is extremely laborious and costly. Moreover, since the lateral women's valley is small, the heat dissipating block is not easily positioned in the central opening, resulting in a gap between the substrate and the heat dissipating block and uneven wiring. In this way, the substrate is only partially adhered to the heat dissipating block, and it is impossible to obtain sufficient supporting force from the heat dissipating block and to easily delaminate. In addition, the chemical etching solution for removing part of the conductive layer to expose the resin flash will also remove some of the heat-dissipating blocks not covered by the resin flash, which makes the political heat block uneven and difficult to combine, eventually resulting in a low yield drop of the group. Shortcomings such as insufficient reliability and high cost. A high heat-dissipating ball grid array package disclosed in U.S. Patent No. 6,528,882 to Ding et al., the substrate of which is incorporated herein by reference. Wherein, an insulating layer is formed on the bottom surface of the metal core layer, and a blind hole is penetrated through the insulating layer to directly pass through the metal core layer, and the hole is filled with a heat-dissipating solder ball, and the heat dissipation is further provided on the substrate. The tin ball corresponds to the tin ball. Thereby, the thermal energy generated by the wafer can flow to the heat-dissipating solder ball through the metal core layer and then to the printed circuit board; however, the insulating layer sandwiched between the metal core layer and the printed circuit board flows to the printed circuit The heat flow of the plate is limited. U.S. Patent No. 6,670,219 to Lee, the entire disclosure of which is incorporated herein by reference to the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire portion a substrate is mounted on the heat sink by a central opening formed by the ground plate, and a substrate having a central opening is disposed on the ground plate through a recess having a central opening. Tin balls are provided on the substrate. However, since the solder ball is located on the substrate, the heat sink does not contact the printed circuit board, and the heat dissipation effect of the heat sink is limited to heat convection instead of heat conduction, thereby greatly limiting the heat dissipation effect. U.S. Patent No. 7,038,311 to Woodall et al. provides a high-heat-dissipation BGA package having a heat sink having an inverted shape and including a column portion and a wide substrate. A substrate having a window-shaped opening is disposed on the wide substrate, and an adhesive layer adheres the pillar portion and the wide substrate to the substrate; a wafer is disposed on the pillar portion and is wire bonded to the substrate A package material is molded on the wafer, and a solder ball is disposed on the substrate. Wherein the post extends through the window opening and the substrate is supported by the wide substrate such that the solder ball is between the wide substrate and the periphery of the substrate. Thereby, the thermal energy generated by the wafer can be transferred to the 5-wide substrate via the pillar β and then transferred to the printed circuit board; however, since the wide substrate must have a space for accommodating the solder ball, the wide substrate is only A position corresponding to the center window and the innermost solder ball protrudes below the substrate. As a result, the substrate is unbalanced during the manufacturing process and is easily shaken and bent, which in turn results in difficulty in mounting, wire bonding, and molding of the package. In addition, the wide substrate may be bent due to the molding of the encapsulating material, and once the solder ball collapses, the package may not be soldered to the next layer. Therefore, the yield of the package is low, the reliability is insufficient, and the cost is too high. U.S. Patent Application Publication No. 2007/0267642 to Erchak et al., which is incorporated herein by reference in its entirety, the disclosure of which is incorporated herein by reference in its entirety, the entire entire entire entire entire entire entire entire entire entire portion The insulating layer is provided with electrical contacts. a packaging system having a through hole and a transparent upper cover is disposed on the electrical contact; - an LED chip is disposed on the protruding portion and connected to the substrate by wire bonding, and the protruding portion is adjacent to the substrate and extends through the insulating layer The through hole on the package enters the package. And the insulating layer is disposed on the substrate, and the insulating layer is provided with electrical contacts, and the packaging system is disposed on the electrical contacts and spaced apart from the insulating layer. Thereby, the heat energy generated by the wafer is

The protruding portion is transmitted to the substrate </ RTI> and then reaches-distributed; fine, the electrical connections are not easily disposed on the insulating layer, and are difficult to electrically connect with the next layer of the body, and no multi-layer routing is provided. Conventional packages and guides have the disadvantage of being heavy A. For example, an electrically insulating material such as Epoxy resin, which has low thermal conductivity, limits the heat dissipation effect; however, the electrical insulating material with a high conductivity of the epoxy tree material of the ceramic or carbonized Weiyin has low riding performance. And the turtle with 4 wire stalks, so that the electrical insulating material may be heated by the enamel layer during the manufacturing process or at the beginning of the operation. The early layer circuit of the substrate has a limited ugly strength, but if the base (four) multilayer circuit system, the excessively thick dielectric layer of the substrate will reduce the heat dissipation effect, and the performance of the front fine squat is insufficient, _ 敬 or _ Next; the manufacturing of the previous technology 4 is also not suitable for low-cost mass production. And 'has a slap in the financial resources of the high-conductor conductors, the county's financial guides to the various types of hair, = and __ 'so' - (four) things _ in line with the actual use of the industry for the industry's f -半导体 效能 : : : : : : : : : : : : : : : : : : : 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 Group. For the above purposes, the county-type semiconductor wafer package provides vertical signal routing, which includes at least half of the components, a bulkhead, a plate, and an adhesive layer. The semiconductor component is coupled to the county plate and thermally coupled to the heat sink, and the heat sink includes at least a pillar and a base. Wherein the stud is extended upwardly through an opening of the adhesive layer and into a through hole of the substrate, the φ* seat extends laterally from the stud, and the adhesive layer extends over the stud Between the substrates and between the pedestals and the substrate. The substrate includes at least a first "first conductive layer" and a dielectric layer therebetween. The group can be passed between the solder bump on the first conductive layer and the terminal under the adhesive layer. A routing line on the second conductive layer, a first conductive via extending through the dielectric layer to the routing line, and a second conductive via extending through the adhesive layer to the routing line provide vertical signal routing. In a preferred embodiment of the present invention, a semiconductor wafer system includes at least a semiconductor component, an adhesive layer, a heat sink, and a substrate, wherein the adhesive layer has at least one opening; the heat sink includes at least one pillar And a pedestal, and the stud is adjacent to the pedestal and extends above the pedestal in an upward direction, the pedestal extending below the stud in a downward direction opposite to the upward direction, and along The side surface extending perpendicularly to the upward and downward directions extends laterally from the stud; the substrate is disposed on the adhesive layer and extends over the pedestal, and includes at least one pad, a routing line, and a First conductive hole and a dielectric layer, wherein the soldering system extends over the S-dielectric layer, the routing line extends under the dielectric layer and is buried in the adhesive layer, and the first conductive via extends through the dielectric layer Up to 201121004, the routing line has a through hole extending through the substrate. Further, a second conductive hole extends through the hybrid layer to the routing line, and the terminal extends below the adhesive layer and is located at the bonding pad Between the terminals, the first conductive hole, the routing line and the second conductive hole form a red conductive path; the thief conductor element is located above the pillar and overlaps the pillar, or is located below the pillar and is The protruding pillars are electrically connected to the terminal and thermally coupled to the stud and the pedestal. The stud string extends through the opening to enter the through hole to pass over the dielectric layer. The holder extends over the adhesive layer and the substrate, wherein the adhesive layer is disposed on the base, and the pedestal extends into the rail - a gap between the pillar and the substrate The towel extends across the dielectric layer and is interposed between the stud and The heat sink can be included between the substrate and the substrate. The heat sink can include a cover body that listens to the top of one of the posts and abuts the top of the stud and is from the top. Extending laterally from the top of the stud (4). For example, the cover may be rectangular or square, and the top of the stud is _; the Wei may also cover the adhesive layer - adjacent to the convex _ stud a portion of the coplanar surface; the domain body may also be coplanar with the solder pad over the dielectric layer. Further, the stud may thermally connect the base plaque to the cover body. Alternatively, the miscellaneous seat can be formed by the stud and the professional ship; the dimple seats of the two configurations can provide the _, _ semi-navigation and the sew to the next layer of the assembly. 'The semiconductor component can be extended Above the stud, the post is retracted and electrically connected to the solder pad to electrically connect to the end, and the semiconductor component is also thermally coupled to the seam, and (4) thermally coupled to the pedestal 1 Shirt, the semi-201121004 conductor element can be a semiconductor wafer, which is disposed on the cover by a solid crystal material. Is electrically connected to the solder pad and thermally coupled to the cover via the die bonding material; or 'the semiconductor component may extend below the pedestal, be overlapped by the stud, and electrically connected to the terminal, and then electrically Connect to the soldering iron. In addition, the semiconductor component can also be thermally bonded to the pedestal and thermally coupled to the cover. For example, the semiconductor component can be a semiconductor wafer that is disposed on the susceptor by a die bonding material, electrically connected to the terminal via a wire, and thermally bonded to the susceptor via the die bonding material. The adhesive layer may follow the stud_dielectric layer in the defect and contact the pedestal, the dielectric, the routing line, the second conductive via and the terminal outside the defect. The adhesive layer may also cover and surround the stud in the lateral directions and extend to the peripheral edge of the set. The adhesive layer can also be planar with the top of one of the studs. The adhesive layer may also fill the gap and a space between the base and the substrate, and be between the briquetting base and the substrate. /Hello posts can be formed with the wire holder-body. For example, the stud and the pedestal may be a single-metal body or include a H-layer in its interface. The stud can also extend through the through hole. The stud can also be coplanar with the adhesive over the dielectric layer. The stud may also be a flat-topped conical cylinder having a diameter that decreases upwardly from the base toward its flat top adjacent one of the covers. * The pedestal can be coplanar with the _ terminal below the adhesive layer, and can also cover the stud from below while supporting the substrate and securing away from the peripheral edge of the set. The substrate can be a structure and maintain a distance from the pillar and the seat. When the semiconductor component is disposed above the heat sink, the germanium can serve as an electrical contact of the (CSS]] 201121004 semiconductor component. The terminal can be used as an electrical contact of the next layer of the assembly. When the semiconductor component is set to a lower node, the terminal can serve as an electrical contact of the semiconductor component, and the resource serves as a lower layer.

Body - electrical contacts. In either case, the material and the terminal can provide vertical signal routing between the semiconductor component and the next layer of components. X This group can be a first or second stage single crystal or polycrystalline device. For example, the body can be a first-stage package comprising a single wafer or a plurality of wafers. or,

The group may also be a second-level module comprising a single-LED body and an LED package, wherein each of the LED packages may comprise a single LED t LED chip. The present invention provides a branch of a difficult-to-semiconductor crystal group comprising: a stud and a pedestal; an adhesive layer disposed on the pedestal and inserting the stud into the adhesive layer Opening-arranging-substrate on the adhesive layer, and inserting the stud into the through-hole of the substrate, thereby forming a gap between the stud and the substrate; and making the adhesive layer upward The gap is formed; the adhesive layer is cured, and the semiconductor component is disposed on a heat sink, wherein the heat sink includes at least the pillar and the base; the electrical connector is disposed on the substrate and the adhesive layer is located on the adhesive layer a lower terminal; and thermally bonding the semiconductor component to the heat sink. The substrate includes at least an m conductive layer and a dielectric layer therebetween, thereby enabling the group to provide vertical signal routing. In a preferred form of the invention, the method of fabricating a semiconductor wafer package comprises the steps of: (A1) providing a - stud, a susceptor, an adhesive layer, and a substrate, wherein the substrate comprises at least - a first conductive layer, a second conductive layer and a dielectric layer therebetween; the pillars are adjacent to the pedestal, extending in the upward direction to the susceptor 12 201121004 and extending through the adhesion layer And extending into one of the through holes of the substrate; the base extends downward in the downward direction opposite to the upward direction below the stud, and from the side of the stud in a direction perpendicular to the upward and downward directions Extending out; the layer is disposed on the pedestal, extends over the base rainbow, and is located between the susceptor and the wire plate, and is uncured; the substrate is disposed on the adhesive layer and extends over the pedestal Above the adhesive layer, wherein the first conductive layer extends over the dielectric layer, the dielectric layer extends over the second conductive layer; and a notch is located in the via and interposed between the pillars Between the substrate; (Β1) causing the adhesive layer to flow upward (C1) curing the adhesive layer; (D1)s5: placing the semiconductor element on the heat sink including at least the stud and the pedestal, and the conductor element is not embossed (four) by the stud overlapping. The group includes at least a pad, a terminal, a routing line, and first and second conductive holes, wherein the pad includes the selected portion (four) - the selected portion; the route includes one of the second conductive layers selected a portion; the first conductive via contacts and extends through a dielectric layer between the first conductive layer and the routing line; the second conductive via contacts and extends through the hybrid layer to the routing line; and the terminal contacts and extends Below the adhesive layer; ~ (E 1 ) electrically connecting the semiconductor component to one of the pad and the terminal, thereby electrically connecting the semiconductor component to the other of the soldering pad and the terminal a conductive path between the pad and the terminal comprising the first conductive via, the routing line and the second conductive via; and (F1) thermally bonding the semiconductor component to the stud and the pedestal Thermally bonding the semiconductor component to the other of the stud and the pedestal. The method according to the present invention includes the following steps: (A 2) providing a stud and a pedestal, wherein the stud is adjacent and integrally formed And the base extends above the pedestal in an upward direction, and the pedestal extends below the stud in a downward direction opposite to the upward direction, and perpendicular to the upward direction from the stud And extending laterally in a downward direction; (B2) providing an adhesive layer including an opening extending through the adhesive layer; (C2) providing a substrate, wherein the substrate comprises at least a first and a a conductive layer and a dielectric layer therebetween, and comprising - a routing line is included in a selected portion of the second conductive layer, and a via extends through the substrate; (D2) providing the adhesive layer on the substrate And inserting the stud into the opening, wherein the adhesive layer extends over the base, and the stud extends through the opening; (E2) the substrate is disposed on the adhesive layer and includes Inserting the stud into the through hole, wherein the substrate is Extending above the adhesive layer, a first conductive layer in the substrate extends over the dielectric layer, the dielectric layer extends over the second conductive layer in the substrate, and the protrusion extends through the opening Entering the through hole, the adhesive layer is between the base and the substrate and is not cured, and a notch is located in the through hole and between the protruding column and the substrate; (F 2) heating and melting the adhesive a layer (G2) abutting the base and the substrate, thereby moving the stud upward in the through hole and applying pressure to the molten adhesive layer between the base and the substrate, Forcing the molten adhesive layer to flow upward into the gap, and the stud and the dazzling adhesive layer extend over the dielectric layer; (Η2) heating and curing the molten adhesive layer, thereby using the stud and the base 201121004 mechanically adhering to the substrate; providing a first conductive hole extending from the dielectric layer to the routing line; (2) providing a second conductive hole Extending through the viscous green, and removing the first (K 2 ) provides an extension over the dielectric layer A selected portion of a conductive layer;

(L 2) providing a terminal extending from a selected portion of the lower portion of the adhesive layer; and removing the base (M2) to provide a cover body on the protruding post, the cover being difficult to be located at the top of the protruding column And covering the top of the stud from above, and extending laterally from the top of the stud in the lateral direction; (N2) providing a semiconductor wafer on the cover, wherein the heat sink comprises at least the stud The pedestal and the cover, and the conductor chip overlaps the stud;

And (〇2) electrically connecting the semiconductor wafer to the detail, thereby electrically connecting the semiconductor to the terminal, wherein the conductive path between the pad and the terminal sequentially includes the first conductive hole The routing line and the second conductive via; and (P 2) thermally bonding the semiconductor wafer to the cover, thereby thermally bonding the semiconductor wafer to the pedestal. The step (A 2 ) providing the stud and the pedestal system may include: providing a metal plate to form a patterned side resist layer on the metal plate, and selectively exposing the metal plate, the 働m metal The plate is formed such that it forms a pattern of the meaning of the film, thereby forming a groove on the metal plate, which extends into the metal plate but does not penetrate 201121004; The towel portion of the metal plate is not covered by the 働j portion, protrudes above the pedestal, and is laterally surrounded, and the pedestal is also the unaffected portion of the metal plate, and the region is formed by the bulge and the groove Below. The step (B 2) providing the adhesive layer may include: providing a film of uncured epoxy resin and the step (G 2) flowing the adhesive layer may include: refining the uncured epoxy resin; and extruding The uncured epoxy between the susceptor and the substrate, and the step (Η 2) heating and curing the fused adhesive layer may comprise: curing the molten uncured epoxy resin. The step (C 2 ) providing the silk plate system may include: providing the routing wire, the step of accommodating the dam portion of the second conductive layer; and then puncturing the through hole. The step (2) providing the pad may include: polishing the stud, the adhesive layer, and the first conductive layer, such that the stud, the adhesive layer, and the first conductive layer face in the upward direction The upper side surfaces are laterally flush with each other; then selected portions of the first conductive layer are removed. The polishing may include grinding the adhesive layer without grinding the pillars and then grinding the pillars, the adhesive layer and the first conductive layer. The step (Κ 2) providing the pad may also include removing selected portions of the first conductive layer. The step (L 2) of providing the terminal system can include removing selected portions of the base. The step (I 2) providing the first conductive via may include: forming a first hole extending through the first conductive layer and the dielectric layer to the routing line; and then in the first hole and the first conductive A conductive metal is deposited on the layer and the routing line to form a third conductive layer. The step (J 2) providing the second conductive via may include: forming a second hole extending through the pedestal and the adhesive layer to the routing line; and then in the second hole and the pedestal and the routing line Conductive metal 201121004 is deposited to form a fourth conductive layer. The step (K2, L2, and 12) providing the pad, the terminal, and the first and second conductive holes may further include: forming the hole; depositing a conductive metal in the hole to form the third and fourth conductive a layer; and then a second patterning defining the terminal using a first------------------------------------ . The step (I2) providing the first conductive via may include: depositing a conductive metal on the pillar, the first conductive layer, the adhesive layer and the routing line to form a third conductive layer. Step (2) provides the second conductive hole and the second hole lake and the base, the adhesive layer and the routing metal to form a four-conducting layer. The step (κ 2) provides the solder joint to remove selected portions of the first and third conductive layers. Step (providing the terminal may include: selecting the wire and the selected portion of the fourth conductive layer. The providing the third and fourth conductive layers may include: simultaneously covering the third and = electrical layers, removing the first portion - The third and fourth conductive layers and the selected core of the pedestal may include: the first, third, and fourth conductive layers and the pedestal. (4) The tidy may include: after curing the hybrid layer And providing a body 7L member to provide a "cover" on the stud, the cover is located above the top of the convex =-, adjacent to the top of the stud, while covering the stud from the top &lt; top, and from The top of the stud extends laterally along the side directions. The step (M2) provides that the age of the cap may include: depositing a conductive metal on the stud after grinding and removing the selected portion of the = conductive layer Forming a second conductive layer. For example, providing the cover body may include: forming a photoresist layer on the third conductive layer; using the patterned memory layer to engrave the 第§]] 17 201121004 Three conductive layers to define the cover; then the patterned etch stop is removed. For example, when the pad is formed, the patterned first and third conductive layers may be etched to define the pad. The step (G 2) of flowing the adhesive layer may include: The adhesive layer fills the gap; and may also include pressing the adhesive layer through the gap to reach the pillar and the substrate, and a portion of the top surface of the pillar adjacent to the top surface of the substrate The step (Η 2) heating and curing the refining adhesive layer may include: mechanically bonding the stud and the base to the substrate. The step (Ν 2) of providing the semiconductor wafer system may include: the semiconductor The semiconductor chip is disposed on the stud, the opening and the through hole, so that the semiconductor wafer is overlapped with the stud, the opening and the through hole. Alternatively, the semiconductor wafer is disposed. The pillar, the opening and the underside of the through hole are configured to overlap the semiconductor wafer by the pillar and the opening. The steps (Ν2, 02, and 2) are provided, electrically connected, and thermally coupled to the semiconductor wafer system. Can include: the semi-conductive The wafer is disposed on the stud; electrically connecting the semiconductor wafer to the solder pad, thereby electrically connecting the semiconductor wafer to the terminal; and thermally bonding the semiconductor wafer to the stud, thereby thermally bonding the semiconductor wafer to The susceptor or the electrical connection and the thermal connection of the semiconductor wafer may include: disposing the semiconductor wafer under the pedestal; electrically connecting the semiconductor wafer to the terminal, thereby electrically connecting the semiconductor wafer And bonding the semiconductor wafer to the susceptor to thermally bond the semiconductor wafer to the stud. The steps (Ν 2, 0 2 and Ρ 2) are provided, electrically connected and thermally bonded to the semiconductor The wafer system may include: a semiconductor wafer is disposed on the cover by using a die bonding material, a wire is provided between the semiconductor wafer and the tantalum, and the solid is provided between the semiconductor wafer and the cover. Crystal material. Or, ^ *日: ^ with two solid crystal materials will be connected to: the pedestal; between the semiconductor wafer and the terminal = for a dozen lines, and between the semiconductor wafer and the pedestal The adhesive layer of the solid crystal material may contact the stud, the base, the cover, the dielectric sound, the second conductive hole and the terminal, and cover the decorative direction; (4) The peripheral edge formed by the separation of other groups from the New Zealand. After the assembly of the group is separated from the other batches produced in the same batch, the base can cover the stud from below and extend laterally from the stud in the lateral directions while supporting the substrate. The invention has several advantages. The heat sink is provided to provide excellent heat dissipation effect and the heat energy does not flow on the adhesive layer. Therefore, the adhesive layer has low cost dielectric and is not easy to be delaminated; the pillar and the base can be integrated to improve reliability; Recording money as a conductor, the body seems to enhance the effect of the thermal connection; the hybrid layer can be thief-column without a substrate _ (10) between the base and the substrate 'to provide a strong between the heat sink and the substrate The mechanical connection; the substrate can provide a complex circuit system pattern to achieve flexible multilayer signal routing 'and the base can provide mechanical support for the substrate to prevent bending deformation. In this way, the system can be manufactured by using a low-temperature process, which not only reduces the stress, but also improves the reliability. In addition, the group can also be easily controlled by the circuit board, the lead frame and the tape-and-reel substrate manufacturer. Made. [2011] The above and other features and advantages of the present invention will be further clarified by the following examples. s, as shown in the "1A to 1F" drawings, which are respectively a structure for forming a stud and a pedestal in the preferred embodiment - a schematic cross-sectional view of a preferred embodiment of the present invention FIG. 2 is a schematic cross-sectional view showing a structure of a column and a pedestal, a third embodiment of the structure of the embossed base of the present invention, and a fourth cross-sectional view of the structure of the pylon and the pedestal in a preferred embodiment of the present invention. The top view of the D-Fig. and the top view of the 1D figure. As shown, the present invention is a semiconductor wafer assembly that is first provided with a metal plate i◦ comprising opposite major surfaces 12, 14 as shown in Figure 1A. The metal sheet can be made of a variety of metals such as copper, aluminum, iron-nickel alloy 42, iron, nickel, silver, gold, mixtures thereof, and alloys thereof. Among them, it is particularly difficult to guide, and the combination is good and the thief (four) point. Therefore, the metal plate i Q of the present embodiment is made of a copper plate having a thickness of 300 μm. # The patterned side layer 丄6 and the fully covered side resist layer i8 are formed on the sugar plate 1 如, as shown in the figure iB. The patterned etched resist layer 16 and the overlying resistive layer i 8 are deposited on the photoresist layer of the metal plate 10, and the method is as follows: using a stamper technology to simultaneously heat the photoresist with a hot roller The combination of the surface i 2, the work 4, in which the wet spin coating method and the curtain coating: the method is also suitable for the formation of photoresist. Then, a reticle (not shown in the figure) is combined with a photoresist layer, and then according to the technique of the stomach, the light is selectively passed through the reticle to remove the soluble filament portion and read the fine layer to form a pattern. , that is, the patterned money is blocked. Therefore, the photoresist layer on the surface 2 has a surface that can be masked and exposed. 20 201121004 The resist layer 1 6 'the fine layer on the surface 14 is not difficult. The coverage is maintained to form a fully covered etch stop layer 18. A groove 2 0 ' into which the metal plate 掘 is dug but not penetrated is formed on the metal plate 10 as shown in Fig. 1C. The groove 2 is formed in the manner of the metal plate 10 to make the metal plate! 〇 forms a _ defined by the patterned resist layer 16. In the implementation of the present invention, the side mode is wet chemical etching, and the top nozzle (not shown) can be used to chemically_liquid_the metal plate 10; or the _ comprehensively covered side resist layer i 8 A backside protection is provided to immerse the structure in the chemical etchant to form the recess 2'. Among them, the chemical etching solution can be highly targeted to copper and can be engraved into the metal plate 'i 0 = 270 microns. Therefore, the groove 2 extends from the surface 丄2 but does not penetrate the metal plate 10, and can be 3 〇 micrometers away from the surface i 4 and has a depth of 27 〇 micrometers. In addition, the chemical etching solution is also The metal plate 10 under the patterned etching resist layer i 6 causes lateral etching. Accordingly, the applicable chemical etching solution may be an alkali ammonia-containing solution or a diluted mixture of nitric acid and hydrochloric acid, in other words, the above chemical etching. The liquid can be acidic or not. Among them, the ideal time for forming the (10) 2 〇 without causing the metal plate 1 Q to be excessively exposed to the chemical slake can be determined by trial and error. The patterned etch stop layer i 6 and the metal plate 1G ' after the etch stop layer 8 is completely covered are shown as IDs, 1E and 1FSI. Wherein the photoresist layer has been removed by solvent treatment, and the solvent used may be a sodium hydroxide/nitrogen oxide clock solution having a pH of 14. For example, the etched metal plate 10 thus includes a structure of a stud 22 and a pedestal 24. The above-mentioned studs 2 2 are portions of the metal plate 1 which are protected by the patterned residual resist layer 16 without being left in the past. The protrusion 2 2 is adjacent to the base 24 and protrudes above the base 24, and is laterally surrounded by the groove. Wherein the height of the stud 22 is equal to the depth t of the groove 2, which is Γ0 μm, and the diameter of the top portion of the surface is equal to _μm, and the bottom portion is rich in the base. Block 2 4 = 2 2 diameter, _ micron. Therefore, the studs 2 2 are similar to the Gan-flat-topped truncated cylinders, the side walls of which are tapered, and the diameter decreases from the base 2 4 toward the flattened top surface thereof. In which the tapered sidewall is chemically

The remaining portion is formed under the resistive layer 16 of the patterned pattern, so that the circumference of the top surface of the top surface is concentric, as shown in the first step. The pedestal 2 4 is an unetched portion of the metal plate 1G under the stud 2 2 , and the yoke from the yoke to the side of the yoke , such as the left and right sides of the lateral direction extending, the thickness of 30 microns (ie 3 〇〇 ~ 27 〇). The stud 22 and the pedestal 24 can be treated to enhance bonding to epoxy and solder. For example, the studs 2 2 and the susceptor 24 may be chemically oxidized or micro-etched to create a rougher surface. In this embodiment, the studs 2 2 and the pedestal 2 4 are passed through a reduction-formed mono-metal (copper) body. The metal plate i Q is stamped by a contact having a groove or a hole to define the portion of the protrusion 2 2, so that the protrusion 2 2 and the base 24 are stamped into a single metal body; Or, the addition method is used to form the 3 pillars 2 2, for example, by electro-mineralization, chemical vapor deposition (CVD), physical vapor deposition (physicai).

The protrusion 2 2 is deposited on the susceptor 24 by a technique such as Vapor Deposition (PVD); or the protrusion 2 2 is formed by a semi-addition method, for example, the protrusion 2 2 is etched to form a lower portion. The upper portion of the stud 2 2 is deposited on top; or the stud 22 may be sintered to the pedestal 24. In addition, the studs 22 and 22 can be multi-piece metal bodies, for example, the copper studs 22 on the copper base 24; in this case, the studs 22 and The pedestals 24 are joined by a gold interface, adjacent to each other but not integrally formed. Referring to FIG. 2A to FIG. 2D1I, respectively, a schematic cross-sectional view showing a structure for forming an adhesive layer in a preferred embodiment of the present invention, and an adhesive layer formed in a preferred embodiment of the present invention. A schematic cross-sectional view of the structure, a top view of the second B diagram, and a bottom view of the second B diagram. As shown, a film of B stage uncured epoxy resin is provided as an adhesive layer 2 6, which is 150 microns, as shown in FIG. The above adhesive layer 26 may be a variety of dielectric enamels or films made of multi-caliber or domain hybrid insulators. For example, the hybrid layer 26 may initially be a film, when the tree-shaped thermosetting epoxy resin is immersed in a After the material is reinforced, it is partially cured to the medium term. Among them, the epoxy resin may be FR_4, and other cycloaliphatic resins such as polyfunctional and bismaleimide-triazabenzene (BT) resins may also be used. In special applications, it is also useful as an epoxy resin for the use of hexafluoroacetic acid (PTFE). In addition, the reinforcing material may be an electronic grade glass, and may also be other reinforcing materials, such as high-strength glass, low-inductance glass, quartz, Kevlar Aramid, paper, etc. Further, the reinforcing material may also be used. For fabrics, woven or non-directional microfibers. In this way, fillers such as enamel (melt fused silica) can be added to the field towel to match the material and scale resistance and thermal expansion. Commercially available prepreg bodies such as SPEEDBOARD C film from W.L. Gore & Associates, Oakland, Wisconsin, USA, are examples. The adhesive layer 26 has at least one opening 2 8, as shown in the second B, 2 C and 2 D drawings. The opening 28 is a central window penetrating the adhesive layer 26 and is formed by mechanically drilling through the film and has a diameter of 1150 microns. Among them, 23 201121004 $ 2 8 φ~χ彳||made by other techniques, such as punching and stamping. </ br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br> BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a schematic cross-sectional view showing a structure of a substrate in a preferred embodiment of the present invention, a schematic view of a substrate fabricated in a preferred embodiment of the present invention, and a preferred embodiment. The middle five-section view _, the first top view, and the third picture ^

Not interested in the circle. As shown, a substrate 30 is provided which includes a first conductive layer 3 - a dielectric layer 34 and a second conductive layer 3 6 as shown in FIG. The first conductive layer 32 contacts the dielectric layer 34 and extends over the dielectric layer 34, and the second electrical layer 36 contacts the dielectric layer 34 and extends below the dielectric layer 3糸The first and second conductive layers 3 2, 3 6 are contacted and sandwiched therebetween.苴 The first and second conductive layers 3 2, 3 6 are electrical conductors, and the dielectric layer 3 4 2 is an electrical insulator. For example, the first and second conductive layers 32, 36 are in the case of the 4 〇 ^ 厚 厚 ® 峨 峨 峨 峨 峨 峨 峨 完 完 完 完 完 完 完 完 完 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及The electrical layer 34 is a (10) micron thick ring gas tree. The above-mentioned base, the third and second conductive layers 3 2 and 3 6 of the 30, respectively, form a fully covered #etch resist layer 38 and a patterned layer 4, as shown in FIG. The fully-covered resist layer 38 and the patterned side layer 40 are both photoresist layers, and are respectively similar to the foregoing resist layer i 8 and 丄, wherein the residual resist layer 38 is without any pattern and Covering the first conductive material 2 and the ship resist layer 4 q is provided with a pattern for selectively exposing the second conductive layer 36. In Fig. 3C, the second conductive layer 36 of the substrate 3 has been removed from the side 24 201121004, thereby forming a patterned wiring layer defined by the chemist 4 〇. Among them, the etching is a back wet type which is similar to that used for the metal plate. At this time, the first conductive layer 32 is still: a copper plate without a picture, and the second conductive layer 36 is exposed to cause the dielectric layer '3, 4 to be exposed, so that the second conductive layer 36 is removed from the first conductive layer 36. The unpatterned layer is converted to a pattern ^. In the present embodiment, in order to facilitate comparison of the figures, the second conductive layer 36 is located below the dielectric in the figure, but in this step, the structure can be inverted to enhance the etching effect by gravity. In the substrate 3 of the 3D®, the overlying resist layer 38 and the patterned etch stop layer 40 are removed. The etching of the etching resist layers 38 and 4 can be performed in the same manner as the stripping of the resist layer i 6 . The first conductive layer 36 after the upper rhombic includes the routing line 42. Therefore, the routing line 42 is protected by the patterned side resist layer 4 该 of the second conductive layer 36. In addition, the routing line 42 is a copper line that contacts the dielectric layer 34 and extends below it.

The substrate 30 has a through hole 44 as shown in Figs. 3E, 3F and 3GH. The through hole 44 is a central window penetrating the substrate 30, and the first conductive layer 32 and the dielectric layer 34 are mechanically drilled through (only the second conductive layer 3 6 is not included). Since the layer has been removed from this region by wet chemical silver etching, the through hole 44 has a diameter of 1150 μm. In this case, the through hole 44 can also be formed by other techniques, such as punching and punching. Preferably, the opening 2 8 and the through hole 44 have a ridge and are formed in the same manner on the same rig by the same drill. The substrate 30 is here shown as a laminated structure, but the substrate 3 can also be other multilayer electrical connectors such as ceramic tape or printed circuit boards. Similarly, the substrate 25 0 21 21 21 21 may additionally comprise a plurality of layers of embedded circuits. Please refer to FIG. 4A to FIG. 40 for a structure for fabricating a heat conducting plate according to a preferred embodiment of the present invention—Wei _, a structure of a heat conducting plate according to a preferred embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a schematic cross-sectional view showing a structure of a heat conducting plate in a preferred embodiment, a fourth cross-sectional view showing a structure for fabricating a heat conducting plate in a preferred embodiment, and a heat conducting plate formed in a preferred embodiment of the present invention. 5 is a cross-sectional view of the structure, the present invention is a structure of a heat-conducting plate made of a preferred embodiment, and the structure of the heat-conducting plate is shown in FIG. The structure of the hot plate of the preferred embodiment is not shown in the figure; t, the invention, the structure of the preferred embodiment of the hot plate of the present invention is a cross-sectional view of the structure, and the present invention is made in the preferred embodiment. STRUCTURE OF THE STRUCTURE OF THE INVENTION, STRUCTURE OF THE INVENTION, STRUCTURE OF THE PRODUCTION THERMAL PLATE, STRUCTURE OF THE INVENTION - Structure of the heat conducting plate in the preferred embodiment FIG, schematic plan view of a first 4M®, 4_ bottom view of the second. As shown in the figure, the heat conducting plate of the present invention comprises the record 2, the susceptor 24, the adhesive layer 26 and the substrate 30. Wherein the adhesive layer 26 is disposed on the pedestal 2 4 as shown in FIG. 4A, the adhesive layer 26 is lowered onto the pedestal 2 &amp; •, the stud 22 is inserted upward and penetrates the The opening 28, wherein the adhesive layer 26 is in contact with and positioned at the center of the base 2, the post 2 2 is located in the center of the opening 28 after being inserted and penetrated through the opening 202 without contact The adhesive layer is 26. The substrate 30 is disposed on the adhesive layer 26 as shown in Fig. 4B. The substrate 30 is lowered onto the adhesive layer 26, and the stud 2 2 is inserted upwardly and penetrates the through hole 44. The substrate 3 (10) is positioned and positioned on the adhesive layer 26 201121004. Preferably, the stud 22 is in a central position within the through hole 44 after being inserted and penetrated through the through hole 44 without contacting the substrate 3◦. Therefore, a gap 46 is formed in the through hole 44 and between the pillar 2 2 and the substrate 30. The notch 4 6 laterally surrounds the stud 2 2 while being laterally surrounded by the substrate 3 〇. Further, the opening 28 and the through hole 44 are aligned with each other and have the same diameter. At this time, the substrate 30 is disposed on and in contact with the adhesive layer 26 and extends over the adhesive layer 26. The stud 2 2 extends through the opening 28 into the through hole 44 and to the dielectric layer 34. The studs 2 2 are 60 microns lower than the top surface of the first conductive layer 32 and are exposed outwardly through the through holes 44. The adhesive layer 26 contacts the pedestal 24 and the substrate 30 and is between the two, but is spaced apart from the dielectric layer 34. At this stage, the adhesive layer 26 is still a film of a B-stage uncured epoxy resin, and the gap 46 is air. The adhesive layer 26 is heated and pressurized and flows into the notch 46 as shown in Fig. 4C. The method of forcing the adhesive layer 26 into the notch 46 is to apply the first conductive layer 3 2 . Lowering the pressure and/or applying an upward pressure to the susceptor 24, that is, pressing the susceptor 24 against the substrate 30, thereby pressing the adhesive layer 26; at the same time, the adhesive layer 2 6 heating. The heated adhesive layer 26 can be arbitrarily formed under pressure. Therefore, after the adhesive layer 26 between the susceptor 24 and the substrate 3 is pressed, the original shape is changed and flows upward. The gap 46. The base 24 and the substrate 30 are still pressed toward each other until the adhesive layer 26 fills the gap 46. Further, between the base 24 and the substrate 30 After the gap is reduced, the adhesive layer 26 is still filled in the narrowed gap. For example, the pedestal 24 and the first conductive layer 3 2 can be placed on a press machine and pressed down. Between the table (not shown), and an upper baffle and an upper buffer paper (not shown) are placed on the first conductive layer 32 and Between the stages, the lower baffle and the lower cushioning paper (not shown) are sandwiched between the base 24 and the lower pressing table. The stacked body is composed of the upper pressing platform from top to bottom. Upper baffle, upper baffle, substrate 30, adhesive layer 26, pedestal 24, lower cushioning paper, lower baffle and lower pressing table. Further, it is possible to extend upward from the lower pressing table and pass through the pedestal 2 4 a tool pin (not shown) of the bit hole (not shown) positions the stack on the lower press table. Then, the upper and lower press tables are heated and pushed each other, thereby bonding the adhesive layer 2 6 heating and pressing, wherein the heat of the pressing table is dispersed by a baffle, so that heat is evenly applied to the base 24 and the substrate 30 or even the adhesive layer 26. The buffer paper presses the pressure of the pressing table. Dispersing, uniformly applying pressure to the susceptor 24 and the substrate 3 or even the adhesive layer 26. Initially, the second conductive layer 36 extends into the adhesive layer 26 and is embedded therein, resulting in the dielectric layer. 3 4 is contacted and pressed against the adhesive layer 26. The adhesive layer 26 between the base 24 and the substrate 3 is squeezed and opened as the platen continues to operate and continues to heat. Melting, thus flowing upward into the gap 46, through the dielectric layer 34, finally reaching the first conductive layer 32. For example, the uncured epoxy resin is melted into the gap 46 after being melted by heat, However, the reinforcing material and the filler remain between the base 24 and the substrate 30. The adhesive layer 26 rises faster in the through hole 44 than the stud 22, and finally fills the gap. 4 6. The adhesive layer 26 also rises to a position slightly higher than the gap 46, and overflows to the top surface of the pillar 2 2 and the top surface of the first conductive layer 3 2 before the pressure stop stops. Adjacent to the notch 46, this may occur if the film thickness is slightly larger than actually needed. In this way, the adhesive layer 26 forms a thin layer of cover on the top surface of the pillar 2 2 . The pressing table stops moving after touching the studs 2 2 , but continues to heat the adhesive layer 26 . The direction in which the adhesive layer 26 flows upward in the notch 46 is as shown by the upward bold arrow in the figure, and the protrusion 2 2 and the pedestal 2 4 move upward relative to the substrate 3, such as a fine arrow. As shown, the downward movement of the substrate 3 〇 relative to the stud 2 2 and the pedestal 24 is as indicated by the downwardly thin arrow. The adhesive layer 26 in Figure 4D has cured. For example, after the platen stops moving, the post 2 2 and the base 24 are continuously clamped and heated, thereby converting the condensed B-stage epoxy resin into a c-stage curing or hardening ring. Oxygen resin. Therefore, the epoxy resin is cured in a manner similar to conventional lamination. After the epoxy resin is cured, the press table is separated 'to remove the structure from the press. The cured adhesive layer 26 provides a strong mechanical bond between the stud 2 2 and the substrate 3 ^ between the pedestal 24 and the substrate 3 。. The adhesive layer 26 can withstand the normal operating pressure without deformation and damage, and is only temporarily distorted when the pressure is too large; and the adhesive layer 26 can also absorb the between the protrusion 2 2 and the substrate 30 and The thermal expansion between the susceptor 2 4 and the substrate 30 does not match. At this stage, the studs 2 2 are substantially coplanar with the first conductive layer 32, and the adhesive layer 26 and the first conductive layer 32 extend to a top surface in the upward direction. For example, the adhesion layer 26 between the pedestal 24 and the second conductive layer 36 is 90 micrometers thicker than the initial thickness ls 〇 micrometer by 0 〇 micrometer, and the pillar 2 2 is in the through hole 44. The substrate is raised by 60 microns, and the substrate 3 is lowered by 6G microns with respect to the column 2 2 . The height of the pillar 2 2 is substantially equal to the first conductive layer 32 (30 micrometers), the dielectric layer 34 (10) micrometers, the second conductive layer 3 6 (3 micrometers), and the adhesive layer 26 (9) below. The combined height of micron). In addition, the protrusion 2 2 is still at the center of the through hole 28 and the through hole 4 29 201121004 4 and is kept away from the substrate 3 , and the adhesive layer 26 fills the base 24 and the substrate 3 0 . The space between the spaces fills the gap 46. For example, the notch 46 (and the adhesive layer 26 between the stud 22 and the substrate 30) is 75 microns ((1150-1000)/2) wide at the top surface of the stud 2 2 . The adhesive layer 26 extends across the dielectric layer 34 in the gap 46. In other words, the adhesive layer 26 of the notch 46 extends in the upward direction and a downward direction and spans the thickness of the dielectric layer 34 of the outer sidewall of the notch 46. The adhesive layer 26 also includes a thin top portion \\ above the notch 46 which contacts the top surface of the stud 2 2 and the first conductive reed 32 and extends 1 〇 micron above the stud 2 2 .除去 Remove the stud 2 2, the hybrid layer 26 and the first guide 3 2 as shown in Fig. 4. The top of the stud 2 2 and the conductive layer 3 2 of the shell 4 is removed by grinding, for example, "the thickness of the adhesive layer 26 is reduced due to the downward movement of the surface to be ground." Grinding the stud 22 and the first '2; not: after the same grinding, the stud 2 2, the layer of the layer is continuously moved to the surface to be thinned. The thickness is reduced by the rinsing of the structure by the distilled water. The drying step is followed by steaming the grinding step to grind the top of the stick 2 to the top of the stud 2 2 to remove 25 m. Go to 15 μm. ^ f card 'and the effect of the top 6 of the first conductive layer 3 2 is not obvious, but 2 or the adhesive layer 2 meters is greatly reduced to 15 microns. Domain, the thickness of the protrusion ^ 3 2 From the 3 〇 micro, the first _ 3 2 paste 、, = layer 2 6 and 4 tens of thousands of faces toward the [s] 30 201121004 up direction smooth splicing side top surface.

The structural system as shown in Fig. 4F has holes 4 8 and 5 〇. The hole 48 is a blind hole extending through the first conductive layer 32 and the dielectric layer 34 to the routing line 42 except for a distance from the adhesive layer 26. The hole 5 〇 is also a blind hole extending through the pedestal 24 and the adhesive layer 26 to the routing line 42 but spaced apart from the dielectric layer 34. The holes 48, 5〇 are formed by laser drilling, but can be combined with other techniques such as mechanical drilling and plasma etching. The hole 4 8 , 5 can have a tapered sidewall and a diameter decreasing with depth, but for convenience of illustration, the holes 4 8 , 50 in the drawing have vertical sidewalls and a fixed diameter. . The structure shown in Fig. 4G has a third conductive layer 5.2, a fourth conductive layer 54, a first conductive via 56 and a second conductive via 58. The third conductive layer 52 is deposited on and in contact with the stud 2 2, the adhesive layer 26 and the first conductive layer 32. From the top, the stud 2 2, the adhesive layer 26 and the first conductive layer 32 are covered. The third conductive layer 52 is a copper layer having a pattern of 15 μm thick and integrally formed with the first conductive via. The fourth conductive layer 54 is deposited on the bottom surface of the susceptor 24 and is in contact with the disk while covering the pedestal 24 from below. Wherein, the first electrically conductive layer 54 is a non-patterned and 15 micron thick, and integrated with the second conductive via 58. The first conductive via 56 extends from the first conductive layer 32 into the hole. 4 8. The first conductive vias 56 are deposited on the dielectric layer 34 and the routing line 42 in the holes 48 and are in contact therewith. Wherein, the first conductive via 56 is a covered via, which can electrically charge the first and third conductive layers 3 2, 5 2

S 31 201121004 is sexually linked to the routing line 4 2 . The second conductive via 58 extends from the pedestal 24 into the hole 50. The second conductive via 58 is deposited in the hole 50 and on the routing layer 2 6 and the routing line 42. And contact with it. The second conductive via 58 is a through-hole that is electrically covered, and the pedestal 24 and the fourth conductive layer 504 are electrically connected to the routing line 42. For example, the structure can be immersed in an activator solution, so that the hole 'is the same as 48, 5 G, and then the dielectric layer 34 and the hybrid layer 26 can react with the electroless copper, and then A first copper layer is disposed on the stud 2 2, the Wei seat 24, the adhesive layer 26, the first conductive layer 3 2, and the routing line 4 2 (on the reverse side of the structure) And the sidewalls t of the holes 4 8 and 5 , and then a second copper layer is electrically deposited on the first copper layer. The second copper layer is about 13 microns thick, so that the total thickness of the copper layer is covered. In this way, the thickness of the first conductive layer 32 is increased by (25+15)', and after the steps of removing the photoresist layer and clearing 2 are completed, the first conductive layer 3 2 The thickness will be reduced to about 30 microns; the thickness of the base 24 is increased to about 55 microns ((4) 5 yuan = light: layer and cleaning steps, the thickness of the meter. - Conduction = electricity = as the bump 22-- and the 4th-: 2nd:: electric see 54 is the base 2 豕 the first and second conductive holes 565 are formed in 3=8, 5Q. For convenience of explanation, the base 2 4 , ^ = 7? The electrical layers 32, 36, 52, 54 and the second ... two conductive two = = are displayed in a single layer. Since the surface is _ covering, the boundary of the pillar is 52, the pedestal 2 4 The boundary between the fourth conductive layer 54 and the 201121004, and the boundary between the first conductive layer 32 and the third conductive layer 52 (both in phantom) may be difficult to detect or even detect. The boundary between the adhesive layer 26 and the third conductive layer 52 is adjacent to the pillar 2 2 . The impurity layer 'the dielectric layer 34 and the first conductive hole 56 are within the hole 48 a boundary line, and the adhesive layer 26 and the second The boundary of the hole 5 8 in the hole 50 is also clearly visible. Moreover, for convenience of illustration, the first and second conductive holes 5 6 , 58 are shown in the drawings to fill the hole 4 8 , 5 The pillars of the crucible are not hollow tubes. On the lower surface of the 7F structure in Fig. 4, the patterned silver etching resist layers 60 and 62 are assigned. The photoresist layer 6 is similar to the photoresist layer of the resist layer 16 and 40. The side resist layer 6 is provided with a pattern for selectively exposing the third conductive layer 52. The etching layer 6 2 is provided with a pattern for selectively exposing the fourth conductive layer 54. In the structure shown in Fig. 4I, the first and third conductive layers 3 2, 5 2 have been removed by etching. The selected portion is patterned to form a patterned etch stop layer 6 ;; the pedestal 24 and the thin conductive layer 504 are also removed by removing portions of the selected portion to form a patterned etch stop layer 6 2 The pattern is similar to the wet chemical etching applied to the front and back sides of the metal sheet. For example, an upper nozzle and a lower nozzle (not shown) may be utilized. The chemical etching liquid spray is applied to the top surface and the bottom surface of the structure, or the structure is immersed in the chemical surname liquid. The first and third conductive layers 3 2, 5 2 are penetrated through the chemical etching liquid to expose the Adhesive layer 26 and the dielectric layer 34, thereby converting the originally unpatterned first and third conductive layers 32, 52 into a pattern layer, wherein the chemical etching solution penetrates the pedestal 2 and corrects The fourth conductive layer 5 4 exposes the adhesive layer 26. 6. In the fourth figure, the patterned etched layers 6 〇 and 6 2 on the structure are removed, and the removal method can remove the residual Resistance layer

the same. The first and third conductive layers 3 2, 5 2 include a solder wire 6 4 and a routing line 6 6 ' and the remaining third conductive layer 5 2 includes a cover body 6 8 . The bonding pad 64 and the routing line 66 are the portions of the first and third conductive layers 3 2, 5 2 and the patterned hexa barrier layer 6 〇 protected, and the cover body 6 is not removed. 8

^ The third conductive layer 52 is protected by the _ _ resistive layer 60 and is not etched. Therefore, the first and third conductive layers 3 2, 5 2 become the pattern 曰 'the solder pad 64 and the routing line 66 are included but the cover body 6 is not included. Moreover, the far-distance route 6 6 is a copper wire. Contacting the dielectric layer 34 and extending over it _ abuttingly connecting the first conductive via 56 and the solder bump 6 4 〇 after etching the pedestal 24 and the fourth conductive layer 54 including the pedestal And the terminal 70, wherein the central portion of the susceptor 24 is covered by the fourth conductive layer 514 from below (hereinafter collectively referred to as the pedestal 2 4/5 4 ). The pedestal 2 4/5 4 is protected by the patterned etched layer 6 2 and the fourth conductive layer 504 by a patterned etched layer 6 2 , which extends laterally beyond the stud 2 ^ 外诵微米. The terminal 7 is protected by the pedestal 24 and the patterned side resist layer 6 2 of the fourth conductive layer 4, and is connected to the adhesive layer 26 and extends below it. The susceptor 2 is still perceived as a non-patterned layer, but is formed outside the periphery of the pedestal 2 4 - a patterned layer comprising the terminal 7 保持 and maintaining a lateral spacing from the pedestal 24. Therefore, the terminal 7 〇 and the pedestal 24 are separated from each other, and the terminal 7 〇 is no longer the pedestal 2 4; In addition, the second conductive via 58 is adjacent to the terminal 7 and forms an electrical connection between the routing line 34 [S] 201121004 42 and the terminal 70. The routing lines 4 2 and 6 6 , the first and second conductive vias 5 6 and 58 , the bonding pad 64 and the terminal 70 together form a wire 7 2 . Similarly, a conductive path between the pad 6 4 and the terminal 70 sequentially passes through the routing line 66, the first conductive via 56, the routing line 4 2, and the second conductive via 58 ( vice versa). The wire 7 2 provides a vertical (top to bottom) route from the pad 64 to the terminal 70, and the wire 72 is not limited to this configuration. For example, the pad 6 4 may be directly formed on the wire. The first conductive via 56 is above, thereby omitting the routing line 6 6; and the second conductive via 58 is through a routing line defined by the patterned etched layer 6 2 under the adhesive layer 26 Electrically connected to the terminal 70. Furthermore, the conductive paths may include other conductive and routing lines (which are located in the first, first, and/or other conductive layers) and passive components, such as resistors and capacitors disposed on other solder pads. The heat sink 7 is constituted by the above-mentioned stud 2 2, the pedestal 2 4/5 4 and the cover Θ 8 . The protrusion 2 2 is integrally formed with the base 2 4/5 4 , and the cover 68 is located above the top of the protrusion 2 2 adjacent to the top of the protrusion 2 2 while covering the top from the top. The top of the stud 2 2 and from the top of the stud 2 2 extend laterally. After the cover body 6 8 is disposed, the protrusion 2 2 is located in the towel center area of the circumference of the cover body 6 8 . The cover body 6 8 also contacts from above and covers the portion of the adhesive layer 26 6 below it. The portion of the adhesive layer 26 is coplanar with the stud 2 2 adjacent to the stud 22 while laterally surrounding the stud 22. The heat dissipating block 74 is substantially an inverted-chat-shaped heat dissipating block, and includes a column portion (ie, a stud 2 2 ), a wing portion (ie, a portion of the pedestal 2 4/5 4 extending laterally from the column portion), and a Thermal pad (ie cover 6 8). In the structure shown in FIG. 4K, a first solder resist green paint 7 6 is disposed on the dielectric layer 34, the third conductive layer 35 201121004, the electrical layer 5 2 and the cover 6 8 . A second solder resist green paint 7 8 is also disposed on the base 2 4/5 4 , the adhesive layer 26 and the terminal 70 . Wherein, the first solder resist green paint 7 6 is an electrical insulating layer, which can be patterned according to the choice of the person to expose the solder pad 64 and the cover body β 8 and cover the dielectric layer 34 from above. Exposed part with the routing line 6 6 . The first solder resist green paint 7 6 has a thickness of 25 micrometers above the solder bumps 6 4 , and the first solder resist green paint 7 6 extends 55 micrometers (30+25 ) above the dielectric layer 34 . And the second solder resist green paint 7 8 is an electrical insulating layer, which can be patterned according to the choice of the person to expose the base 2 4 / 5 4 and the terminal 7 〇, and cover the adhesive layer 2 from below 6 exposed parts. The second solder resist green paint 7 8 has a thickness of 25 micrometers below the terminal 70, and the second solder resist green paint 7 extends 70 micrometers (45+25) below the adhesive layer 26. The first and first anti-welding green paints 7 6 and 7 8 are initially coated with a light-developing liquid resin on the structure, and then patterned on the first and second solder resist green paints γ 6 , 78 . The method is such that the light is selectively transmitted through the reticle (not shown), and then the developing portion is used to remove the soluble portion of the first and second solder resist green paints 7, 6 and 7 and finally hard baked. The steps are known techniques. In the structure shown in Fig. 4L, a covered contact 8 is provided on the susceptor 2 4/5 4, the pad 64, the cover 68 and the terminal 7 〇. The cover contact 80 is a multi-layer metal money layer, which contacts the solder pad 6 4 from above and the cover body 6 8 simultaneously covers the exposed portion thereof, and contacts the base 2 bucket / 5 4 from below Terminal 70 also covers its exposed portion. For example, a nickel layer is provided on the susceptor 2 4/5 4 , the pad 6 4 , the cover body 6 8 and the terminal 70 in an electroless plating manner, and then a gold layer is used as an electroless ore. The coating is disposed on the nickel layer, wherein the inner nickel layer is about 3 micrometers thick, and the surface gold layer is about 365 36 201121004 micrometers, so the thickness of the covered joint 8 Q is about 35 micrometers. The above-mentioned point of attack is 8 〇 as the county seat 2 is still 4, 4, the cover body 6 8 and the terminal 7 〇 + ° the surface of the person's face at the county has the advantage of money, the package I and the day provide the main machinery And bonding and/or thermal bonding, and = layer, a wettable surface for solder reflow; the covered contact 8 2 2 4 / 5 4, the soldering 塾 64, the cover 6.8 and the Terminal 7 0 is not occupied; and the service contact 8 Q can contain various metals to match the outside

Introduce the need. For example, the silver layer covered on _ can be matched with solder or wire. For convenience of explanation, the pedestal 2 4 /5 4 , the solder 塾 6 4 , the cover 6 8 and the terminal 7 设有 provided with the covered contact 8 显 are all displayed in a single-layer manner, and the covered The boundary between the point 8 〇 and the base 2 4/5 4 'the soldering ring 6 4 , the cover body 6 8 and the terminal 7 ( (not shown) is a copper/recording interface. So far, the fabrication of a heat conducting plate 8 2 has been completed. The edge of the heat conducting plate 82 has been separated from the branch frame and/or the adjacent heat conducting plates of the same batch along the cutting line as shown in Figures 4M, 4N and 40. The heat conducting plate 8 2 includes the pedestal 2 4/5 4 , the adhesive layer 26 , the substrate 3 〇 , , such as the sub 70 , the heat sink 7 4 , and the first and second bismuth green paint 7 6 . 7 8. The substrate 30 includes the dielectric layer 34, the routing lines 4 2, 6 β, the first conductive vias 56 and the bonding pads 64; the heat sink 7 4 includes the protruding posts 2 2 Base 2 4/5 4 and s-cover 6 8 . The wire 7 2 is composed of the routing wires 4 2, 66, the first and second conductive holes 56, 58, the pad 64 and the terminal 70. The post 2 2 extends through the opening 28 and enters the through hole 44 , and is still located at the center of the opening 28 and the through hole 44 , and is located at the dielectric layer 3 with the adhesive layer 26 . One of the adjacent portions above 4 is coplanar. The stud 2 2 holds 37 201121004 ===, which tapers the wall such that its diameter decreases from the base 2 4/5 4 toward the flat dome of the neighbor f. The base 2 4/5 4 is spaced from the lower cover & is spaced from the edge of the heat conducting plate 8 2 . The β β4 stud 2 2 is adjacent to and thermally coupled, and the cover covers the top of the stud 22 from above and extends from the top of the stud 2 2 . The cover body 6 8 also contacts from above and covers the adhesive layer 2 6 ′. The portion of the adhesive layer 26 is adjacent to the protrusion 2 2 , and the protrusion column

2 2, planar, and laterally surrounding the stud 2 2 . The cover 8 is also ten-sided with the soldering iron D 4 . The adhesive layer 26 is disposed on and extended over the county seat 4 4/5 4 . The adhesive layer 26 contacts and the space between the pillars 2 2 and the dielectric layer 34 is used to fill the space between the pillars 2 2 and the dielectric layer 34. In addition, the adhesive layer 26 is also in contact with and between the pedestal 2 4/5 4 and the substrate 3 以 to fill the middle (4). The adhesive layer 26 simultaneously covers and circulates the stud 22 in the lateral direction, and the adhesive layer 26 is cured. The substrate 30 is disposed on and in contact with the adhesive layer 26, and also extends over the lower adhesive layer 26 and the base 2 4/5 4; wherein the first conductive layer 3 2 (and the pad 64 and the routing line 6 6 are in contact with and extending over the electrical layer 34; the dielectric layer 34 contacts the second conductive layer 36 (comprising the routing line 4 2) and Extending above it, and the dielectric #3: is between the first and second conductive layers 32, 36; the second conductive electrical layer = including the routing line 4 2 ) contacts the adhesive layer 26 and is embedded Set it. The protrusion 2 2, the pedestal 2 4/5 4 and the cover 6 8 are all kept at a distance from the substrate 30. Therefore, the substrate 30 is mechanically connected to the heat sinks 7 and electrically isolated from each other. 38 201121004 The heat-transfer plate 8 2 produced in the same batch is cut, and the adhesive layer 26, the dielectric layer 34 and the first and second solder resist green paints 7 6 and 7 8 are extended to the vertical edge of the cut. . The pad 64 is an electrical interface tailored to a semiconductor component such as a semiconductor wafer, and the semiconductor component is disposed on the cover 6 8 in a subsequent process. The terminal 70 is an electrical interface tailored to the next layer of the body. For example, the next layer can be a printed circuit board, and the heat conducting plate 82 is disposed on the printed circuit board in a subsequent process. on. The cover 68 is a thermal interface tailored to the semiconductor component. The pedestal 2 4/5 4 is a thermal interface tailored to the printed circuit board. Further, the cover body 6 is thermally coupled to the base 2 4/5 4 via the studs 2 2 . The solder bumps 6 4 are offset from the terminals 70 in the vertical direction and exposed to the top and bottom surfaces of the heat conducting plate 82, thereby providing a vertical route between the semiconductor component and the next layer. The top surface of the soldering pad 64 and the cover body 6 8 above the μ electrical layer 34 is coplanar with each other, and the bottom surface of the bottom plate 4 and the terminal 70 located below the adhesive layer 26 are also mutually Coplanar. For convenience of explanation, the wire 72 is shown as a continuous circuit trace in a cross-sectional view; however, the wire 72 generally provides horizontal signal routing in the X and γ directions, that is, the pad 6 4 The terminals 70 are laterally offset from each other in the X and γ directions and the routing lines 4 2 and 6 6 respectively or together form a path of the 乂 and ^ directions. The heat sink 74 can diffuse thermal energy generated by the semiconductor component subsequently disposed on the cover 68 to the lower layer of the base 2 4/5 4 . The cover member 6 8 generated by the semiconductor component enters the stud 2 2 from the cover body 2 and enters the pedestal 2 4/5 4 via the stud 2 2 . 39 201121004 Thermal energy is dissipated from the pedestal 2 4/5 4 in the downward direction, for example, to the lower heat sink. Similarly, the heat sink 74 can also diffuse thermal energy generated by the semiconductor components subsequently disposed on the susceptor 2 4/5 4 to a lower group to which the cover 68 is connected. The protrusions 2 2 of the heat conducting plate 8 2, the first and second conductive holes 5 6 and 58 or the routing lines 4 2 and 6 6 are not exposed. The protrusions 2 2 are covered by the cover body 68, and the first and second conductive holes 5 6 and 58 and the routing wires 4 2 and 6 6 are covered by the first anti-welding green paint 7 6 . The top surface of the layer 26 is simultaneously covered by the cover 68 and the first solder resist green paint 76. For convenience of description, the pillar 2 2, the adhesive layer 26, the first and second conductive holes 5 6 and 58 and the routing lines 4 2 and 6 6 will be shown in broken lines in the 4N figure. The heat conducting plate 82 also includes other wires 72. The wires 72 are basically composed of the first and second conductive holes 56, 58, the routing wires 42 and 66, the pad 64 and the terminal 7. The crucible is configured to have a plurality of conductive paths between the pad 64 and the terminal 70. For convenience of explanation, only the single wire 7 2 will be illustrated and illustrated herein. In the wire 7 2 , the first and second conductive holes 5 6 , 58 , the pad 6 4 and the terminal 70 generally have the same shape and size, and the routing lines 4 2 and 6 6 are generally used. Different routing configurations. For example, some of the wires 7 2 are provided with a pitch, separated from each other, and are electrically isolated, and a part of the wires 7 2 are staggered or directed to the same pad 6 4 , routing lines 4 2, 6 6 or terminals 7 link. Similarly, a portion of the pads 64 can be used to receive an independent signal and a portion of the pads 6 4 share a signal, power or ground. In addition, a portion of the wire 72 may include the routing wire 42 and the first and second conductive holes 56, 58 to provide a multilayer routing 'and the partial wire 72 does not include the routing wire 42 and the first and second The conductive holes 5 6 , 5 8 and only the first conductive layer 32 provide a single 201121004 layer routing. The structure of the far heat conducting plate 8 2 can be adjusted to be used with a plurality of wafers so that the respective input/output signals are guided from the individual glow pads 64 to the individual terminals 7 〇, and the pads 64 are oriented at the same time when grounded. — Ground terminal 7〇.

At each stage of manufacture, the cleaning step can be carried out by removing the oxide and the material on the exposed metal. For example, the present invention can be used for a short-term oxygen polymerization cleaning step. Or, can be _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Similarly, it is also possible to remove the soil when the structure of the present invention is rinsed with fine water. This cleaning step cleans the surface without causing significant damage or damage to the structure. An advantage of the present invention is that the wire does not require separation or separation of the confluence point or associated circuitry from the towel. The junction point may be formed by the wet soldering of the soldering ring 64, the =6, the cover 68 and the terminal 7 步骤. The heat conducting plate 8 2 may include drilling or cutting through the adhesive layer 2 6. The substrate 3 is aligned with the first and second solder resist green paints 76 and 78 (not shown). In this way, when the heat conducting plate 8 is not required to be disposed in the subsequent carrier in the subsequent process, the tool pin can be inserted into the matching hole to position the bar 2 . &amp; The heat conducting plate 82 can omit the cover 68. To achieve this purpose, the etch resist layer 6 图案 can be patterned so that the third conductive layer 2 over the entire via hole 44 is exposed to the chemical etching Φ for forming the pad 6 4 and the routing line 6 6 . . The heat conducting plate 8 2 can accommodate a plurality of semiconductor elements and not only a single conductor element. To achieve this - the purpose of the 'adjustable patterning' layer 6 to define more of the protrusions 2 2, 201121004, adjust the adhesive layer 26 to include more openings 2 8, adjust the substrate 30 to include more Hole 44, 赃 patterned side resist layer 4 〇 to define more routing lines 4 2 , thinned side resist layers 6 〇 and 6 2 to define more solder 塾 6 4 , routing line 6 6 , cover 6 8 and terminal 70, and adjust the first and second solder resist green paints 7 6 and 7 8 to include more openings. Similarly, the substrate 30 can also include more routing lines 4 2 and conductive holes 56 and 58. Elements other than the die 70 can change the lateral position to provide a -2x2 array for the four semiconductor components. In addition, some but not all of the cross-sectional shapes and heights (ie, side shapes) may be adjusted. For example, the pad 64, the cover 68 and the terminal 7 can maintain the same side shape, and the routing lines 42 and 66 have different routing configurations. Referring to FIG. 5A to FIG. 5C, respectively, a semiconductor crystal according to a preferred embodiment of the present invention, a group cage, and a semiconductor crystal of the preferred embodiment of the present invention. A schematic top view of the assembly and a bottom view of the semiconductor wafer assembly of the preferred embodiment of the invention. As a thief shows: This implementation of the semiconductor component is &amp; the wafer placed on the cover. The wafer is superposed on the stud and electrically connected to the pad, and is electrically connected to the terminal. The wafer is simultaneously thermally coupled to the cover to form a thermal connection with the secret base. The semiconductor wafer package body 1◦0 of the embodiment comprises a heat conducting plate 8.2, a semiconductor wafer 1〇2, a wire bonding process 4, a die bonding material workpiece 6 and a packaging material 1 〇8, and The semiconductor wafer 1 〇 2 includes a top surface 1 1Q, a bottom surface 112 and a wire bonding interface 114, wherein the top surface 1 1 is an active surface and includes the wire bonding pad 1 1 4 , and the bottom surface Ί 2 is the thermal contact surface. The semiconductor wafer 102 is disposed on the heat sink 74, electrically connected to the substrate 3, and thermally coupled to the heat sink 7. In detail, the semiconductor body 1 〇 2 is disposed on the cover body 68, and is disposed on the periphery of the cover body 曰 曰 曰 曰 曰 。 。 。 。 。 。 。 。 。 。 。 。. Further, when the semiconductor sheet 1 〇 2 is electrically connected to the substrate 37 via the bonding wires 1 〇 4, the solid bonding material 丨Q6 is thermally bonded to the heat dissipation 4 . For example, the wire 丄〇 4 is connected and electrically connected to the pad 6 4 and the wire contact i i 4 , which electrically connects the semiconductor wafer i Q 2 to the = terminal, 70. Similarly, the bonding device 6 is in contact with and located between the cover 6 and the thermal contact surface 1 1 2, and is bonded to the cover 68 and the thermal contact surface by the bonding domain! ! 2, whereby the semiconductor wafer 2 is thermally coupled to the susceptor 24. The pad 6 4 is provided with a nickel/silver coated metal pad to facilitate the unloading of the wire 1 〇 4 stable county, and the transfer from the county plate 3 to the semiconductor crystal #1 0 2 is transmitted. In addition, the shape and size of the difficult body 68 is adapted to the thermal contact surface 1 i 2 to improve heat transfer from the semiconductor wafer 0 to the heat sink 74.忒Encapsulation material 1〇8 is a solid compressible protective plastic coating ’ can be the semiconductor wafer! 〇 2 and the line 1〇 4 provide environmental protection against tidal and anti-particles. The semiconductor wafer process 2 and the wire bonding process 4 are embedded in the package material 1 〇 8 . Moreover, if the semiconductor wafer 1 〇 2 is an optical wafer such as an LED, the encapsulation material i 〇 8 may be transparent, in which the encapsulation material 108 is transparent in FIG. 5B for illustration. Description. If the semiconductor wafer assembly 100 is to be fabricated, the semiconductor wafer i 〇 2 may be disposed on the cover 6 8 by using the die bonding material 106, and then the pad 6 4 and the bonding pad 1 1 4 bonding by wire bonding, and then forming the package 3 43 201121004 material 10 8 . The tree is like a material 1 〇 6 was originally - silver-containing epoxy with high thermal conductivity, 6.3 paste. Then _-grab the county-self-purity __ system, Caijin placed on the epoxy resin silver paste; then _ paste, so that it hardens at a relatively low temperature (such as -c)

Two ==, which is then connected to the soldering wire 6 by thermal ultrasonic waves, and then the molded material is electrically connected to the structure by a plurality of connecting media. 6 4 'A variety of thermal adhesives are thermally bonded or mechanically adhered to the dispersion to this point. The semiconductor wafer assembly 1 is a - first-order single crystal package. Please refer to FIG. 6A to FIG. 6C for a schematic cross-sectional view of a semiconductor wafer assembly according to another preferred embodiment of the present invention, and a semi-conductive H-domain top view of another preferred embodiment of the present invention. And a schematic view of the semiconductor crystal body of another preferred embodiment of the present invention. As shown in the figure: The semiconductor wafer in this embodiment is disposed on the pedestal _ on the cover. The wafer is overlapped by the studs and electrically connected to the _ terminal for electrical connection with the squeegee, and (4) thermally coupled to the pedestal to form a junction with the cover. *', for the sake of brevity, the descriptions relating to the group 1〇〇 (please refer to the pictures shown in Figures 5A to 5C) apply to this embodiment, and the same description will not be repeated. . Similarly, the components of the group of the embodiment are similar to those of the component of the group, and the corresponding reference numerals are used, but the base number of the code is changed from J 2 to 2 44 201121004 0 0 °, for example, 'semiconductor wafer 2 0 2 corresponds to the semiconductor wafer 1 〇 2, and the wiring 2 0 4 corresponds to the wiring 1Q 4 , and so on. The semiconductor wafer package 2 of the present embodiment comprises a heat conducting plate 8 2 , a semiconductor wafer 2 0 2 , a bonding wire 2 0 4 , a solid crystal material 2 0 6 and a packaging material 208, and the semiconductor The wafer 2 Q 2 is inverted here and includes (when not inverted) a top surface 210, a bottom surface 212 and a wire bonding interface 2 1 4, wherein the top surface 21 is an active surface and includes the wire bonding pad 214 And the bottom surface 2丄2 is a thermal contact surface. The semiconductor wafer 2 〇 2 is disposed on the heat sink 7 4 , electrically connected to the substrate 3 Q , and thermally coupled to the heat sink 7 4 . In detail, the semiconductor wafer 2 Q 2 is disposed on the susceptor 24 in the periphery of the susceptor 24, and is overlapped by the studs 2 2 but not overlapped by the substrate 3 。. In addition, the semiconductor wafer 2 0 2 is electrically connected to the terminal 7 0 ′ via the bonding wire 2 Q 4 while being thermally coupled via the bonding material 2 〇 6 and mechanically adhered to the heat sink 7 4 such as a shai line The 〇4 series is electrically connected to the wire splicing port 2 1 4 and the terminal 7 Q, thereby electrically connecting the conductor chip 2 Q 2 to the pad 6 4 . Similarly, the solid crystal material 2 〇 6 is located between the susceptor 2 and the thermal contact surface 2 1 2 , while being thermally coupled and mechanically to the pedestal 24 and the thermal contact surface 212 , thereby The semiconductor wafer 2 Q 2 is thermally coupled to the cover 68. Here, the encapsulating material 2 〇 8 is transparent in Fig. 6c for illustration. If the semiconductor wafer package 2 is to be fabricated, the semiconductor wafer 206 can be disposed on the susceptor 24 by using the die bonding material 206, and then the ==4 is bonded to the terminal 70 by wire bonding. Then, the package 201121004 is formed. The semiconductor wafer package 2 is a first-order single crystal package. The semiconductor wafer package and the heat conducting plate described above are merely illustrative examples, and the present invention can be implemented by other various embodiments. In addition, the above embodiments may be used in combination with other embodiments or in combination with other embodiments in consideration of design and reliability. For example, a heat conducting plate having a plurality of studs for mating a plurality of semiconductor wafers, a portion of the wires 72 may include the routing lines 4 2 and 6 6 , the first and second conductive holes 5 6 and 58 , and the terminal 7 0, and the other portion of the wire 7 2 does not include the routing wires 4 2 and 6 6 and the first and second conductive holes 5 6 and 5 8 and does not extend through the adhesive layer 26 or the dielectric layer 34. Similarly, the semiconductor element and the cover may overlap the substrate and the underlying adhesive layer, and the semiconductor device may be overlapped by the substrate. The semiconductor element can use the heat sink alone or share the heat sink with other semiconductor elements. For example, a single semiconductor component can be disposed on the heat sink or a plurality of semiconductor components can be disposed on the heat sink. For example, four small wafers arranged in a 2×2 array can be adhered to the bump. The substrate can then contain additional wires to accommodate the electrical connections of the wafers. This practice is far more economical than setting a tiny stud on each wafer. The semiconductor wafer can be optical or non-optical. For example, the wafer can be an LED, a solar cell, a power die or a controller wafer. In addition, the semiconductor element can be mechanically bonded, electrically connected, and thermally bonded to the thermally conductive plate using a variety of bonding media, including by soldering and using conductive and/or thermally conductive adhesives. The heat sink can quickly, efficiently and uniformly dissipate the thermal energy generated by the semiconductor component to the next layer assembly without passing heat through the adhesive layer, the substrate or the heat conducting plate elsewhere. In this way, an adhesive layer having a lower thermal conductivity can be used, so that 46 201121004 significantly reduces the cost. The heat sink can be made of copper and includes an integrally formed stud and base, and a cover for metallurgical and thermal connection with the stud, thereby improving reliability and reducing cost. The cover may be coplanar with the fuse to electrically, thermally and mechanically bond to the semiconductor component 1. In addition, if the semiconductor component is to be placed on the hot seat, the cover semiconductor component is tailor-made, and the pedestal can be customized according to the next layer, thereby strengthening the self. The semiconductor element is thermally coupled to the lower-layer assembly. For example, the stud may be circular in a lateral plane. The cover may be square or rectangular in a lateral plane, and the side shape of the cover is the same as the side shape of the thermal junction of the semiconductor component. Or similar. Similarly, if the semiconductor component is to be placed under the heat sink, the pedestal can also be tailored to the semiconductor component, and the cover can be customized according to the next layer. - The Hi-Tech hot seat can be electrically or electrically isolated from the 4 semiconductor components and the substrate. For example, a routing line of the third conductive layer may extend through the adhesive layer between the substrate and the cover to electrically connect the shaker element to the heat sink. Then, the heat sink can be electrically grounded, thereby electrically connecting the semiconductor component to the ground. The stud can be deposited on the base or integrally formed with the base. For example, the stud can be formed into a single metal body with the pedestal body, or the stud and the pedestal can comprise a single metal body in its interface and other metals in other parts. The stud may comprise a flat top or top. For example, the stud can be coplanar with the adhesive layer, or the stud can be engraved after the adhesive layer is cured, thereby forming a recess in the adhesive layer above the scud. We can also selectively engrave the studs to form a recess in the stud that extends below its top surface. In the above-mentioned case, the semiconductor component can be disposed on the stud and located in the recess 47 201121004, and the wire can extend to the semiconductor component located in the recess, leaving the cavity after missing Extend to the soldering iron. In this example, the semiconductor element is made of - UD wafers. The recesses focus the LED light toward the upward direction. ',' The pedestal provides mechanical support for the substrate. For example, the susceptor prevents the substrate from being bent and deformed during metal grinding, wafer placement, wire bonding, and molding of the sealing material. In addition, the back of the base may include a piece of material protruding in the downward direction, such as a 'drill-drilling machine to cut the bottom surface of the base to form a lateral groove, and the lateral grooves are bound sheet. In this example, the pedestal has a thickness of 500 microns and the depth of the grooves is 3 Å, i.e., the fins have a degree of 300 microns. Thus, the fins may increase the surface area of the susceptor, and if the slabs are exposed to the air rather than being disposed on the heat sink, the thermal conductivity of the susceptor via heat convection may be enhanced. The cover may be formed by various deposition techniques, including electroplating, electroless plating, evaporation, and sputtering, before, during, or after the bonding of the bonding layer, including plating, electroless plating, evaporation, and sputtering. Multi-layer structure. The cover body can be made of the same metal material as the protrusion. In addition, the cover may extend across the through hole and reach the substrate or be maintained within the circumference of the through hole. Therefore, the cover can contact or be spaced from the substrate. In either case, the cover extends laterally from the top of the stud in the lateral direction. The adhesive layer provides a strong mechanical bond between the heat sink and the substrate. For example, the adhesive layer can fill the space between the heat sink and the substrate, the adhesive layer can be located in the space, and the adhesive layer can be a non-porous structure with a uniformly distributed bonding line. A mismatch caused by thermal expansion between the heat sink and the substrate is absorbed. In addition, the adhesive layer can be a low cost dielectric and does not require high thermal conductivity. Furthermore, the adhesive layer is not easily delaminated. 48 201121004. The thickness of the hybrid (4) can be adjusted so that the second = all adhesives after curing and / or grinding, if the ideal film thickness can be determined by trial and error. Provides multi-layer signal routing in the x and γ directions to enhance the routing. The pad touches the conductor element and the next package. In addition, the substrate can be a low cost laminate structure and * need to have high thermal conductivity.

The top surface of the body may be coplanar, so that the semiconductor element can be soldered to the heat conducting layer by controlling the degree of 2_. The solder layer and the routing line can be formed on the substrate by the deposition technique = a plurality of deposition techniques, including forming a single layer or a multilayer structure by techniques such as electro-mine, electroless ore, and _. . For example, when the substrate is not placed on the adhesive layer, that is, the first and second conductive layers 0 are formed on the substrate, and the surface treatment of the overlay is 4 (four) soldering and cutting Then or after that. For example, the coating layer can be deposited on the third and fourth conductive layers </ RTI> and then patterned and etched using a patterned layup layer to impart a pattern to the coated layer. The wire may include additional balls, terminals, routing wires and conductive holes, and driven components, and may be of different configurations. The wire can be used as a signal layer, a power layer or a ground layer depending on the purpose of its corresponding semiconductor component pad. The wire may also comprise various conductive metals such as copper, gold, nickel, silver, hexa, tin, mixtures thereof and alloys thereof. Ideal Decheng depends on the nature of the introduction of the foreign materials and on the consideration of guilt. In addition, those skilled in the art should be able to understand that 'in the oblique conductor crystals' {the copper in the group can be pure copper, but usually is 49 201121004 copper-based alloy, such as copper · wrong (99.9% copper) , steel, silver, phosphorus, magnesium (99.7% copper) and copper-tin-iron-phosphorus (99.7% steel), in order to improve mechanical properties such as tensile strength and ductility. In general, the cover, the solder resist green lacquer, the covered contacts, and the second and fourth conductive layers are preferably provided, but may be omitted in some embodiments. The thermal shield can be operated in a single or multiple thermally conductive plates, depending on the manufacturing design. For example, a single-heat conducting plate can be fabricated separately. Alternatively, a single metal plate, a single-adhesive layer, a single-substrate, a single top surface solder resist green lacquer, and a single bottom surface anti-weld green lacquer can be used to simultaneously manufacture multiple thermal plates and then separate. Similarly, for each thermal plate in the same batch, we can also use the single metal plate, single adhesive layer, single-twist, single-top anti-weld green paint and single bottom anti-weld green paint to make batches at the same time. Jobs - semi-navigation pieces of smoke and wires. For example, 'more than 4 fine grooves (10) can be formed on the metal plate to form the base and a plurality of studs; and then an uncured adhesive layer having an opening corresponding to the stud can be disposed on the base. The pillars extend through a corresponding opening; and then the substrate (which has a single-first conductive layer, a single-dielectric layer, a plurality of corresponding corresponding convex pillars, and a new one) The lower routing line is disposed on the adhesive layer 俾 such that each of the studs extends through a corresponding opening and enters into a corresponding through hole; and the rear slab presses the wire base and the substrate against each other to force the adhesive layer Entering a gap between the pillars and the substrate in the through holes and then curing the adhesive layer, and then grinding the pillars, the adhesive layer and the first conductive layer to form a top surface; a plurality of first holes and a plurality of second holes, wherein the first holes penetrate the first conductive layer and the dielectric layer to the routing lines, and the second holes penetrate the base and the adhesive layer to The routing lines; then the third conductive layer is coated on the studs, Adhesive layer and Ε 50 201121004 The fourth conductive layer is coated on the pedestal on the first conductive layer, and a plurality of first conductive holes are respectively disposed on the material, and the plurality of Two conductive holes are respectively disposed in the second holes; then the first and third conductive layers are touched to form a plurality of pads corresponding to the corresponding columns, and the third conductive layer is formed to form a plurality of respectively Corresponding to the cover of the stud, and the side and the fourth conductive layer are formed to form a plurality of terminals respectively corresponding to the studs; then the pp-p solder green paint is placed on the structure, and The first solder resist green paint is patterned to expose the solder (four) body, and the second solder resist scale is placed on the structure body to make the second solder resist green paint pattern, thereby exposing the base The base and the terminals; and then the base, the soldering wires, the terminals and the covers are surface-treated with the covered contacts; and finally the substrate is cut or split at appropriate positions on the peripheral edges of the thermally conductive plates The adhesive layer and the solder resist green paint, so that the individual heat conducting plates are separated from each other "^ Job set format of the body of the semiconductor wafer may be a single group or a plurality of groups thereof, depending on the production design. For example, a single set can be manufactured separately. Or, (4) the batch of the shirt is made of her body, and then the heat-conducting plates are separated - the same is the same; the same is the same, the Ke Xiangxiang navigation parts are linked, reduced and connected to each of the heat-dissipating plates in batch production. . For example, a plurality of solid crystal materials may be separately deposited on a plurality of covers, and then a plurality of wafers are respectively placed on the solid crystal materials, and then the solid crystal materials are simultaneously heated to harden and form a plurality of The crystals are bonded, and then the wafers are wire bonded to the corresponding pads, and then the corresponding package materials are formed on the wafers and the wires, and finally the heat conduction plates are separated one by one. We can separate the heat conducting plates from each other in a single step or in multiple steps. For example, a plurality of heat conducting plates can be batched into a flat plate, and then a plurality of semiconductor elements can be assembled. [201121004 The flat plate, and then the plurality of semiconductor wafer sets formed by the flat plate or a plurality of heat conducting plates can be batched. Subsequently forming a flat plate, and then dividing the plurality of heat conducting plates into a plurality of heat conducting strips, then placing a plurality of the heat conducting strips on the strips, and finally, the plurality of semiconductor wafer stacks of the heat conducting strips Separated by strips into individuals. Also, in points. The second plate can be mechanically cut, laser cut, split or other suitable technology. Thereby, the red sequence of the present invention is highly compliant, and is uniquely spliced, and the combination of the two types of wires, the electric wires, the fresh knots, and the mechanical joints of the present invention can be carried out without the use of expensive tools. Therefore, the k process can greatly increase the yield, yield, and efficiency of the traditional packaging technology. Furthermore, the group in this case is extremely suitable for steel wafers and error-free environmental requirements. As used herein, the term "adjacent" means that the elements are formed without being _ or not. For example, the convex = ""the earthen seat" is independent of the addition or reduction method when forming the stud. "Overlapping" - the term means that the periphery is overlapped and extends over the periphery of a lower element "including extending within or outside of the circumference or within the circumference." 5 wearing a stud, because the - _ _ line can be the same as ^ ^ hai + conductor π pieces and the stud, regardless of the existence of f between the semiconductor element and the stud is the same as the imaginary vertical line through the component (such as the cover Body), ^ is also good - the imaginary vertical line only runs through the semiconductor component and does not pass through the stud (the foot of the stud is recorded). The adhesive layer I is attached to the terminal and the terminal by the pad, and the pedestal is overlapped by the stud. Similarly, the convex (four) overlaps the base and is suspected of being in the position. In addition, "overlap" is synonymous with "above" and "overlap" is synonymous with "below." 52 201121004 The term "contact" means direct contact. For example, the dielectric layer contacts the first and second conductive layers but does not contact the stud or the pedestal. The term "covering" means completely covering from above, from below and/or from the side. For example, the pedestal covers the stud from below, but the stud does not cover the pedestal from above.

The word "layer" contains a layer with or without a pattern. For example, when the substrate is disposed on the adhesive layer, the first conductive layer may be a blank unpatterned flat plate and the first conductive layer may be a circuit pattern having spaced wires; when the semiconductor component is disposed on the When the heat sink is on the heat sink, the first conductive layer may be a circuit having a pattern. Further, the 'layer' may include a plurality of stacked layers. "Welding pad" - used in conjunction with the substrate - means a connection area for connecting and / or connecting an external connection medium (such as solder or wire); when the semiconductor element is located above the heat sink, the material is connected Age can be electrically connected to the semiconductor element. The term "terminal" as used in connection with the group means a joint region that can contact and/or engage an external medium (eg, a wire); # the semiconductor component is located on the heat sink. The media serviceable terminal is electrically connected to the eve of the device, such as - printed circuit board or connected to it - wire °, "body" - the word and the splicing means - for connection and / or Bonding an external material (such as a contact area that turns or guides the ship; when the light is placed above the heat sink), the external connection medium can thermally connect the body to the semiconductor component. "Open" and "through hole" The same finger refers to the through hole. For example, when the pillar is layered, the layer is exposed to the adhesive layer in an upward direction. Similarly, when the (10) stud is inserted into the through hole of the substrate, the stud is The film is exposed to the substrate along the direction 53 201121004. Insertion "1" means the relative movement between the elements. For example, "inserting the stud into the through hole" includes: the stud is fixed and the substrate is directed to the The pedestal moves 'the far substrate is fixed and the pillar is directed to the substrate Moving; and the protrusion and the substrate are in abutment with each other. For example, "inserting (or extending into) the through hole" includes: the through hole penetrating (passing in and out) the through hole And the through hole is inserted but not penetrated (penetrated but not worn out).

The phrase "together with each other" also refers to the relative movement between components. For example, "the pedestal and the substrate abut each other" includes: the susceptor is fixed and moved from the substrate to the pedestal, the substrate is fixed and moved by the pedestal to the substrate; and the pedestal and the pedestal The substrates are close to each other. The term "set in" encompasses contact and non-contact with a single or multiple support elements. For example, the semiconductor device is provided on the heat sink, regardless of whether the semiconductor 70 is actually in contact with the rest or is separated from the heat sink by a crystal material: similarly, the semiconductor component is disposed on the heat sink. In the above, the semiconductor read system is disposed only on the heat sink or on the side of the heat sink. ^ "Adhesive layer...in the gap" means the adhesive layer located in the gap. For example, &quot;&quot;adhesion extends across the dielectric layer in the gap&quot; means that the squat layer within the gap extends and spans the ageing layer. Similarly, "the adhesive layer is in the gap = the contact ride between the stud and the dielectric layer" means that the gap is in contact with the stick and the stud is outside the gap Between the dielectric layers of the wall. ;壬2^"—the semantically oriented upwards' and includes contiguous and non-contiguous elements and overlapping and non-overlapping elements. For example, the stud string extends above the base and abuts, overlaps, and protrudes from the base at 54 201121004. Similarly, the stud extends over the dielectric layer even if the stud does not abut or overlap the dielectric layer. The word "below" is intended to mean a downward extension and includes adjacent and non-adjacent elements and overlapping and non-overlapping elements. For example, the pedestal extends adjacent to the δ mysterious column below the stud, and is overlapped by the ridged column. The studs protrude out. Similarly, the stud is extended below the dielectric layer, even if the stud is not adjacent to or overlapped by the dielectric layer. The vertical directions of "upward" and "downward" are not dependent on the The orientation of the semiconductor wafer package (or the heat conductive plate) can be easily understood by those skilled in the art. For example, the stud column extends vertically above the pedestal in an upward direction, and the adhesive layer extends vertically below the solder pad in a downward direction, and whether the set is inverted and/or is disposed in a heat dissipation manner. Not relevant on the device. Similarly, the base extends "laterally" from the stud along a lateral plane, regardless of whether the set is inverted, rotated or tilted. Therefore, the upward and downward directions are opposite to each other and perpendicular to the side direction, and further, the laterally aligned elements are coplanar with each other on a lateral plane perpendicular to the upward and downward directions. The body has several advantages. The reliability of this group is 咼, the price is flat and it is very suitable for mass production. This group is particularly suitable for high-power semiconductor devices such as large semiconductor wafers that are prone to high heat and require excellent heat dissipation to operate efficiently and reliably. The embodiments described herein are illustrative, and the elements or steps of the present invention are either simplified or omitted to avoid obscuring the features of the present invention. Similarly, in order to clarify the drawings, the repeated or non-essential components and reference numerals in the drawings [55 201121004 may be omitted. Those skilled in the art will readily appreciate various changes and modifications in the embodiments described herein. For example, the foregoing materials, dimensions, shapes, sizes, steps, and the order of the steps are only for the order. The above-mentioned persons can perform such changes, adjustments and equalization skills without departing from the spirit of the present invention, wherein the details of the present invention are defined by the latter. In summary, the present invention is a semiconductor wafer package that can effectively improve various disadvantages of the prior art. The reliability of the group is high, the price is flat, and it is very suitable for mass production. The sixth is particularly suitable for generating high heat such as large semiconductor wafers. High-power semiconductor components that require excellent heat dissipation for efficient and reliable operation can greatly improve production, yield, performance and cost-effectiveness, and meet environmental requirements, thereby making the invention more profitable, more practical, and more In accordance with the requirements of the user, it has indeed met the requirements of the invention patent application, and Newfa filed a patent application. The above description is only a preferred embodiment of the present invention, and should not be limited to the scope of the present invention; therefore, the simple equivalent of the scope of the invention and the content of the specification according to the invention Changes and modifications are still within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 18 is a cross-sectional view showing the structure of a projection and a base of the preferred embodiment of the present invention. The first drawing is a cross-sectional view of the structure in which the stud and the pedestal are made in the preferred embodiment. Fig. 1c is a schematic cross-sectional view showing the structure of the post and the pedestal in the preferred embodiment of the present invention. 56 201121004 FIG. 1D is a schematic cross-sectional view showing a structure in which a stud and a pedestal are fabricated in a preferred embodiment of the present invention. Fig. 1E is a top plan view of Fig. 1D. Figure 1F is a bottom view of Figure 1D. Fig. 2A is a cross-sectional view showing the structure of the adhesive layer in a preferred embodiment of the present invention. Fig. 2B is a cross-sectional view showing the structure of the adhesive layer in the preferred embodiment of the present invention. Figure 2C is a top plan view of Figure 2B. Figure 2D is a bottom view of the 2nd figure. Fig. 3 is a cross-sectional view showing the structure of a substrate in a preferred embodiment of the present invention. Fig. 3B is a schematic cross-sectional view showing the structure of a substrate in a preferred embodiment of the present invention. Figure 3C is a cross-sectional view showing the structure of a substrate in a preferred embodiment of the present invention. Fig. 3D is a cross-sectional view showing the structure of a substrate in a preferred embodiment of the present invention. Fig. 3E is a schematic cross-sectional view showing the structure of a substrate in a preferred embodiment of the present invention. Figure 3F is a top plan view of Figure 3E. Figure 3G is a bottom view of Figure 3E. Fig. 4A is a cross-sectional view showing the structure of a heat conducting plate in a preferred embodiment of the present invention. Fig. 4B is a schematic view showing the structure of a heat conducting plate in a preferred embodiment of the present invention. ί S3 57 201121004 Figure 4C is a cross-sectional view showing the structure of a heat conducting plate in a preferred embodiment of the present invention. Fig. 4D is a cross-sectional view showing the structure of a heat conducting plate in a preferred embodiment of the present invention. Fig. 4E is a cross-sectional view showing the structure of a heat conducting plate in a preferred embodiment of the present invention. Figure 4F is a cross-sectional view of the structure of the hot plate of the preferred embodiment of the present invention. Fig. 4G is a cross-sectional view showing the structure of a heat conducting plate in a preferred embodiment of the present invention. Fig. 4 is a cross-sectional view showing the structure of a heat conducting plate in the preferred embodiment of the present invention. Figure 4 is a cross-sectional view showing the structure of a heat conducting plate of the present invention. Fig. 4J is a schematic view showing the structure of the heat conducting plate in a preferred embodiment of the present invention. Fig. 4 is a cross-sectional view showing the structure of a heat conducting plate in a preferred embodiment of the present invention. Fig. 4L is a cross-sectional view showing the structure of the heat conducting plate in a preferred embodiment of the present invention. Fig. 4 is a cross-sectional view showing the structure of a heat conducting plate in a preferred embodiment of the present invention. Figure 4 is a top plan view of Figure 4. Figure 40 is a bottom view of Figure 4. 58 201121004 Figure 5A is a cross-sectional view of a semiconductor wafer package in accordance with a preferred embodiment of the present invention. Figure 5B is a top plan view of a semiconductor wafer package in accordance with a preferred embodiment of the present invention. Figure 5C is a bottom plan view of a semiconductor wafer package in accordance with a preferred embodiment of the present invention. Figure 6A is a schematic cross-sectional view of a semiconductor wafer assembly in accordance with another preferred embodiment of the present invention. Fig. 6B is a perspective view of a semiconductor wafer package in accordance with another preferred embodiment of the present invention. Figure 6C is a schematic elevational view of a semiconductor wafer package in accordance with another preferred embodiment of the present invention. [Description of main component symbols] Metal plate 10 Surface 12, 14 Patterned resist layer 16, 40, 60, 62 Fully covered etching resist layer 18, 3 8 Groove 2 0 Post 2 2 Base 2 4 Adhesive layer 2 6 Opening 2 8 Substrate 3 0 First conductive layer 3 2 59 201121004 Dielectric layer 3 4 Second conductive layer 3 6 Routing line 4 2, 6 6 Through hole 4 4 Notch 4 6 Hole 4 8, 5 0 Third conductive layer 52. Fourth conductive layer 5 4 • First conductive via 56 Second conductive via 5 8 Pad 6 4 Cover 6 8 Terminal 7 0 Conductor 7 2 Heat sink 7 4 First solder resist green paint 76 • Second solder mask green paint 78 covered joint 80 0 heat conducting plate 8 2 semiconductor wafer set 10 0, 2 0 0 semiconductor wafer 10 2, 2 0 2 wire 10 4, 2 0 4 solid crystal material 106, 206 packaging material 10 8, 2 0 8 top surface 110, 210 201121004 bottom surface 112, 2 1 2 wire bonding pad 1 14,214

Claims (1)

201121004 VII. Patent application scope: 1. A f-chip group can provide vertical signal routing, which includes: an adhesive layer having at least one opening; Adjacent to the pedestal to include a stud and a pedestal, wherein the stud is extended in the upward direction above the pedestal, and the pedestal is extended downward in the direction of the ancient upward direction Behind the stud, and extending laterally from the stud in the direction of the side in the upward and downward directions; the substrate '5 is placed on the adhesive layer and extends over the base, and the V-package is provided. a solder pad, a routing line, a first conductive hole and a dielectric layer, wherein the soldering boat extends above the dielectric layer, and the scale extends from the line below the dielectric layer and is buried in the adhesive layer. And the first conductive via extends through the dielectric layer to the squama, and has a ship extending through the substrate; a second conductive hole extending through the adhesive layer to the routing line; a terminal extending from the The semiconductor element is located above the pillar and overlaps the pillar, or is located below the pillar and overlaps the pillar. The semiconductor component is electrically connected to the solder joint and the terminal is thermally connected. To the stud and the base; and the protruding post extends through the The through hole is formed above the dielectric layer, the pedestal extends over the adhesive layer and the substrate, and is formed by the first conductive hole, the routing line and the n-electrode - the pad a conductive path between the terminal and the lining of the pedestal is disposed on the pedestal, and extends over the pedestal into the through hole, and a gap between the protruding post and the substrate extends in the notch Across the dielectric layer and between the stud and the dielectric layer, and between the pedestal and the substrate. The semiconductor wafer assembly according to claim 1, wherein the semiconductor device is a semiconductor wafer extending over the pillar, overlapping the pillar, and electrically connected to the semiconductor wafer. The solder bump is electrically connected to the terminal, and the conductor wafer is thermally coupled to the stud to be mirrored to the pedestal. The semiconductor wafer package according to the above-mentioned patent application, wherein the semiconductor 7L is a semiconductor wafer, and the bonding-solid crystal material is disposed on the heat sink, and is electrically connected to the heat via the wire. a pad and is thermally bonded to the stud via the die bond material. 4. The semiconductor crystal X body according to the invention of claim 1, wherein the adhesive layer contacts the convex age electrical layer in the thin portion, and contacts the pedestal outside the notch, the medium The semiconductor wafer assembly of the first aspect of the invention, wherein the adhesive layer is covered in the lateral direction and surrounds the convex column. 6 · According to the patent application, the sub-group of the H-group described in item i, wherein the adhesive layer fills the gap. The semiconductor wafer package of claim i, wherein the adhesive layer fills a space between the pedestal and the substrate. The semiconductor wafer package according to the first aspect of the invention, wherein the adhesive layer is superposed on the terminal. / 9 According to the towel, please refer to (4) 1 riding semi-guided H纟, where the adhesive layer extends to the outer edge of the group. 1 0▲• According to the application, the first reference is made to the semiconductor (9)_, wherein the stud is integrally formed with the base. The semiconductor wafer assembly of claim 1, wherein the k-bump and the adhesive layer are coplanar above the dielectric layer. 63 201121004 12 兮 : : 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体The semiconductor wafer package of claim 1, wherein the susceptor and the terminal are coplanar below the point layer. 1 The patent semiconductor package of the above-mentioned item 1, wherein the underlying cover covers the stud, the domain plate, and maintains a distance from the outer edge of the set. The semiconductor wafer package of claim 1, wherein the 'wafer line' is spaced apart from the stud and the base. The semiconductor wafer package of claim 1, wherein the substrate is a laminated structure. The invention relates to a semiconductor wafer assembly according to the first aspect of the invention, wherein the '^兮', the seat at least includes a cover body located above the top of the protruding column, adjacent to the top of the adjacent column and covering from above. At the same time, the lateral direction of the stud is extended laterally from the top of the stud. The semiconductor wafer assembly according to the item of claim 17, wherein the WII is rectangular or square, and the convex The top of the column is circular. , : · According to the semiconductor crystal plate described in the patent application, wherein the hot seat contains at least a cover body, and the cover body is not expected to be coplanar on the dielectric layer. 20 · According to the lion's patent, the semiconductor crystal plate described in item i, in the basin, the material of the heat sink is steel. /, 21 kinds of semiconductor chip sets, which can be used to provide direct signal routing, including: An adhesive layer having at least one opening; 64 201121004 A political hot seat comprising at least one protrusion, a base and a cover, wherein the protrusion is adjacent to the base and formed integrally with the base And the stud is extended above the base in an upward direction, And forming a thermal connection between the base and the cover body, the base extending in a downward direction of the upward direction from the lower side of the protruding column and in a direction perpendicular to the upward and downward directions The protrusion is laterally extended. The cover system is located above the top of the protrusion, adjacent to the top of the protrusion and covered from above, and extends laterally from the top of the protrusion along the side directions. The adhesive layer extends over the pedestal, and includes a first and second conductive layer, a first conductive hole and a dielectric layer, wherein the first conductive layer is connected to the dielectric layer and extends Above the dielectric layer, the second conductive layer is attached to the dielectric layer and extends under the dielectric layer and buried in the adhesive layer, and has a pad included in one of the first conductive layers. The material is connected to the dielectric layer and extends over the dielectric layer of the thief, and has a selected portion of the second conductive layer, which is connected to the dielectric layer and extends below the dielectric layer. And the first conductive hole extends through the first conductive layer and the routing line a through hole extends through the substrate; two conductive holes 'contact and extend through the adhesive layer to the routing line; a terminal 'contacts and extends below the wire layer; an electrical 2-conductor wafer is disposed on The cover body is superposed on the protruding post, and the film is rotated to be electrically connected to the terminal, and the semiconductor crystal is connected to the cover body to be thermally coupled to the base; And a square 'St: extending through the opening into the via hole to reach the X layer on the dielectric layer. The downward direction extends over the semiconductor wafer, the adhesive layer 65 201121004 and the underside of the substrate and covers the underlying layer The semiconductor has no bumps and supports the substrate, and the first conductive hole, the routing line and the second conductive hole form a conductive path between the hybrid and the _ sub-segment, and the towel wire is disposed on the wire seat. And extending into the through hole in the through hole - a gap between the protruding post and the wire plate, the thin towel extending across the dielectric layer and in the notch; Between the dielectric layers, outside the gap, between the pedestal and the miscellaneous board In the meantime, the hybrid layer covers the studs in the direction of the web and extends to the peripheral edges of the group. 2: The semiconductor wafer package according to the second aspect of the patent application, wherein the semiconductor wafer is disposed on the cover by using a solid crystal material, and the material is passed through a single line of μ, and Knot to the cover. The semiconductor wafer package according to the second aspect of the patent application, wherein the column and the susceptor maintain a distance, and the adhesive layer fills the gap between the pedestal and the substrate H, and the heat dissipation Seat and the substrate. 0 is about 2 The core of the semiconductor wafer package as described in claim 21 of the patent application is in the top of the stud.卩为卿, and the upper cover of the county is rectangular or square, and the cover is a flat-topped cone-shaped column with a diameter of from the base to the cover system. The semiconductor wafer assembly described in item 21 Wherein, the second = /, the hybrid layer and the cover and the solder (four) are coplanar, and the base and the terminal are made of material copper of the heat sink under the adhesive layer. Face and 66