201120999 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種堆疊式電容結構的製造方法，特 別有關於埋入式閘極字元線連結dram裝置的堆疊式電容 結構的製造方法。 【先前技術】 埋入式閘極字元線連結（Buried Wordline DRAM)技 術，不同於傳統的溝槽式（Trench)技術’而是以溝槽為基礎 φ 改良的標準雄疊電容器技術’具有效能、低功耗和小尺寸 晶片等特點，進而發展出達成完全垂直單元(vertical cells) 的技術領域突破。 於先前技術中，在製作埋入式閘極字元線連結DRAM 裝置的堆疊式電容結構時，需配合製作極高深寬比的電容 結構的製程。第1A和1B圖係顯示傳統堆疊式電容結構的 部分製程的示意圖。請參閱第1A圖’形成一介電層2於 一半導體基底1上。接著形成高深寬比的電容開口 5於介 # 電層2中，並且沉積一導電層3 (做為電容結構的下電極) 於介電層2和電容開口 5内側壁上。接著，請參閱第1B 圖，施以化學機械研磨將介電層2表面上的導電層3移除， 再以濕録刻製程’或稱模版姓刻（mold etch)，回钱刻介電 層2露出導電層3的上部分，形成部分外露的電容杯體， 以利進行後續的製程。 隨著記憶體陣列區的電容密度提升，電容結構的間距 就愈靠近。尤其是’在進行上述形成電容杯體的步驟時， 常因微影製程的曝光失焦（defocus)，或者由於蝕刻開口製 98-018 /0492-A42184TW/fmal/ 5 201120999 程造成局部區域蝕刻率不同，所導致電容杯口蝕刻深度不 足，如第1C圖的開口 5’和5”所示。進而導致在後續製程 時，例如模版蝕刻（mold etch)，電容杯體的底部因失去支 撐而倒塌或剝離，如第1D圖的電容杯體3’和3”所示。 【發明内容】 本發明之一實施例提供一種堆疊式電容的製造方法， 包括：提供一基底具有一記憶胞陣列區域和一週邊區域， 其中所述記憶胞陣列區域包括多個電容堆疊的結構，所述 週邊區域具有一對準標記；形成一第一介電層於該基底 上；形成一穩定堆疊層包括一氮化矽層和一氧化矽層於該 第一介電層上；形成一第二介電層於該穩定堆疊層上；實 施一第一圖案化步驟以形成多個電容開口於記憶胞陣列區 域及一溝槽環繞該對準標記；順應性地沉積一第一電極層 於該基底上並填入所述多個電容開口與溝槽的内侧表面 上；沉積一第三介電層於該第一電極層上並覆蓋整個基底 上，並填滿電容開口與溝槽的内部；平坦化該第三介電層 並移除該第二介電層表面上多餘的第三介電層；實施一第 圖案化步驟將該第二介電層圖案化，定義出一第一開口 露出該電容開口的表面以及一第二開口露出該溝槽所環繞 的區域；依序移除該第一和第二開口所露出的該第三介電 層和該穩定堆疊層的該氧化梦層部分；順應性地沉積一高 介電常數介電層和一第二電極層於該基底上並填入所述多 個電容開口與溝槽的内側表面上；沉積一金屬層於該基底 上並填滿所述多個電容開口與溝槽的内部；圖案化該金屬 98-018 /0492-A42184TW/fmal/ 6 201120999 層露出該週邊區域的一開口區域；移除該週邊區域的該開 口區域下方的該穩定堆疊層和該第一介電層，並露出該對 準標記；以及沉積一第五介電層於該基底上並填入該週邊 區域的該開口區域，並接著將該第五介電層平坦化。 本發明另一實施例提供一種埋入式閘極字元線DRAM 裝置的堆疊式電容結構，包括：一基底具有一記憶胞陣列 區域和一週邊區域，所述週邊區域具有一對準標記；一第 一介電層設置於該基底上；一穩定堆疊層設置於該第一介 • 電層上；一第二介電層於該穩定堆疊層上；以及多個堆疊 式電容結構設置於記憶胞陣列區域及一阻障結構環繞該對 準標記設置於該週邊區域；其中於該週邊區域的該對準標 記上方與該阻障結構的内部為一透明的第三介電層。 為使本發明能更明顯易懂，下文特舉實施例，並配合 所附圖式，作詳細說明如下： 【實施方式】 • 以下以各實施例詳細說明並伴隨著圖式說明之範例， 做為本發明之參考依據。在圖式或說明書描述中，相似或 相同之部分皆使用相同之圖號。且在圖式中，實施例之形 狀或是厚度可擴大，並以簡化或是方便標示。再者，圖式 中各元件之部分將以分別描述說明之，值得注意的是，圖 中未繪示或描述之元件，為所屬技術領域中具有通常知識 者所知的形式，另外，特定之實施例僅為揭示本發明使用 之特定方式，其並非用以限定本發明。 為了能有效地提升堆疊式電容結構的製程裕度及良 98-018 /0492-A42184TW/fmal/ 7 201120999 率，可在介電層上增加一穩定層（stabilize structure，簡稱 st)結構，例如藉由增加氮化矽/氧化矽層，以穩定電容杯體 的結構。再者，在定義電容開口的製程中，藉由一圖案化 的氮化梦層環繞相連保護住電容開σ的杯緣。在進行模版 蝕刻（mold etch)的步驟時，可避免電容杯體倒榻 第2圖係顯示藉由增加氮化石夕/氧化石夕層的 堆疊式電容杯體結構倒塌的示意圖。繪^^ °月参閱第2圖，首先 提供-半導體基底11，具有-記憶胞陣列區域 邊區域10P。在記憶胞陣列區域10A且古+ 4 一百主動元件15電性 連接一電性接觸25 ’對應一堆疊式電容的 的位置。電性接觸 25形成於介電層20中，是藉由金屬化製程形成 化的氮化矽層30設置於半導體基底u卜〜M ° 一圖案 上疋義出雄疊式電 容的位置。所述週邊區域10P且右 ^ 、’一連接導電層 (Interconnect Layer)所形成之對準標記於& 於氮化碎層30 上。 -第-介電層35設置於半導體基底^上，並將稃定 層結構(ST)包括氮化矽40和氧化矽層45讯 " J 6又置於第一介電 層35上。接著，進行圖案化電容開口製程’形成對應電性 接觸25位置的開口，並且在開口内側壁及底部形成導電層 62填入介電層63於開口的中心部份。接这 θ 接耆’以氮化矽層 50做為硬遮罩層，其具有開口 65a和65b沐膝，BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a stacked capacitor structure, and more particularly to a method of fabricating a stacked capacitor structure for a buried gate word line connection dram device. [Prior Art] Buried Wordline DRAM technology, unlike the traditional Trench technology, but based on trenches φ improved standard male capacitor technology 'with performance Features such as low power consumption and small size wafers have led to breakthroughs in technology that achieve complete vertical cells. In the prior art, in the fabrication of a stacked capacitor structure in which a buried gate word line is connected to a DRAM device, it is necessary to cooperate with a process for fabricating a very high aspect ratio capacitor structure. Figures 1A and 1B show schematic diagrams of a partial process of a conventional stacked capacitor structure. Referring to Fig. 1A', a dielectric layer 2 is formed on a semiconductor substrate 1. A high aspect ratio capacitor opening 5 is then formed in the dielectric layer 2, and a conductive layer 3 (as a lower electrode of the capacitor structure) is deposited on the dielectric layer 2 and the inner sidewall of the capacitor opening 5. Next, referring to FIG. 1B, the conductive layer 3 on the surface of the dielectric layer 2 is removed by chemical mechanical polishing, and then the wet recording process or the mold etch is used to return the dielectric layer. 2 Exposing the upper portion of the conductive layer 3 to form a partially exposed capacitor cup for subsequent processing. As the capacitance density of the memory array region increases, the closer the capacitance structure is spaced. In particular, 'in the above-mentioned step of forming a capacitor cup, the defocusing of the lithography process is often caused, or the local area etching rate is caused by etching the opening 98-018 /0492-A42184TW/fmal/ 5 201120999. Differently, the capacitor cup mouth etching depth is insufficient, as shown by openings 5' and 5" in Fig. 1C, which leads to collapse in the subsequent process, such as mold etch, the bottom of the capacitor cup is lost due to loss of support. Or peeling, as shown in the capacitor cups 3' and 3" of Figure 1D. SUMMARY OF THE INVENTION An embodiment of the present invention provides a method of fabricating a stacked capacitor, comprising: providing a substrate having a memory cell array region and a peripheral region, wherein the memory cell array region comprises a plurality of capacitor stacked structures. The peripheral region has an alignment mark; forming a first dielectric layer on the substrate; forming a stable stacked layer comprising a tantalum nitride layer and a hafnium oxide layer on the first dielectric layer; forming a first a second dielectric layer is disposed on the stable stacked layer; a first patterning step is performed to form a plurality of capacitor openings in the memory cell array region and a trench surrounds the alignment mark; and a first electrode layer is compliantly deposited thereon Depositing a plurality of capacitor openings on the inner side surface of the trench; depositing a third dielectric layer on the first electrode layer and covering the entire substrate; and filling the capacitor opening and the inside of the trench; Flattening the third dielectric layer and removing excess third dielectric layer on the surface of the second dielectric layer; performing a patterning step to pattern the second dielectric layer to define a first opening exposed a surface of the capacitor opening and a second opening exposing a region surrounded by the trench; sequentially removing the third dielectric layer exposed by the first and second openings and the oxidized dream layer portion of the stable stacked layer; Complianceally depositing a high-k dielectric layer and a second electrode layer on the substrate and filling the plurality of capacitor openings and the inner surface of the trench; depositing a metal layer on the substrate and filling The plurality of capacitor openings and the interior of the trench; patterning the metal 98-018 /0492-A42184TW/fmal/ 6 201120999 to expose an open area of the peripheral region; removing the underlying region of the peripheral region Stabilizing the stacked layer and the first dielectric layer and exposing the alignment mark; and depositing a fifth dielectric layer on the substrate and filling the opening region of the peripheral region, and then the fifth dielectric layer flattened. Another embodiment of the present invention provides a stacked capacitor structure of a buried gate word line DRAM device, comprising: a substrate having a memory cell array region and a peripheral region, the peripheral region having an alignment mark; a first dielectric layer is disposed on the substrate; a stable stacked layer is disposed on the first dielectric layer; a second dielectric layer is disposed on the stable stacked layer; and a plurality of stacked capacitor structures are disposed on the memory cell An array region and a barrier structure are disposed around the alignment mark in the peripheral region; wherein the alignment mark is over the alignment mark and the interior of the barrier structure is a transparent third dielectric layer. In order to make the present invention more obvious and obvious, the following detailed description of the embodiments and the accompanying drawings will be described in detail as follows: [Embodiment] The following examples are described in detail with reference to the accompanying drawings. It is the reference for the invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and in particular, The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention. In order to effectively improve the process margin of the stacked capacitor structure and the good 98-018 /0492-A42184TW/fmal/ 7 201120999 rate, a stabilizing structure (st) structure can be added to the dielectric layer, for example, The tantalum nitride/yttria layer is added to stabilize the structure of the capacitor cup. Furthermore, in the process of defining the capacitance opening, the edge of the capacitor opening σ is protected by a patterned nitride layer. In the step of stencil etching, the capacitor cup can be avoided. Fig. 2 shows a schematic diagram of collapse of the stacked capacitor cup structure by increasing the nitride/oxidation layer. Referring to Fig. 2, first, a semiconductor substrate 11 having a memory cell array region side region 10P is provided. In the memory cell array region 10A, the ancient + 4 hundred active device 15 is electrically connected to a position where an electrical contact 25 ′ corresponds to a stacked capacitor. The electrical contact 25 is formed in the dielectric layer 20, and the tantalum nitride layer 30 formed by the metallization process is disposed on the semiconductor substrate at a position on the pattern of the semiconductor substrate. The alignment of the peripheral region 10P and the right ^, ' an interconnecting layer is marked on & on the nitride layer 30. The first dielectric layer 35 is disposed on the semiconductor substrate, and the tantalum layer structure (ST) includes tantalum nitride 40 and a hafnium oxide layer 45, and the J 6 is again placed on the first dielectric layer 35. Next, a patterned capacitor opening process is performed to form an opening corresponding to the position of the electrical contact 25, and a conductive layer 62 is formed on the inner sidewall and the bottom of the opening to fill the dielectric layer 63 at the central portion of the opening. Connected to the θ junction, the tantalum nitride layer 50 is used as a hard mask layer having openings 65a and 65b,
0於陣列區域10A 與開口 65c於週邊區域10P，接著定義雷办、 两电奋杯口，即移除 部份氧化梦層45a、45]^ 45c，以及繼續進行後續的步驟。 然而，僅僅藉由增加穩定層結構，其氣化石夕為透光陡 差的介電層，在進行後續如上電極層之全屬道& m屬導線製程(plate 98-018 /0492-A42184TW/final/ 201120999 導致上Μ罩^ 鶴金屬(Tungsten)為非透光屢會 曰先罩對準對準標記_ 準標記的方法為採用間接 服對準對 上方的穩定層結構移除：或者將對準標記_ 累進誤差增加。另對準方法，會導致 層f構移除，例如在定義電容杯口時了=1二：定 時’所可順利地將對40 is in the array area 10A and the opening 65c is in the peripheral area 10P, and then the thunder and the two electric cups are defined, that is, the partial oxidation dream layers 45a, 45], 45c are removed, and the subsequent steps are continued. However, only by increasing the stabilizing layer structure, the gasification stone is a dielectric layer with a steep light transmission, and the subsequent full-channel & m-wire process of the above electrode layer is performed (plate 98-018 /0492-A42184TW/ Final/ 201120999 Causes the upper cover ^ Tungsten is a non-transparent 曰 曰 对准 对准 Alignment mark _ The standard mark method is to use the indirect clothing alignment to remove the upper stable layer structure: or will be The quasi-marker _ progressive error increases. Another alignment method will cause the layer f structure to be removed, for example, when defining the capacitor cup mouth = 1 2: timing 'can be smoothly 4
由週邊區域二=與=層：， 延八如箭頭E所示，進而橫向傳 區域10A，進而影響元件效能。 陣列From the peripheral area two = and = layer:, as shown by the arrow E, and then laterally pass the area 10A, thereby affecting the component performance. Array
在移除對準標記_上方的穩定層結構時，為 钱刻液由週邊區域橫向侵人陣列區域，本發明所揭露的 施例k供一種阻隔構造，設置於週邊區域且環繞對準授 記，以有效地避免蝕剡液由週邊區域橫向侵入陣列區域。v 第3A圖係顯示根據本發明之一實施例的埋入式閘極 字元線連結DRAM装置的平面示意圖。於第3A圖中，埋 入式閘極字元線連結DRAM裝置100晶圓包括多個記传胞 陣列區域100A和週邊區域ι〇〇ρ(或稱週邊街道(Kerf^切 割道區域(kerf line))，對準標記M0設置於週邊區域1〇〇p 内。為了將對準標記M0上方的穩定層結構移除，利用微 影製程形成一窗口（例如區域R)中。 第3B和3C圖係顯示第3A圖的局部區域R的矛土卸 J /卜思圖〇 根攄本發明之一實施例，形成一阻隔構造於週邊區域且穿 繞對準標記M0’請參閱第3B圖，在形成電容開口的步驟1 同時形成一溝槽80環繞對準標記M0，溝槽80的寬度為 98-018 /0492-A42184TW/fmaiy 9 201120999 W’沿X方向與區域R的距離為ΔΧ、沿γ方向與區域R 的距離為ΔΥ°在形成與電容相同的導電層結構於溝槽80 ^之再以微影製程形成窗口區域85，並將窗口内的穩 定層、纟。構移除’由於溝槽8〇内導電層結構的阻隔能有效 地避免蝕刻液由週邊區域橫向侵入陣列區域。 第4A-4J係顯示根據本發明之實施例的堆疊式電容杯 體結構於製造過程中各步驟的剖面示意圖。請參閱第4Α 圖’首先提供一半導體基底110，具有一記憶胞陣列區域 100Α和一週邊區域1〇〇ρ。在記憶胞陣列區域1〇〇α具有多 個主動元件115，例如M〇s場效電晶體，電性連接一電性 接觸125 ’對應堆疊式電容的位置。電性接觸125可形成 於介電層120中，例如金屬間介電層（IMD),可藉由各種金 屬化連線製程形成。 氮化石夕層130設置於半導體基底11〇上定義出堆疊 式電容的位置。所述週邊區域100P具有一對準標記M〇於 氮化矽層130上。 一第一介電層135設置於半導體基底110上，例如以 電漿輔助化學氣相沉積法（PECVD)形成四乙氧基矽酸鹽 (TEOS)層，厚度範圍約為800士 100nm。並將穩定層結構包 括一氮化矽層140 (例如由PECVD形成的SiN層，厚声約 50±10nm)和一氧化石夕層145 (例如由PECVD形成的 層’厚度約500士lOOnm)設置於第一介電層135上。 接著’進行圖案化電容開口製程，於記憶胞陣列區、 形成對應電性接觸位置的開口，以及於週邊區域形成 — 環繞對準標記M0。請參閱第4B圖，實施一第—微影製矛。曰 98-018 /0492-A42184TW/fmal/ 10 201120999 包括由PECVD形成的SiN層150 (厚度約100±10nm)於第 一介電層135。接著，形成一碳硬遮罩層（Carbon hard mask) 152 ’其組成為碳氫高分子(carb〇n-hydrgen polymer)及頂部 薄的氮氧化矽(top thin SiON)於SiN層150上，其中碳氫高 分子的厚度範圍約為2000埃至5000埃，SiON的厚度範圍 約為250-1500埃，接著’形成一抗反射塗層（ARC，厚度 約50nm) 154於碳硬遮罩層152上，再形成圖案化光阻層 156於抗反射塗層154上，並定義出對應電容位置的開口 155a於記憶胞陣列區域100a和環繞對準標記M0的溝槽 的開口 155b於週邊區域loop。 以圖案化光阻層156為遮罩定義抗反射塗層154,碳硬 遮罩層152和SiN層150，再以定義後的SiN層150為遮 罩’例如以氫氟酸緩衝蝕刻（BHF)溶液，蝕刻氧化矽層 145、氮化矽層140、第一介電層135和氮化矽層130，露 出下方的基底結構’如第4C圖所示。由此，形成電容開口 160a以及環繞的溝槽i60b，由於電容開口 160a的頂端受 到連續環繞的圖案化SiN層150保護，因此在餘刻電容開 口時，可避免電容杯口崩塌。 請參閱第4D圖，順應性地形成一導電層ία於上述基 底結構上，在開口 16〇a及溝槽160b内侧壁及底部形成導 電層162，例如以原子層沉積法(ALD)形成氮化鈦(TiN)層 (厚度約為26±5nm) ’接著以化學氣相沉積法(CVD)形成臭 氧-四乙氧基矽酸鹽（〇_TEOS，厚度約330±l〇〇nm)層164 於基底結構上並填入開口 160a及溝槽l60b的中心部份。 接著’請參閱第4Έ圖，施以化學機械研磨法(CMP) 210When the stabilizing layer structure above the alignment mark_ is removed, the engraving liquid laterally invades the array area from the peripheral area, and the embodiment k disclosed in the present invention provides a barrier structure, is disposed in the peripheral area, and surrounds the alignment. In order to effectively prevent the etchant from invading the array region laterally from the peripheral region. v Figure 3A is a plan view showing a buried gate word line bonded DRAM device in accordance with an embodiment of the present invention. In FIG. 3A, the buried gate word line connected DRAM device 100 wafer includes a plurality of cell array regions 100A and a peripheral region ι〇〇ρ (or a surrounding street (Kerf^ kerf line) )), the alignment mark M0 is disposed in the peripheral region 1 〇〇p. In order to remove the stable layer structure above the alignment mark M0, a window (for example, region R) is formed by a lithography process. Figs. 3B and 3C Referring to an embodiment of the present invention, a portion of the present invention is shown in FIG. 3A, and a barrier structure is formed in the peripheral region and the alignment mark M0' is seen. See FIG. 3B. Step 1 of forming a capacitor opening simultaneously forms a trench 80 around the alignment mark M0. The width of the trench 80 is 98-018 /0492-A42184TW/fmaiy 9 201120999 W'the distance from the region R along the X direction is ΔΧ, along γ The distance between the direction and the region R is ΔΥ°, and the same conductive layer structure as the capacitor is formed in the trench 80^, and the window region 85 is formed by the lithography process, and the stable layer and the structure in the window are removed. The barrier structure of the conductive layer in the groove 8〇 can effectively prevent the etching liquid from being horizontally traversed from the surrounding area. 4A-4J shows a cross-sectional view of various steps in a manufacturing process of a stacked capacitor cup structure according to an embodiment of the present invention. Please refer to FIG. 4A first to provide a semiconductor substrate 110 having a memory. The cell array region 100Α and a peripheral region 1〇〇ρ. In the memory cell array region 1〇〇α has a plurality of active elements 115, such as M〇s field effect transistors, electrically connected to an electrical contact 125' corresponding stacked The position of the capacitor. The electrical contact 125 may be formed in the dielectric layer 120, such as an inter-metal dielectric layer (IMD), which may be formed by various metallization wiring processes. The nitride layer 130 is disposed on the semiconductor substrate 11 The position of the stacked capacitor is defined. The peripheral region 100P has an alignment mark M on the tantalum nitride layer 130. A first dielectric layer 135 is disposed on the semiconductor substrate 110, for example, by plasma assisted chemical vapor phase A deposition method (PECVD) forms a tetraethoxy phthalate (TEOS) layer having a thickness in the range of about 800 ± 100 nm, and the stabilizing layer structure includes a tantalum nitride layer 140 (for example, a SiN layer formed by PECVD). 50±10nm) and A oxidized layer 145 (e.g., a layer formed by PECVD having a thickness of about 500 Å nm) is disposed on the first dielectric layer 135. Then, a patterned capacitor opening process is performed to form a corresponding electrical contact position in the memory cell array region. The opening is formed in the peripheral area - around the alignment mark M0. Please refer to Fig. 4B to implement a first lithography spear. 曰98-018 /0492-A42184TW/fmal/ 10 201120999 Include the SiN layer formed by PECVD 150 (thickness about 100 ± 10 nm) on the first dielectric layer 135. Next, a carbon hard mask 152 ′ is formed, which is composed of a carb〇n-hydrgen polymer and a top thin silicon oxide layer (top thin SiON) on the SiN layer 150. The hydrocarbon polymer has a thickness in the range of about 2000 angstroms to 5,000 angstroms, and the SiON has a thickness in the range of about 250 to 1500 angstroms, followed by 'forming an anti-reflective coating (ARC, thickness about 50 nm) 154 on the carbon hard mask layer 152. Then, a patterned photoresist layer 156 is formed on the anti-reflective coating layer 154, and an opening 155a corresponding to the capacitance position is defined in the memory cell array region 100a and the opening 155b of the trench surrounding the alignment mark M0 in the peripheral region loop. The anti-reflective coating 154, the carbon hard mask layer 152 and the SiN layer 150 are defined by the patterned photoresist layer 156 as a mask, and the defined SiN layer 150 is used as a mask, for example, hydrofluoric acid buffer etching (BHF). The solution, the ruthenium oxide layer 145, the tantalum nitride layer 140, the first dielectric layer 135, and the tantalum nitride layer 130 are exposed to expose the underlying substrate structure as shown in FIG. 4C. Thereby, the capacitor opening 160a and the surrounding trench i60b are formed. Since the top end of the capacitor opening 160a is protected by the continuously surrounding patterned SiN layer 150, the capacitor cup opening can be prevented from collapsing when the capacitor is opened. Referring to FIG. 4D, a conductive layer is formed compliantly on the substrate structure, and a conductive layer 162 is formed on the sidewalls and the bottom of the opening 16〇a and the trench 160b, for example, by atomic layer deposition (ALD). Titanium (TiN) layer (thickness: about 26 ± 5 nm) 'Next, a layer of ozone-tetraethoxy silicate (〇_TEOS, thickness about 330 ± l 〇〇 nm) is formed by chemical vapor deposition (CVD). The base structure is filled with the opening 160a and the central portion of the groove 160b. Then, please refer to Figure 4, applying chemical mechanical polishing (CMP) 210
98-018 /〇492-A42184TW/fmal/ ,ι I 201120999 於基底結構，移除表面的〇_TE〇S層164，露出平坦的SiN 層150與0-TEOS層164表面。 請參閱第4F圖，實施一第二微影製程，包括形成一碳 硬遮罩層（厚度約2〇〇nm) no於SiN層150上，形成一抗 反射塗層（ARC，厚度約為5〇nm的氮氧化矽層）172於碳硬 遮罩層170上，再形成圖案化光阻層174於抗反射塗層172 上並疋義出對應電谷位置的開口 和對準標記上 方的開口 175b。 請參閱第4G圖，以圖案化光阻層174為遮罩，透過開籲 口 175a和i75b向下鍅刻，例如以反應性離子钱刻或電漿 #刻’並過度蝕刻部分露出的TiN層162和SiN層150， 再移除圖案化光阻層174和碳硬遮罩層17〇。接著，實施 濕钱刻製程將露出的〇_TE〇s層祕和祕移除，並將 穩定層結構所露出的氧化矽層145a和145b移除，如第4H 圖所示。於一實施例中，可於第一階段利用氫氟酸緩衝蝕 刻（BHF)溶液移除約400nm的氧化矽層，再以第二階段利 用稀釋氫氟酸(DHF)溶液移除約100nm的氧化矽層。應理 _ 解的是，在週邊區域100P處，環繞對準標記訄〇的溝槽因 受到導電層（TiN) 162的襯墊，因而在進行濕蝕刻步驟時， 可避免蝕刻液由週邊區域橫向侵入陣列區域。更明確地 說，在週邊區域100P處的導電層（TiN) 162可做為避免蝕 刻液由週邊區域橫向侵入陣列區域的阻隔構造。 請參閱第41圖，以化學氣相沉積法(CVD)或原子層沉 積法(ALD)順應性地形成一高介電常數(high_k)介電層^们 於基底結構上，以化學氣相沉積法（CVD)或原子層沉積法 98-018 /0492-A42184TW/final/ i? 201120999 (ALD)順應性地形成一導電層（例如TiN) 2 84於high_k介電 層182上。由導電層150、high_k介電層182、和導電層i84 構成電容堆疊構造。接著，以化學氣相沉積法(CVD)順應 性地形成一金屬層（例如鎢）186於基底結構上並填入開口 及溝槽的中心部份。 接著，形成一光阻層188於金屬層（鎢）186上，光阻層 188遮蔽陣列區域ιοοΑ的金屬層（鎢）186與露出週邊區域 100P的金屬層（鎢）186’形成對準標記M〇上方的開口 185。 請參閱第4J圖’移除光阻層188後，形成一介電層195 於基底結構上，例如以電漿輔助化學氣相沉積法(PECVD) 形成四乙氧基矽酸鹽(TE0S)層並填入對準標記M〇上方的 開口。接者再將介電層195平坦化，以利實施後續的製程’ 例如半導體的後段製程(BE0L)。應理解的是’由於此時對 準標記M0上方是由透明的介電層（TE〇s) ι95覆蓋，因此 在進行後續製程時，例如進行上電極層之金屬導線製程 (plate line’簡稱pl)製程，可藉由直接對準對準標記M0 增加製程精度。 本發明所揭露的動態隨機存取記憶（DRAM)裝置的堆 疊式電容的製造方法，其優點在於提供了穩定層結構以避 免在進行模版钱刻（m〇ld etch)時造成電容杯體傾倒或崩 塌。再者’為了後續製程的對準需求，在移除對準標記M0 上方的不透明穩定層結構時，增加了環繞的阻隔構造，能 有效地避免钱刻液由週邊區域橫向侵入陣列區域。並且， 本發明提供微影製程中所需對準標記及其製作方法，不會 造成後段製程(BEOL)或上電極層（PL)無法對準及曝光。 98-018 /〇492-A42184TW/fmay η [ 201120999 本發明雖以各種實施例揭露如上，然其並非用以限定 本發明的範圍，任何所屬技術領域中具有通常知識者，在 不脫離本發明之精神和範圍内，當可做些許的更動與潤 飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。 【圖式簡單說明】 第1A和1B圖係顯示傳統堆疊式電容結構的部分製程 的不意圖， 第1C圖係顯示對應第1A圖的開口，因曝光失焦 (defocus)或因局部區域蝕刻率不同，所導致電容開口深度 不足的不意圖， 第1D圖係顯示對應第1B圖的電容杯體，在進行模版 鞋刻（mold etch)後，造成電容杯體崩塌或剝離的示意圖； 第2圖係顯示藉由增加氮化矽/氧化矽層的幫助，避免 堆疊式電容杯體結構倒塌的示意圖。； 第3A圖係顯示根據本發明之一實施例的埋入式閘極 字元線連結DRAM裝置的平面示意圖，第3B和3C圖係顯 示第3A圖的局部區域R的示意圖；以及 第4A-4J係顯示根據本發明之實施例的堆疊式電容杯 體結構於製造過程中各步驟的剖面示意圖。 【主要元件符號說明】 1〜半導體基底； 98-018 /0492-A42184TW/final/ 14 201120999 2〜介電層； 3〜導電層； 3’、3”〜倒塌、剝離的電容杯體； 5〜電容開口； 5’、5”〜曝光失焦、蝕刻不足的電容開口； 11、110〜半導體基底； 10A、100A〜記憶胞陣列區域； 10P、100P〜週邊區域； • 15、115〜主動元件； 20、120〜介電層； 25、125〜電性接觸； 30、130〜氮化矽層； 35、135〜第一介電層； 40、140〜氮化矽； 45、145〜氧化矽層； 45a、45b和45c〜部份氧化石夕層； — 50、150〜氮化矽層； 62〜導電層； 63〜介電層； 65a、65b、65c〜開口； 80〜溝槽； 85〜窗口區域； 100〜DRAM裝置； 145a和145b〜露出的氧化矽層； 152、170〜碳硬遮罩層； 98-018 /0492-A42184TW/fmal/ 15 201120999 154、172〜抗反射塗層； 156、174、188〜圖案化光阻層； 155a 、 155b〜開口； 160〜介電層； 16 0 a〜開口； 160b〜溝槽； 162〜導電層（TiN); 164〜臭氧-四乙氧基矽酸鹽（O-TEOS)層； 164a和164b〜露出的0-TE0S層； 175a 和 175b~開口； 182〜high-k介電層； 184〜導電層（TiN); 185〜對準標記M0上方的開口； 186〜金屬層（鎢）； 195〜介電層（TEOS); 210〜化學機械研磨法(CMP); R〜局部區域； M0〜對準標記； E〜钱刻液侵入方向。 98-018 /0492-A42184TW/fmal/ 1698-018 / 〇 492-A42184TW / fmal / , ι I 201120999 In the substrate structure, the surface of the 〇 〇 〇 层 S layer 164 is removed to expose the surface of the flat SiN layer 150 and the 0-TEOS layer 164. Referring to FIG. 4F, a second lithography process is performed, including forming a carbon hard mask layer (about 2 Å thick) on the SiN layer 150 to form an anti-reflective coating (ARC, thickness about 5). 〇 的 氮 172 172 172 172 on the carbon hard mask layer 170, and then form a patterned photoresist layer 174 on the anti-reflective coating 172 and the opening corresponding to the location of the electric valley and the opening above the alignment mark 175b. Referring to FIG. 4G, the patterned photoresist layer 174 is used as a mask, and is etched down through the opening openings 175a and i75b, for example, by reactive ion etching or plasma etching and over etching a partially exposed TiN layer. 162 and SiN layer 150, and then removing patterned photoresist layer 174 and carbon hard mask layer 17A. Next, a wet etching process is performed to remove the exposed 〇TEP layer and remove the yttrium oxide layers 145a and 145b exposed by the stabilizing layer structure as shown in Fig. 4H. In one embodiment, a cerium oxide layer of about 400 nm may be removed using a hydrofluoric acid buffered etch (BHF) solution in a first stage, and an oxidation of about 100 nm may be removed in a second stage using a dilute hydrofluoric acid (DHF) solution.矽 layer. It should be understood that, in the peripheral region 100P, the trench surrounding the alignment mark 因 is received by the conductive layer (TiN) 162, so that the etching liquid can be prevented from being laterally traversed from the peripheral region during the wet etching step. Invade the array area. More specifically, the conductive layer (TiN) 162 at the peripheral region 100P can serve as a barrier structure for preventing the etching liquid from laterally invading the array region from the peripheral region. Referring to Figure 41, chemical vapor deposition (CVD) or atomic layer deposition (ALD) is used to form a high dielectric constant (high_k) dielectric layer on the substrate structure by chemical vapor deposition. A method (CVD) or atomic layer deposition method 98-018 /0492-A42184TW/final/i? 201120999 (ALD) conformally forms a conductive layer (e.g., TiN) 2 84 on the high_k dielectric layer 182. A capacitor stack structure is formed by the conductive layer 150, the high_k dielectric layer 182, and the conductive layer i84. Next, a metal layer (e.g., tungsten) 186 is conformally formed by chemical vapor deposition (CVD) on the base structure and filled in the central portion of the opening and the trench. Next, a photoresist layer 188 is formed on the metal layer (tungsten) 186, and the photoresist layer 188 shields the metal layer (tungsten) 186 of the array region ι from the metal layer (tungsten) 186 ′ exposing the peripheral region 100P to form an alignment mark M. The opening 185 above the 〇. Referring to FIG. 4J, after removing the photoresist layer 188, a dielectric layer 195 is formed on the substrate structure, for example, by plasma-assisted chemical vapor deposition (PECVD) to form a tetraethoxyphthalate (TEOS) layer. And fill in the opening above the alignment mark M〇. The dielectric layer 195 is then planarized to facilitate subsequent processing, such as semiconductor back-end processing (BE0L). It should be understood that 'because the alignment mark M0 is covered by the transparent dielectric layer (TE〇s) ι95 at this time, when performing the subsequent process, for example, the metal wire process of the upper electrode layer is performed (plate line 'abbreviated as pl The process can increase the process accuracy by directly aligning the alignment mark M0. The method for manufacturing a stacked capacitor of a dynamic random access memory (DRAM) device disclosed in the present invention has the advantage of providing a stable layer structure to prevent the capacitor cup from falling over when performing a stencil or collapse. Furthermore, in order to meet the alignment requirements of the subsequent process, when the opaque stable layer structure above the alignment mark M0 is removed, the surrounding barrier structure is added, and it is possible to effectively prevent the money engraving from laterally invading the array region from the peripheral region. Moreover, the present invention provides an alignment mark required in a lithography process and a method of fabricating the same, which does not cause the back end of the process (BEOL) or the upper electrode layer (PL) to be misaligned and exposed. 98-018 / 〇 492-A42184 TW / fmay η [ 201120999 The present invention is disclosed in the above various embodiments, but it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art without departing from the invention. In the spirit and scope, the scope of protection of the present invention is defined by the scope of the appended claims. [Simple description of the drawings] The 1A and 1B drawings show the partial process of the conventional stacked capacitor structure. The 1C figure shows the opening corresponding to the 1A figure, due to the defocus of the exposure or the local area etching rate. Differently, the result is that the capacitance opening depth is insufficient. The first DD shows a schematic diagram corresponding to the capacitor cup of FIG. 1B, which causes a collapse or peeling of the capacitor cup after performing a mold etch; FIG. It is shown that the stacking capacitor cup structure collapses by avoiding the help of the tantalum nitride/yttria layer. 3A is a plan view showing a buried gate word line-connected DRAM device according to an embodiment of the present invention, and FIGS. 3B and 3C are views showing a partial region R of FIG. 3A; and 4A- 4J shows a cross-sectional view of various steps of a stacked capacitor cup structure in accordance with an embodiment of the present invention. [Main component symbol description] 1~Semiconductor substrate; 98-018 /0492-A42184TW/final/ 14 201120999 2~ Dielectric layer; 3~ Conductive layer; 3', 3"~ Collapsed, stripped capacitor cup; 5~ Capacitor opening; 5', 5"~exposure out of focus, under-etched capacitor opening; 11, 110~ semiconductor substrate; 10A, 100A~ memory cell array area; 10P, 100P~ peripheral area; • 15, 115~ active component; 20, 120~ dielectric layer; 25, 125~ electrical contact; 30, 130~ tantalum nitride layer; 35, 135~ first dielectric layer; 40, 140~ tantalum nitride; 45, 145~ yttrium oxide layer 45a, 45b and 45c~ part of the oxidized stone layer; - 50, 150~ tantalum nitride layer; 62~ conductive layer; 63~ dielectric layer; 65a, 65b, 65c~ opening; 80~ trench; Window area; 100~DRAM device; 145a and 145b~ exposed ruthenium oxide layer; 152, 170~carbon hard mask layer; 98-018 /0492-A42184TW/fmal/ 15 201120999 154, 172~ anti-reflective coating; 174, 188~ patterned photoresist layer; 155a, 155b~ opening; 160~ dielectric layer; 16 0 a~ opening; 160b~ trench 162~ conductive layer (TiN); 164~ozone-tetraethoxy silicate (O-TEOS) layer; 164a and 164b~ exposed 0-TE0S layer; 175a and 175b~ opening; 182~high-k dielectric Layer; 184~ conductive layer (TiN); 185~ alignment mark above M0; 186~ metal layer (tungsten); 195~ dielectric layer (TEOS); 210~ chemical mechanical polishing (CMP); Area; M0~ alignment mark; E~ money engraving intrusion direction. 98-018 /0492-A42184TW/fmal/ 16