201113954 六、發明說明： 【發明所屬之技術領域】 本發明是鑛-種畫素結構與其製妨法H種以摻雜半 導體材料來形成畫素電極的畫素結構與其製造方法。 【先前技術】 液晶顯示器由於具有輕薄短小、低輻射與低耗電等特性，已取 =傳統陰極射線管顯示器成為顯示器市場之主流產品。一般說 來，液晶顯示面板主要包含—薄膜電晶體之陣列基板、一彩色遽 光片基板，以及填充於陣列基板與彩色濾光片基板之_液晶 子層。陣醜板包含複數個呈_排狀晝素，且每—晝素係利 用複數條平行之掃描軸複數條與掃絲垂直之平行資料線定義 而成並以薄膜電晶體作為開關元件，利用一畫素電極驅動各晝 ，上方之液晶分子作獨程度之旋轉關整各畫素之亮度，同時 藉由彩色濾w基板上與各4素對應設置之紅色、綠色與藍色濾 光片使各晝素產生不同亮度之紅色、綠色與藍色光線，進而輸出 尚晝質之彩色影像。 現今晝素結構中的的薄膜電晶體主要包含—閘極電極、—源 極、一没極以及一做為電晶體通道的非晶石夕(amorphous silicon) 1 h而Ik著顯示裝置朝著大尺寸、高解析度以及低動態殘影 、方向4進’由非晶石夕層所構成的薄膜電晶體在導電性、穩定性、 ^漏電、以及遂光率等條件上已漸漸無法滿足目前齡裝置的要 :其一人’晝素結構中的晝素電極通常是由氧化銦錫(ITO)等透明 導電材料所構成。氧化銦錫中的銦屬稀有金屬，在長久使用下容 易4遇原料祕及價格高㈣問題。此外，以現有的標準製程來 201113954 製作晝素結構時，通常需 的各元件圖案，包括閘極 洞等，在繁瑣的製程步驟 同時耗費製作成本。 要五道以上的光罩衫義出4素結構中 、源極/没極、通道、畫素電極以及接觸 下不但無法提升薄膜電晶體的效能，又 L贫明内容】 本明疋揭路一種晝素結構與盆製 製程中製作細構所遇__—心’ 1 韻上述傳統 下列露=素结構的方法，包含有 *區。然後形成至少一 _極;基板區：: 並覆蓋閘極電極，然後形成-圖案化= -保護層覆蓋_化半導=:===第 ===為，體的-^ 之間的-ί道的圖案化半導體層作為源極和晝素電極 本發明另-實施例是揭露一種晝素結構， 畫素區;至少-閘極電極設於基板二 電晶體區及畫極絲板上；以及―半導體層設於 以用來作為-㈣心其中畫素區之半導體層具有摻質 用來作部分的Μ體區之半導體層具有摻質以 5 201113954 於此’根據本發明所揭露的一種晝素結構與其製造方法，可同 時在畫素結躺電晶魏及畫素區製作出所需的電晶體通道及書 素電極，而不S分難料電晶體區㈣道及 電 極，在製程上不但簡化製歸驟，又可達翁低㈣成本的= 【實施方式】 請參照圖i至圖5’圖i至圖5為本發 例的製造方法之主要步驟示咅同^ _傅平乂住耳把 1?其柘19钎勹人女地 ^ ^ 圖1所示，首先提供一基板 〇 3有機材料或無機材料，例如玻璃、石英、塑膠、 樹脂、壓克^材質，縣板12上具有—電晶艇Μ、一晝素區 16 乂及‘線區18。然飾成複數個問極電極如 ^201113954 VI. Description of the Invention: [Technical Field] The present invention is a mineral-species pixel structure and a method for producing the same, and a pixel structure for forming a pixel electrode by doping a semiconductor material and a method for fabricating the same. [Prior Art] Due to its characteristics of light and thin, low radiation and low power consumption, liquid crystal displays have taken the traditional cathode ray tube display to become the mainstream product in the display market. Generally, the liquid crystal display panel mainly comprises an array substrate of a thin film transistor, a color ray substrate, and a liquid crystal sublayer filled on the array substrate and the color filter substrate. The ugly board comprises a plurality of sputum sputum elements, and each sputum element is defined by a plurality of parallel scanning axes and a parallel data line perpendicular to the scanning wire, and the thin film transistor is used as a switching element, and one The pixel electrode drives each of the cymbals, and the liquid crystal molecules on the upper side rotate to completely adjust the brightness of each pixel, and at the same time, the red, green and blue filters corresponding to each of the four elements are arranged on the color filter w substrate. The alizarin produces red, green, and blue light of different brightness, which in turn outputs a color image that is still enamel. The thin film transistor in the present germanium structure mainly includes a gate electrode, a source, a immersion, and an amorphous silicon as a transistor channel, and the display device is oriented toward the large Dimensions, high resolution, low dynamic image sticking, and direction 4's thin film transistor composed of amorphous austenite layer have gradually failed to meet the current age in terms of conductivity, stability, leakage, and luminosity. The main point of the device: the halogen electrode in the one-person structure is usually made of transparent conductive material such as indium tin oxide (ITO). Indium indium tin oxide is a rare metal, which is easy to use in the long-term use and has a high price (four). In addition, when the conventional standard process is used to make the structure of the element in 201113954, the pattern of each component, including the gate hole, is usually required, and the manufacturing cost is also cumbersome in the complicated process steps. It is necessary to have more than five smocks in the four-layer structure, the source/ditpole, the channel, the pixel electrode, and the contact, not only can not improve the performance of the thin film transistor, but also L poor content] The structure of the prime structure and the process of making a fine structure in the potting process __-heart' 1 rhyme The above-mentioned traditional method of the following formula = containing the * area. Then forming at least one _ pole; substrate region: and covering the gate electrode, and then forming - patterning = - protective layer covering _ _ semi-conducting =: = = = = = = for, between the body - ^ - The patterned semiconductor layer as a source and a halogen electrode. Another embodiment of the present invention discloses a pixel structure, a pixel region; at least a gate electrode is disposed on a substrate and a plate; And a semiconductor layer having a semiconductor layer disposed on the semiconductor layer of the pixel region for use as a - (iv) core having a dopant for use as a portion of the semiconductor region having a dopant 5 201113954, a 'disclosed according to the present invention The structure of the halogen element and the manufacturing method thereof can simultaneously produce the required transistor channel and the book element electrode in the pixel layer and the pixel region, and do not divide the difficult transistor region (four) channel and the electrode in the process. Not only the simplified system, but also the low (four) cost = [Embodiment] Please refer to Figure i to Figure 5 'Figure i to Figure 5, the main steps of the manufacturing method of this example show the same ^ _ Fu Ping Ear 1? Its 柘19 brazing woman's land ^ ^ As shown in Figure 1, first provide a substrate 〇 3 organic material or Inorganic materials, such as glass, quartz, plastic, resin, acrylic material, the county board 12 has - electric crystal boat, a single element area 16 乂 and 'line area 18. However, it is decorated into a plurality of question electrodes such as ^
電晶體區14以及複數個導雷巧安^ ^ J ^ Η . 12 -個導線區料包含一個二=:上的閘極電極20 ’每 ^ 4個以上的導電圖案60。其中，閘極 tr/案6G的製作方式可先形成—由金屬所構成的導 :ΓΓ=)在基板12上’此金屬材料可包含鎢、㈣鉬 ^金、脑合金、赌合金等材料，然祕配進行-微影暨侧 製程’去除部分的導電材料層（圖未示），以於 : 條掃描線(圖未示)與複數個薄膜 托2 ^ 6〇。 联€日日體之閘極電極20及導電圖案 接著如圖2至圖3所示，形山 声的¥靜22於成—做為_電晶體之閘極絕緣 層的％緣層22於基板12上並憑罢 6〇，且絕靜2?縛各間極電極2〇及各導電圖案 ^ 又⑽所構成。然後依序沉積-透明之半 層24 H賴26切緣層22上’靖導體層24 201113954 ^保遵層26進行一圖案轉移製程，以於絕緣層22上形成一 III*半導則34與圖案化第-保護層36。其中，半導體層24 一 銦鎵鋅氧化物(InGaZnO)所構成，而第一保護層26則可由 氧化矽所構成。The transistor region 14 and a plurality of conductive guides ^ ^ J ^ Η . 12 - wire material comprises a second =: upper gate electrode 20 ' per 4 or more conductive patterns 60. Among them, the gate tr / case 6G can be formed first - the formation of a metal: ΓΓ =) on the substrate 12 'this metal material can contain tungsten, (4) molybdenum ^ gold, brain alloy, gambling alloy and other materials, The secret is carried out - lithography and side process 'removing part of the conductive material layer (not shown), so that: a scanning line (not shown) and a plurality of film holders 2 ^ 6 〇. The gate electrode 20 and the conductive pattern of the Japanese body are then shown in FIG. 2 to FIG. 3, and the shape of the mountain sound is formed as a % edge layer 22 of the gate insulating layer of the transistor. It is composed of 6 〇, and it is composed of 2 poles and each conductive pattern ^10. Then, a pattern-transfer process is performed on the insulating layer 22 to form a III* semi-conductive 34 on the insulating layer 22. The first protective layer 36 is patterned. Among them, the semiconductor layer 24 is made of indium gallium zinc oxide (InGaZnO), and the first protective layer 26 is made of yttrium oxide.
在本實施例中，形成圖案化半導體層34及圖案化第一保護層 36的，仏步驟是先以一半透型㈣彻〇光罩(圖未示)形成一具有 不同厚度的第―圖案化細層28在第-保護層26上，其中第一 圖案化光阻層28㈣—部位30姆應設於電晶舰14内之閘極 ^極2〇上方，而第—圖案化光阻層28的第二部位32則分別設於 :素區16與電晶體區14内源極級極的預定位置，且第—圖案化 光阻層28的第-部位3〇的厚度大於第二部位％的厚度。然後進 仃侧製程’例如一乾姓刻或濕侧製程，利用第一圖案化光 =層28去除電晶體區14及晝素區16以外的第一保護層％、及半 ‘體層24，並使剩餘的半導體層Μ形成圖案化半導體層弘。隨 後利用灰化(涵ng)製程以非等向性縮減第一圖案化光阻層Μ的 厚度，亦即去除第-_化光阻層28設於電晶體區14及畫素區 16中的第二部位32，並縮減第—圖案化光阻層μ之第—部位％ 的厚度之後’再细第—随化光阻層28剩餘在電晶體區14 ㈣’3G恤w，去除電晶體區 f化第—保護層36於電晶體區14内的圖案化半導體層^定 義出一，道區38。錢完全去除嶋的第一®案化光阻層28。 值得注意岐’本實關是_半透型光罩來軸且有 厚度的第-圖案化光阻層28’然後再以此第一圖案阻 來進行圖案轉移並形成圖案化半導體層34與圖案化第一保g 201113954 36。換句話說，本發明僅需一道半透型光罩便可將半導體層％與 第一保護層26進行圖案化，以製作出所需之圖案化半導體層弘 及圖案化第-條層36。但不讎於此，本發明之其他實施例又 可依照傳統製程叫道光罩的方絲分細彡成随化半導體層％ 與設於其上的圖案化第一保護層36，此作法也屬本發明所涵蓋的 範圍。 然後如圖4所示，進行一化學氣相沉積(chemical vapor deposition’ CVD)製矛王以於基板上全面性形成—第二保護層4〇 並覆蓋圖案化第—保護層36、®案化半導體層34及絕緣層22。 依據本發明之較佳實施例，第二保護層4〇包含氮化石夕，且覆蓋第 =保護層4〇於圖案化半導體層％上的時候，較佳是在化學氣相 沉積製程中引人-含有氫原子的氣體，使氫原子植人未覆蓋圖案 化第—保護層36 _案化半導體層34 t以職具有摻質的半導 體層。 省在本實施例中’由於圖案化第一保護層36所覆蓋的圖案化半 V體層34在上述第二保護層4〇沉積的過程中並不會被植入換 質因，父佳做為本發明薄膜電晶體的通道42，而電晶體區Μ 及畫素區16中未覆蓋有圖案化第-保護層36的部分圖案化半導 =層34則祕分別做為薄膜電晶體的源極μ以及晝素區％的畫 可^46*換句話說，本發明藉由圖案化第一保護層36的遮蔽， 積第二保護層4〇的過程中將原本的圖案化半導體層34同 出薄膜電晶體的源極44與通道42以及一晝素電極46。此 +德枯^明亦可藉由圖案化第—保護層36的遮蔽，直接實施一離 郝K程或高濃度電漿摻賴程，骑未覆蓋有_化第一保 曰的部分醜化半導縣34進行_，而職薄膜電晶體 201113954 的源極44以及畫素區16的晝素電極46，之後再沉積第二保護層 40，此等作法同屬本發明的涵蓋範圍。 然後如圖4至圖5所示，對第二保護層4〇進行—微影暨蝕刻 製程，以於第二保護層40中形成複數個接觸洞48。其中，每一個 電晶體區14可包含一個或一個以上的接觸洞48，每—個導線區 18可包含-個或-個以上的接觸洞48。隨後再形成一金屬層（圖未 不)於第二保護層40上並同時填入該金屬層於各接觸洞48中，所 述之金屬層可由鎢、鉬、鎢鉬合金、鋁鉬合金、鋁鈦合金等金屬 _材料所構成，P連後再對該金屬層進行一微影暨姓刻製程^於電 晶體區14的接觸洞48中與電晶體區14夕卜的第二保護層4〇上形 成一導線50，例如為訊號線(加泣〇1^41^1111^)，以及於導線區18 的接觸洞48中與導線區18外的第二保護層4〇上形成另一導線 52，用來當作與驅動積體電路(driving Ic)或軟性印刷電路版 (Hexibie Printed Circuit，FPC)等互相電性連接以對外提供訊號的 輸入以及輸出的接難結構，或者是傳輸共通參考電壓(Vc〇m)的 導線，隨後並搭配進行-熱處理製程，例如一升溫退火(咖 •程。此外’本發明在形成上述導線5〇與導線52時同時在掃描線 62及資料線64交界處形成一導線結構，如圖6所示。圖6為本發 明上述實施繼掃描線62與#騎64交界處之示賴， 描線62具有-突出部，用來當作間極電極2〇，而圖5的電晶體區 14與晝親騎猶之結猜為圖6巾沿著姆从，之剖面示 意圖。 在本實施财，形成接觸洞48、導線如與導線％的製程， 如Ή 5及圖6所示’可以-半透贱罩來形成—具有不同厚 度的第二圖案化光阻層54在第二保護層4〇上並定義出一接觸洞 201113954 區(如圖6中接觸洞區48)，其中接觸洞區可以是一個或—個以上。 第二圖案化光阻層54的第三部位58設於資料線64的第二保護層 40上’第二圖案化光阻層54的第四部位56設於接觸洞區48及資 料線64以外的第二保護層40上，其中第二圖案化光阻層54的第 四部位56的厚度大於第三部& 58的厚度。然後進行一餘刻製程， 例如-乾勤彳或·刻製程’利用第二圖案化光阻層54當作遮罩 去除電晶體區14的部分第二保護層40及導魏18的部分第二保 護層及絕緣層22以職複數個接_ 48。隨後_灰化製程 縮減第二圖案化紐層54的厚度以及去除第二圖案化光阻層％ 的第三部位58,並沉積一金屬層（圖未示)在接觸洞48中、第0二保 4層40上及第二圖案化光阻層54上。接著利用剝離卿哗技術 -起去除第二圖案化光阻層54及設於第二随化光_ %上的 部分金屬層，並搭配進行-熱處理製程，例如—升溫退 j於電晶體區i4及導線區18分別形成一導線5〇與導線52,以及 =-保護層上形成-㈣線64 _。本實施例僅需_ =便可將第二紐層4〇與金屬層進行随化，⑽作出 觸洞48、導線50、導線52及資料線料。 請接著參照圖7 ’圖7為本發明另一實施例於掃描線泣 =64交界處形成-導線結構之示意圖，其中圖電巴、4 ^晝素區16所揭露之結構即為圖7中沿著切_，之 在本實施例中，如圖8所示，本發明 音 將第二保護層4〇與金屬層進行 、一般光罩來 你、導線5〇、導線52及資料線^錢以㈣^需之接觸洞 40中的導線結構。舉例來說，、可先_ ^乍出埋藏於第二保護層 了先般鮮形成—圖案化光 201113954 如-層4G上’接著直接進行，1製程，例 除電晶體區!:的：二’利】圖_^^ 區,的部分第二;保護層4〇、接觸洞區(如圖7中接觸洞 二保護層4G卿· ;/與絕緣層22以及導線區18的部分第 屬屛-、Γ、4層X形賴數贿_48。然後沉積—金 洞48中及圖案化光阻層(圖未示)上並以剝離 广去-竹起去除圖案化光阻層（圖未示)及設於圖案化光阻層In this embodiment, the patterned semiconductor layer 34 and the patterned first protective layer 36 are formed by first forming a first pattern having different thicknesses by using a half-transparent (four) transparent mask (not shown). The fine layer 28 is on the first protective layer 26, wherein the first patterned photoresist layer 28 (four)-portion 30 should be disposed above the gate electrode 2 of the crystal cell 14 and the first patterned photoresist layer 28 The second portion 32 is respectively disposed at a predetermined position of the source region of the element region 16 and the transistor region 14, and the thickness of the first portion 3〇 of the first patterned photoresist layer 28 is greater than that of the second portion. thickness. Then, the first side process or the wet side process is performed, and the first patterned light layer 28 and the first protective layer % and the half 'body layer 24 except the halogen region 16 are removed by the first patterned light=layer 28, and The remaining semiconductor layer Μ forms a patterned semiconductor layer. Then, the thickness of the first patterned photoresist layer 缩 is reduced by an unequality by using an ashing process, that is, the first _ photoresist layer 28 is disposed in the transistor region 14 and the pixel region 16 After the second portion 32, and reducing the thickness of the first portion % of the first patterned photoresist layer μ, the 'refiner-passurizing photoresist layer 28 remains in the transistor region 14 (4) '3G shirt w, removing the transistor region The patterned semiconductor layer in the transistor region 14 defines a track region 38. The money completely removes the first photoresist layer 28 of the crucible. It is worth noting that 'this is a semi-transmissive reticle with a thickness of the first-patterned photoresist layer 28' and then patterned with the first pattern to form a patterned semiconductor layer 34 and pattern The first guarantee g 201113954 36. In other words, the present invention requires only a semi-transmissive mask to pattern the semiconductor layer % and the first protective layer 26 to form the desired patterned semiconductor layer and the patterned first layer 36. However, other embodiments of the present invention may further divide the square wire of the reticle into a patterned semiconductor layer % and a patterned first protective layer 36 disposed thereon according to a conventional process. The scope of the invention is covered. Then, as shown in FIG. 4, a chemical vapor deposition (CVD) spear is formed to form a comprehensive surface on the substrate - the second protective layer 4 〇 and covers the patterned first protective layer 36, Semiconductor layer 34 and insulating layer 22. According to a preferred embodiment of the present invention, the second protective layer 4 includes a nitride nitride and covers the first protective layer 4 on the patterned semiconductor layer, preferably in a chemical vapor deposition process. a gas containing a hydrogen atom such that the hydrogen atom is implanted without covering the patterned first protective layer 36 - the semiconductor layer 34 t has a semiconductor layer having a dopant. In the present embodiment, the patterned semi-V body layer 34 covered by the patterned first protective layer 36 is not implanted in the process of depositing the second protective layer 4, and the parent is The channel 42 of the thin film transistor of the present invention, and the portion of the transistor region Μ and the pixel region 16 not covered with the patterned first-protective layer 36 are respectively used as the source of the thin film transistor. The painting of μ and the pixel region % can be 46*. In other words, the present invention separates the original patterned semiconductor layer 34 by patterning the shielding of the first protective layer 36 and accumulating the second protective layer 4? The source 44 of the thin film transistor is connected to the channel 42 and a halogen electrode 46. The etched half of the etched half can also be directly subjected to the masking of the patterned first protective layer 36, and a part of the ugly half that is not covered with the first protective layer is directly implemented. The guide 34 performs _, and the source 44 of the thin film transistor 201113954 and the halogen electrode 46 of the pixel region 16 are then deposited with the second protective layer 40, and such practices are within the scope of the present invention. Then, as shown in FIG. 4 to FIG. 5, the second protective layer 4 is subjected to a lithography and etching process to form a plurality of contact holes 48 in the second protective layer 40. Each of the transistor regions 14 may include one or more contact holes 48, and each of the wire regions 18 may include one or more contact holes 48. Then, a metal layer (not shown) is formed on the second protective layer 40 and simultaneously filled with the metal layer in each contact hole 48. The metal layer may be made of tungsten, molybdenum, tungsten-molybdenum alloy, aluminum-molybdenum alloy, A metal such as aluminum-titanium alloy is formed by a material, and after the P is connected, a lithography and a lithography process is performed on the metal layer, and a second protective layer 4 in the contact hole 48 of the transistor region 14 and the transistor region 14 is formed. A wire 50 is formed on the crucible, for example, a signal line (adding a weeping 1^41^1111^), and another conductor is formed in the contact hole 48 of the wire region 18 and the second protective layer 4〇 outside the wire region 18. 52, used as a connection structure for driving input integrated circuit (driving Ic) or flexible printed circuit (FPC) to provide external input and output signals, or a common reference for transmission The voltage (Vc〇m) of the wire is then combined with a heat treatment process, such as a temperature-raising annealing process. Further, the present invention simultaneously forms the boundary between the scanning line 62 and the data line 64 when forming the above-mentioned wire 5 turns and the wire 52. A wire structure is formed as shown in Fig. 6. Fig. 6 is the present invention Referring to the indication of the intersection of the scan line 62 and the #骑64, the trace 62 has a protrusion, which serves as the interpole electrode 2〇, and the transistor region 14 of FIG. Figure 6 is a schematic cross-sectional view of the scarf along the ridge. In this implementation, the formation of the contact hole 48, the wire such as the wire % process, such as Ή 5 and Figure 6 can be formed by a semi-transparent hood - different The thickness of the second patterned photoresist layer 54 is on the second protective layer 4 and defines a contact hole 201113954 region (such as the contact hole region 48 in FIG. 6), wherein the contact hole region may be one or more. The third portion 58 of the second patterned photoresist layer 54 is disposed on the second protective layer 40 of the data line 64. The fourth portion 56 of the second patterned photoresist layer 54 is disposed outside the contact hole region 48 and the data line 64. The second protective layer 40, wherein the thickness of the fourth portion 56 of the second patterned photoresist layer 54 is greater than the thickness of the third portion & 58. Then a process is performed, such as - dry or engraved process Utilizing the second patterned photoresist layer 54 as a mask to remove a portion of the second protective layer 40 of the transistor region 14 and a portion of the second portion of the waveguide 18 The protective layer and the insulating layer 22 are connected to each other _ 48. The subsequent ashing process reduces the thickness of the second patterned layer 54 and removes the third portion 58 of the second patterned photoresist layer, and deposits a metal layer. (not shown) on the contact hole 48, on the 0th layer 4 layer 40 and on the second patterned photoresist layer 54. Then, the second patterned photoresist layer 54 is removed and removed by the stripping technique. a portion of the metal layer on the second illuminating light _ %, and in conjunction with the heat treatment process, for example, the temperature rise and return j in the transistor region i4 and the wire region 18 respectively form a wire 5 turns and a wire 52, and a protective layer Form a - (four) line 64 _. In this embodiment, only the _= can be used to carry out the second layer 4〇 with the metal layer, and (10) to make the contact hole 48, the wire 50, the wire 52 and the data line. Please refer to FIG. 7 ' FIG. 7 is a schematic diagram of a wire structure formed at the intersection of the scanning line and the blank at 64 intersections according to another embodiment of the present invention, wherein the structure disclosed in FIG. 7 is the structure disclosed in FIG. In the present embodiment, as shown in FIG. 8, the sound of the present invention is carried out by the second protective layer 4〇 and the metal layer, and the general mask is provided to you, the wire 5〇, the wire 52, and the data line. The wire structure in the contact hole 40 is required by (4). For example, you can first bury it in the second protective layer and form it as soon as possible - patterned light 201113954 such as - layer 4G on - then directly, 1 process, for example, in addition to the transistor area!: 】 ^ ^ ^ zone, part of the second; protective layer 4 〇, contact hole zone (such as contact hole two protective layer 4G qing in Figure 7; / with the insulating layer 22 and part of the wire area 18 屛 -, Γ, 4 layers of X-shaped Lai _48. Then deposited - gold hole 48 and patterned photoresist layer (not shown) and stripped away - bamboo to remove the patterned photoresist layer (not shown) And patterned photoresist layer
σ不上的部分金屬層（®絲）’隨後並搭配進行-熱處理製 私一例如-升溫退火製程’以於電晶體區^及導線區Μ分卿 、一導線5〇與‘線52，以及於接觸洞區形成一設於接觸洞* 的資料線64圖案。 力在本貝施例中，掃描線62與資料線64交界處的資料線64與 絶緣層22之間雖設有一具有摻質的圖案化半導體層μ當作阻 ’但不侷限這個設計，又可由—個不具有摻質的圖案化半導體 層34取代具有摻質的圖案化半導體層3和此設計也屬本發明所涵 蓋的範圍。 如圖5所示，本發明另揭露一種晝素結構，其包含一具有電 晶體區14、晝素區16以及導線區18的基板12、至少一閘極電極 20 ^又於基板12上的電晶體區14、一絕緣層22設於閘極電極2〇 與基板12上、一圖案化半導體層34設於電晶體區14及晝素區16 的絕緣層22上、一圖案化第一保護層36設於電晶體區14的圖案 化半導體層34上以及一第二保護層40設於圖案化第一保護層 36、圖案化半導體層34及絕緣層22上。其中，圖案化半導體層 34主要由銦鎵辞氧化物(inGaZnO)所構成、圖案化第一保護層36 係由氧化矽所構成而第二保護層40則由氮化矽所構成。另外在本 201113954 貝鉍例中，由圖案化第一保護層3 %較佳«出-_電晶體的通道圖魏半導體層 有捧質的半導體層。部分電晶體區14 ^係為一不具 體層34則且有#皙，八/ —素區16的圖案化半導 極46。綱刀別作為溥膜電晶體的源極私與一晝素電 综上所述’本發明所揭露的晝 (inGaZn0)所構成的透料來:^以銦鎵鋅氧化物 通道的非晶辦以及在書Γ區本作為薄膜電晶體 及降低漏電。此外，依據上晶體的充電能力 製程ίο—η 本發明可在一道微影賊刻 衣帅h〇t〇_etchmg Ρ峨ss，ΡΕΡ)下就同時在 :j 及晝素區製作出所需的薄膜電晶體通道及書^=，電J體區 等材料來製作出薄膜電‘的通道及== 素結二可僅用三道光罩就完 料屬於广發明所揭露的銦鎵鋅氧化物半導體材 構成ιϊ電Γ 可與難絕緣層及閘極電極等元件一同 電容能力並^面影響開口率的情況下提供良好的儲存 杯Γΐ伽叫叙紐實施觸露如上，财並_以限定 = 相像鄕者，在视離本㈣之精神和範圍内 ，申明專利乾圍所界定者為準。 12 201113954 【圖式簡單說明】 圖1〜圖5為本發明晝素結構一較佳實施例的製造方法之主要 步驟示意圖； 圖6為圖5所示晝素結構的掃描線與資料線交界處之示意圖； 圖7為本發明另一實施例晝素結構的掃描線與資料線交界處 之不意圖， 圖8為圖7沿切線BB’之剖面示意圖。 φ 【主要元件符號說明】 12 基板 14 電晶體區 16 晝素區 18 導線區 20 閘極電極 22 絕緣層 24 半導體層 26 第一保護層 28 第一圖案化光阻層 30 第一部位 32 第二部位 34 圖案化半導體層 36 圖案化第一保護層 38 通道區 40 第二保護層 42 通道 44 源極 46 晝素電極 48 接觸洞 50 導線 52 導線 54 第二圖案化光阻層 56 第四部位 58 第三部位 60 導電圖案 62 掃描線 64 資料線 AA， 切線 BB’ 切線A portion of the metal layer (® wire) that is not on the σ is subsequently subjected to a heat treatment process such as a heat-temperature annealing process for the transistor region and the wire region, a wire 5 〇 and a wire 52, and A pattern of data lines 64 disposed in the contact holes* is formed in the contact hole region. In the example of the present embodiment, a patterned semiconductor layer μ having a doped pattern is provided between the data line 64 at the boundary of the scanning line 62 and the data line 64 and the insulating layer 22, but the design is not limited, and The replacement of the patterned semiconductor layer 3 with dopants by a patterned semiconductor layer 34 having no dopants and this design are also within the scope of the present invention. As shown in FIG. 5, the present invention further discloses a halogen structure comprising a substrate 12 having a transistor region 14, a halogen region 16 and a wire region 18, at least one gate electrode 20, and electricity on the substrate 12. The crystal region 14 and an insulating layer 22 are disposed on the gate electrode 2 and the substrate 12, and a patterned semiconductor layer 34 is disposed on the insulating region 22 of the transistor region 14 and the pixel region 16, and a patterned first protective layer. 36 is disposed on the patterned semiconductor layer 34 of the transistor region 14 and a second protective layer 40 is disposed on the patterned first protective layer 36, the patterned semiconductor layer 34, and the insulating layer 22. Among them, the patterned semiconductor layer 34 is mainly composed of inGaZnO, the patterned first protective layer 36 is made of yttrium oxide, and the second protective layer 40 is made of tantalum nitride. In addition, in the case of the 201113954 shell example, it is preferable to pattern the first protective layer by 3%, and the channel of the semiconductor layer has a semiconductor layer. The partial transistor region 14 is a patterned semiconductor semiconductor 46 having a body layer 34 and having a #皙, 八/素 region 16. As the source of the enamel film and the 昼 电 电 综 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' in in in in in in in in in in in in And in the book area as a thin film transistor and reduce leakage. In addition, according to the charging ability of the upper crystal process ίο - η, the invention can be produced in a lithography thief under the handsome 〇 〇 〇 etch etch etch etch etch s 就 就 就 就 就 : : j j j j j j j j j j j j Thin film transistor channel and book ^=, electric J body region and other materials to make the film's channel and == prime 2 can be completed with only three masks, which belong to the indium gallium zinc oxide semiconductor disclosed by the broad invention构成 ϊ ϊ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ The latter, in the spirit and scope of this (4), shall be subject to the definition of the patent shack. 12 201113954 [Simplified illustration of the drawings] FIG. 1 to FIG. 5 are schematic diagrams showing main steps of a manufacturing method of a preferred embodiment of the pixel structure of the present invention; FIG. 6 is a boundary between a scanning line and a data line of the halogen structure shown in FIG. 7 is a schematic view of a boundary between a scanning line and a data line of a pixel structure according to another embodiment of the present invention, and FIG. 8 is a schematic cross-sectional view taken along line BB' of FIG. 7. φ [Main component symbol description] 12 substrate 14 transistor region 16 halogen region 18 wire region 20 gate electrode 22 insulating layer 24 semiconductor layer 26 first protective layer 28 first patterned photoresist layer 30 first portion 32 second Portion 34 patterned semiconductor layer 36 patterned first protective layer 38 channel region 40 second protective layer 42 channel 44 source 46 germanium electrode 48 contact hole 50 wire 52 wire 54 second patterned photoresist layer 56 fourth portion 58 Third part 60 conductive pattern 62 scan line 64 data line AA, tangent line BB' tangent