201112211 六、發明說明： 【發明所屬之技術領域】 本發明相關於一種液晶顯示裝置及相關驅動方法，尤指 一種利用多組電路來分時驅動之液晶顯示裝置及相關驅動 方法。 【先前技術】 液晶顯示器（liquid crystal display，LCD)具有低輻射、體 積小及低耗能等優點，已逐漸取代傳統的陰極射線管 (cathode raytube display, CRT)顯示器，因而被廣泛地應用在 筆記型電腦、個人數位助理（personal digital assistant，PD⑸、 平面電視，或行動電話等資訊產品上。傳統液晶顯示器之方 W式是利用外部驅動晶片來驅動面板上的晝素以顯示影像，但 為了減少元件數目並降低製造成本，近年來逐漸發展成將驅 動電路之結構直接製作於顯示面板上，例如應用將閘極驅動 電路（gate driver)整合於液晶面板（gate〇narray,G〇A) 之技術。 言青參考第i圖，第i圖為先前技術中一液晶顯示裝置 7〇〇之簡化方塊示意圖。第i圖僅顯示了液晶顯示裝置7〇〇 3 201112211 間極驅 間極、線 之部分結構，包含複數條閘極線GL(1)〜GL(N)、 動電路10和一時序控制器（timing controller) 2〇 可 問極驅 GL(1)〜GL(N)設於液晶顯示裝置700之顯示區域3〇内 分別依據閘極驅動訊號GS(1)〜GS(N)來驅動晝素 動電路10設於液晶顯示裝置700之非顯示區域4〇为 鬥，其句 含複數級移位暫存單元SR ( 1)〜SR (N)，可依據 制器20所產生之起始脈衝訊號VST ( 1)和時脈訊藏 工 XCK來輸出閘極驅動訊號GS(1)〜GS(N)至相對應之 、 μ \〜1極始 液晶顯示裴置7〇〇採 單邊佈局單端驅動之架構，亦即閘極驅動電路1〇 & 诉k置於 閘極線GL(1)〜〇L(N)之一側，並從同一側來驅動閘極' GL(1)〜GL(N)。 線 GL(1)〜GL(N)，其中Ν為正整數 - 綠 清參考第2圖，第2圖為先前技術之液晶顯示敦置川〇 在運作時之時序圖。在驅動液晶顯示裝置7〇〇時，第一級移 位暫存單元SR⑴依㈣序控制器2()所產生之料 訊號vst⑴來輸出第一級閘極驅動訊號Gs(i)，而第二级至、 第N級移位暫存單元从⑴〜犯⑻則分職據前'一級 移位暫存單元SR⑴〜SR⑽）所產生之起始脈衝訊號 VST⑺VST (Ν)來輸出第二級至第Ν級閘極驅動訊號 GS(2)〜 GS(N)。第2圖說明了液晶顯示裝置700在顯示複數 個旦面中兩相鄰晝面F⑻和F 時’起始脈衝訊號、 VST ( 1)〜VST (N)之時序圖。 ' 4 201112211 液晶顯示器一般使用無晶石夕（amorphous silicon，a-Si) 製程來製作各個移位暫存單元内之薄膜電晶體（thin film transistor，TFT )。薄膜電晶體之電特性相關於其閘極電壓之 應力，施加閘極電壓的時間越長，薄膜電晶體之電特性劣化 情形越嚴重，如此會降低液晶顯示器的使用期限與可靠度。 【發明内容】 本發明提供一㈣晶顯示裝置，包含一顯示區域，其上 設有N條互相平行之閘極線，其中N為正整數；一第」非 顯示區域和-第二非顯示區域，分別位於該顯示區域之兩對 向側；-第-驅動電路，其依據—第—組控制訊號來運作， 該第-驅動電路設於該第一非顯示區域内且包含N級串接 ·· 之第-移位暫存單其中該㈣第—移位暫存單元中 η級第-移位暫存單元制來驅動該線中—相對應 之第η條閘極線以顯示複數個晝面中之—第—畫面且4 不大於Ν之正整數；及—第二驅動電路，其依據—第二· 制訊號來運作且包含㈣串接之第二移位暫存單元、二 Ν級第二移位暫存單元中—第讀第二移位暫存單元係= 驅動該h條閘極線以顯示該複數個晝面中接續於該第一者 面後之一第二畫面。 201112211 本發明另提供-種液晶顯示裝置’包含一顯示區域，1 上設有複數條互相平行之閘極線；—第—非顯示區域和一第 二非顯示區域，分別位於該顯示區域之兩對向側；一第一驅 動電路，設於該第-非顯示區勒並依據—第—組控制訊號 來運作’該第-驅動電路包含複數級串接之第—移位暫存單 7C ’分別絲驅動該複數條閘極線中相對應之奇數條問極線 以顯示複數個晝面中之-第-晝面；—第二驅動電路，設於 該第二非顯示區域内並依據—第二組控制訊號來運作，該第 二驅動電路包含複數㈣接H位暫存單元，分別用來 驅動該複數條閘極線中相對應之偶數條閘極線以顯示該第 一晝面；-第三驅動電路，其依據—第三組控制訊號來運作 且包含複數級串接之第三移位暫存單元，分則來驅動該相 對應之奇數條閘極線以顯示該複數個晝面中接續於該第一 晝面後之m及—第四驅動電路，其依據—第四組 控制訊號來it作且包含複數級_接之帛四移位暫存單元，分 別用來驅動該相對應之偶數條閘極線以顯示該第二畫面。 本發明另提供-種液晶顯示裝置，包含—顯示區域，其 上設有n條互相平行之閘極線，其中N為正整數；一第一 非顯示區域和-第二非顯示區域，分別位於該顯示區域之兩 ^向侧’Ί驅動電路’麟該第—非顯示區域内並依據 -第-組控制訊號來運作，該第一驅動電路包含1級串接之 第一移位暫存單元’分別絲驅動該N條閘極線中相對應之 201112211 閘極線以顯示複數個畫面中之一—全 路，其依據-第二組控制訊號來運二第：::雷驅動電 N級串接之第二移位暫存單心八卿:第―驅動電路包含BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a related driving method, and more particularly to a liquid crystal display device and a related driving method which are driven by time-sharing using a plurality of sets of circuits. [Prior Art] Liquid crystal display (LCD) has the advantages of low radiation, small size and low energy consumption, and has gradually replaced the traditional cathode ray tube display (CRT) display, so it is widely used in notes. Computer, personal digital assistant (PD (5), flat-screen TV, or mobile phone and other information products. The traditional LCD display W-type is to use external drive chip to drive the pixels on the panel to display images, but to reduce The number of components and the reduction of manufacturing cost have gradually evolved in recent years to directly fabricate the structure of the driving circuit on the display panel, for example, a technique of integrating a gate driver into a liquid crystal panel (gate〇narray, G〇A). Referring to Figure i, Figure i is a simplified block diagram of a liquid crystal display device 7 in the prior art. Figure i shows only the portion of the pole and the line between the liquid crystal display device 7〇〇3 201112211 The structure includes a plurality of gate lines GL(1) to GL(N), a moving circuit 10, and a timing controller 2 The polar drive GL(1) to GL(N) are disposed in the display area 3 of the liquid crystal display device 700, and the driving circuit 10 is driven according to the gate driving signals GS(1) to GS(N). The non-display area 4 of the display device 700 is a bucket, and the sentence includes a plurality of stages of the shift register units SR(1) to SR(N), which can be based on the start pulse signal VST(1) generated by the controller 20. The pulse collector XCK outputs the gate drive signals GS(1)~GS(N) to the corresponding, μ\~1, and the liquid crystal display device 7 〇〇 unilateral layout single-ended drive architecture, that is, The gate driving circuit 1〇& is placed on one side of the gate lines GL(1) to 〇L(N), and drives the gates 'GL(1) to GL(N) from the same side. Line GL (1) ~ GL (N), where Ν is a positive integer - Green clear reference to Fig. 2, and Fig. 2 is a timing chart of the prior art liquid crystal display of the built-in liquid crystal display device. The first stage shift register unit SR(1) outputs the first stage gate drive signal Gs(i) according to the material signal vst(1) generated by the (4) sequence controller 2(), and the second stage to the Nth stage shift. The temporary storage unit is from (1) to the offense (8). Stage shift register unit SR⑴~SR⑽) a start pulse signal VST⑺VST (Ν) arising from the second stage to the output stage of the gate drive signals v GS (2) ~ GS (N). Fig. 2 is a timing chart showing the start pulse signal, VST (1) to VST (N) when the liquid crystal display device 700 displays two adjacent planes F(8) and F in a plurality of planes. ' 4 201112211 Liquid crystal displays generally use an amorphous silicon (a-Si) process to fabricate thin film transistors (TFTs) in each shift register unit. The electrical characteristics of the thin film transistor are related to the stress of the gate voltage. The longer the gate voltage is applied, the more serious the deterioration of the electrical characteristics of the thin film transistor, which lowers the lifetime and reliability of the liquid crystal display. SUMMARY OF THE INVENTION The present invention provides a (four) crystal display device comprising a display region having N parallel gate lines, wherein N is a positive integer; a "non-display region" and a second non-display region , respectively located on two opposite sides of the display area; a first-drive circuit, which operates according to a first-group control signal, the first-drive circuit is disposed in the first non-display area and includes N-level serial connection The first-shift temporary storage list, wherein the (n) first-shift temporary storage unit has an n-th stage-shift temporary storage unit to drive the corresponding n-th gate line to display a plurality of gates Medium-first-picture and 4 is not greater than the positive integer of Ν; and - the second driving circuit, which operates according to the second signal, and includes (4) the second shift register unit in series, the second level The second shift temporary storage unit - the first read second shift temporary storage unit = drive the h gate lines to display a second picture of the plurality of sides following the first face. 201112211 The present invention further provides a liquid crystal display device comprising a display area, wherein a plurality of gate lines are arranged in parallel with each other; a first non-display area and a second non-display area are respectively located in the display area. The first driving circuit is disposed in the first non-display area and operates according to the first-group control signal. The first driving circuit includes a plurality of serially connected first-shift temporary storage sheets 7C' respectively The wire drives the corresponding odd-numbered lines in the plurality of gate lines to display the -first-side surface of the plurality of gates; the second driving circuit is disposed in the second non-display area and is based on - The second driving circuit comprises a plurality of (four) connected H-bit temporary storage units for respectively driving the corresponding even-numbered gate lines of the plurality of gate lines to display the first surface; a third driving circuit, which operates according to the third group of control signals and includes a plurality of serially connected third shift register units, and drives the corresponding odd gate lines to display the plurality of gates In the middle of the first And a fourth driving circuit, which is based on the fourth group of control signals and includes a plurality of stages of four shift register units for driving the corresponding even number of gate lines to display the The second picture. The invention further provides a liquid crystal display device comprising: a display area, wherein n parallel gate lines are arranged, wherein N is a positive integer; a first non-display area and a second non-display area are respectively located The two-way side 'Ί driving circuit' of the display area operates in the first-non-display area according to the -th group control signal, and the first driving circuit comprises a first-stage serial storage unit of one-stage serial connection 'The respective wires drive the corresponding 201112211 gate line of the N gate lines to display one of the plurality of pictures-all the way, according to the second group of control signals to transport the second::: Thunder drive electric N level The second shift of the serial connection is temporarily stored in the heart of the heart: the first drive circuit includes
條閘極線以顯示該第—晝面；-第三驅動^相f應之該N :顯示區域内並依據-第三組控制訊號來運作:::： ，路包含N級串接之第三移位暫存單元，分別用來_相對 應之該N條鬧極線以顯示該複數個晝面中接續於該第一畫 面後之-第二畫面；及—第四驅動電路，設於該第二非顯示 區域内並依據-第四組控制訊號來運作，該第四驅動電路包 級串接之第四移位暫存料，分湘來驅動相對應之該 N條閘極線以顯示該第二畫面。 本發明另提供一種液晶顯示褒置，包含一顯示區域，其 上設有複數條互相平行之_線；―第—非顯示區域和一第 非,.、·員示區域，为別位於該顯示區域之兩對向側丨一第一驅 ，電路’設於該第-非顯示區域内並依據—第—組控制訊號 來運作，該第一驅動電路包含複數級串接之第一移位暫存單 元，分別用來驅動該複數條閘極線中相對應之奇數條閘極線 以顯示複數個畫面中之一第一畫面；一第二驅動電路，設於 該第一非顯示區域内並依據一第二組控制訊號來運作，該第 二驅動電路包含複數級串接之第二移位暫存單元，分別用來 驅動該複數條閘極線中相對應之偶數條閘極線以顯示該第 —晝面；一第三驅動電路，設於該第二非顯示區域内並佟據 201112211 一第二組控制訊號來運作，該第三驅動電路包含複數級串接 之第三移位暫存單元，分別用來驅動該相對應之奇數條閘極 線以顯示該複數個晝面中接續於該第一晝面後之一第二書 面；及一第四驅動電路，設於該第二非顯示區域内並依據一 第四組控制訊號來運作，該第四驅動電路包含複數級串接之 第四移位暫存單元，分別用來驅動該相對應之偶數條閘極線 以顯示該第二晝面。 本發明另提供一種液晶顯示裴置之驅動方法，包含以一 第一驅動電路來驅動一閘極線以顯示複數個晝面令之一第 一晝面；及關閉該第一驅動電路並以一第二驅動電路來驅動 該閘極線以顯示該複數個晝面中接續於該第一晝面後之一 第二晝面。 【實施方式】 請參考第3圖，第3圖為本發明第一實施例中一液晶顯 示裝置100之簡化方塊示意圖。第3圖僅顯示了液晶顯示裝 置100之部分結構，包含複數條閘極線GL(1)〜GL(N)、兩 閘極驅動電路10和11，.以及一時序控制器2〇。閘極線 〜GL(N)設於液晶顯示裝置1〇〇之顯示區域30内，可分別依 據閘極驅動訊號GS(1)〜GS(N)來驅動晝素。閘極驅動電路 10設於液晶顯示裝置100之非顯示區域40L内，其包含複 201112211 數級移位暫存單元SR ( 1 )〜SR ( N ) ’可依據時序控制器 20所產生之起始脈衝訊號VST ( 1 )和時脈訊號CK、XCK 來分別輸出閘極驅動訊號GS(1)〜GS(N)至相對應之閘極線 GL(1)〜GL(N);閘極驅動電路11設於液晶顯示裝置1〇〇之 非顯示區域40R内’其包含複數級移位暫存單元sr，（ 1 ) 〜SR’（N)，可依據時序控制器2〇所產生之起始脈衝訊號 vst’（ 1)和時脈訊號CK’、XCK，來分別輸出閘極驅動訊號 φ GS⑴〜GS(N)至相對應之閘極線GL(1)〜GL(N)。其中，非 顯示區域40L和40R分別位於顯示區域3〇之兩對向側，且 N為正整數。在第3圖中，顯示區域3〇和非顯示區域仙[、 40R之標示範圍僅為了說明各元件之位置，並不限定本發明 液晶顯示裝置1〇〇中各元件之實際大小比例。 本發明第一實施例之液晶顯示裝置1〇〇採用雙邊佈局 單端驅動之_，並以分時啟動的方式來驅^^換而言之， •間極驅動電路10和u係分別設置於間極線GL⑴〜沉⑼ 之兩對向側，在顯示複數個晝面中一晝面F 時，閘極 f動訊號GS⑴〜GS(N)由第3圖左側之閘極驅動電路⑺來 提供（由實線‘頭來表示）；在顯*接續晝面F(N)之後的 晝面F (N+1)時，閘極驅動訊號GS(1)〜GS(N)由第3圖右 側之閘極驅動電路11來提供（由虛線箭頭來表示）。 。月參考第4圖，第4圖為本發明第二實施例中-液晶顯 201112211 不裝置200之簡化方塊示意圖。第4圖僅顯示了液晶顯示裝 置200之部分結構，包含複數條閘極線GL(1)〜GL(N)、兩 閘極驅動電路1()和u，以及一時序控制器2()。閘極線沉⑴ 〜GL(N)设於液晶顯示裝置200之顯示區域30内，可分別依 據閘極驅動訊號GS(1)〜GS(N)來驅動晝素。閘極驅動電路 10 β又於液日日顯示裝置2〇〇之非顯示區域4〇内，其包含複數 級移位暫存單元SR(1)〜SR(N)，可依據時序控制器2〇 所產生之起始脈衝訊號VST (丨）和時脈訊號CK、XCK來 分別輸出閘極驅動訊號GS(1)〜GS(N)至相對應之閘極線 GL(1)〜GL(N);閘極驅動電路η亦設於液晶顯示裝置2〇〇 之非顯示區域40内，其包含複數級移位暫存單元SR，（ j ) 〜SR (Ν) ’可依據時序控制器2〇所產生之起始脈衝訊號 VST’（1)和時脈訊號CK，、XCK，來分別輸出閘極驅動訊號 GS(1)〜GS(N)至相對應之閘極線GL(1)〜,其中N為 正整數。在第4圖中，顯示區域3〇和非顯示區域4〇之標示 範圍僅為了說明各元件之位置，並不限定本發明液晶顯示裝 置200中各元件之實際大小比例。 本發明第二實施例之液晶顯示裝置2〇〇採用單邊佈局單 端驅動之架構’並以分時啟動的方式來驅動。換而言之，閘 極驅動電路10和11皆設置於閘極線GL(1)〜GL(N)之一侧， 並從同一側來驅動閘極線GL(1)〜GL(N)。在顯示複數個晝 面中一晝面F (N)時，閘極驅動訊號gs(1)〜GS(N)由閘極 201112211 .驅動電路10來提供（由實線箭頭來表示）；在顯示接續畫面 F(N)之後的畫面F(N+1 )時’閘極驅動訊號⑴〜g柳) 由閘極驅動電路U來提供（由虛線箭頭來表示）。 請參考第5圖，第5圖為本發明第—實施例之液晶顯示 裝置100和本發明第二實施例之液晶顯示裝置2⑼在運作時 之時序圖。在閘極驅動電路10中，第一級移位暫存單元 φ (1)依據時序控制器20所產生之起始脈衝訊號vstu) 來輸出帛、級閘極驅動訊號GS⑴，而第二級至帛N級移位 暫存單tlSR(2)〜SR(N)則分別依據前一級移位暫存單 元SR ( 1 )〜SR ( N-1 )所產生之起始脈衝訊號VST ( 2)〜 VST (N)來分別輸出第二級至第N級閘極驅動訊號gS(2) GS(N)，在閘極驅動電路中，第一級移位暫存單元sr， (1 )依據時序控制器20所產生之起始脈衝訊號VST，（ j ) 來輸出第一級閘極驅動訊號Gs(1)，而第二級至第N級移位 ♦，存單元SR，（2)〜SR，（N)則分別依據前一級移位暫存 單元SR ( 1 )〜SR’（N-1 )所產生之起始脈衝訊號VST，（ 2) 〜VST (N)來輸出第二級至第N級閘極驅動訊號gS(2)〜 gs(n)。在本發明中之液晶顯示裝置1〇〇和2〇〇中兩組閘 極驅動電路1〇和u可依據不同畫面而交替地開啟和關閉， 父替開關之週期可為一個或多個晝面。假設複數個畫面中兩 '* 相鄰晝面F ( N )和F ( N+1 )之間為切換閘極驅動電路1〇 - 和11之時間點，此時起始脈衝訊號VST ( 1 )〜VST ( N ) 201112211 和VST’（ 1 )〜VST’（N)之時序圖如第5圖所示。 請參考第6圖，第6圖為本發明第三實施例中一液晶顯 示裝置300之簡化方塊示意圖。第6圖僅顯示了液晶顯示裝 置300之部分結構’包含複數條閘極線GL(1)〜GL(N)、四 閘極驅動電路1 〇A、10B、10A’和10B ’，以及一時序控制 20。閘極線GL(1)〜GL(N)設於液晶顯示裝置3〇〇之顯示區 域30内’可分別依據閘極驅動訊號GS(1)〜GS(N)來驅動書 素。閘極驅動電路10A設於液晶顯示裝置3〇〇之非顯示區域 40L内，其包含複數級移位暫存單元SR_A( 1)〜SR_A(n)， 可依據時序控制器20所產生之起始脈衝訊號vst A ( 1 )和 時脈訊號CKA、XCKA來分別輸出奇數級閘極驅動訊號 08(1)、08(3)、."、08(义1)至相對應之奇數條閘極線（}乙(1)、 GL (3)、…、GL(N-l)。閘極驅動電路10B設於液晶顯示事 置300之非顯示區域40L内，其包含複數級移位暫存單元 SR一B (1)〜SR_B (η)’可依據時序控制器2〇所產生之起 始脈衝訊號VST—B ( 1 )和時脈訊號CKB、XCKB來分別輸 出偶數級閘極驅動訊號GS(2)、GS (4)、...、GS(N)至相對 應之偶數條閘極線GL(2)、GL (4)、...、gL(N)。閘極驅動 電路10A’設於液晶顯示裝置300之非顯示區域4〇R内，其 包含複數級移位暫存單元SR〜A，（1)〜SR—A，（n)，可依據 時序控制器20所產生之起始脈衝訊號vST—A，（1)和時脈 訊號CKA、XCKA來分別輸出奇數級閘極驅動訊號1)、 12 201112211 GS (3)、…、GS(N-l)至相對應之奇數條閘極線gl(1)、GL (3)、…、GL(N-l)。閘極驅動電路10B，設於液晶顯示裝置 300之非顯示區域40R内，其包含複數級移位暫存單元 SR_B’（ 1 )〜SR—Β’（η)，可依據時序控制器2〇所產生之 起始脈衝訊號VST_B’（ 1 )和時脈訊號CKB，、XCKB’來分 別輸出偶數級閘極驅動訊號GS(2)、GS (4)、…、GS(N)至 相對應之偶數條閘極線GL(2)、GL ( 4)、...、GL(N)。其中， 非顯示區域40L和40R分別位於顯示區域3〇之兩對向側， N和η為正整數’且N之值為2n。在第6圖中，顯示區域 30和非顯示區域40L、40R之標示範圍僅為了說明各元件之 位置’並不限定本發明液晶顯示裝置300中各元件之實際大 小比例。 本發明第三實施例之液晶顯示裝置300採用雙邊佈局單 端驅動之架構，並以分時啟動的方式來驅動。換而言之，閘 # 極驅動電路10A和10B設置於閘極線GL(1)〜GL(N)之一 側，閘極驅動電路10A’和10B’設置於閘極線GL(1)〜GL(N) 之另一側，但顯示畫面時僅會開啟設置於閘極線GL(1)〜 GL(N)其中一側之閘極驅動電路。舉例來說，在顯示複數個 畫面中一晝面F(N)時，閘極驅動電路10A和10B為開啟， 而閘極驅動電路10A’和10B’為關閉，此時閘極驅動訊號 GS(1)〜GS(N)由閘極驅動電路10A和10B來提供（由實線 箭頭來表示）；在顯示接續晝面F(N)之後的畫面F (N+1) 201112211 時，閘極驅動電路10A，和10B，為開啟，而閘極驅動電路i〇a 和10B為關閉，此時閘極驅動訊號GS(1)〜GS(N)*閘極驅 動電路10A，和10B，來提供（由虛線箭頭來表示）。 δ月參考第7圖，第7圖為本發明第四實施例中一液晶顯 示裝置4〇〇之簡化方塊示意圖。第7圖僅顯示了液晶顯示裝 置400之部分結構’包含複數條閘極線^以丨）〜gl(n)、四 閘極驅動電路1〇Α、10B、10A’和1〇B’，以及一時序控制器 2〇 °閘極線GL(1)〜GL(N)設於液晶顯示裝置400之顯示區 域30内，可分別依據閘極驅動訊號GS(1)〜GS(N)來驅動晝 素。閘極驅動電路10Λ設於液晶顯示裝置400之非顯示區域 40L内’其包含複數級移位暫存單元SR_A( 1 )〜SR_A( η)， 可依據時序控制器20所產生之起始脈衝訊號VST_A( 1)和 時脈訊號CKA、XCKA來分別輸出奇數級閘極驅動訊號 GS(1)、GS( 3 )、...、GS(N-1)至相對應之奇數條閘極線gl(1)、 GL (3)、…、GL(N-l)。閘極驅動電路i〇B設於液晶顯示裝 置400之非顯示區域40R内’其包含複數級移位暫存單元 SR—B ( 1 )〜SR_B ( η)，可依據時序控制器20所產生之起 始脈衝訊號VST—Β ( 1)和時脈訊號CKB、XCKB來分別輸 出偶數級閘極驅動訊號GS(2)、GS (4)、…、GS(N)至相對 應之偶數條閘極線GL(2)、GL ( 4 )、…、GL(N)。閘極驅動 電路10A’設於液晶顯示裝置400之非顯示區域40R内，其 包含複數級移位暫存單元SR一A，（ 1)〜SR_A，（n)，可依據 201112211 時序控制器20所產生之起始脈衝訊號VST_A，（ 1)和時脈 訊號CKA’、XCKA’來分別輸出奇數級閘極驅動訊號GS(1)、 GS (3)、...、GS(N-l)至相對應之奇數條閘極線GL(1)、GL (3)、…、GL(N-l)。閘極驅動電路10B’設於液晶顯示裝置 .400之非顯示區域40L内’其包含複數級移位暫存單元SR_B， (1)〜SR_B’（η) ’可依據時序控制器20所產生之起始脈 衝訊號VST—Β’（ 1)和時脈訊號CKB，、XCKB，來分別輸出 偶數級閘極驅動訊號GS(2)、GS (4)、…、GS(N)至相對應 之偶數條閘極線GL(2)、GL ( 4 )、…、GL(N)。其中，非顯 示區域40L和40R分別位於顯示區域30之兩對向側，N和 η為正整數，且N之值為2n。在第7圖中，顯示區域30和 非顯示區域40L、40R之標示範圍僅為了說明各元件之位 置’並不限定本發明液晶顯示裝置400中各元件之實際大小 比例0 本發明第四實施例之液晶顯示裝置400採用雙邊佈局雙 端驅動之架構’並以分時啟動的方式來驅動。換而言之，閘 極驅動電路10A和10A’分別設置於閘極線GL(1)〜GL(N)之 兩對向側，而閘極驅動電路10B和10B，分別設置於閘極線 GL(1)〜GL(N)之兩對向側，但顯示畫面時僅會在閘極線 GL(1)〜GL(N)之兩側各開啟一閘極驅動電路。舉例來說，在 顯示複數個晝面中一晝面F(N)時，閘極驅動電路10A和 10B為開啟’而閘極驅動電路i〇A，和10B’為關閉，此時閘 15 201112211 極驅動訊號GS(1)〜gs(n)由閘極驅動電路1〇A和1〇B來提 供（由實線箭頭來表示）；在顯示接續畫面F (N)之後的書 面F (N+1)時，閘極驅動電路1〇A，和1〇B，為開啟，而閘極 驅動電路10A和10B為關閉，此時閘極驅動訊號GS(1)〜 GS(N)由閘極驅動電路1〇A，和10B，來提供（由虛線箭頭來表 示）。 凊參考第8圖，第8圖為本發明第五實施例中一液晶顯 不裝置500之簡化方塊示意圖。第8圖僅顯示了液晶顯示襞 置500之部分結構，包含複數條閘極線GL(1)〜GL(N)、四 閘極驅動電路l〇A、10B、10A，和l0B，，以及一時序控制器 20。閘極線GL(1)〜GL(N)設於液晶顯示裝置5〇〇之顯示區 域30内，可分別依據閘極驅動訊號（^(1)〜〇3(>〇來驅動晝 素。閘極驅動電路10A設於液晶顯示裝置5〇〇之非顯示區域 40L内’其包含複數級移位暫存單元SR_A(；， 可依據時序控制器20所產生之起始脈衝訊號vst_A( 1 )和 時脈訊號CKA、XCKA來分別輸出奇數級閘極驅動訊號 〇8(1)、〇3(3)、."、〇3(1^1)至相對應之奇數條閘極線0^(1)、 GL (3)、…、GL(N-l)。閘極驅動電路1〇B設於液晶顯示骏 置500之非顯示區域40R内，其包含複數級移位暫存單元 SR一B (1)〜SR_B (η)’可依據時序控制器2〇所產生之起 始脈衝訊號VST_B ( 1)和時脈訊號CKB、XCKB來分別輸 出偶數級閘極驅動§凡说GS(2)、GS ( 4 )、· ·、GS(N)至相針 201112211 應之偶數條閘極線GL(2)、GL (4)、...、gl(n)。閘極驅動 電路，設於液晶顯示裝置獨之非顯示區域视内且包 含複數級移㈣存單元SR_A，⑴〜Sr_a，u)，可依據時 序控制器2G所產生之起始脈衝訊號Vst_a,⑴和時脈訊The gate line is to display the first surface; the third driving phase f should be in the N: display area and operate according to the third group of control signals::::, the road includes the N series connection a three-shift temporary storage unit for respectively corresponding to the N noise lines for displaying a second picture after the first picture is connected to the first picture; and a fourth driving circuit is provided The second non-display area operates according to the fourth group of control signals, and the fourth driving circuit is connected in series with the fourth shift temporary storage material, and the corresponding driving of the N gate lines is driven by This second screen is displayed. The invention further provides a liquid crystal display device, comprising a display area on which a plurality of parallel lines are arranged; a first-non-display area and a non-display area, and a member area, which is located in the display The first driving circuit is disposed in the first non-display area and operates according to the first group control signal, and the first driving circuit includes a first shift of the plurality of serial connections. a memory unit, configured to drive a corresponding one of the plurality of gate lines of the plurality of gate lines to display a first picture of the plurality of pictures; a second driving circuit disposed in the first non-display area Working according to a second group of control signals, the second driving circuit includes a plurality of serially connected second shifting temporary storage units for respectively driving corresponding even-numbered gate lines of the plurality of gate lines to display The third driving circuit is disposed in the second non-display area and operates according to a second group of control signals of 201112211, wherein the third driving circuit comprises a third shift of the plurality of serial connections Storage unit, respectively used to drive the phase Corresponding odd-numbered gate lines for displaying a second one of the plurality of top faces connected to the first one of the first faces; and a fourth driving circuit disposed in the second non-display area and according to a fourth The fourth control circuit includes a plurality of serially connected fourth shift temporary storage units for driving the corresponding even number of gate lines to display the second side. The present invention further provides a driving method of a liquid crystal display device, comprising: driving a gate line with a first driving circuit to display a first surface of a plurality of surface commands; and turning off the first driving circuit and The second driving circuit drives the gate line to display a second one of the plurality of sides that is connected to the first one. [Embodiment] Please refer to FIG. 3, which is a simplified block diagram of a liquid crystal display device 100 according to a first embodiment of the present invention. Fig. 3 shows only a part of the structure of the liquid crystal display device 100, and includes a plurality of gate lines GL(1) to GL(N), two gate driving circuits 10 and 11, and a timing controller 2A. The gate lines WL(N) are provided in the display area 30 of the liquid crystal display device 1A, and the pixels can be driven according to the gate driving signals GS(1) to GS(N), respectively. The gate driving circuit 10 is disposed in the non-display area 40L of the liquid crystal display device 100, and includes a plurality of 201112211 digital shift register units SR(1) to SR(N)' which may be generated according to the timing controller 20. The pulse signal VST (1) and the clock signals CK, XCK respectively output the gate driving signals GS(1) to GS(N) to the corresponding gate lines GL(1) to GL(N); the gate driving circuit 11 is disposed in the non-display area 40R of the liquid crystal display device 1', and includes a plurality of shift register units sr, (1) to SR'(N), which can be generated according to the start pulse generated by the timing controller 2 The signal vst'(1) and the clock signals CK' and XCK respectively output the gate driving signals φ GS(1) GS(N) to the corresponding gate lines GL(1) GL GL(N). The non-display areas 40L and 40R are respectively located on opposite sides of the display area 3, and N is a positive integer. In Fig. 3, the display area of the display area 3 and the non-display area [, 40R is only for explaining the position of each element, and does not limit the actual size ratio of each element in the liquid crystal display device 1 of the present invention. The liquid crystal display device 1 of the first embodiment of the present invention adopts a bilaterally-arranged single-ended driving mode, and is driven in a time-division manner. The inter-polar driving circuit 10 and the u-system are respectively disposed on On the opposite sides of the inter-polar line GL(1)~Sink(9), when one of the plurality of kneading planes is displayed, the gate f-motion signals GS(1) to GS(N) are provided by the gate driving circuit (7) on the left side of FIG. (indicated by the solid line 'head); the gate drive signals GS(1) to GS(N) are from the right side of the third figure when the surface F (N+1) after the F(N) is connected The gate drive circuit 11 is provided (indicated by a dashed arrow). . Referring to FIG. 4, FIG. 4 is a simplified block diagram of a liquid crystal display 201112211 non-device 200 in a second embodiment of the present invention. Fig. 4 shows only a part of the structure of the liquid crystal display device 200, and includes a plurality of gate lines GL(1) to GL(N), two gate driving circuits 1() and u, and a timing controller 2(). The gate lines sinking (1) to GL(N) are provided in the display area 30 of the liquid crystal display device 200, and the pixels can be driven according to the gate driving signals GS(1) to GS(N), respectively. The gate driving circuit 10β is further included in the non-display area 4〇 of the liquid day display device 2〇〇, and includes a plurality of stages of shift register units SR(1) to SR(N), which can be according to the timing controller 2〇 The generated start pulse signal VST (丨) and the clock signals CK, XCK respectively output the gate drive signals GS(1) to GS(N) to the corresponding gate lines GL(1) to GL(N) The gate driving circuit η is also disposed in the non-display area 40 of the liquid crystal display device 2, and includes a plurality of shift register units SR, and (j)~SR(Ν)' can be used according to the timing controller 2 The starting pulse signal VST'(1) and the clock signals CK, XCK are generated to output the gate driving signals GS(1)~GS(N) to the corresponding gate lines GL(1)~, wherein N is a positive integer. In Fig. 4, the indication ranges of the display area 3 〇 and the non-display area 4 仅为 are only for explaining the positions of the respective elements, and do not limit the actual size ratio of each element in the liquid crystal display device 200 of the present invention. The liquid crystal display device 2 of the second embodiment of the present invention employs a single-sided layout single-ended driving architecture' and is driven in a time-division manner. In other words, the gate driving circuits 10 and 11 are disposed on one side of the gate lines GL(1) to GL(N), and drive the gate lines GL(1) to GL(N) from the same side. When one of the plurality of faces F (N) is displayed, the gate drive signals gs(1) to GS(N) are provided by the gate 201112211. The drive circuit 10 is provided (indicated by a solid arrow); When the picture F(N+1) after the picture F(N) is connected, the 'gate drive signal (1) to g will be supplied by the gate drive circuit U (indicated by a broken line arrow). Referring to Fig. 5, Fig. 5 is a timing chart showing the operation of the liquid crystal display device 100 of the first embodiment of the present invention and the liquid crystal display device 2 (9) of the second embodiment of the present invention. In the gate driving circuit 10, the first stage shift register unit φ(1) outputs the 闸, level gate driving signal GS(1) according to the starting pulse signal vstu generated by the timing controller 20, and the second stage is帛N-stage shift temporary storage lists tlSR(2)~SR(N) are respectively based on the start pulse signals VST(2)~VST generated by the previous stage shift register units SR(1)~SR(N-1) (N) respectively output the second to Nth gate drive signals gS(2) GS(N), in the gate drive circuit, the first stage shift register unit sr, (1) according to the timing controller 20 generated start pulse signals VST, (j) to output the first stage gate drive signal Gs (1), and the second stage to the Nth stage shift ♦, the memory unit SR, (2) ~ SR, ( N) outputs the second to Nth stages according to the start pulse signals VST, (2) to VST (N) generated by the previous stage shift register units SR(1) to SR'(N-1), respectively. The gate drive signals gS(2) ~ gs(n). In the liquid crystal display devices 1 and 2 of the present invention, the two sets of gate driving circuits 1 and u can be alternately turned on and off according to different screens, and the period of the parenting switch can be one or more sides. . Assume that between the two '* adjacent faces F ( N ) and F ( N+1 ) in a plurality of pictures is the time point at which the gate drive circuits 1 〇 - and 11 are switched, and the start pulse signal VST ( 1 ) The timing diagrams of ~VST (N) 201112211 and VST'(1)~VST'(N) are shown in Figure 5. Please refer to FIG. 6. FIG. 6 is a simplified block diagram of a liquid crystal display device 300 according to a third embodiment of the present invention. 6 shows only a part of the structure of the liquid crystal display device 300 including a plurality of gate lines GL(1) to GL(N), four gate driving circuits 1A, 10B, 10A', and 10B', and a timing. Control 20. The gate lines GL(1) to GL(N) are disposed in the display area 30 of the liquid crystal display device 3' to drive the pixels in accordance with the gate driving signals GS(1) to GS(N), respectively. The gate driving circuit 10A is disposed in the non-display area 40L of the liquid crystal display device 3, and includes a plurality of stages of shift register units SR_A(1) to SR_A(n), which can be generated according to the timing controller 20 The pulse signal vst A (1) and the clock signals CKA and XCKA respectively output the odd-numbered gate drive signals 08(1), 08(3), .", 08(1) to the corresponding odd gates Lines (} B (1), GL (3), ..., GL (Nl). The gate driving circuit 10B is disposed in the non-display area 40L of the liquid crystal display device 300, and includes a plurality of stages of the shift register unit SR. B (1) ~ SR_B (η)' can output the even-numbered gate drive signal GS(2) according to the start pulse signal VST-B (1) generated by the timing controller 2〇 and the clock signals CKB and XCKB, respectively. GS (4), ..., GS (N) to the corresponding even number of gate lines GL (2), GL (4), ..., gL (N). The gate driving circuit 10A' is provided at The non-display area 4〇R of the liquid crystal display device 300 includes a plurality of stages of shift register units SR~A, (1) to SR_A, (n), which can be generated according to the start pulse generated by the timing controller 20. Signal vST-A, (1) and clock signal CKA, XCK A to output the odd-numbered gate drive signals 1), 12 201112211 GS (3), ..., GS (Nl) to the corresponding odd gate lines gl (1), GL (3), ..., GL (Nl ). The gate driving circuit 10B is disposed in the non-display area 40R of the liquid crystal display device 300, and includes a plurality of stages of shift register units SR_B'(1) to SR_Β'(n), which can be used according to the timing controller 2 The generated start pulse signal VST_B'(1) and the clock signal CKB, XCKB' respectively output the even-numbered gate drive signals GS(2), GS(4), ..., GS(N) to the corresponding even numbers Bar gate lines GL(2), GL(4), ..., GL(N). The non-display areas 40L and 40R are respectively located on opposite sides of the display area 3, N and n are positive integers and the value of N is 2n. In Fig. 6, the indication ranges of the display area 30 and the non-display areas 40L, 40R are merely for explaining the position of each element' and do not limit the actual size ratio of each element in the liquid crystal display device 300 of the present invention. The liquid crystal display device 300 of the third embodiment of the present invention adopts a double-sided layout single-ended driving architecture and is driven in a time-division manner. In other words, the gate electrode driving circuits 10A and 10B are disposed on one side of the gate lines GL(1) to GL(N), and the gate driving circuits 10A' and 10B' are disposed on the gate line GL(1)~ On the other side of GL(N), only the gate driving circuit provided on one side of the gate lines GL(1) to GL(N) is turned on when the screen is displayed. For example, when one face F(N) is displayed in a plurality of pictures, the gate drive circuits 10A and 10B are turned on, and the gate drive circuits 10A' and 10B' are turned off, and the gate drive signal GS ( 1) ~GS(N) is provided by the gate drive circuits 10A and 10B (indicated by solid arrows); the gate drive is displayed on the screen F (N+1) 201112211 after the display of the F(N) The circuits 10A, and 10B are turned on, and the gate driving circuits i 〇 a and 10 B are turned off, at which time the gate driving signals GS (1) GS GS (N) * the gate driving circuits 10A, and 10B are provided ( It is indicated by a dotted arrow). Reference is made to Fig. 7, which is a simplified block diagram of a liquid crystal display device 4 according to a fourth embodiment of the present invention. FIG. 7 shows only a part of the structure of the liquid crystal display device 400 including a plurality of gate lines 〜 gl (n), four gate driving circuits 1 〇Α, 10B, 10A ′, and 1 〇 B ′, and A timing controller 2 〇 ° gate lines GL (1) GL GL (N) are provided in the display area 30 of the liquid crystal display device 400, and can be driven according to the gate driving signals GS (1) to GS (N), respectively. Prime. The gate driving circuit 10 is disposed in the non-display area 40L of the liquid crystal display device 400 and includes a plurality of stages of shift register units SR_A(1) to SR_A(n), which can be generated according to the start pulse signal generated by the timing controller 20. VST_A(1) and clock signals CKA and XCKA respectively output odd-numbered gate drive signals GS(1), GS(3), ..., GS(N-1) to corresponding odd gate lines gl (1), GL (3), ..., GL (Nl). The gate driving circuit i〇B is disposed in the non-display area 40R of the liquid crystal display device 400. The macro driving circuit includes a plurality of stages of the shift register units SR_B (1) to SR_B (n), which can be generated according to the timing controller 20. The start pulse signal VST—Β (1) and the clock signals CKB and XCKB respectively output the even-numbered gate drive signals GS(2), GS(4), ..., GS(N) to the corresponding even gates Lines GL(2), GL(4), ..., GL(N). The gate driving circuit 10A' is disposed in the non-display area 40R of the liquid crystal display device 400, and includes a plurality of stages of the shift register units SR-A, (1) to SR_A, (n), which can be according to the timing controller 20 of 201112211. The generated start pulse signal VST_A, (1) and the clock signals CKA', XCKA' respectively output odd-numbered gate drive signals GS(1), GS(3), ..., GS(Nl) to corresponding The odd gate lines GL(1), GL(3), ..., GL(Nl). The gate driving circuit 10B' is disposed in the non-display area 40L of the liquid crystal display device 400. 'It includes a plurality of stages of shift register units SR_B, and (1) to SR_B'(n)' may be generated according to the timing controller 20. The start pulse signal VST—Β'(1) and the clock signals CKB, XCKB respectively output the even-numbered gate drive signals GS(2), GS(4), ..., GS(N) to the corresponding even numbers. Bar gate lines GL(2), GL(4), ..., GL(N). The non-display areas 40L and 40R are respectively located on opposite sides of the display area 30, N and η are positive integers, and the value of N is 2n. In FIG. 7, the display range of the display area 30 and the non-display areas 40L, 40R is only for explaining the position of each element' and does not limit the actual size ratio of each element in the liquid crystal display device 400 of the present invention. The liquid crystal display device 400 adopts a double-sided layout architecture of bilateral layout and is driven in a time-division manner. In other words, the gate driving circuits 10A and 10A' are respectively disposed on the opposite sides of the gate lines GL(1) to GL(N), and the gate driving circuits 10B and 10B are respectively disposed on the gate lines GL. (1) Two opposite sides of GL(N), but a gate drive circuit is turned on only on both sides of the gate lines GL(1) to GL(N) when the screen is displayed. For example, when one of the plurality of facets F(N) is displayed, the gate drive circuits 10A and 10B are turned "on" and the gate drive circuits i〇A, and 10B' are turned off, at which time the gate 15 201112211 The pole drive signals GS(1) to gs(n) are provided by the gate drive circuits 1A and 1B (indicated by solid arrows); written F (N+) after the display of the subsequent picture F (N) 1), the gate drive circuits 1〇A, and 1〇B are turned on, and the gate drive circuits 10A and 10B are turned off, at which time the gate drive signals GS(1) to GS(N) are driven by the gates. Circuits 1A, and 10B are provided (represented by dashed arrows). Referring to Figure 8, Figure 8 is a simplified block diagram of a liquid crystal display device 500 in accordance with a fifth embodiment of the present invention. Fig. 8 shows only a part of the structure of the liquid crystal display device 500, including a plurality of gate lines GL(1) to GL(N), four gate driving circuits 10A, 10B, 10A, and 10B, and a moment Sequence controller 20. The gate lines GL(1) to GL(N) are provided in the display area 30 of the liquid crystal display device 5, and can be driven by the gate driving signals (^(1) to 〇3(> The gate driving circuit 10A is disposed in the non-display area 40L of the liquid crystal display device 5', and includes a plurality of stages of the shift register unit SR_A (;, according to the start pulse signal vst_A(1) generated by the timing controller 20. And the clock signals CKA and XCKA respectively output odd-numbered gate drive signals 〇8(1), 〇3(3), .", 〇3(1^1) to the corresponding odd gate lines 0^ (1), GL (3), ..., GL (Nl). The gate driving circuit 1B is disposed in the non-display area 40R of the liquid crystal display 500, and includes a plurality of shift register units SR-B ( 1) ~SR_B (η)' can output the even-numbered gate drivers according to the start pulse signal VST_B (1) and the clock signals CKB and XCKB generated by the timing controller 2〇 § GS(2), GS (4), ··, GS(N) to phase pin 201112211 The even number of gate lines GL(2), GL(4), ..., gl(n). Gate drive circuit, set on liquid crystal display The device is unique to the display area and contains multiple levels (Iv) storage unit SR_A, ⑴~Sr_a, u), may be based upon the timing controller 2G start pulse signal arising Vst_a, ⑴ clock information, and
號CKA’、XCKA’來分別輸出奇數級間極驅動訊號gs⑴、 GS (3)、…、GS(N-l)至相對應之奇數條閘極線gl⑴、GL (3)、...、GL(N·”。閘極驅動電路_，設於液晶顯示裝置 500之非顯示區域40R内，其包含複數級移位暫存單元 SR一B’（1)〜SR_B’（η)，可依據時序控制器2〇所產生之 起始脈衝訊號VST_B’（ 1 )和時脈訊號ckb，、XCKB，來分 別輸出偶數級閘極驅動訊號GS(2)、GS ( 4 )、…、GS(N)至 相對應之偶數條閘極線GL(2)、GL ( 4 )、…、GL(N)。其中， 非顯示區域40L和40R分別位於顯示區域3〇之兩對向側， N和η為正整數’且N之值為2n。在第8圖中’顯示區域 30和非顯示區域40L、40R之標示範圍僅為了說明各元件之 馨位置，並不限定本發明液晶顯示裝置500中各元件之實際大 小比例。 本發明第五實施例之液晶顯示裝置500採用雙邊佈局雙 端驅動之架構’並以分時啟動的方式來驅動。換而言之，閘 極驅動電路10A和10A’設置於閘極線GL(1)〜GL(N)之一 側，而閘極驅動電路10B和10B’則設置於閘極線GL(1)〜 GL(N)之另一側，但顯示晝面時僅會在閘極線GLO)〜GL(N) 17 201112211No. CKA', XCKA' respectively output odd-numbered inter-level drive signals gs(1), GS(3), ..., GS(Nl) to corresponding odd-numbered gate lines gl(1), GL(3), ..., GL( N·”. The gate driving circuit _ is disposed in the non-display area 40R of the liquid crystal display device 500, and includes a plurality of shift register units SR-B'(1) to SR_B'(n), which can be controlled according to timing The start pulse signal VST_B'(1) and the clock signal ckb, XCKB generated by the device 2〇 output the even-numbered gate drive signals GS(2), GS(4), ..., GS(N) to Corresponding even-numbered gate lines GL(2), GL(4), ..., GL(N), wherein the non-display areas 40L and 40R are respectively located on opposite sides of the display area 3〇, and N and η are positive The integer ' and the value of N are 2n. The indication range of the display area 30 and the non-display areas 40L, 40R in Fig. 8 is only for explaining the position of each element, and does not limit the components of the liquid crystal display device 500 of the present invention. The actual size ratio. The liquid crystal display device 500 of the fifth embodiment of the present invention adopts a double-sided layout architecture of bilateral layout and drives in a time-division manner. In other words, the gate driving circuits 10A and 10A' are disposed on one side of the gate lines GL(1) to GL(N), and the gate driving circuits 10B and 10B' are disposed on the gate lines GL(1) to GL. (N) on the other side, but only when the surface is displayed on the gate line GLO) ~ GL(N) 17 201112211
而閘極驅動電路10A，和應，為關閉，此時閘極驅動訊號 GS(1)〜GS(N)由閘極驅動電路10A和1〇B來提供（由實線 箭頭來表示）；在顯示接續晝面F (N)之後的晝面f &便的畫面F (N+1) 而閘極驅動電路1 〇 A 1)〜GS(N)由閘極驅 時，閘極驅動電路l〇A，和10B，為開啟，而 和10B為關閉，此時閘極驅動訊號 動電路10A’和10B’來提供（由虛線箭頭來表示）。 。月參考第9圖’第9圖為本發明第三實施例之液晶顯示 裝置300、本發明第四實施例之液晶顯示裝置4〇〇以及本發 明第五實施例之液晶顯示裝置5〇〇在運作時之時序圖。在閘 極驅動電路10A中，移位暫存單元811-入（1)依據時序控 制器20所產生之起始脈衝訊號VST一a (丨）來輸出第一級閘 極驅動訊號GS(1)，而移位暫存單元SR-A 〜sr_a 則分別依據前一級移位暫存單元SR—A ( 〜SR—A (η—。 所產生之起始脈衝訊號VST_A (2)〜VST—A (n)來分別 輸出奇數級閘極驅動訊號Gs(3)、GS(5)、…、GS(N-l)。在 閘極驅動電路10Β中，移位暫存單元SR—B (丨）依據時序控 制态20所產生之起始脈衝訊號VST_B( 1)來輸出第二級閘 極驅動訊號GS(2)，而移位暫存單元SR_B (2)〜SR B (n) 則分別依據前一級移位暫存單元SR_B (丨）〜SR-B ΐ ) 所產生之起始脈衝訊號VST—B (2)〜VST一B (n)來分別輸 201112211 出偶數級閘極驅動訊號Gs(2)、GS⑷、、GS(N)。在門極 驅動電路10A，中，移位暫存單元SR_A，（1)依據時序控= 器20所產生之起始脈衝訊號VST-A，（丨）來輸出第一級門 極驅動訊號GS(1) ’而移位暫存單元SR_A，（2)〜sr A，（） 則分別依據前一級移位暫存單元SR A，（丨）〜s — vn-l) 所產生之起始脈衝訊號VST一A，〜VST—A，來八別 輸出奇數級閘極驅動訊號GS(3)、GS⑺、…、gs(n_1)。在 閘極驅動電路10B，中，移位暫存單元SR_B，（1)依據時序 控制器20所產生之起始脈衝訊號VST_B，（丨）來輪出第一 級閘極驅動訊號GS(2)，而移位暫存單元SR__B (2)〜sr b (η)則分別依據前一級移位暫存單元SR—B，（ ！）〜b， (n_1)所產生之起始脈衝訊號VST_B，（2)〜VS丁 B，I 來分別輸出偶數級閘極驅動訊號Gs(4)、GS(6)、 、GS(N)n 在本發明中之液晶顯示裝置3〇〇、4〇〇和5〇〇中閘極驅動 電路10A/10B和閘極驅動電路10A，/1〇B，可依據 ^ 』思面而 父替地開啟和關閉，交替開關之週期可為一個或多個晝面。 假設複數個畫面中兩相鄰畫面F (N)和F (N+1)之間為切 換閘極驅動電路10A/10B和閘極驅動電路1〇a，/1〇b,之時間 點，此時起始脈衝訊號VST_A(1) 〜VST—Α(η)、ν§τΒΒ ⑴〜VST—B ( η)、VST一a’ ⑴〜VST—A，（ n)、和州 b， (1)〜VST—B’（n)之時序圖如第9圖所示。 ~ 液晶 °月參考第10圖，第1〇圖為本發明第六實施例中一 201112211 顯示裝置600之簡化方螝示意圖β第10圖僅顯示了液晶顯 示裝置600之部分結構，包含複數條閘極線GL(1)〜GL(N)、 四閘極驅動電路10A、10B、10A’和10B’，以及一時序控制 器20。閘極線GL(1)〜GL(N)設於液晶顯示裝置600之顯示 區域30内，可分別依據閘極驅動訊號GS__A(1)〜GS_A(N) 和GS_B(1)〜GS_B(N)來驅動晝素。閘極驅動電路10A設於 液晶顯示裝置600之非顯示區域40L内，其包含複數級移位 暫存單元SR_A ( 1)〜SR_A (N)，可依據時序控制器20 ^ 所產生之起始脈衝訊號VST_A( 1)和時脈訊號CKA、XCKA 來分別輸出閘極驅動訊號GS_A(1)〜GS_A(N)至相對應之 閘極線GL(1)〜GL(N)。閘極驅動電路10B設於液晶顯示裝 置600之非顯示區域40R内，其包含複數級移位暫存單元 SR_B (1)〜SR_B (N)，可依據時序控制器20所產生之起 始脈衝訊號VST_B ( 1 )和時脈訊號CKB、XCKB來分別輸 出閘極驅動訊號GS_B(1)〜GS_B(N)至相對應之閘極線 GL(1)〜GL(N)。閘極驅勤電路i〇A，設於液晶顯示裝置60〇 # 之非顯示區域40L内，其包含複數級移位暫存單元SR_A，（ i ) SR-A ( N )，可依據時序控制器20所產生之起始脈衝訊 號VST一A’（ 1 )和時脈訊號CKA，、XCKA，來分別輸出閘極 驅動訊號GS_A⑴〜GS一A(N)至相對應之閘極線GL⑴〜 gl(n)。閘極驅動電路10B，設於液晶顯示裝置6〇〇之非顯示 區域4〇R内，其包含複數級移位暫存單it SR_B，（ 1 )〜SR_B， (N)’可依據時序控制n 2Q所產生之起始脈衝訊號 VST B’ 20 201112211 (1 )和時脈訊號CKB’、XCKB’來分別輸出閘極驅動訊號 GS_B(1)〜GS_B(N)至相對應之閘極線沉⑴〜GL(N)e其 中’非顯示區域40L和40R分別位於顯示區域之兩對向 側，而N為正整數。在第1 〇圖中，顯示區域3〇和非顯示區 域40L、40R之標示範圍僅為了說明各元件之位置，並不限 定本發明液晶顯示裝置600中各元件之實際大小比例。 鲁 本發明第六實施例之液晶顯示裝置600採用雙邊佈局 雙端驅動之架構，並以分時啟動的方式來驅動。換而言之， 閘極驅動電路10A和10B分別設置於閘極線gl(1)〜GL(N) 之兩對向側，而閘極驅動電路10A’和10B ’分別設置於閘極 線GL( 1)〜GL(N)之兩對向側，顯示畫面時會在閘極線gl(1 ) 〜GL(N)之兩側皆各開啟一閘極驅動電路。舉例來說，在顯 示複數個晝面中一畫面F ( N )時，閘極驅動電路1 〇 a和1 〇B 為開啟，而閘極驅動電路10A’和10B’為關閉，此時閘極驅 • 動訊號GS_A(1)〜GS_A(N)和GS—B(l)〜GS_B(N)分別由閘 極驅動電路10A和10B來提供（由實線箭頭來表示）；在顯 示接續晝面F (N)之後的晝面F (N+1)時，閘極驅動電路 10A’和10B’為開啟，而閘極驅動電路10A和10B為關閉， 此時閘極驅動訊號GS__A( 1)〜GS_A(N)和GS JB( 1)〜 分別由閘極驅動電路10A’和10B’來提供（由虛線箭頭來表 示）。 21 201112211 1署月Inf Γ 11圖’第U圖為本發明第六實施例之液晶顯 不議在運作時之時序圖。在閘極驅動電路ι〇Α中，移 2 :早兀SR—A⑴依據時序控制器2〇所產生之起始脈 暫存單元SR A⑺H GW1)，而移位 ,〇p ^ 一 } R~A(N)則分別依據前一級移位暫 子早^_A⑴〜SR—A (N_1}所產生之起始脈衝訊號 —()VST~A(N)來分別輸出閘極驅動訊號GS_A (2)〜GS-A(N)。在閘極驅動電路議中，移位暫存單元SR』 ⑴依據時序控制n 2G所產生之起始脈衝訊號VST—B⑴ 來輸出閘極驅動訊號Gs—B⑴，而移位暫存單元sr—B⑴ SR_B (N)則分別依據前—級移位暫存單元sr—b⑴〜 SR一B (N-1)所產生之起始脈衝訊號ν§τ—b⑴〜b (N)來分別輸出GS—B (2)〜GS-B(n)。在閘極驅動電路⑺八， 中移位暫存單元SR—a，（ 1 )依據時序控制器2〇所產生之 起始脈衝訊號VST—A，⑴來輸出閉極驅動訊號GS A⑴， 而移位暫存單元SR、A，⑴〜SR（N)則分別依據前一 級移位暫存單A，⑴〜狄-α，（ν·ι)職生之起始 脈衝訊號VST_A’⑺〜VST_A，（N)來分別輸出間極驅動 ^ GS_A(2)〜GS—A(N)。在閘極驅動電路1〇B，中，移位暫 存早tlSR_B (1)依據時序控制器2〇所產生之起始脈衝訊 ，VST一B’⑴來輸出閘極驅動訊號gs—b(i)，而移位暫存 f元SR—B’（2)〜SR-B，（N)則分別依據前一級移位暫存 單το SRj ( 1)〜SR—b’（N_1：)所產生之起始脈衝訊號 22 201112211 VST—B (2)〜VST一B’（N)來分別輸出 dB ⑺〜Gs—b(n)。 在本發明中之液晶顯示裝置6〇〇中，閉極驅動電路1〇心卿 和間極驅動電路1〇A7_，可依據不同晝面而交替地開啟和 關閉’交替_之㈣可為―個❹個畫面。假設複數個晝 面中兩相鄰晝面F(N)和F(N+1)之間為切換閘極驅動電 路1〇Α/10Β*閘極驅動電路1〇a，/1〇b，之時間點，此時起始 脈衝訊號 VST—A (1)〜VST—MN)、VST_B (丨}〜vst_b # ( N )、VST一A，⑴〜VST—A，( N )、和 vst—b，⑴〜vst—b， (N)之時序圖如第I〗圖所示。 本發明利用多組閘極驅動電路以分時啟動之方式來驅 動閘極線’可減少移位暫存單元㈣膜電晶體之閘極電壓應 力，因此能增加液晶顯示器的使用期限與可靠度。 产以上所述僅為本發明之較佳實施例，凡依本發明申請專 •利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為先前技術中一液晶顯示裝置之簡化方塊示意圖。 第2圖為第1圖之液晶顯示裝置在運作時之時序圖。 第3圖為本發明第一實施例中一液晶顯示裂置之簡化方塊示 意圖。 23 201112211 第4圖為本發明第二實施例中一液晶顯示裝置之簡化方塊示 意圖。 第5圖為本發明第一和第二實施例之液晶顯示裝置在運作時 之時序圖。 第6圖為本發明第三實施例中一液晶顯示裝置之簡化方塊示 意圖。 第7圖為本發明第四實施例中一液晶顯示裝置之簡化方塊示 意圖。 第8圖為本發明第五實施例中一液晶顯示裝置之簡化方塊示 意圖。 第9圖為本發明第三至第五實施例之液晶顯示裝置在運作時 之時序圖。 、 第10圖為本發明第六實施例中一液晶顯示裴置之簡化方塊 示意圖。 第11圖為本發明第六實施例之液晶顯示裴置在運作時之時 序圖。 亏 【主要元件符號說明】 閘極線 非顯示區域 間極驅動電路 20 時序控制器 GL( 1)〜GL(N)The gate driving circuit 10A, and should be turned off, at which time the gate driving signals GS(1) to GS(N) are provided by the gate driving circuits 10A and 1B (indicated by solid arrows); Displaying the picture F (N+1) of the face f & after the F (N) is connected and the gate drive circuit 1 〇A 1) to GS(N) are driven by the gate, the gate drive circuit 1 〇A, and 10B are turned on, and the sum 10B is off, at which time the gate drive signal circuits 10A' and 10B' are provided (indicated by dashed arrows). . 9 is a liquid crystal display device 300 according to a third embodiment of the present invention, a liquid crystal display device 4 according to a fourth embodiment of the present invention, and a liquid crystal display device 5 according to a fifth embodiment of the present invention. Timing diagram for operation. In the gate driving circuit 10A, the shift register unit 811-in (1) outputs the first-stage gate driving signal GS(1) according to the start pulse signal VST_a (丨) generated by the timing controller 20. The shift register units SR-A to sr_a are respectively based on the previous stage shift register unit SR_A (~SR_A (n-.) the generated start pulse signals VST_A (2) ~ VST-A ( n) respectively output odd-numbered gate drive signals Gs(3), GS(5), ..., GS(Nl). In the gate drive circuit 10A, the shift register unit SR_B (丨) is controlled according to timing The start pulse signal VST_B(1) generated by the state 20 outputs the second-stage gate drive signal GS(2), and the shift register units SR_B(2) to SRB(n) are respectively shifted according to the previous stage. The temporary pulse signals SR_B (丨) ~ SR-B ΐ ) are generated by the start pulse signals VST-B (2) ~ VST - B (n) to respectively input the 201112211 out of the even-numbered gate drive signals Gs (2), GS (4) GS(N). In the gate driving circuit 10A, the shift register unit SR_A, (1) outputs the first according to the start pulse signal VST-A (丨) generated by the timing controller=20. Stage gate drive signal GS(1) The shift register units SR_A, (2) ~ sr A, () are respectively based on the start pulse signal VST-A generated by the previous stage shift register unit SR A, (丨) ~ s - vn - l) , ~VST-A, to eight output odd-numbered gate drive signals GS (3), GS (7), ..., gs (n_1). In the gate driving circuit 10B, the shift register unit SR_B, (1) according to the start pulse signal VST_B generated by the timing controller 20, (丨) to turn out the first stage gate driving signal GS (2) The shift register units SR__B (2) to sr b (n) are respectively based on the start pulse signal VST_B generated by the previous stage shift register unit SR_B, (!)~b, (n_1), ( 2) ~ VS D, B, respectively output even-numbered gate drive signals Gs (4), GS (6), GS (N) n In the present invention, liquid crystal display devices 3, 4, and 5 The middle gate driving circuit 10A/10B and the gate driving circuit 10A, /1〇B can be turned on and off according to the surface of the gate, and the period of the alternating switch can be one or more sides. Suppose that between two adjacent pictures F (N) and F (N+1) in a plurality of pictures is a time point at which the gate driving circuit 10A/10B and the gate driving circuit 1a, /1〇b are switched, Time start pulse signal VST_A(1) ~ VST - Α (η), ν§τΒΒ (1) ~ VST - B (η), VST - a' (1) ~ VST - A, (n), and state b, (1) The timing chart of ~VST-B'(n) is shown in Figure 9. ~ Liquid crystal ° month refers to FIG. 10, and FIG. 1 is a simplified schematic diagram of a display device 600 according to a sixth embodiment of the present invention. FIG. 10 shows only a part of the structure of the liquid crystal display device 600, including a plurality of gates. The polar lines GL(1) to GL(N), the four gate drive circuits 10A, 10B, 10A' and 10B', and a timing controller 20. The gate lines GL(1) to GL(N) are disposed in the display area 30 of the liquid crystal display device 600, and can be respectively driven according to the gate driving signals GS__A(1) to GS_A(N) and GS_B(1) to GS_B(N). To drive the vegan. The gate driving circuit 10A is disposed in the non-display area 40L of the liquid crystal display device 600, and includes a plurality of shift register units SR_A(1) to SR_A(N), which can be generated according to the start pulse generated by the timing controller 20^. The signal VST_A(1) and the clock signals CKA and XCKA respectively output the gate driving signals GS_A(1) to GS_A(N) to the corresponding gate lines GL(1) to GL(N). The gate driving circuit 10B is disposed in the non-display area 40R of the liquid crystal display device 600, and includes a plurality of stages of shift register units SR_B (1) to SR_B (N), which can be generated according to the start pulse signal generated by the timing controller 20. The VST_B (1) and the clock signals CKB and XCKB respectively output the gate driving signals GS_B(1) to GS_B(N) to the corresponding gate lines GL(1) to GL(N). The gate drive circuit i〇A is disposed in the non-display area 40L of the liquid crystal display device 60〇#, and includes a plurality of shift register units SR_A, (i) SR-A (N), which can be based on the timing controller 20 generated initial pulse signals VST-A'(1) and clock signals CKA, XCKA, respectively output gate drive signals GS_A(1)~GS-A(N) to corresponding gate lines GL(1)~gl ( n). The gate driving circuit 10B is disposed in the non-display area 4〇R of the liquid crystal display device 6〇〇, and includes a plurality of shift temporary storage sheets it SR_B, (1) to SR_B, and (N)′ can be controlled according to the timing control n 2Q The generated starting pulse signal VST B' 20 201112211 (1 ) and the clock signals CKB', XCKB' respectively output the gate driving signals GS_B(1) to GS_B(N) to the corresponding gate lines sinking (1)~ GL(N)e where 'non-display areas 40L and 40R are respectively located on opposite sides of the display area, and N is a positive integer. In the first diagram, the display areas of the display area 3A and the non-display areas 40L, 40R are only for explaining the positions of the respective elements, and do not limit the actual size ratio of each element in the liquid crystal display device 600 of the present invention. The liquid crystal display device 600 of the sixth embodiment of the present invention adopts a double-sided layout of a double-sided layout and is driven in a time-division manner. In other words, the gate driving circuits 10A and 10B are respectively disposed on the opposite sides of the gate lines gl(1) to GL(N), and the gate driving circuits 10A' and 10B' are respectively disposed on the gate lines GL. (1) ~ GL (N) on the opposite side, when the screen is displayed, a gate drive circuit is turned on on both sides of the gate lines gl(1) to GL(N). For example, when a picture F ( N ) is displayed in a plurality of facets, the gate drive circuits 1 〇 a and 1 〇 B are turned on, and the gate drive circuits 10A' and 10B' are turned off, and the gate is turned on. The drive signals GS_A(1) to GS_A(N) and GS_B(l) to GS_B(N) are respectively provided by the gate drive circuits 10A and 10B (indicated by solid arrows); When the F (N+1) after the F (N), the gate driving circuits 10A' and 10B' are turned on, and the gate driving circuits 10A and 10B are turned off, and the gate driving signal GS__A(1)~ GS_A(N) and GS JB(1)~ are provided by gate drive circuits 10A' and 10B', respectively (indicated by dashed arrows). 21 201112211 1 Department of Inf Γ 11 Figure 'U is a timing chart of the liquid crystal display in the sixth embodiment of the present invention. In the gate driving circuit ι〇Α, shift 2: early SR-A(1) according to the start pulse temporary storage unit SR A(7)H GW1) generated by the timing controller 2〇, and shift, 〇p ^ a} R~A (N) respectively output the gate drive signal GS_A (2) according to the start pulse signal generated by the previous stage shifter__(1) to SR_A (N_1}-() VST~A(N) GS-A(N). In the gate drive circuit, the shift register unit SR (1) outputs the gate drive signal Gs_B(1) according to the start pulse signal VST_B(1) generated by the timing control n 2G, and shifts The bit buffer unit sr_B(1) SR_B (N) is based on the start pulse signal ν§τ_b(1)~b (N) generated by the pre-stage shift register unit sr_b(1)~SR-B(N-1), respectively. ) to output GS-B (2) to GS-B(n) respectively. In the gate drive circuit (7) VIII, shift the temporary storage unit SR-a, (1) according to the start of the timing controller 2〇 The pulse signal VST-A, (1) outputs the closed-pole driving signal GS A(1), and the shift register units SR, A, (1) to SR(N) are respectively based on the previous stage shift temporary storage unit A, (1) ~ Di-α, ( ν·ι) Starting pulse signal VST_A' (7) ~VST_A, (N) to output the interpole drive ^ GS_A (2) ~ GS - A (N). In the gate drive circuit 1 〇 B, shift temporary storage tlSR_B (1) according to the timing controller 2 The initial pulse generated by 〇, VST-B'(1) outputs the gate drive signal gs-b(i), and shifts the temporary storage f-element SR-B'(2)~SR-B, (N) According to the start pulse signal 22 201112211 VST—B (2)～VST−B′(N) generated by the previous stage shift temporary storage list το SRj ( 1)～SR—b′(N_1:), respectively, dB (7) ~Gs-b(n). In the liquid crystal display device 6 of the present invention, the closed-circuit driving circuit 1 and the interlayer driving circuit 1A7_ can be alternately turned on and off according to different sides. Alternate _ (4) can be "one picture". It is assumed that between two adjacent facets F(N) and F(N+1) in a plurality of facets is a switching gate drive circuit 1〇Α/10Β* gate At the time of the drive circuit 1〇a, /1〇b, the start pulse signal VST-A (1)~VST-MN), VST_B (丨}~vst_b # (N), VST-A, (1)~ VST-A, (N), and vst-b, (1) ~ vst-b, (N) timing diagram as shown in Figure I The invention utilizes multiple sets of gate driving circuits to drive the gate line in a time-division manner to reduce the gate voltage stress of the film temporary transistor of the shift temporary storage unit (4), thereby increasing the service life and reliability of the liquid crystal display. degree. The above description is only the preferred embodiment of the present invention, and all changes and modifications made to the specific scope of the application of the present invention are intended to be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a simplified block diagram of a prior art liquid crystal display device. Fig. 2 is a timing chart of the liquid crystal display device of Fig. 1 in operation. Figure 3 is a simplified block diagram showing a liquid crystal display split in the first embodiment of the present invention. 23 201112211 Figure 4 is a simplified block diagram of a liquid crystal display device in a second embodiment of the present invention. Fig. 5 is a timing chart showing the operation of the liquid crystal display device of the first and second embodiments of the present invention. Figure 6 is a simplified block diagram showing a liquid crystal display device in a third embodiment of the present invention. Figure 7 is a simplified block diagram of a liquid crystal display device in a fourth embodiment of the present invention. Figure 8 is a simplified block diagram showing a liquid crystal display device in a fifth embodiment of the present invention. Fig. 9 is a timing chart showing the operation of the liquid crystal display device of the third to fifth embodiments of the present invention. Figure 10 is a simplified block diagram of a liquid crystal display device in a sixth embodiment of the present invention. Figure 11 is a timing chart showing the operation of the liquid crystal display device of the sixth embodiment of the present invention. Loss [Description of main component symbols] Gate line Non-display area Inter-pole drive circuit 20 Timing controller GL(1)~GL(N)
30 顯示區域 40、40L、40R 10、1卜 10A、l〇A，、10B、10B， 100、200、3〇〇、4〇〇、500、 24 201112211 液晶顯不裝置 600、700 • SR ( 1 )、SR ( 2)、SR (N)、SR, ( 1 )、 SR’（ 2)、SR，（N)、SR_A ( 1 )、 移位暫存單元 SR—A ( 2 )、SR_A ( n )、SR—A ( N )、 SR_A，（ 1 )、SR一A，（ 2 )、SR一A，（ n)、 SR_A? ( N ) ' SR_B ( 1 ) ' SR_B ( 2 ) > SR_B (n)、SR_B (N)、SR—B，（ 1)、 SR B，（2)、SR_B’（n)、SR_B，（N)30 Display area 40, 40L, 40R 10, 1 Bu 10A, l〇A, 10B, 10B, 100, 200, 3〇〇, 4〇〇, 500, 24 201112211 LCD display device 600, 700 • SR ( 1 ), SR ( 2), SR (N), SR, ( 1 ), SR' ( 2), SR, (N), SR_A ( 1 ), shift register unit SR-A ( 2 ), SR_A ( n ), SR_A ( N ), SR_A, ( 1 ), SR - A, ( 2 ), SR - A, ( n ), SR_A? ( N ) ' SR_B ( 1 ) ' SR_B ( 2 ) > SR_B ( n), SR_B (N), SR-B, (1), SR B, (2), SR_B'(n), SR_B, (N)
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