TW201110329A - Bias voltage generation circuit for an SOI radio frequency switch - Google Patents

Abstract

A radio frequency (RF) switch located on a semiconductor-on-insulator (SOI) substrate includes at least one electrically biased region in a bottom semiconductor layer. The RF switch receives an RP signal from a power amplifier and transmits the RF signal to an antenna. The electrically biased region may be biased to eliminate or reduce accumulation region, to stabilize a depletion region, and/or to prevent formation of an inversion region in the bottom semiconductor layer, thereby reducing parasitic coupling and. harmonic generation due to the RF signal. A voltage divider circuit and a rectifier circuit generate at least one bias voltage of which the magnitude varies with the magnitude of the RF signal. The at least one bias voltage is applied to the at least one electrically biased region to maintain proper biasing of the bottom semiconductor layer to minimize parasitic coupling, signal loss, and harmonic generation.

Description

201110329 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor circuit, and more particularly to a semiconductor circuit including a semiconductor chip on an insulating layer (Soi) substrate and a voltage generating circuit for the RF switch And the method of operating the circuit. [Prior Art] A semiconductor device such as a field effect transistor is analogous to an RF signal switching device in a radio frequency (RF) application. Insulating layer-on-insulator (SOI) substrates are commonly used for this application because parasitic coupling between devices through the substrate is reduced by the low dielectric constant of the buried insulating layer. For example, the dielectric constant of 矽 (the entire substrate including the bulk ruthenium substrate) is approximately in the range of 11.9 GHz. In contrast, the dielectric constant of yttrium oxide which insulates the top semiconductor layer of the device from the handle substrate is about 3.9. By providing an embedded insulating layer having a dielectric constant smaller than a dielectric constant of the semiconductor material in the bulk substrate, the 801 substrate reduces capacitive coupling between the independent semiconductor device and the substrate, thereby reducing the secondary device of the semiconductor device through the substrate Light and light. However, even if an SOI substrate is used, the electrical signal between the semiconductor devices will become significant because b is used in the high frequency range of the RF application, and the range can be, for example, from about 9 〇〇 MHz to about i. 8 GHz' and can contain even higher frequency ranges. This is because the capacitive coupling between the electrical components increases linearly with frequency. 201110329 For a radio frequency (RF) switch formed on an SOI substrate, a semiconductor device including an RF switch and a signal processing unit in the top semiconductor layer is capacitively coupled to the bottom semiconductor layer via an insulating layer. Even if the half-body device in the top semiconductor a uses a power supply voltage from about to about 9V, the transient signal and signal reaction in the antenna circuit will increase the top half of the semi-conducting, layer = actual voltage to about 3 () ^ this voltage The condition induces capacitive coupling between the semiconductor device subjected to the voltage signal and the upper half of the bottom semiconductor layer '- the induced charge layer changes thickness with the RIMf number of the top semiconducting = inner + guiding refractory towel and the charge = 1 The other semiconductor device in the top semiconductor layer contains an RF switch in the electrical conductor layer of the semiconductor layer to support the incoming charge of the charge and the other semiconductor package. The secondary capacitor is combined for the secondary capacitor 'it is reduced RF ί == combination' here In the case, although the RF switch has been turned off, the sand signal is supplied to other semiconductors through the secondary capacitive coupling. Please refer to Figure OB. The prior art emitter (SOI) substrate has a shape of δ, and the ΛM 隹A group of series field effect transistors that are guided. The SOI 柘8 includes a bottom semiconductor layer 1G, and a (4) _ a patrol (10) substrate 8 30. The top semiconductor sidewall and the top semiconductor layer top layer 30 comprise a top semiconductor junction top semiconductor portion 32 gate '32 and a 乂 每 every field effect transistor both & a closed trench isolation structure The drain & plate 44 and the semiconductor portion] field (not shown). Field effect electric a sculpture (four) into the source and the polar region Electric Japanese limbs extended through a set of contact holes 88 201110329 series. The contact holes 88 are embedded in the middle-of-line (MOL) dielectric layer 80, and the metal lines 98 are formed in the interconnect level dielectric layer 90. A high voltage signal having a voltage swinging between approximately +/- 30V transmits a charge layer u in the upper half of the bottom semiconductor layer 1 through capacitive coupling, which is a set of capacitors 22 between the semiconductor device and the bottom semiconductor layer 1? Graphical instructions. The induced charge layer 11 contains a positive charge when the voltage in the semiconductor device of the top semiconductor layer 3 has a negative voltage, and contains a negative charge when the voltage in the semiconductor device of the top semiconductor layer has a positive voltage. The high frequency RF signal in the semiconductor device senses the thickness variation in the induced charge layer 11 and the polarity of the charge in the induced charge layer at the same frequency as the RF signal frequency. In the accumulation mode, the RC time constant characterizes the time required to dissipate the charge in the induced charge layer u, which is determined by the capacitance of a set of capacitors 22 and substrate impedance. The substrate impedance is the impedance between the inductive charge layer 11 and the electrical ground, which is typically provided by an edge seal on the boundary of the semiconductor wafer. The substrate impedance is symbolically represented by the resistance 12 between the inductive charge layer 11 and the electrical ground. 'Because the bottom semiconductor layer 1 〇 usually uses a shouting semiconductor (4) having a minimum occupational flow of about 5 Ohms. high. Further, the lateral distance to the edge seam may be at most - half of the lateral dimension of the semiconductor wafer, for example about Um. In the inversion mode, the rate of generation and recombination within the semiconductor is characterized by the time required to generate and dissipate the induced charge. This large substrate blocker 12 increases the charge charge layer 1] 201110329 2 = 2 letter to the RF switch off state, the top semi-conduct = number = organized, even in the = semi-conducting (four) Hybrid step, from the RF signal through the semiconductor dream, "causes the 仏 耗 耗 。 。 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进 进The semiconductive insulating layer 2:::=;=direct bit_lower, wherein the bottom semiconductor layer 1QSS2 is a type of sputum light, which is when the conductive conductor 屌10 of the bottom semiconductor layer 10 is snowy ^ The voltage of the semiconductor portion 32 is positive with respect to the voltage of the bottom half layer 10 ^ Λ + 32 with respect to the bottom semiconductor, that is, if the bottom semiconductor $, p | is a hole or When the bottom semiconductor layer 1 is n-type, it is electrically formed and accumulated in the upper half of the bottom semiconductor layer 1G to form an inductive electrode 11 . The thickness of the induced charge layer u is then proportional to the square root of the voltage difference between the top semiconductor portion 32 and the bottom semiconductor layer 10. The thickness of the inductive charge layer 11 and the change in the amount of charge in the inductive charge layer produce an additional harmonic signal of the RF bub rate that is coupled to the semiconductor device within the top semiconductor portion 32, thereby providing a dummy even when the RF switch is turned off. (spurious) signal. Further 'in the other half of each frequency cycle of the RF signal' straight 201110329 is connected to the bottom half of the underlying insulating layer 20, wherein the bottom semiconductor layer 1 〇H 〇 upper half is embedded The bottom end surface of the insulating layer 20 is sprinkled. The conductive type of the partial charge sub-layer 10 is P-type and the top-conductance j' is positive when the bottom-side semi-conducting voltage is opposite to the bottom-end semiconductor layer 10, and the electric conductivity type of the 3232 is n-type and The top semiconductor is opposite to the voltage of the bottom semiconductor layer 10 at the bottom semiconductor layer 10

If the bottom semiconductor layer H) is a hole or a sub-portion, that is, an electron in the n-type, an inductive charge layer (1) is formed on the upper layer 10 of the bottom semiconductor layer, which consumes a main charge. When entering =iX, the voltage difference between the lightning/layer is large enough to be semi-conducting, and the main charge is formed, that is, if the bottom type is Ray II, the ^ type is electron or the bottom semiconductor Layer 10 is an inversion zone within η/5/5. The thickness of the depletion region and the amount of the inductive charge layer 11 are determined by the magnitude of the voltage difference between the top semiconductor portion 32 and the bottom semiconductor. The thickness of the induced charge layer η and the change in the amount of charge in the layer of the electric signal are in the phase of the RF signal frequency period m μ ^ RF frequency of the additional harmonic signal, which is consumed by the top semiconductor portion 3 2 for the dummy signal In order to improve the signal isolation and reduce the eddy current and harmonic generation, there is a need for a semiconductor-on-insulator (S01):----------- Semiconductor germanium and its method of operation. SUMMARY OF THE INVENTION In order to address the above needs, the present invention provides a semiconductor circuit including a radio frequency (RF) switch on a semiconductor-on-insulator (SOI) substrate, wherein the switch has at least an electrical bias region in the bottom-k semiconductor layer. And a bias generating circuit for generating a bias voltage from the RF signal in the RF switch, and a method of operating the circuit. In the present invention, a radio frequency (RF) switch on a semiconductor-on-edge (SOI) substrate includes at least an electrically biased region within the bottom semiconductor layer. The RF switch receives an RF signal from a power amplifier and transmits the rf signal to an antenna. The electrical biasing region can be biased to eliminate or reduce the accumulation region, stabilize a depletion region, and/or avoid forming an inversion region in the bottom semiconductor layer, thereby reducing parasitic coupling 盥 harmonics due to the RF signal . A voltage divider circuit branches (taps) the RF signal and provides some of the RF signal as an input signal to a rectifier circuit. The rectifier produces at least a bias voltage whose amplitude varies with the magnitude of the RIMf number. The at least one bias voltage is supplied to the at least one electrically biased region to maintain an appropriate bias of the native conductor layer to minimize parasitic coupling and signal loss. According to the present invention, a method of operating a semiconductor circuit includes: providing a semiconductor circuit in a method, the circuit comprising: a radio frequency (RF) switch comprising at least one active power on an upper half of an insulating layer Crystal; —) a radio frequency (RF) signal line for transmitting a radio frequency (RF) signal, i Swallow RF "is 5 tiger line connected to έ海rf switch; and, S] 12 201110329 a circuit from The RF signal generates at least one bias voltage; and the at least one bias voltage is supplied to a bottom semiconductor layer of the SOI substrate. In a specific embodiment, the semiconductor circuit further includes: a voltage divider 'connected between the RF signal line and the electrical ground; and a rectifier circuit 'connected to the voltage divider and generating the RF signal from the RF signal At least one bias voltage. In other embodiments, the semiconductor circuit further includes at least one biasing feed line ' supplying at least one bias voltage to the bottom semiconductor layer of the SOI substrate. In other embodiments, the semiconductor structure further includes at least one conductive via impedance connected to the bottom semiconductor layer, and wherein the at least one bias voltage is provided to the bottom semiconductor layer through the at least one conductive via. In still other embodiments, the at least one bias voltage includes a positive bias voltage 'the positive bias voltage has a magnitude greater than a maximum positive swing amplitude of the RF signal during the RF signal period, and wherein the at least one bias voltage A negative bias voltage is included. The 5 hp negative bias has an amplitude greater than a maximum negative swing amplitude of the RF signal during the RF signal period. In still other embodiments, the semiconductor circuit further includes a power amplifier' to connect and provide the RF signal to the RF signal line. 13 201110329 In still other embodiments, the semiconductor circuit described above further includes an antenna for transmitting the RF signal and other RF signal lines connected to the RF switch and the antenna. In another embodiment, the voltage divider comprises a first set of at least one impedance element having a first impedance and a second set of at least one impedance element having a second impedance, wherein the One end of a set of at least one impedance element is directly connected to the RF signal line, and wherein one end of the second set of at least one impedance element is directly connected to the electrical ground. In still another embodiment, the semiconductor circuit further includes: at least one first doped semiconductor region embedded in the bottom semiconductor layer and having a p-type doping; and at least a second doped semiconductor region, Embedded in the bottom semiconductor layer and having an n-type doping. In still another embodiment, the method further includes: supplying the rectifier circuit from a negative bias generated by the RF signal to the at least one first doped semiconductor region; and the rectifying circuit from the RF signal A positive bias voltage is generated to be supplied to the at least one second doped semiconductor region. In still another embodiment, the method further includes: suppressing formation of an accumulation region using one of the negative bias and the positive bias, wherein a majority of charge carriers in the accumulation region accumulate at the bottom semiconductor 14 201110329 And using the negative bias and the positive bias to suppress the formation of an inversion region in which a minority of charge carriers are accumulated in the bottom layer. In still another embodiment, the method further includes discharging a minority of charge carriers in the bottom semiconductor layer through at least one conductive via connected to the bottom semiconductor layer via an impedance. In accordance with other aspects of the present invention, a semiconductor circuit is provided comprising: 'a radio frequency (RF) switch comprising at least one field effect transistor on a semiconductor (s〇i) substrate on an insulating layer; ^ a radio frequency (RF) a signal line for transmitting a radio frequency (RF) signal, wherein the _RF signal line is connected to the RF switch; a voltage divider connected between the RF signal line and the electrical ground; and a rectifier circuit connected to the voltage component And generating at least one bias voltage from the RF signal, wherein the at least one bias voltage varies with a time constant greater than the RF signal period; and the at least one bias feed line 'supplied the at least one bias voltage to the SOI a bottom semiconductor layer of the substrate. In a specific embodiment, the semiconductor circuit further includes at least one via hole impedance connected to the bottom semiconductor layer, wherein the at least one bias voltage is supplied to the bottom semiconductor layer through the at least one conductive via. 15201110329 In another embodiment, the at least one bias voltage comprises a positive bias voltage having a magnitude greater than a maximum positive swing amplitude of the RF signal during the period of the RF signal induced in the substrate, and wherein The at least one bias voltage includes a negative bias voltage having a magnitude greater than a maximum negative swing amplitude of the RF signal during the period of the RF signal induced in the substrate. In still other embodiments, the semiconductor circuit further includes a power amplifier' to connect and provide the RF signal to the RF signal line. In still other embodiments, the semiconductor circuit further includes: an antenna ' for transmitting the RF signal; and other RP signal lines connected to the RF switch and the antenna. In another embodiment, the voltage divider comprises a first set of at least one impedance element having a first impedance and a second set of at least one impedance element having a second impedance, wherein the One end of a set of at least one impedance element is directly connected to the RF signal line, and wherein one end of the second set of at least one impedance element is directly connected to the electrical ground, and wherein a common node between the first group and the second group Directly connected to an input node of the rectifier circuit. In a further embodiment, the rectifier circuit includes at least one resistor directly connected to the electrical ground, at least one capacitor directly connected to the electrical ground, at least one diode directly connected to the electrical ground, and directly connected to the rectifier circuit At least another diode of the input node. 201110329 In another embodiment, the semiconductor circuit further includes: at least one first doped semiconductor region embedded in the bottom semiconductor layer and having a P-type doping, wherein the rectifying circuit is generated from the RF signal a negative bias voltage is supplied to the at least one first doped semiconductor region; and at least a second doped semiconductor region is embedded in the bottom semiconductor layer and has an n-type doping, wherein the rectifying circuit is A positive bias generated by the RF signal is supplied to the at least one second doped semiconductor region. In accordance with other aspects of the present invention, a design constructed in a machine readable medium is provided to design, fabricate or test a design of a semiconductor structure. The design structure comprises: a first data representing a radio frequency (RF) switch, the switch comprising at least one effect transistor on a semiconductor-on-insulator (SOI) substrate; and a second data representing a radio frequency (RF) a signal line for transmitting a radio frequency (RF) signal, wherein the RF signal line is connected to the RF switch; ° - a third data 'represents a voltage divider, the voltage divider being connected to the RF signal line And a fourth lean material, representing a rectifier circuit, the circuit is connected to the voltage divider and generates at least one dust from the RF signal, wherein the bias voltage is greater than the #海RF仏 cycle And a fifth data representing at least one bias feed line, the feed line supplying the at least one bias voltage to a bottom semiconductor layer of the SOI substrate. In a specific embodiment, the design structure further includes an additional material 'representing at least - conductive hole impedance connected to the bottom semiconductor layer, wherein" 7 201110329 ^ the at least - the conductive hole provides the at least "bias" to the bottom The terminal semi-steering, t in the specific embodiment, the design structure further includes a further power amplifier that connects and provides the RF k to the RF signal line. In another embodiment, the design structure further includes: a number; 2 data> represents an antenna, and the antenna is used to transmit the seventh material of the letter, representing its #RP signal line, and the signal line is connected to The ruler 17 switches with the antenna. In still another specific embodiment, the third data includes an eighth resource and a tenth data, the eighth resource: two at least one impedance component of the first impedance, and the ninth data represents At least one impedance element of a second impedance, the tenth data generation - at least - the impedance element is in series with the second group of at least - impedance element two - wherein one end of the at least one impedance element of the first group is directly connected An RF signal line, and wherein the second set of at least - impedance elements = directly connected to the electrical ground, and wherein the first set and the second set of -, the shared node are directly connected to an input node of the rectifier circuit. Data Si: In other embodiments, each of the eighth data and the ninth 憎 represents at least one of a resistance, a capacitance, and an inductance. 18 201110329 In yet another embodiment, the fourth material includes an eleventh data, a twelfth data ... a thirteenth material, and a fourteenth data, the tenth - representing a direct connection to the electrical ground. At least—resistance, the twelfth data represents at least one capacitor directly connected to the electrical ground, and the thirteenth data represents at least a diode directly connected to the electrical ground, the data representing the direct connection to the rectifier circuit At least another diode of the input node. In another embodiment, the design structure further includes: a first additional material representing at least one first doped semiconductor region, the region being embedded in the bottom semiconductor layer and having a p-type doping; a second other material representing a first electrical wiring structure for supplying the rectifier circuit from a negative bias generated by the RF signal to the at least one first doped semiconductor region; Λ a second other data Representing at least a second doped semiconductor region embedded in the bottom semiconductor layer and having a doping; and a fourth additional material representing a second electrical wiring structure for rectifying the region The circuit supplies a positive bias voltage generated by the RF signal to at least one of the second doped semiconductor regions. EMBODIMENT As described above, the present invention relates to a semiconductor structure including a radio frequency switch on a semiconductor (8〇1) substrate on an insulating layer, and a design structure thereof, which will be described later. The drawings are not drawn to scale. As used herein, radio frequency (RF) is the frequency of electromagnetic waves in the range of 3 Hz to 3 GHz. The radio frequency corresponds to the electricity used to produce and detect radio waves. 19 201110329 Magnetic wave frequency. Radio frequencies include very high frequency (VHF), ultra high frequency (UHF), super high frequency (SHF) and extreme high frequency (EHF) ° as used here. Very high frequency (VHF) is a frequency ranging from 3〇MHz to 300MHz' VHF is especially used for FM (called Hyundai's modulation 'FM) broadcast. Ultra High Frequency (UHF) is a frequency range from 3 〇〇 MHz to 3 GHz. UHF is especially used in mobile phones, wireless networks, and microwave ovens. Super high frequency (7): ^^ is the frequency ranging from 3 GHz to 3 〇 gHz, and SHF is especially _路, #达和卫魏路. Extremely high frequency (EHF) is a frequency range from 30 GHz to 3 GHz, which produces millimeter waves with wavelengths from 1 mm to l 〇 mm, and is especially used for data-bonding of some charge carriers in the Pleistocene region. = Most of the charge carriers in the semiconductor region, because of the external; the second is p-type doped semiconductor i and the right region is in the accumulation mode, and the π-type doped semiconductor region is the second and the second. If too much electrons are accumulated in the n-type doped half: the carrier 'because of the external positive voltage, the n-type doped semiconductor region has a region located in the accumulated mode bias and repels most of the semiconductors The term “dwelling zone” refers to the majority of charge carriers and minority body regions due to external charge carriers and does not accumulate most of the charge. If the hole is a P-doped semiconductor = sub-doped semiconductor, the weak external positive voltage is in the P-type mixed == number of charge-doped semiconductor regions in the depletion mode, if the P-type The charge is if the electron 'is' type doped semiconducting two = 2 = heteroconducting two = body region has a net positive charge. , "So η-type doped semi-guided telemetry "reverse f"-Wei table in which the accumulation of a few charge carriers is abundant = zone pass: electrically close to strong external == Gonggongshan Electronics, 疋卩A small number of Thunder carriers in a doped semiconductor region are accumulated by a strong external positive voltage. ^ Miscellaneous semi-conductor purchases _, so let p negative charge "if the hole, that is, the n-type doped semiconductor ^ doped negative charge accumulated in the "type-type hybrid semiconductor region and let the region have a net positive charge £ in the opposite Such a n-type doped semiconductor sputum in the transfer mode, FIG. 2' shows a vertical cross-section of the semiconductor structure of the exemplary semiconductor structure during operation, which can be used as the present invention - a partial conjugate of a semiconductor circuit. The semiconductor structure comprises a radio frequency (RF) switch, the package of which is directly located on the top of the semiconductor substrate 8 on the insulating layer, and at least one field effect transistor on the semiconductor portion 32. The electrical wiring between the two % effect transistors is provided by the third upper conductive vias (10) D di interconnected metal lines 98. Each of the at least one field effect 201110329 transistor includes an interpolar dielectric body 4, Closed pole 44. Source region (not shown) and drain region of each at least one semiconductor portion 3 42 crystal (not: all: 2 electric field 2, shallow trench insulating structure 33 and line center buried The insulating layer electrically insulates the at least one field effect transistor, the combination of the electric diodes 202 is off, and the other semiconductors are placed and the bottom end of the body; the body is included in the bottom opening during the RF opening operation The germanium conductor layer 1G is electrically insulated. In the layer B, the inductive charge layer 13 is a "charged portion of the semiconductor layer forming an inductive charge dry layer in the semiconductor package. The mother-bottom semiconductor layer 1 and at least - both contain - Like a sliced semiconductor (4) 1 ^ ^ conductor part ^ = 金: gold area, alloy area, • carbon alloy; ί:: indium , Desalination Indium Gallium, Indium Phosphide, Sulfide Ma, j (4), and Group 1 semiconductor materials. Bottom semiconductor layer =: The semiconductor material of the top semiconductor portion 32 may be the same or different. The pass-through semiconductor layer 1G And the at least --terminal semiconductor portion % W is an early-crystal half-V body material. For example, the single crystal semiconductor material may be germanium. The bottom semiconductor layer usually has a resistivity greater than 50 〇hms_cm, which includes, for example, having an atomic concentration lower than a p-type of approximately 2 〇 x 1 〇 u/cm 3 , a P-type doped single crystal germanium of a hetero object, or an n-type doping of an n-type dopant having an atomic concentration of less than about 1 〇χ l〇 14/cm 3 Preferably, the bottom semiconductor layer 10 typically has a resistivity greater than 50 Ohlns_cm, including, for example, a p-type doped single crystal germanium having a p-type dopant having an atomic concentration of less than about 2.0 X l〇14/cm3. , or an atomic concentration lower than about L0 X l 〇 M / cnr5 t S] 22 201110329 n-type doped type doped single crystal #. More preferably, = usually has a repair factor greater than lk0hms_em, which includes 2 (10) ^ Miscellaneous Crystal Dreams or concentrations below about 5.0 x at concentrations below about LO X MW 1() 12w, the n-type doped single crystal of the object... The conduction of the bottom semiconductor layer 1G is referred to herein as a fast conductivity type, and may be p-type or n-type. 1 High resistivity of the ruthenium layer 10 The eddy current is reduced, and the parasitic rectification of the bottom semiconductor layer 10 in the top semiconductor layer 3 is less used, although the dopant level required for the bottom end = the mother resistivity value is explained here. However, the parent-semiconductor materials have established a good relationship between the resistivity of the dopant concentration material, so that the target dopant concentration of the semiconductor material can be quickly increased. The thickness of the bottom semiconductor layer 10 is typically from about 4 Å to about 1 μm, and is typically about 5 μm from about 5 (8) μm in this step. If the bottom semiconductor layer 1G is later thinned, the thickness of the substrate can be from about 5 〇 micron to about _ micron 丨 " + the conductive layer buried insulating layer 20 contains a combination of such as yttrium oxide, or yttrium. Electrical material. The embedded insulating layer is 5 〇 to about 诵 (10), usually from about U) 〇 nm; It 5 〇 l However, small and large thicknesses are also considered here. , '' 矽, tantalum nitride, nitrogen The oxygen shallow trench insulation structure 33 contains, for example, oxidation

S J 23 201110329 Fossil or these combinations of dielectric materials. Forming at least one trench extension # into the top surface of the top semiconductor layer 30 in which the insulating layer 20 is embedded, filling the at least one trench with a dielectric material such as hafnium oxide, tantalum nitride, and/or hafnium oxynitride And forming a shallow trench isolation structure 33 by removing the dielectric material portion on the top surface of the top surface of the top semiconductor layer 30 by, for example, chemical planarization (CMP) and/or recess etching. In the continuous manner of the at least one trench, the shallow trench isolation structure 33 may be of a single structure, that is, integrated into the shallow trench isolation structure 33, which may laterally adjoin and surround each of the at least two semiconductor portions. 32. ^ The thickness of the top 1 semiconductor layer 30 can range from about 2 Å to about 4 G nm to about (10) nm', although smaller and larger thicknesses are also considered here. At least one top semiconductor partial or n-type dopant. Typically at least one of the top semiconducting dopant concentrations can be from about 1 〇X 1 〇 15/ 3 1018/rm3 , from 3⁄4 r- to about 1.0 x 10 /cm & corresponding to the % effect transistor body region Smaller or larger concentrations are also considered here. The semiconductor structure comprises at least a first region 18 and at least one second doped semiconductor region 28. = L hetero-conductor region 18 comprises a semiconductor material of the bottom semiconductor layer H) = Doping the semiconductor conductivity type _. The second conductivity type is the if and has the first - for example. If the first conductivity type is the opposite of the 'member type. And vice versa. The second _ semiconductor region 28 is ^^^ Η-type, semiconductor material 'and having a first-conductivity type of layer 1 24 24 201110329, the thickness of the first-doped semiconductor region 18 and the at least one second doped semiconductor region 28 may be from about 10 Fine to about Sangha, the commons are often from about 50 nm to about 3 〇〇 nm, but small and large thicknesses are also considered here. At least one of the first doped semiconductor regions 18 is usually heavy to reduce the resistivity. The dopant doping of each of the at least -^ body regions 18 and the at least one second doped semiconductor region 28 from about iO x to about 1 可 may take into account a smaller or larger dopant concentration. Cm 'but here also demonstrates that the semiconductor structure further contains and at least one Interconnecting a first conductive via 79, a first doped semiconductor region provides an electrical bias to at least one second interconnect level metal line 99, which provides a sum of electrical-conductive holes and at least a second doped semiconductor region 28 a hierarchical metal line 98. at least one of the cage conductive holes 88 and the third interconnected first interconnected metal lines 94, i of the first interconnected metal lines 99 are embedded in the interconnect level In the electrical layer 9Q, the at least one first conductive hole 79 may be at least one first conductive hole 79 extending from the survey surface to at least one top-doping day of the first conductive hole 79 The entire = face 'each of the first-lower conductive holes 47 is at least 77 of them. - At least one second conductive (10) extends from the top surface of the 4 conductive holes to at least - "the surface of the electrical layer 80, each - At least one of the first _=/: hetero-conductor regions 18 may have an overall configuration, or may include at least one of the second lower conductive vias 37 and at least one of the second upper conductive vias 87. one of them. The MOL dielectric layer 80 may comprise ruthenium oxide, tantalum nitride, arsenic oxynitride, organosilicate glass 'OSG', l〇wk chemical vapor deposition (CVD) oxide, image It is a self-planar material of spin-on glass (S0G) and/or a spin-coated low-k dielectric material such as SiLKTM. Exemplary oxidized oxides include undoped silicate glass 'USG', borosilicate glass (BSG), phosphosilicate glass (PSG), and fluorene fluorene Fluorosilicate glass 'FSG', borophosphosilieate glass (BPSG) or a combination of these. The total thickness of the MOL dielectric layer 80, measured from the top surface of the shallow trench isolation structure 33, can range from about nm to about

10,000 nm' is typically from about 2 〇〇 nm to about 5,000 nm. The top surface of the MOL dielectric layer 80 can be planarized by, for example, chemical mechanical planarization. The dielectric material of interconnect level dielectric layer 90 comprises any dielectric material that can be used for MOL dielectric layer 80 as described above. The thickness of the interconnected dielectric layer 9 可 can range from about 75 nm to about i, 〇〇〇 nm, typically from about 15 〇 nm to about 500 nm, although smaller and larger thicknesses are also considered here. The at least one first interconnect level metal line 94, the at least one second interconnect level metal line 99, and the third interconnect level metal line 98 may comprise, for example, C:u 'Al 'W, Ta, Ti, WN, TaN, D (8) or a combination of these. To 26 201110329, one less interconnect level metal line 94, at least one second interconnect level metal line 99, and third interconnect level metal line 98 may comprise the same metal material. At least one field effect transistor forms a radio frequency switch for signals having a frequency from about 3 Hz to about 3 GHz. In particular, at least one field effect transistor constitutes a radio frequency switch operable on VHF, UHF, SHF and EHF. At this high frequency, 'at least one field effect transistor and the bottom half of the semiconductor display will change due to the linear increase of the electric coherence. The radio frequency signal in a field effect transistor is caused at the bottom end. Half-pressure = bottom semiconductor layer material, directly forming = inductive charge layer 13 and inducing a positive or negative charge underneath the bottom half-conductor layer to; the charge of the charge 23 ? is supplied to the frequency at an electric bias Change the polarity: two: f less than one field effect transistor RF signal in the bottom semiconductor layer 1 〇ϋ a field effect transistor inside the motor. When at least one field band, %' electrons accumulate in the induced charge layer 13 = negative, the electric (four) accumulates in the layer relative to the money semiconductor layer. In the previous dry apricots, the type of most charge carriers in the io^ig from the bottom end has a net charge for the bottom semiconductor. The 'inductive charge layer' can be in the mode, or can be opposite in conductivity. What is the type of depletion electricity? The conductivity of the bottom semiconductor layer 丨0 is the same type of inversion mode of 201110329 and the thickness of the induced charge layer 13 varies with at least the internal signal frequency (four). In other words, the thickness of the inductive electrode 13 is the radio frequency of the signal in at least one field effect transistor. According to the present invention, the electrical bias is supplied to at least one of the second semiconductors to stabilize f. One of the fields of the induced charge layer during operation of the field effect transistor can be used as an RF switch. To ΐί: 92Γ electric path to supply electric bias to at least a second _ 敎 induced charge layer 13. The magnitude and polarity of the voltage bias supplied to at least the first body region 28 are selected, layer 13 is in the u mode, and (iv) the region in the bottom half charge layer u is avoided. In other words, the induction 曰 "the entire period of the 唬 is not in the accumulation mode. Both the semiconductor layer 1G and at least a second doped semiconductor region 28 semi-conducting & a second doping changed anamorphism and at least one of the first conductive holes 89 is strange or slowly connected to the bottom end, / preferably, the magnitude of the negative voltage is approximately equal phase or greater than the top of the coupling layer The maximum negative swing amplitude of the RF signal is larger. The negative value of the rf signal that is converted in the #i voltage is lower than that in any phase. Under induction, the entire inductive charge layer 13 is charged with a fixed negative charge. i 13 constitutes a depletion region, from which a hole is consumed. 28 201110329 In the case where the bottom semiconductor layer 10 and the at least one second doped semiconductor region 2 have n-type doping, the bias supply is supplied to at least one second doping. The semiconductor region 28, and the at least one first conductive via 89 is a constant or slowly changing positive voltage. Preferably, the magnitude of the positive voltage is about equal phase or greater than the top of the bottom semiconductor layer 1 during the positive swing of the RF signal. Surface large electromotive force In other words, the positive voltage is greater than the positive value of the electromotive force from the RF signal in any phase inner layer. In this case, the entire inductive charge layer 13 is charged with a positive charge. The induced charge layer 13 constitutes a depletion region, thereby consuming electrons The thickness of the inductive charge layer 13 varies with the frequency of the RF signal in at least one of the field effect transistors. However, the inductive charge layer 13 is in the accumulation mode during the entire period of the RF signal. 13 is left in the depletion mode. The reduced variation in the inductive charge layer 13 is due to the electrical bias, which reduces the linearity of the inductive charge layer 13 (4) to reduce the generation of spectral waves, which does not require at least one second doped semiconductor region 28 and The conductive hole 89 or the supply of the electrical bias can be present. The average thickness of the depletion region of the induced charge layer 13 is increased. Since the charge is not moved, the bottom semiconductor layer ω is also reduced: The bottom semiconductor layer _ π does not move and does not contribute to at least one field effect transistor operation _ current, signal loss and generation, but a few charge carriers are The transition zone (if the prior art internal force 201110329 is moved ' thereby causing eddy currents, signal loss and harmonic generation. According to the invention, an electrical bias is supplied to the at least one first doped semiconductor region 18 so that once heat generates a minority load The sub-discharge immediately 'to avoid forming an inversion region. At least = first-conducting holes 79 provide an electrical path to supply an electrical bias to the at least one first doped semiconductor region 18. The bottom semiconductor layer 1G is p-doped In the case where a small number of charge carriers are electrons, in the case where the bottom semiconductor layer 1G is n-doped, a small number of charge carriers are holes, and the magnitude and polarity of the voltage supplied to the at least one first doped semiconductor region 18 are examined. Alternatively, a small number of charge carriers can be immediately discharged after heat generation, thus avoiding the formation of an inversion region in all phases of the RF signal in at least one of the field effect transistors. Thus, the structure of the present invention eliminates any inversion regions such that eddy currents and harmonic generation due to movement are minimized. If the bottom semiconductor layer 10 is p-type doped, at least one semiconductor region 18 has an n-type doping and at least a second doping = body region 28 has a p-type doping. The first bias voltage supplied to the at least one first doped region 18 and the at least one first conductive via 79 is a positive voltage 3 and is supplied to at least one second doped semiconductor region 28 and at least: an electrical hole 87 The two bias voltages are negative voltages. In one case, positive = approximately equal to or greater than the magnitude of the large positive swing that is sensed within the bottom semiconductor layer 10. The magnitude of the negative voltage is large. The maximum negative swing of the RF signal induced in the aged semiconductor layer 10 is 5 at the bottom end. If the bottom semiconductor layer has an n-type doping, the doped semiconductor region has a Ρ-type impurity and is (b) 30 201110329 conductor region 2k θ + has an n-type doping. Supplying at least one first doped semiconductor

The first region of the at least one first conductive via 79 is first and negatively charged first and supplied to the at least one second doped semiconductor region 28 and the at least one conductive via 87. The second bias voltage is an equal positive voltage. In one case, the RF degrees are approximately equal to or greater than the magnitude of the maximum positive swing induced in the bottom semiconductor layer 10. The magnitude of the negative voltage is approximately equal or; The maximum negative swing of the induced RIMt number in the body: Referring to FIG. 3, the semiconductor circuit β of the present invention is illustrated. The semiconductor semiconductor includes a power amplifier, a first radio frequency (RP) signal line, and a path. Two off=, a second RF signal line, an antenna, and a bias generating power. Generating at least one bias switch from only the RF signal in the first RF signal line may include, for example, the exemplary semiconductor structure of FIG. 2 above. RF connection: The at least one field effect transistor and the at least one wiring structure are disposed on the bottom end of the S01 substrate on which at least one field effect transistor is placed. The circuit comprises a voltage divider 11 connected At the first, catch the line and electricity Between the ground and from the signal, at least one household is generated, by: ΐί |, the bias is supplied to the bottom semiconductor of the S〇1 substrate, and the performance of the RF switch is provided by using the secondary capacitors. Subtracting >, the formation of an accumulation region in the bottom semiconductor phase charge conductor layer and/or the reverse is difficult. In the case of using a wafer-on-system (System_on_chip, S〇c) semiconductor wafer, 'in (4) SgC Formed on the semiconductor wafer =, RF switch, voltage divider and rectifier circuit. Selective, blood-RF k line can be integrated into the SoC semiconductor chip. - Power amplifier produces a radio frequency (RF) signal, which has from about 3 Hz to a frequency of about 300 GHz. In particular, the power amplification thin can generate RF signals in the range of Li, Chat, SHF or Qing. The frequency of the liver signal is more quotient: the greater the power, the larger the The benefit of slowing down the secondary capacitive coupling effect is greater. Thus, when R is at a frequency of about 3 GHz to about 300 GHz: the present invention is also explicitly considered. The invention extends to frequencies extending beyond 3 GHz. The first RF signal line will come from the work The RF signal of the amplifier is transmitted to the RF switch. Typically, the first RF signal line entity is implemented as an interconnected metal line that connects the physical structure of the power amplifier to the physical structure of the RF switch. The switch includes at least one field effect transistor. The switch can be configured to electrically or electrically interrupt the first RF signal line from the :RF signal line. Optionally, at least the other input ports can be provided in the RF switch to be from the first RF signal line to the at least one other input port Select an input. The signal selected by the RF switch is routed through the second RF signal line to the antenna 'where the electromagnetic wave of the RF signal frequency is generated. 32 201110329 In addition, the antenna can be used to receive RF signals in the form of electromagnetic waves. In this case, the 'electromagnetic signal is captured by the antenna and transmitted through the second RF signal line to the RF switch, and is routed to at least the other wheel trips provided in the RF switch, if the RF switch contains at least other ports received or transmitted from The signal of the antenna 'the second RF signal line can be electrically connected to the node selected from the RF signal line and at least the other. The amplitude of the RF signal can range from approximately 〇 lv to approximately 3 〇 v. Generally, when a signal generated by a power amplifier is transmitted to an antenna through a first line, an RF switch, and a second RF signal line, the amplitude of the RF signal can be, for example, from about 3 V to about 12 V. In some cases, the rF signal line, the RF switch, and the signal reflection within the antenna can increase the amplitude to approximately 3 〇v. The high-voltage-sensing mobile charge carriers in the embedded insulating layer of the SOI substrate have the at least one field effect transistor constituting the RF switch. In order to provide at least one biased semiconductor layer to the bottom semiconductor substrate, a voltage divider is coupled to the first RF signal line. The voltage divider includes a first set of at least one impedance element having a first impedance Z1 in series with a second set of at least one impedance element having a second impedance Z2. One end of the first set of at least one impedance element is directly connected to the first RF signal line, and one end of the second set of at least one impedance element is directly connected to the electrical ground. A common node between the first group having the first impedance Z1 and the second group having the second impedance is directly connected to the input node of the rectifier circuit. Since the first set of at least one impedance element is connected in series with the second set of at least one impedance element, the magnitude (or absolute value) of the total impedance, ie, 201110329 I zi Z2 I Tk is greater than the magnitude of the impedance Z2 z2, ie, I The ratio of Z2 I to the first impedance and the first resistance amplitude 'ie 疋ΙΖΗΖ 2 卜 is good to L0, preferably from about 〇2〇 to the RF signal frequency! Bu is re-inducing and :::: Like a reactive component such as a capacitor and / or an inductor, the absolute value of the ratio of Ζ to (Ζ1 Ζ2), that is, Ζ2Η, represents the output voltage of the voltage divider relative to the voltage divider. The human voltage (amplitude 0 - 3 = = 4 Α, Fig. 4 Β and Fig. 4C, respectively, shows the first, first, and second voltage partial voltages of the present invention, respectively, and the components include resistors, capacitors, and capacitors including resistors, Impedance = Α 4 Γ In the exemplary voltage divider, the first group is at least - two ;; the anti-component is the same as the first reactance R1 having the second blocking resistance R2 and the first impedance Z1 and the first blocking resistance, The impedance Z2 is the same as the second barrier impedance ruler 2. Impedance = 3 2 In the exemplary voltage divider, the first group is at least one and the second, and is; And the second resistor is connected in parallel with the capacitor having the second blocking impedance equal to the round-increasing rate disc two electric valleys, and the impedance Z3 is the inverse of the product of the capacitance capacity, wherein " 』·” represents the main square root of the negative value of 2011 201132. In this case, the first impedance ζι and the first blocking impedance R1 Similarly, and the second impedance Z2 is equivalent to the inversion of the second blocking impedance R2 inversion and the third capacitive impedance Z3 inversion sum. It is understood from this that it is customary to use a complex number to represent the magnitude and phase of the voltage and current, thus using a complex number Representing the impedance of the resistor, capacitor and inductor. In the third exemplary voltage divider of Figure 4C, the first set of at least one impedance element is comprised of a first resistor having a first inductance L1 having an impedance ZL equal to the radiation frequency and j times the inductance product, and the second set of at least one impedance element includes a second resistor having a second blocking impedance R2 in parallel with a capacitance having a second electrostatic capacitance impedance ZC, which is equal to an inverse of the product of the light-frequency frequency and the electrostatic capacitance C3. In this case, the first impedance Z1 is the same as the first inductive impedance ZL, and the second impedance Z2 is equivalent to the inversion of the second blocking impedance R2 inversion and the third capacitive impedance Z3 inversion sum. Other variations of the voltage divider, wherein each of the first set of at least one impedance element and the second set of at least one impedance element can be arbitrarily combined. The voltage regulator is directly connected to the configuration between the first signal line and the electrical ground. Here, it is also explicitly considered that the voltage divider is directly connected between the second RF signal line and the electrical ground. The output node of the voltage device is a common node between the at least one impedance element and the second group of at least one element, and generates other RF signals from the RF signal in the first RF signal line. Voltage division = crying wheel 35 The signal on the out/node of 201110329 has a smaller medium than the RF signal in the first-RF signal line and has the same frequency. The rf apostrophe on the output node of the voltage divider is transmitted to the input node of the rectifier circuit. The 13⁄4 degree of the RiMs number on the input node of the rectifier circuit is the product of the amplitude of the RF signal on the first-RF signal line and the magnitude (absolute value) of the second impedance Z2 divided by the sum of the first impedance and the second impedance. The rectifier circuit produces at least one bias that varies with a time constant greater than the period of the RF signal, i.e., an inverse of the RF signal frequency. Typically, the time constant is at least greater than the amplitude of the RF signal period, and is typically greater than two or more amplitudes of the RF signal period. For example, in applications such as ambiguous telephones, the RF signal can range from 9 〇〇 MHz to over 2 Ghz. The time constant of the rectifier circuit can be ο·ι ms. For RF nicknames from about 3 GHz to about 300 GHz, the time constant of at least one bias can be from about 30 picoseconds to about j milliseconds, and typically from about picoseconds to about 10 microseconds. Therefore, on the time scale of the good signal period, the y (five) bias can be considered as the general (four) voltage showing the behavior of the direct current (9). In this aspect, the at least one of the dusts herein is at least one direct current (DC) turn-off voltage whose amplitude is modulated by the amplitude of the RF signal in the first RF signal line over a time constant of the _ times amplitude, usually For the amplitude - some money times, greater than the RF (four) cycle. In a particular embodiment, the at least one bias 'four' voltage has a magnitude that is less than the amplitude of the RF signal transmitted to the Qiu switch. In other implementations, the at least one bias voltage can include a positive direct current (DC) output voltage having a magnitude equal to or greater than the amplitude of the RF signal transmitted to the RF switch. In other words, the magnitude of the positive bias is greater than the magnitude of the maximum positive swing of the RF signal in the RF signal period within the RF switch. In still other embodiments, the at least one bias voltage can include a negative direct current (DC) output voltage having a magnitude that is less than an amplitude of the RF signal transmitted to the RF switch. Still in other embodiments, the at least one bias voltage can include a negative direct current (DC) output voltage' having a magnitude equal to or greater than the amplitude of the RF signal transmitted to the RF switch. In other words, the magnitude of the negative bias is greater than the magnitude of the maximum negative swing of RF k in the RF signal period within the RF switch. Referring to Figures 5A, 5B and 5C, the first, second and third exemplary rectifier circuits of the present invention are shown, respectively. Each of the first to third exemplary rectifier circuits includes at least one resistor directly connected to the electrical ground, at least one capacitor directly connected to the electrical ground, at least one diode directly connected to the electrical ground, and directly connected to the rectifier circuit At least another diode of the input node.

In the first exemplary rectifying circuit of FIG. 5A, R is connected to the first exemplary rectifying circuit of the two diodes; the following can be used to obtain the input voltage on the input node of the first exemplary rectifying circuit Vi(t):

Vi(t)= Vm(1) X Sin(2 7Γ f X t) χ Z2 / (Z1 + Z2), where Vm(t) is the time-dependent amplitude of the RF signal in the -RF signal line, and is at least greater than the RF signal axis - Time ratio of the amplitude is slower. m 37 201110329 Slow change 'f is the frequency of the RF signal, t is time, Z1 is the first impedance and Z2 is the second impedance. Please note that Z1 and Z2 can be plural. In this case, the time-dependent output voltage VO(t) on the output node in the first exemplary rectifier circuit is a positive direct current (DC) voltage, which is modulated by Vm(t), which is the time-dependent amplitude of the RF signal. Obtained by: V〇(t)Lan 2xV (1)χ|Ζ2/(Ζ1 + Ζ2)|, where I Z2 / (Z1+ Z2)丨 is the magnitude of Z2 / (Z1+ Z2). The time dependent output voltage Vo(1) does not include any RF components. In 丨z2 / (Z1+ Z2) | From about 〇·ι to! In the case, the time dependent output voltage v 〇 (t) may have an amplitude equal to or greater than Vm(t), that is, a time dependent amplitude of RF ^ in the first RF signal line. In the second exemplary rectifying circuit of Fig. 5B, the RF signal is supplied to the input node of the second exemplary rectifying circuit to which the two diodes are coupled. From the column: the wheeled voltage on the wheel node of the second exemplary rectifier circuit Vi<t):

Vi(1)=Vm(t) X sin(2 7Γ f X t) X Z2 /(Z1+ Z2) , the first first time dependent positive wheel voltage vi〇(t) in the first exemplary rectification electric m demonstration rectifier circuit is The positive DC through vm(t), that is, the time dependent amplitude of the treacherous signal, is obtained by the following: v 10 (t) S V".(1) X |Z2/(Z 1 + Z2)|, 38 201110329 where I Z2 / (zi+ Z2) 丨 is the magnitude of Z2 / (Z1 + Z2). The first time dependent output voltage Vlo(1) does not include any RF components. The first time dependent output voltage (1) may have an amplitude less than Vm(1), i.e., a time dependent amplitude of the rf signal in the first RF signal line. The second time-dependent positive output voltage 乂2〇 on the second output node in the second exemplary rectifier circuit (〇 is a negative direct current (DC) voltage, which is modulated by Vm(1), that is, the time-dependent amplitude of the Rjp signal, by the following Obtain: V20(t)sV (t)x|Z2/(Zl + Z2)|, where I Z2 / (Z1+ Z2) I is the magnitude of Z2 / (Z1+ Z2). The second time dependent output voltage V2o(1) does not include any The second time dependent output voltage Vo(1) may have an amplitude less than ym(t), that is, a time dependent amplitude of the RF signal in the first RF signal line. In the third invariant rectifier circuit of FIG. 5C, the RF signal is An input node of a third exemplary rectifier circuit supplied to a node on which two pairs of two connected diodes are connected. The time dependent input voltage Vi(1) on the input node of the third exemplary rectifier circuit can be derived from:

ViW =Vm(t) X sin(2 7Γ f X t) X Z2/ (zi+ Z2) is the same as the first-example rectifier circuit. The first-time dependent positive output voltage νι〇 on the first-out node of the third exemplary rectifier circuit (〇 is a positive direct current (DQ voltage, which is the RF signal (four) time dependent amplitude), obtained by the following:

Vl〇(t^2xV",(1) χ|Ζ2/(Ζ1 + Ζ2)|, 201110329 where I Z2 / (Z1+ Z2) I is the amplitude of Z2 / (Z1+ Z2). The first time dependent output voltage Vl〇(1) is not Including any RF component. In the case of 丨η /(Z1+Z2)丨 from about 0.5 to 1, the first time dependent output voltage Vlo(1) may have an amplitude equal to or greater than Vn^t), that is, the first k line The time dependent amplitude of the internal RF signal. The second time dependent positive output voltage V2 〇(t) on the second output node in the third exemplary rectifier circuit is a negative direct current (DC) voltage ', after Vm(t), that is, the time dependent amplitude of the RF signal Variable, obtained by: V20(t) = -2x Vm(t)x|Z2/(Zl + Z2)|, where I Z2 / (Z1+ Z2) I is the magnitude of Z2 / (Z1 + Z2). The second time dependent output voltage V2o(1) does not include any RF components. In the case of 丨z2 /(Z1+Z2) | from about 0.5 to i, the second time dependent output voltage V2o(1) may have an amplitude equal to or greater than νιηω, that is, the time dependent amplitude of the RF signal in the first rf signal line. In other words, other rectifying circuits can be used instead of the first, second or second non-parametric rectifying circuit. Here, a rectifying circuit that provides a DC output voltage can be used. The output voltage exceeds twice the amplitude of the input RF signal supplied to the input node of the rectifying circuit, and is particularly useful if 丨Z2/(Z1+Z2) 丨 is less than 〇5. Referring to Figure 3, the at least one output bias is supplied to the RF switch by at least one bias feed line which provides at least one bias to the bottom semiconductor layer of the sI substrate. The at least one bias feed line may include a first electrical wiring 201110329 structure for supplying a negative bias generated by the rectifier circuit from the RIMf number to the at least one first doped semiconductor in the bottom semiconductor layer Area. The at least one bias feed line may further include a second electrical wiring structure that supplies a positive bias voltage generated by the rectifying circuit (IV) RF money to the at least one second doped semiconductor region. The first doped semiconductor region may be, for example, at least one of the first doped semiconductor regions 18 of FIG. The at least one second doped semiconductor region can be exemplified by at least one second doped sheep conductor region 28 in FIG. The first electrical wiring ===== at least one of the first doped semiconductor regions. The at least one first interconnected metal wire-electrical wiring structure of the vertically adjacent CM H conductive vias 79 shown in FIG. 2 may include, for example, an impedance connection. At least one second conductive via 89 to at least one doped semiconductor region 28, and at least one first level metal line 99 that does not vertically abut at least one second conductive via 89 as in FIG. Each of the at least one bias voltage is supplied to the bottom semiconductor layer 1 through at least one of the holes (79, 89). For example, the at least one first conductive hole 79 is used to supply the rectifier circuit from the negative bias generated by the RF signal to at least one of the first doped semiconductor regions 18, and through at least one of the first conductive vias (four) to the entire circuit from the RF trust Zhao Red test = two - mountain second holding hetero semiconductor area 2δ. At least one first doping half is increased in the bottom semiconductor layer 1G and has ? Type doping; and at least = lower than the mountain, at least one field effect transistor. At least one second doped semiconductor product is in the bottom semiconductor layer and has n-type doping using positive and negative · generated from the rectifying circuit, using the above method = system = 41 201110329 end semiconductor layer Η) Charge. It is true that at least one of the output bias voltages supplied to the RF switch semiconductor is located at or above the top end of the semiconductor layer at the top of the S?1 substrate to reduce the secondary capacitance fit, otherwise the implementation of the RF switch performance is improved. example. Referring to Figure 6, the time-dependent amplitude of the RF signal, Vm(t), is used to automatically adjust the amplitude of at least one of the bias voltages. In other words, the amplitude of each of the at least one bias generated from the rectifying circuit is automatically adjusted to the t-level of the treacherous signal. This self-aligning function has the advantage of optimizing at least one bias amplitude so that excessive bias is avoided and the optimum level of at least one bias can be provided to the RF switch at any time. Figure 7 shows a block diagram of an exemplary design flow, such as used in semiconductor 1C logic design, simulation, test 'deployment, and fabrication. Design flow 900 includes processing structures or devices for processing the design structures described above and illustrated in Figures 2, 3, 4A, 4B, 4C, 5A, 5B, 5C, and 6 and/or The logic or other functions of the device are equivalent to the processing and organization. The design structure processed and/or produced by the design flow can be encoded with a machine readable transport or storage medium to include hardware components, circuits, devices or systems when executed or processed on a data processing system. Information and/or instructions that are logically, structurally, institutionally, or functionally equivalent. The design flow 900 may vary depending on the representative class being designed. For example, the design flow for creating an application-specific integrated circuit (ASIC) is different from the design flow 900 for designing a standard component, or Designed into a programmable array, such as a programmable gate array (PGA) or field programmable gate array (FPGA) from Altera® Inc. or Xilinx® Inc. Process 900 is different. FIG. 7 illustrates a variety of such design structures including an input design structure 920 that is preferably processed by design process 910. Design structure 920 is a logical analog design structure generated and processed by design process 910 to produce a logically equivalent functional representation of the hardware device. The design structure 92 can also or additionally include negatives and/or program instructions that, when processed by the design process 910, generate functional representations of the hardware structure of the hardware. Whether representing functional and/or structural design features, a design structure 920 can be created using an electronic computer-aided design (ECAD) implemented by a core programmer. When the design structure 920 is encoded on a machine readable data transfer, gate array or storage medium, it can be accessed or processed by one or more hardware and/or software modules within the design process to simulate or function. Electronic components, circuits, electronics or logic modules, devices, devices or systems are shown in Figures 2, 3, 4A, 4B, 4C, 5A, 5B, 5C and 6. As such, the design structure 920 can include files or other data = constructs including human and/or state-of-the-art source code, compiled structures, and computer executable code structures when processed by a design or analog data processing system. Analog or represent circuit or other hardware logic design level. This kind of material,,,. The structure may include a hardware description language (HDL) design entity or conform to and/or compatible with a low-order HDL design language such as Veril〇g 201110329 and/or a class such as c or c++. Other data structures for the hierarchical design language. 〆

The figure is preferably used and combined for synthesis, translation or processing. 4B, Figure 4C, Figure 5A, Figure 5B, Figure 5C package: =1 connection table 980. Network connection table _ can be 1 / 〇 3 devices; ιΛ配望 ί early, distributed components, logic gates, control circuits, ^,, and /, Ming in the integrated circuit design for other components and electricity use Lean structure. The network connection table 980 can be integrated with the number i; %, the cross-connection table 980 according to the design specifications of the device, such as the other material structure type volatile storage medium as described herein, such as magnetic W, the medium is Not for the system or cache, hate body, slow + in addition or another 'media media material, electrical or optical conduction cracking and transmission and mediation: purely available Mei Mei μ Wei turn suitable way to include many rounds of data structure Type (package can be located at ==== including this, structure type 45 [ΤΤ〇^ ^ ^ ^ 5_, 90nm4) type, design and symbolic representation. The data 201110329 structure type may further include design specifications 940, feature data 95, identification data 960, design rules 970, and test data files 985, which may include input test patterns, output test results, and other test information: design process 910 may further These include, for example, standard mechanical design processes such as force analysis, thermal analysis, mechanical event simulation, and operational processing simulations such as fabrication, molding, and stamping. Those skilled in the art will appreciate that the scope of the mechanical design tools and applications used in designing process 910 does not depart from the scope and spirit of the invention. Design processing 91〇 may also include modules for performing standard circuit design processing such as timing analysis, validation, design rule checking, location and path operations, and the like. The design process 910 utilizes and incorporates logic and physical design tools such as HDL compilers and analog style building tools to match the design structure 920 with some or all of the described supporting data structures with any additional mechanical design or material (if applicable). Processed together to produce a second design structure 990. Design structure 990 is used in a data format for the exchange of information between mechanical devices and structures (eg, stored in IGES, DXF, Parasolid XT, JT, DRG, or any other format suitable for storing or presenting such mechanical design structures), Located in the storage medium or in the programmable editing gate array. The design structure 990 is similar to the design structure 920 and preferably includes one or more trough 'data structures or other computer-encoded data or instructions located in the transport or data storage medium, and after being processed by the ECAD system, produces Figure 2, Figure 3. A logical or functional equivalent of one or more of the specific embodiments of the invention illustrated in Figures 4A, 4B, 4C, 5A, 5B, 5C and 6. In a specific embodiment, the design structure 990 can include compiled features that functionally simulate the devices shown in FIG. 2, FIG. 3, FIG. 4A, FIG. 4B, FIG. 4C, FIG. 5A, FIG. 5B, FIG. 45, 201110329 5C, and FIG. The RiHDL analog version can be implemented. The design structure 990 may also utilize data formats and/or symbolic data formats for integrated circuit design data exchange (eg, stored in GDSII (GDS2), GU, OASIS, map files, or other suitable storage structure for such design data. Information in any format). The design structure 99〇 may contain information such as, for example, symbol data, map files, test data files, design content files, manufacturing materials, configuration parameters, wiring, metal levels, perforations, shapes, path data through manufacturing lines, and manufacturing. The quotient or other programmer produces any of the data required for the apparatus or structure described above and illustrated in Figures 2, 3, 4A, 4, 5A, 5B, 5C, and 6. The design structure 990 then proceeds to stage 995 where it is, for example, set up to branch, start manufacturing, send to the shell factory, send it to other departments, and send it back to the customer. While the invention has been described in terms of specific embodiments, it will be understood that many modifications, modifications and Therefore, the present invention is intended to cover all such alternatives, modifications, and variations of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a vertical cross-sectional view of a prior art RF switch structure. 2 is a vertical cross-sectional view of an exemplary semiconductor structure implemented as an embodiment of a semiconductor circuit of the present invention. And <8> Figure 3 is an exemplary semiconductor circuit of the present invention. 4A, 4B and 4(: respectively, the first and second embodiments of the voltage divider of the present invention, S] 46 201110329. Figures 5A, 5B and 5C are the first and the first of the rectifier circuit of the present invention, respectively. Second and third embodiments. Figure 6 is a time diagram showing the radio frequency (RF) signal, the positive bias supplied to the radio frequency (RF) switch, and the negative bias voltage supplied to the RF switch. Flow chart of design and fabrication of semiconductor design and fabrication of semiconductor structure of the invention. [Description of main component symbols] 8 On-insulator semiconductor (SOI) substrate 10 Bottom semiconductor layer 11 Charge layer 12 Resistor 13 Inductive charge layer 18 First doped semiconductor Area 20 buried insulating layer 22 capacitor 28 second doped semiconductor region 30 top semiconductor layer 32 top semiconductor portion 33 shallow trench insulating structure 37 second lower conductive hole 40 gate dielectric 42 gate electrode 44 gate spacer Plate 47 First lower conductive hole 201110329 77 First upper conductive hole 79 First conductive hole 80 Line center (MOL) dielectric layer 87 Second upper conductive hole 88 Contact hole 89 Second conductive hole 90 Interconnected dielectric layer 94 An interconnected metal line 98 A third interconnected metal line 99 A second interconnected metal line 900 Design flow 910 Design processing 920 Input design structure 930 Library component 940 Design specification 950 Characteristic data 960 Confirmation tribute 970 Design rule 980 Network Connection Table 985 Test Data File 990 Second Design Structure 995 Stage Z1 First Impedance Z2 Second Impedance 48

Claims (1)

201110329 VII. Patent application scope 1. The method of semiconductor circuit includes the following steps: providing a semiconductor circuit, the semiconductor device (RF), which comprises a semiconductor (s〇i) base on the insulating layer At least one effect transistor; a radio frequency (RF) signal line 'for transmitting a radio frequency (RF) signal, wherein the RF signal line is connected to the RF switch; and a circuit for generating at least one bias from the RF signal And a method of supplying the at least one bias voltage to the bottom semiconductor layer of the SOI substrate. The method of claim W, wherein the semiconductor circuit further comprises a latent, biased <1 feed line, the at least one bias The method of claim 1, wherein the at least one conductive hole of the semiconductor is electrically connected to the conductor layer, and wherein the at least one conductive hole is penetrated The at least one bias voltage is provided to the bottom semiconductor layer. 4. The method of claim 2, wherein the at least the bias voltage comprises a positive bias voltage, the positive bias voltage having an amplitude greater than the signal at the location a maximum positive swing amplitude of the signal at the period, and wherein the at least one bias voltage comprises a bias voltage having an amplitude greater than a maximum negative swing amplitude of the RF signal during the RF signal period. For example, in the method of the patent application, the semiconductor circuit further includes a power amplifier that connects and provides the RF signal to the signal line. 49 201110329 6. The method of claim 1, wherein the method The circuit further includes a voltage divider connected between the RP signal line and the electrical ground, the voltage divided state comprising a first group of at least one impedance element having a first impedance and a second group having At least one impedance element of the second impedance, wherein one end of the first set of at least one impedance element is directly connected to the RF signal line, and wherein one end of the second set of at least one impedance element is directly connected to the electrical ground. The method of claim 1, wherein the semiconductor circuit further comprises: at least one first doped semiconductor region embedded in the bottom semiconductor layer and having a p-type doping And at least a second doped semiconductor region embedded in the bottom semiconductor layer and having an n-type doping. The method of claim 7, wherein the circuit further comprises a rectifying circuit connected to a voltage divider and generating at least a voltage from the RJ7 signal, and further comprising: supplying the rectifier circuit from a negative bias generated by the RF signal to the at least one first doped semiconductor region; and The rectifier circuit supplies a positive bias generated by the RF signal to the at least one second doped semiconductor region. 9. The method of claim 8 further comprising: using the negative bias and the positive bias One of the suppression-formation of the accumulation region' wherein most of the charge carriers in the accumulation region accumulate in the bottom semiconductor 50 201110329 layer; and use the negative bias; 1 and the positive bias The formation of the transition zone 'where a small number of charge carriers accumulate within the bottom semiconductor sound.曰10· A semiconductor circuit comprising: - a radio frequency (four) switch 'comprising at least one effect transistor on a semiconductor (s〇I) substrate on an insulating layer; a radio frequency (RF) signal line for transmitting a radio frequency ( An RF signal, wherein the RF signal line is connected to the RF switch; the voltage is a voltage regulator connected between the RJ? signal line and the electrical ground; and a rectifier circuit is coupled to the voltage divider and from the signal Generating to > a bias voltage, wherein the at least one bias voltage varies with a time constant greater than the flag period; and at least one bias feed line providing the at least one bias voltage to a bottom end of the SOI substrate Semiconductor layer. 11. The semiconductor circuit of claim 1, further comprising at least one via impedance connected to the bottom semiconductor layer, wherein the at least one bias is provided to the bottom semiconductor layer through the at least one conductive via. The material circuit of claim 10, wherein the at least one bias voltage comprises a positive bias voltage having a magnitude greater than a maximum positive swing amplitude of the RF signal during the signal period. 13. The semiconductor circuit of claim 1, wherein the at least one bias 51 201110329 voltage comprises a negative bias having a magnitude greater than a maximum negative swing amplitude of the RF signal during the signal period. 14. The semiconductor circuit of claim 10, wherein the at least one bias voltage comprises - positively biased ink, the positive bias having an amplitude greater than a maximum positive swing amplitude of the RP signal during the signal period, and wherein The at least 〆 dust includes a negative bias 'the negative bias has a magnitude greater than a maximum negative swing amplitude of the RF signal during the RF signal period. 15. The semiconductor circuit of claim 10, further comprising a power amplifier that connects and provides the RF signal to the signal line. 16. The semiconductor circuit of claim 1, wherein the voltage divider-series-stage has at least one impedance j of the first impedance and a second group has at least a second impedance An impedance element, wherein = one end of the group to the J-impedance element is directly connected to the signal there and wherein the second set of at least - the _ end of the impedance element is directly connected to the rake, the rake and wherein the first group and the second The shared node between the groups is directly connected to the input node of the rectifier circuit. 17. The semiconductor circuit of claim 16, wherein each of the first = to 乂-impedance I and the second set of at least - the impedance element comprise at least one of a resistor, a capacitor and an inductor. 52 18. 201110329 A ratio between the amplitudes of the second impedance is generally 〇5 to 丨〇. 19. The semiconductor circuit of claim 16, wherein the rectifier circuit comprises at least one resistor directly connected to the electrical ground, at least one capacitor directly connected to the electrical ground, at least one diode directly connected to the electrical ground, and Directly connected to at least one other diode of the input node of the rectifier circuit. 20. The semiconductor circuit of claim 1, further comprising: at least a first doped semiconductor region embedded in the bottom semiconductor layer and having a germanium type doping, wherein the rectifying circuit is a negative bias voltage generated by the RF signal is supplied to the at least one first doped semiconductor region; and at least a second doped semiconductor region embedded in the bottom semiconductor layer and having an n-type doping, wherein The rectifier circuit supplies a positive bias generated by the RF signal to the at least one second doped semiconductor region. 21. A design data structure embodied in a mechanically readable medium for designing, manufacturing or testing a design for a semiconductor structure, the design data structure comprising: a first data representing a radio frequency ( An RF switch comprising at least one effect transistor on a semiconductor-on-insulator (SOI) substrate; a second tribute representing a radio frequency (RF) signal line for transmitting a radio frequency (RF) signal, wherein the signal line is connected to the liver switch; a second tribute represents a voltage divider, the voltage divider is connected between the RF line and the electrical ground; Representing a rectifier circuit connected to the voltage component 53 201110329, the RF signal generating at least one bias 'where the bias voltage varies with a time constant greater than the RF signal period; and the fifth data 'its Representing at least a bias feed line that provides at least one bias voltage to a bottom semiconductor layer of the SOI substrate. 22. The design data structure of claim 21, further comprising an additional two shell material, wherein at least one conductive via is electrically connected to the bottom semiconductor layer, wherein the at least one is provided through the at least one conductive via The primer conductor layer. _ 23. If the design data structure of the patent application scope is included, the following: and the /, the material 'representative-antenna, which is used to transmit the signal; the fine line, the line is connected to the 24. The design data structure of item 21, wherein the third asset-di VIII data, the ninth data, the tenth data, the eighth resource-first group has at least a first impedance-impedance element, the second The lean material represents - the second group has at least - the impedance of the second impedance - the tenth data represents that the first group - at least - the impedance element has no second group to >, - the impedance between the - series, wherein The at least one impedance end of the first group is directly connected to the signal line there, and wherein the - terminal of the first read 〆-impedance τ 直接 is directly connected to a common node between the second group of the electrical ground and directly connected to the heart path An input node. 1 54 201110329 25. The design data structure of claim 21, further comprising: - the first-other material 'represents at least a - doped semiconductor region, the region being strictly within the bottom semiconductor layer and having a a p-type doping; a second other material representing a -first electrical wiring structure for supplying the rectifier circuit from a negative bias generated by the RF signal to the first doped semiconductor region - a third other material 'represents at least - a second doped conductor region embedded in the bottom turn layer and having -n type doping; and Jiang: his data representing a second electrical wiring structure, The structure is used for the small circuit to supply a positive bias generated by the good signal to the second doped semiconductor region. 55